ZRI/ZQI Block Diagram

lock iagram RIII-SOIMM RM P Mb**pcs/ = G P, hannel (00 MHZ) hannel R PU Richland PU (W) mm X mm FP pin G P,,, GFX P P P0 PEG0~(PI-E x ) ep PNEL P HMI ONN TXP/N,0/ P GPU Mars XT(W) mm X mm P~ X'TL.0MHz hannel hannel VRM P, VRM R-M* = G VRM R-M* = G P STK UP LYER : TOP LYER : LYER : IN LYER : IN LYER : SV LYER : IN LYER : LYER : OT UMI UMI LINK.GT /s UMI(x) TXP/N,/ US- US- SW HSS P TXP/N,/ US US MINI P ONN P ST - H P ST0 ST US.0 US-0 US-0 US.0 on. (charger) P ST - SS P ST US on. P / US on. P P Touch Panel P US-0 US- US- US- TTERY P US.0 RT FH olton M.mm X.mm PIE X'TL MHz P X'TL.KHz P US- PIE-0 PIE- MINI R WLN+T LN & R Q 0/00/G P P0 X'TL MHz RJ onn. P ard Reader onn. P harger (QRGRR) P SYSTEM V/V (TPSRUKR) P +.VSUS(TPS) P0 +.V(TPS) / +.V P HUIO P,,, 0, LP SPIROM IOSROM P.V_UL(TPS) +V_ORE (ISL) P P +VGPU_ORE(TPS) P udio odec L P E L P +PIE_V_GFX(TPS) P +.V_GFX(TPSRTER) P INT. MI P HP/MI P MP L00 P PU FN GPU FN HLL Sensor K/ Touch Pad P P P P P / TPM onn. P ischarge /Thermal P Seaker onn. P Quanta omputer Inc. PROJET : Size ocument Number Rev LOK IGRM Wednesday, pril, 0 ate: Sheet of 0

OM Option Power Sequence ITEM LVS Panel Sku ep Panel Sku VG Sku ESRIPTION VG Thames Sku VG Mars Sku VG Sku for Thames and Mars stuff different value parts GPU bit Sku GPU bit Sku of Special part value change MRK LVS@ ep@ EV@ EV_T@ EV_M@ EV_SP@ EV_@ EV_SP@ US harge Functions Sku H@ 0 No US harge Functions Sku NH@ US.0 Re-river Sku R@ No US.0 Re-river Sku NR@ lways connect functions Sku @ IN V/VPU NSWON# NSWON# S_ON/S RSMRST# PIE_WKE# SUS SUS SUSON MINON Hudson M SMUS PLK_SM PT_SM (+V) SLK ST (+V_S) FH SMUS SM_E_LK (SLK) SM_E_T (ST) (+V_S) SLK ST (+VPU) SL ST (+V_S) Pin NO. T R H G G G J K SMUS Function efine R / WLN Touch Pad E Not used Not used No lways connect functions Sku N@ VR_ON Special part value change or modify for different OM sku Key oard ack light Sku SS Sku SP@ KL@ SS@ Touch panel Sku TP@ Page GPIO strap pin ITEM ESRIPTION MRK Synaptics touch pad SYNP@ ELN touch pad ELN@ For UM Sku UM@ PU_ORE VRM_PWRG HWPG EPWROK S_PWRG_IN PU RESET PU POWER OK E SMUS K SMUS MLK MT (+VPU) PU_SI_E PU_SI_E (+V_S) GPUT_LK GPUT_T (+V_GFX) Pin NO. SMUS Function efine 0 attery, FH PU 0 GPU ELPI on board RM ELP@ HYNIX on board RM HYN@ TPLK TPT (+V) Touch Pad E FH evice I_evice(S) Ie_(M) If_(M) harger attery LL/S Ie_(M) PU LL Ie_(M) If_(M) PU S If_(M) S If_0(M) R WLN/G Image Sensor S0 E will onflict with FH. o not mount Quanta omputer Inc. PROJET : Size ocument Number Rev SYSTEM INFORMTION Wednesday, pril, 0 ate: Sheet of 0

PEG X U [] PEG_RXP0 P PEG_TXP0_ P_GFX_RXP[0] P_GFX_TXP[0] N EV@0.u/0V_ [] PEG_RXN0 P PEG_TXN0_ P_GFX_RXN[0] P_GFX_TXN[0] N EV@0.u/0V_ [] PEG_RXP M PEG_TXP_ P_GFX_RXP[] P_GFX_TXP[] M EV@0.u/0V_ [] PEG_RXN M PEG_TXN_ P_GFX_RXN[] P_GFX_TXN[] M EV@0.u/0V_ [] PEG_RXP K PEG_TXP_ P_GFX_RXP[] P_GFX_TXP[] K EV@0.u/0V_ [] PEG_RXN K PEG_TXN_ P_GFX_RXN[] P_GFX_TXN[] K EV@0.u/0V_ [] PEG_RXP J PEG_TXP_ P_GFX_RXP[] P_GFX_TXP[] H 0 EV@0.u/0V_ [] PEG_RXN J PEG_TXN_ P_GFX_RXN[] P_GFX_TXN[] H EV@0.u/0V_ [] PEG_RXP H PEG_TXP_ EV@0.u/0V_ P_GFX_RXP[] P_GFX_TXP[] F [] PEG_RXN H PEG_TXN_ P_GFX_RXN[] P_GFX_TXN[] F EV@0.u/0V_ [] PEG_RXP F PEG_TXP_ P_GFX_RXP[] P_GFX_TXP[] E EV@0.u/0V_ [] PEG_RXN F PEG_TXN_ P_GFX_RXN[] P_GFX_TXN[] E EV@0.u/0V_ [] PEG_RXP PEG_TXP_ P_GFX_RXP[] P_GFX_TXP[] EV@0.u/0V_ [] PEG_RXN PEG_TXN_ P_GFX_RXN[] P_GFX_TXN[] EV@0.u/0V_ [] PEG_RXP PEG_TXP_ P_GFX_RXP[] P_GFX_TXP[] EV@0.u/0V_ [] PEG_RXN PEG_TXN_ P_GFX_RXN[] P_GFX_TXN[] EV@0.u/0V_ P_GFX_RXP[] P_GFX_TXP[] Y FP only support PEG X P_GFX_RXN[] P_GFX_TXN[] Y FP only support PEG X Y P_GFX_RXP[] P_GFX_TXP[] V Y P_GFX_RXN[] P_GFX_TXN[] V V P_GFX_RXP[0] P_GFX_TXP[0] U V P_GFX_RXN[0] P_GFX_TXN[0] U T P_GFX_RXP[] P_GFX_TXP[] T T P_GFX_RXN[] P_GFX_TXN[] T P P_GFX_RXP[] P_GFX_TXP[] P P P_GFX_RXN[] P_GFX_TXN[] P N P_GFX_RXP[] P_GFX_TXP[] M N P_GFX_RXN[] P_GFX_TXN[] M M P_GFX_RXP[] P_GFX_TXP[] K M P_GFX_RXN[] P_GFX_TXN[] K K P_GFX_RXP[] P_GFX_TXP[] J K P_GFX_RXN[] P_GFX_TXN[] J GRPHIS PEG_TXP0 [] PEG_TXN0 [] PEG_TXP [] PEG_TXN [] PEG_TXP [] PEG_TXN [] PEG_TXP [] PEG_TXN [] PEG_TXP [] PEG_TXN [] PEG_TXP [] PEG_TXN [] PEG_TXP [] PEG_TXN [] PEG_TXP [] PEG_TXN [] PEG X 0 J0RT0 J0UT0 J0T0 [] UMI_RXP0 [] UMI_RXN0 [] UMI_RXP [] UMI_RXN [] UMI_RXP [] UMI_RXN [] UMI_RXP [] UMI_RXN +.V_VP R /F_ P_ZVP H H G G E E M0 N0 N M P R R P R P_GPP_RXP[0] P_GPP_RXN[0] P_GPP_RXP[] P_GPP_RXN[] P_GPP_RXP[] P_GPP_RXN[] P_GPP_RXP[] P_GPP_RXN[] P_UMI_RXP[0] P_UMI_RXN[0] P_UMI_RXP[] P_UMI_RXN[] P_UMI_RXP[] P_UMI_RXN[] P_UMI_RXP[] P_UMI_RXN[] P_ZVP GPP UMI P_GPP_TXP[0] P_GPP_TXN[0] P_GPP_TXP[] P_GPP_TXN[] P_GPP_TXP[] P_GPP_TXN[] P_GPP_TXP[] P_GPP_TXN[] P_UMI_TXP[0] P_UMI_TXN[0] P_UMI_TXP[] P_UMI_TXN[] P_UMI_TXP[] P_UMI_TXN[] P_UMI_TXP[] P_UMI_TXN[] P_Z G G E E N M P R P R P R P UMI_TXP0_ UMI_TXN0_ UMI_TXP_ UMI_TXN_ UMI_TXP_ UMI_TXN_ UMI_TXP_ UMI_TXN_ P_Z 0 0 0 0 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0 0 0 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ UMI_TXP0 [] UMI_TXN0 [] UMI_TXP [] UMI_TXN [] UMI_TXP [] UMI_TXN [] UMI_TXP [] UMI_TXN [] RIHLN_PU_G R0 /F_ HT+ onnector for ebug only +.V [] PU_TRST# PU_TRST# R R0 R0 *0K_ *0K_ *0K_ +.VSUS J PU_VIO PU_TRST_L PU_RY PU_RY PU_RY PU_VIO PU_TK PU_TMS PU_TI PU_TO PU_PWROK_UF 0 PU_RST_L_UF PU_RY0 PU_REQ_L PU_PLLTEST0 PU_PLLTEST 0 PU_TK PU_TMS PU_TI PU_TO PU_PWROK_UF PU_RST_L_UF PU_REQ# PU_TK [] PU_TMS [] PU_TI [] PU_TO [] PU_RY [] PU_REQ# [] PU_TEST_PLLTEST0 [] PU_TEST_PLLTEST [] [,] PU_RST# [,] PU_PWRG_R R *K_ U Y V +V Y 0 *LVG0 *0.u/0V_ R *K_ PU_RST_L_UF PU_PWROK_UF *HT+ HEER lose by HT+ onector PU_TI PU_TK PU_TMS PU_TRST# PU_REQ# R R R R R K_ K_ K_ K_ K_ +.VSUS Quanta omputer Inc. PROJET : Size ocument Number Rev PU /(PIE/UMI/GPP/HT) ate: Wednesday, pril, 0 Sheet of 0

M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M S#0 M S# M S# M M M M M M M M M M M M0 M M M M M M M M M M M 0 M M M M M 0 M M M M +M_ZVIO M M M M 0 M M M M M M S# M M 0 M M M M S# M S#0 M M M Q[0..] [] M Q[0..] [,] M M[..0] [] M S#[..0] [] M [:0] [] M [:0] [,] M S#[..0] [,] M QSP0 [] M QSP [] M QSP [] M QSP [] M QSP [] M QSP [] M QSP [] M QSP [] M QSN0 [] M QSN [] M QSN [] M QSN [] M QSN [] M QSN [] M QSN [] M QSN [] M LKP0 [] M LKN0 [] M LKP [] M LKN [] M KE0 [] M KE [] M OT0 [] M OT [] M S#0 [] M S# [] M RS# [] M S# [] M WE# [] M RST# [] M EVENT# [] M QSP0 [,] M QSP [,] M QSP [,] M QSP [,] M QSP [,] M QSP [,] M QSP [,] M QSP [,] M QSN0 [,] M QSN [,] M QSN [,] M QSN [,] M QSN [,] M QSN [,] M QSN [,] M QSN [,] M LKP0 [] M LKN0 [] M OT0 [] M KE0 [] M S#0 [] M RS# [,] M S# [,] M WE# [,] M RST# [,] M M0 [,] M M [,] M M [,] M M [,] M M [,] M M [,] M M [,] M M [,] M LKP [] M LKN [] M KE [] M OT [] M S# [] +.VSUS +MEMVREF_PU +.VSUS +MEMVREF_PU Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : PU /(R MEM I/F) Wednesday, pril, 0 0 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : PU /(R MEM I/F) Wednesday, pril, 0 0 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : PU /(R MEM I/F) Wednesday, pril, 0 0 Place close to PU within " Soldermask openings for all bottom side vias/tps under FS 0 J0RT0 J0UT0 J0T0 TP TP R *short_ R *short_ R K/F_ R K/F_ R./F_ R./F_ 000p/0V_ 000p/0V_ 0 0.u/0V_ 0 0.u/0V_ U RIHLN_PU_G U RIHLN_PU_G M_[0] Y M_[] R M_[] T M_[] P M_[] P M_[] P M_[] N M_[] M M_[] M M_[] L M_[0] M_[] M M_[] K M_[] F M_[] K M_[] J M_NK[0] M_NK[] M_NK[] K M_M[0] M_M[] M_M[] M_M[] M_M[] M M_M[] N0 M_M[] R M_M[] N M_QS_H[0] M_QS_L[0] M_QS_H[] M_QS_L[] M_QS_H[] 0 M_QS_L[] M_QS_H[] M_QS_L[] M_QS_H[] M M_QS_L[] M M_QS_H[] N M_QS_L[] P M_QS_H[] P M_QS_L[] P M_QS_H[] R M_QS_L[] P M_LK_H[0] W M_LK_L[0] Y M_LK_H[] V M_LK_L[] V M_LK_H[] U M_LK_L[] V M_LK_H[] T M_LK_L[] T M_KE[0] H M_KE[] H M0_OT[0] F M0_OT[] H M_OT[0] E M_OT[] H M0_S_L[0] M0_S_L[] F M_S_L[0] M_S_L[] G M_RS_L M_S_L M_WE_L M_RESET_L H M_EVENT_L Y M_T[0] M_T[] M_T[] 0 M_T[] 0 M_T[] M_T[] M_T[] M_T[] 0 M_T[] M_T[] M_T[0] M_T[] M_T[] M_T[] M_T[] M_T[] M_T[] M_T[] M_T[] M_T[] M_T[0] M_T[] M_T[] 0 M_T[] 0 M_T[] M_T[] M_T[] F M_T[] F M_T[] M_T[] M_T[0] E M_T[] F M_T[] K M_T[] L M_T[] P M_T[] N M_T[] K M_T[] K M_T[] N M_T[] P M_T[0] P0 M_T[] R0 M_T[] P M_T[] N M_T[] R M_T[] P M_T[] R M_T[] P M_T[] P M_T[] N M_T[0] R M_T[] P M_T[] P M_T[] R M_T[] N M_T[] P M_T[] R0 M_T[] P M_T[] P M_T[] R M_T[0] N0 M_T[] P0 M_T[] P M_T[] N 0.u/.V_ 0.u/.V_ R K/F_ R K/F_ U RIHLN_PU_G U RIHLN_PU_G M_[0] M_[] R M_[] T0 M_[] R M_[] R M_[] P M_[] P M_[] P0 M_[] P M_[] M M_[0] M_[] M M_[] M M_[] E M_[] L M_[] L M_NK[0] M_NK[] M_NK[] M0 M_M[0] M_M[] 0 M_M[] E M_M[] F0 M_M[] K M_M[] L M_M[] M0 M_M[] M M_QS_H[0] G M_QS_L[0] H M_QS_H[] F M_QS_L[] G M_QS_H[] E M_QS_L[] F M_QS_H[] H0 M_QS_L[] G0 M_QS_H[] L M_QS_L[] L0 M_QS_H[] H M_QS_L[] J M_QS_H[] K0 M_QS_L[] L0 M_QS_H[] K M_QS_L[] L M_LK_H[0] W M_LK_L[0] Y0 M_LK_H[] W M_LK_L[] W M_LK_H[] U M_LK_L[] V0 M_LK_H[] U M_LK_L[] U M_KE[0] L M_KE[] K0 M0_OT[0] 0 M0_OT[] G M_OT[0] E M_OT[] G M0_S_L[0] M0_S_L[] E M_S_L[0] 0 M_S_L[] F0 M_RS_L M_S_L M_WE_L M_RESET_L J M_EVENT_L M_VREF G M_ZVIO J M_T[0] F M_T[] E M_T[] H M_T[] F M_T[] E M_T[] H M_T[] E M_T[] M_T[] G0 M_T[] E0 M_T[0] H M_T[] G M_T[] E M_T[] H0 M_T[] E M_T[] M_T[] H M_T[] F M_T[] M_T[] M_T[0] E M_T[] M_T[] M_T[] M_T[] G M_T[] G M_T[] H M_T[] J M_T[] E M_T[] F M_T[0] H M_T[] H M_T[] H M_T[] J0 M_T[] M M_T[] M M_T[] H M_T[] H M_T[] J M_T[] K M_T[0] K M_T[] J M_T[] K M_T[] J M_T[] M M_T[] L M_T[] M M_T[] L M_T[] K M_T[] H M_T[0] K M_T[] H M_T[] M M_T[] L M_T[] J0 M_T[] L M_T[] K M_T[] J M_T[] K M_T[] H M_T[0] M M_T[] L M_T[] H M_T[] L

Note: LK_PU_HLKP/N is 00MHZ SS Note: LK_P_NSSP/N is 00MHZ non-ss [] E FH [,] [,] H_PROHOT# +.V ORE_PWM_PROHOT# PU ore Power P0 MINI P P HMI P ep [,] PU_RST# PU_PWRG_R 0K_ R [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] INT_HMI_TXP INT_HMI_TXN INT_HMI_TXP INT_HMI_TXN INT_HMI_TXP0 INT_HMI_TXN0 INT_HMI_TXP INT_HMI_TXN [] [] [] [] [] [] [] [] [] [] [] [] MINI_P_TXP0 MINI_P_TXN0 MINI_P_TXP MINI_P_TXN MINI_P_TXP MINI_P_TXN MINI_P_TXP MINI_P_TXN EP_TXP0 EP_TXN0 EP_TXP EP_TXN EP_TXP EP_TXN EP_TXP EP_TXN LK_PU_HLKP LK_PU_HLKN LK_P_NSSP LK_P_NSSN [] +.VSUS PU_PWRG_R +.VSUS R 00_ +.VSUS R0 K_ PU_V_RUN_F_L PU_SVT R Q METR0-G_00M PU_VN_RUN_F_H PU_V_RUN_F_H R 00_ +.V *short_ [] [] [] [] [] [] [] SV SV R R 0 PU_TI PU_TO PU_TK PU_TMS PU_TRST# PU_RY PU_REQ# 0 *short_ *K_ 0P/0V_ 0P/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ PU_SVT_R PU_SI PU_SI INT_HMI_TXP_ INT_HMI_TXN_ INT_HMI_TXP_ INT_HMI_TXN_ INT_HMI_TXP0_ INT_HMI_TXN0_ INT_HMI_TXP_ INT_HMI_TXN_ INT_EP_TXP0_ INT_EP_TXN0_ INT_EP_TXP_ INT_EP_TXN_ INT_EP_TXP_ INT_EP_TXN_ INT_EP_TXP_ INT_EP_TXN_ H_PROHOT# PU_THERMTRIP#_ PU_LERT TP TP TP0 H H H H F F F F E E L K L K E E J H K H L K R0 E G H F H E E G H H G G H U P0_TXP[0] P0_TXN[0] P0_TXP[] P0_TXN[] P0_TXP[] P0_TXN[] P0_TXP[] P0_TXN[] P_TXP[0] P_TXN[0] P_TXP[] P_TXN[] P_TXP[] P_TXN[] P_TXP[] P_TXN[] P_TXP[0] P_TXN[0] P_TXP[] P_TXN[] P_TXP[] P_TXN[] P_TXP[] P_TXN[] LKIN_H LKIN_L ISP_LKIN_H ISP_LKIN_L SV SV SVT SI SI RESET_L PWROK PROHOT_L THERMTRIP_L LERT_L TI TO TK TMS TRST_L RY REQ_L _SENSE VP_SENSE VN_SENSE VIO_SENSE V_SENSE VR_SENSE ISPLY PORT ISPLY PORT ISPLY PORT 0 ISPLY PORT MIS. LK SER. TRL JTG SENSE RSV TEST RIHLN_PU_G P0_UXP P0_UXN P_UXP P_UXN P_UXP P_UXN P_UXP P_UXN P_UXP P_UXN P_UXP P_UXN P0_HP P_HP P_HP P_HP P_HP P_HP P_LON P_IGON P_VRY_L P_UX_Z TEST TEST TEST0 TEST TEST TEST TEST TEST TEST TEST0 TEST TEST_H TEST_L TEST_H TEST_L TEST0_H TEST0_L TEST TEST_H TEST_L TEST MTIVE_L TEST TEST RSV RSV RSV RSV RSV M M L L J J P P R R U U M L J P R U L Y V G F E G F E F G J H G H V Y H R T L P0 T R L P H J K INT_HMI_UXP INT_HMI_UXN INT_EP_UXP_ INT_EP_UXN_ R ep_l_en PU_IGON P_UX_Z PU_TEST PU_TEST0 PU_TEST_P0 PU_TEST_P PU_TEST_P PU_TEST_P PU_TEST_PLLTEST PU_TEST_PLLTEST0 PU_TEST0_SNLK PU_TEST_SNLK PU_TEST_H PU_TEST_L PU_TEST0_H PU_TEST0_L M_TEST PU_TEST_H PU_TEST_L PU_TEST R PU_THERM PU_THERM 00K_ K_ 0.u/0V_ 0.u/0V_ R TP TP TP TP TP TP +.VSUS ep_l_en [] R0 R0 R R TP0 TP M_TEST PU_VRY_L 0/F_ INT_MINI_HP_Q [] INT_HMI_HP [] INT_eP_HP [] K_ K_ 0/F_ 0/F_ TP TP TP TP +.VSUS R *./F_ R0 R0 MINI_P_UXP [] MINI_P_UXN [] INT_HMI_UXP [] INT_HMI_UXN [] ep_uxp [] ep_uxn [] To M HT K_ K_ +.V_VP MTIVE_L controls entry and exit from the sleep and power states MTIVE_L [] INT_EP_UXP_ INT_EP_UXN_ PU_TEST_PLLTEST [] PU_TEST_PLLTEST0 [] PU_TEST R R +.VSUS R 00_.K_.K_ ep PU_VRY_L R *ep@00k_ PU_IGON R ep@00k_ Q0 ep@pttt +V R ep@0k_ +V R ep@0k_ Q ep@pttt R ep@0k_ 0 J0RT0 J0UT0 J0T0 R ep@0k_ EP_RIGHT [] Q ep@n00 ep_igon [] Q ep@n00 [,] FH_PWRG +.VSUS Q M_TEST ONNETION T R./F_ / For omal. TEST PU FOR INTERNL TEST P FOR USTOMER R *00_ +.VSUS FV0N_00M R 00K_ [] PU_THERMTRIP# METR0-G_00M R 0K_ Q R K_ PU_THERMTRIP#_ R K_ Q METR0-G_00M SYS_SHN# SYS_SHN# [,,,,] OOT VOLTGE SV SV VFIX_+V VFIX_+V =V/ =OPEN 0 0.. +.VSUS +.VSUS 0.0. +.V 0 0..0 R K/F_ R K/F_ R K_ R K_ +.VSUS 0. 0. R *K_ R *K_ R0 *.K_ [] PU_SI_E PU_SI R K_ PU_LERT SV SV PU_PWRG_R R Rd R Re R Rf *short_ *short_ *short_ PU_SV PU_SV PU_PWRG_SVI_REG PU_SV [] PU_SV [] PU_PWRG_SVI_REG [] [] PU_SI_E FV0N_00M Q FV0N_00M Q0 PU_SI R *0_ Ra R *0_ Rb R *0_ Rc for normal operation open Ra, Rb,Rc *0.u/0V_ Quanta omputer Inc. PROJET : Size ocument Number Rev PU /(isplay/misc) Wednesday, pril, 0 ate: Sheet of 0

+VP_P +V_ORE +V_ORE +VN_ORE +VN_ORE +VN_ORE +VN_P +VN_P +.V +.V +.V +.V_VP +.VSUS +.V_VR +.V_V +.VSUS +.VSUS Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : PU /(POWER/) Wednesday, pril, 0 0 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : PU /(POWER/) Wednesday, pril, 0 0 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : PU /(POWER/) Wednesday, pril, 0 0. Up to R- @.V VIO If the plane is cut to create a VIO plane, ceramic capacitors are connected across the VIO and plane split as follows VP =. V= 0. Maximum Ispike Maximum INspike VR =. ( Up to R- @.V ) For EMI For EMI For EMI cross VIO and split EOUPLING between PROESSOR and IMMs +.V_V VN PIN NME VOLTGE V.0V ~.V PU POWER TLE +VN_ORE +.V VIO +.V VP VR +.V V.0V ~.V +.VSUS +.V_VP +.V_VR NET NME.V +V_ORE 0 J0RT0 J0UT0 J0T0 u/.v_ u/.v_ 0.u/.V_ 0.u/.V_ 0.u/.V_ 0.u/.V_ 0p/0V_ 0p/0V_ p/0v_ p/0v_ 0 0.u/0V_ 0 0.u/0V_ *0.0u/V_ *0.0u/V_ 0p/0V_ 0p/0V_ 0.u/0V_ 0.u/0V_ R *short_ R *short_ 0.u/0V_ 0.u/0V_ 0 0.u/0V_ 0 0.u/0V_ 0.u/0V_ 0.u/0V_ *0.u/0V_ *0.u/0V_ 000p/0V_ 000p/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0 *0p/0V_ 0 *0p/0V_ *u/.v_ *u/.v_ 00p/0V_ 00p/0V_ *u/.v_ *u/.v_ u/.v_ u/.v_ 0.u/.V_ 0.u/.V_ 0.u/0V_ 0.u/0V_ 0p/0V_ 0p/0V_ 0.u/0V_ 0.u/0V_ 000p/0V_ 000p/0V_ UF RIHLN_PU_G UF RIHLN_PU_G 0 E E E E0 E F F F F F F0 F F F G G G G G G G G G H H H H J J J J J J J J J0 K K K K K K K K0 K L L L M M M N N N N N N N N0 N R R R T T T T T T T T0 T U W W W W W W Y Y Y Y Y Y Y Y0 Y 0 E F F F F F F F F0 F F F G G G G G G H H H0 H H H0 J J J J J J J J J J J J K K K K K0 L L L L L L L L M M M M M M M M M M M M0 N N N P P R R R R R R R R R R R 0.u/0V_ 0.u/0V_ p/0v_ p/0v_ *u/.v_ *u/.v_ 0.0u/V_ 0.0u/V_ u/.v_ u/.v_ 0 u/.v_ 0 u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ 0p/0V_ 0p/0V_ u/.v_ u/.v_ u/.v_ u/.v_ 0 *u/.v_ 0 *u/.v_ 0.u/0V_ 0.u/0V_ 0p/0V_ 0p/0V_ u/.v_ u/.v_.u/.v_.u/.v_ u/.v_ u/.v_ R *short_ R *short_ 0 0p/0V_ 0 0p/0V_ L H0KF-T0_ L H0KF-T0_ 0.0u/V_ 0.0u/V_ 0p/0V_ 0p/0V_ p/0v_ p/0v_ u/.v_ u/.v_ 0.u/0V_ 0.u/0V_ p/0v_ p/0v_ u/.v_ u/.v_ 0p/0V_ 0p/0V_ 0.u/0V_ 0.u/0V_ 0 p/0v_ 0 p/0v_ p/0v_ p/0v_ 0 u/.v_ 0 u/.v_ 0p/0V_ 0p/0V_ 0.u/0V_ 0.u/0V_ *u/.v_ *u/.v_ u/.v_ u/.v_ p/0v_ p/0v_ *u/.v_ *u/.v_ u/.v_ u/.v_ 00.u/.V_ 00.u/.V_ 0 0.u/0V_ 0 0.u/0V_ u/.v_ u/.v_ u/.v_ u/.v_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ p/0v_ p/0v_.u/.v_.u/.v_ 0 0p/0V_ 0 0p/0V_.u/.V_.u/.V_ u/.v_ u/.v_ 0p/0V_ 0p/0V_ p/0v_ p/0v_ 0.u/0V_ 0.u/0V_ 0 0.u/0V_ 0 0.u/0V_ 0 u/.v_ 0 u/.v_ 0.u/0V_ 0.u/0V_.u/.V_.u/.V_ 0 u/.v_ 0 u/.v_ 0.u/0V_ 0.u/0V_ 0p/0V_ 0p/0V_ 0 0p/0V_ 0 0p/0V_ u/.v_ u/.v_ 0.u/.V_ 0.u/.V_ 0.0u/V_ 0.0u/V_ *u/.v_ *u/.v_ u/.v_ u/.v_ 0 0p/0V_ 0 0p/0V_ 0 0p/0V_ 0 0p/0V_ UE RIHLN_PU_G UE RIHLN_PU_G V J V J V J V J V J V J0 V J V M V M V M V M V M V M V M0 V M V R V R V R V R V R V R V R V R V R0 V R V U V V V V V V V V V V V V V V V V0 V V V W V V V V V V V V V 0 V V V V V V V V V 0 V V G V G V G V G V G V G0 V G VN VN VN VN 0 VN VN VN VN VN VN VN VN VN 0 VN VN VN VN VN VN VN 0 VN VN VN VN 0 VN VN_P M VN_P N VIO J VIO K VIO K VIO L VIO L0 VIO L VIO M VIO N VIO N VIO N0 VIO N VIO P VIO R VIO R0 VIO R VIO U VIO U0 VIO U VIO W VIO W0 VIO W VIO VIO VIO VIO 0 VIO VIO VIO 0 VIO VIO VIO VIO VIO E VIO E0 VIO E VIO G VIO G VIO G VIO G0 VIO G VP M VP N VP P VP P VP R VP R VP_P VP_P VR N VR P VR P VR R VR R V M V M VN u/.v_ u/.v_.u/.v_.u/.v_

+V_S R N,no install by default *.K_ FH_TEST0 0 0p/0V_ [,0,] FH_PIE_RST# +V R R +V_S +V_S FH_TEST FH_TEST remove pull hi ( chip internal have pull hi ) R R R R R R R R R *.K_ *.K_.K_.K_ *0K_.K_.K_ *0K_ *0K_ 0K_ 0K_ PLK_SM PT_SM GPIO SLK ST SYS_RST# [] PU_THERMTRIP# O_# O_0# PH_RSMRST# +V_S R K/F_.u/0V_ [,0,,] R00V-0_00M PLTRST# [] RSMRST# [] [] [,] [] [] [,] [] [] [] [] [] [] SUS# NSWON# FH_PWRG SIO_0GTE SIO_RIN# SIO_EXT_SI# SIO_EXT_SMI# FH_LP_P# PIE_WKE# PU_THERMTRIP# [] SPKR [,,] PLK_SM [,,] PT_SM [0,] SLK [0,] ST [0] [] [] E_WLN_WKE# PIE_REQ_LN# OR_I OR_I PIE_REQ_WLN# [] SPI_HOL# PIE_REQ_GPU# TP R _ R00V-0_00M +V R PLK_SM PT_SM SLK ST R R TP *short_ *EV@0_ PIE_RST# SUS# PWR_TN# FH_TEST0 T FH_TEST T0 FH_TEST V E G R T SYS_RST# U PIE_WKE# K GEVENT0# TP V PU_THERMTRIP# R0 R0 0K/F_ W_PWRG F *0K_ VG_P GPIO R W T W J N U G E E F H G F T R G G J G V W Y V0 F U PIE_RST#/GEVENT# RI#/GEVENT# SPI_S#/GE_STT/GEVENT# SLP_S# SLP_S# PWR_TN# PWR_GOO RSMRST# HUSON-M Part of TEST0 TEST/TMS TEST G0IN/GEVENT0# KRST#/GEVENT# PME#/GEVENT# LP_SMI#/GEVENT# LP_P#/GEVENT# SYS_RESET#/GEVENT# WKE#/GEVENT# IR_RX/GEVENT0# THRMTRIP#/SMLERT#/GEVENT# W_PWRG LK_REQ#/ST_IS0#/GPIO LK_REQ#/ST_IS#/GPIO SMRTVOLT/ST_IS#/GPIO0 LK_REQ0#/ST_IS#/GPIO0 ST_IS#/FNOUT/GPIO ST_IS#/FNIN/GPIO SPKR/GPIO SL0/GPIO S0/GPIO SL/GPIO S/GPIO LK_REQ#/FNIN/GPIO LK_REQ#/FNOUT/GPIO IR_LE#/LL#/GPIO SMRTVOLT/SHUTOWN#/GPIO R_RST#/GEVENT#/VG_P GE_LE0/GPIO SPI_HOL#/GE_LE/GEVENT# GE_LE/GEVENT0# GE_STT0/GEVENT# LK_REQG#/GPIO/OSIN/ILEEXIT# PI / WKE UP EVENTS GPIO USLK/M_M_M_OS US MIS US. US.0 US_ROMP US_FSP/GPIO US_FSN US_FS0P/GPIO US_FS0N US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HS0P US_HS0N US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN G H H H H H0 G0 K0 J G F K K E0 F0 0 0 H G F E US_ROMP_S TP TP TP TP0 R.K/F_ USP+ [] USP- [] MINI P USP0+ [] USP0- [] US.0 co-lay US.0 port USP+ [] USP- [] Touch Panel USP+ [0] USP- [0] WLN USP+ [] USP- [] on ep USP+ [] USP- [] US.0 / HU HU HU +V_S R0 R R R Z_SOUT_R Z_SYN_R Z_LK_R Z_RST#_R FH_PIE_RST# PIE_WKE# PWR_TN# PIE_REQ_LN# Note:LL#, WKE# and PWR_TN need pull up to +VPU only if S+ mode is supported To zalia *0K_ 0K_ 0K_ *0K_ R0 _ R0 _ R _ R _ Z_SOUT Z_SYN Z_ITLK Z_RST# Z_SIN0 *P/0V_ Z_SOUT_UIO [] Z_SYN_UIO [] Z_ITLK_UIO [] Z_RESET#_UIO [] Z_SIN0 [] [] [] O_# O_0# GEVENT# ~# are +V_S [,,] [] SUS# GPU_PWREN Haudio interface are +V_S [] R R GPU_RST_L TP TP TP TP *short_ *short_ R 0 +V *0KX R *EV@0K_ Q EV@N00K +V_S FH_LINK SMLERT#_R GEVENT# FH_JTG_TO FH_JTG_TK FH_JTG_TI FH_JTG_RST# +V_S *R00V-0_00M Z_LK_R Z_SOUT_R Z_SIN0 Z_SIN Z_SIN Z_SIN Z_SYN_R Z_RST#_R TP TP R0 *EV@0K_ M R T P F P J T Y Y Y E K J J 0 F E0 F0 E 0 J H G K LINK/US_O#/GEVENT# US_O#/IR_TX/GEVENT# US_O#/IR_TX0/GEVENT# US_O#/IR_RX0/GEVENT# US_O#/_PRES/TO/GEVENT# US_O#/TK/GEVENT# US_O#/TI/GEVENT# US_O0#/SPI_TPM_S#/TRST#/GEVENT# Z_ITLK Z_SOUT Z_SIN0/GPIO Z_SIN/GPIO Z_SIN/GPIO Z_SIN/GPIO0 Z_SYN Z_RST# PSK_T/GPIO PSK_LK/GPIO0 PSM_T/GPIO PSM_LK/GPIO KSO_0/GPIO0 KSO_/GPIO0 KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_0/GPIO KSO_/GPIO0 KSO_/GPIO KSO_/GPIO KSO_/X0/GPIO KSO_/X/GPIO KSO_/X/GPIO KSO_/X/GPIO H UIO PS_T/S/GPIO PS_LK/E/SL/GPIO SPI_S#/GE_STT/GPIO EMEE TRL US O US.0 US_HSP US_HSN US_HS0P US_HS0N USSS_LRP USSS_LRN US_SS_TXP US_SS_TXN US_SS_RXP US_SS_RXN US_SS_TXP US_SS_TXN US_SS_RXP US_SS_RXN US_SS_TXP US_SS_TXN US_SS_RXP US_SS_RXN US_SS_TX0P US_SS_TX0N US_SS_RX0P US_SS_RX0N SL/GPIO S/GPIO SL_LV/GPIO S_LV/GPIO E_PWM0/E_TIMER0/GPIO E_PWM/E_TIMER/GPIO E_PWM/E_TIMER/WOL_EN/GPIO E_PWM/E_TIMER/GPIO00 KSI_0/GPIO0 KSI_/GPIO0 KSI_/GPIO0 KSI_/GPIO0 KSI_/GPIO0 KSI_/GPIO0 KSI_/GPIO0 KSI_/GPIO0 E E E F F G H G J H J K H G G G E H J H K K F F E F USSS_LRP USSS_LRN SM_E_LK SM_E_T R R0 USP0+ [] USP0- [] US.0 K/F_ K/F_ +FH_V SSUS_S US_TXP [] US_TXN [] MINI P US_RXP [] US_RXN [] US_TXP0 [] US_TXN0 [] US.0 US_RXP0 [] US_RXN0 [] GPIO ~ are +V_S E_PWM [] +V SM_E_LK R *0K_ R *0K_ Q0 MLK MLK [,] OLTON-M [] SMLERT# R *0K_ Q *N00K SMLERT#_R SM_E_T *N00W MT MT [,] Quanta omputer Inc. PROJET : Size ocument Number Rev FH /(GPIO/US/Z) Wednesday, pril, 0 ate: Sheet of 0

TO LN TO WLN TO LN TO WLN LK_P_NSSP/N is 00MHZ non-ss LK_PU_HLKP/N is 00MHZ SS LK_PIE_VGP/N is 00MHZ SS GPP_LKP/N is 00MHZ SS capable GPP_LKP/N is 00MHZ SS capable [] [] [0] [0] [] [] [0] [0] [] [] [] [] [] [] [0] [0] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] PIE_RST# UMI_RXP0 UMI_RXN0 UMI_RXP UMI_RXN UMI_RXP UMI_RXN UMI_RXP UMI_RXN UMI_TXP0 UMI_TXN0 UMI_TXP UMI_TXN UMI_TXP UMI_TXN UMI_TXP UMI_TXN PIE_FH_TXP0_LN PIE_FH_TXN0_LN PIE_FH_TXP_WLN PIE_FH_TXN_WLN PIE_FH_RXP0_LN PIE_FH_RXN0_LN PIE_FH_RXP_WLN PIE_FH_RXN_WLN LK_P_NSSP LK_P_NSSN LK_PU_HLKP LK_PU_HLKN LK_PIE_VGP LK_PIE_VGN LK_PIE_WLNP LK_PIE_WLNN LK_PIE_LNP LK_PIE_LNN +.V_PIE_VR +.V_KV 0p/0V_ RP RP RP RP RP UE HUSON-M R _ PIE_RST#_R E _RST#_R PIE_RST# PILK0 F _RST# Part of PILK/GPO F PI_LK [] 0.u/0V_ UMI_RXP0_ PILK/GPO F E0 PI_LK [] 0.u/0V_ UMI_RXN0_ UMI_TX0P PILK/GPO G E PI_LK [] 0.u/0V_ UMI_RXP_ UMI_TX0N PILK/M_OS/GPO F 0.u/0V_ UMI_RXN_ UMI_TXP UMI_RXP_ UMI_TXN PIRST# TP 0.u/0V_ 0.u/0V_ UMI_RXN_ UMI_TXP 0.u/0V_ UMI_RXP_ UMI_TXN 0 SYS_OM_REQ [] 0.u/0V_ UMI_RXN_ UMI_TXP 0/GPIO0 J UMI_TXN /GPIO L RT ircuitry(rt) /GPIO G UMI_RX0P /GPIO L UMI_RX0N /GPIO H R00 *SHORT_ UMI_RXP /GPIO J +VPU UMI_RXN /GPIO L Y UMI_RXP /GPIO N Y UMI_RXN /GPIO N Y UMI_RXP /GPIO J Y +V_RT +VRT_ UMI_RXN 0/GPIO0 L PIE_LRP /GPIO L R 0/F_ F T--F_00M R K/F_ PIE_LRN PIE_LRP /GPIO M F PIE_LRN /GPIO J 0MIL R 0/F_ +VRT 0.u/0V_ PIE_FH_TXP0_ /GPIO K V 0 0.u/0V_ PIE_FH_TXN0_ GPP_TX0P /GPIO N V 0 0.u/0V_ PIE_FH_TXP_ GPP_TX0N /GPIO G W0 0MIL 00 0.u/0V_ PIE_FH_TXN_ GPP_TXP /GPIO M W u/0v_ 0MIL GPP_TXN /GPIO J0 GPP_TXP /GPIO L GPP_TXN 0/GPIO0 K GPP_TXP /GPIO N R GPP_TXN /GPIO G /GPIO E PI_ [] K/F_ GPP_RX0P /GPIO PI_ [] PI_ [] +V_S GPP_RX0N /GPIO E W GPP_RXP /GPIO F PI_ [] V PI_ [].K/J_ R VRT_.K/J_ R0 VRT_ GPP_RXN /GPIO H V GPP_RXP /GPIO H PE_PWRG [] W HUSON_MEMHOT# +V Q GPP_RXN /GPIO R *.K_ W MMT0--F_00M GPP_RXP 0/GPIO0 W R 0MIL GPP_RXN /GPIO E.K/F_ E0# N E# J R K/F_ LK_LRN E# N0 F Net GPIO I/O Power Well OS LK_LRN E# FRME# G0 EVSEL# K G0 PE_PWRG GPIO GPU_PWRG I +.V "0->" R PIE_RLKP IRY# L0 G 0K/F_ PIE_RLKN TRY# F0 INT_LK_P_NSSP PR E0 R PE_GPIO0 GPIO GPU_RST# O +.V "0->" N INT_LK_P_NSSN ISP_LKP STOP# H T RT_ML0 *shortx ISP_LKN PERR# M SERR# H H PE_GPIO GPIO GPU_PWREN O +.V "0->" ISP_LKP REQ0# G H ISP_LKN REQ#/GPIO0 G INT_LK_PU_HLKP REQ#/LK_REQ#/GPIO F T TP INT_LK_PU_HLKN PU_LKP REQ#/LK_REQ#/GPIO M T *shortx PU_LKN GNT0# INT_LK_PIE_VGP GNT#/GPO J0 INT_LK_PIE_VGN SLT_GFX_LKP GNT#/S_LE/GPO K TP_INT_FH [] *shortx SLT_GFX_LKN GNT#/LK_REQ#/GPIO K LKRUN# LKRUN# [,] H GPP_LK0P LOK# H H GPP_LK0N INT_LK_PIE_WLNP INTE#/GPIO F J INT_LK_PIE_WLNN GPP_LKP INTF#/GPIO E K *shortx GPP_LKN INTG#/GPIO INTH#/GPIO F GPP_LKP F GPP_LKN LK_PI_E [,] R _ PLK_EUG [0] INT_LK_PIE_LNP E INT_LK_PIE_LNN GPP_LKP E LP_LK0_R LP_LK0 [,] *shortx GPP_LKN LPLK0 R _ LP_LK_R R _ For EMI LPLK LP_LK [,] M GPP_LKP L0 LP_L0 [0,,] M GPP_LKN L LP_L [0,,] LP_L [0,,] LP_LK *p/0v_ L M GPP_LKP L LP_L [0,,] M LP_LFRME# [0,,] LK_PI_E *p/0v_ GPP_LKN LFRME# LRQ#0 LRQ0# TP N LRQ# GPP_LKP LRQ#/LK_REQ#/GPIO E TP N GPP_LKN SERIRQ/GPIO E IRQ_SERIRQ [,] PI EXPRESS INTERFES LOK GENERTOR PI LKS PI INTERFE LP +VT 0p/0V_ TP M_X R R N R J GPP_LKP GPP_LKN GPP_LKP GPP_LKN M_M_M_OS M_X PU M_TIVE# PROHOT# PU_PG LT_STP# PU_RST# K_X K_X G E E G F G G PU_RST# K_X K_X *0.u/0V_ MTIVE_L [] H_PROHOT# [,] PU_PWRG_R [,] PU_RST# [,] K_X R 0M_ K_X Y.KHZ USE GROUN GUR FOR K_X N K_X p/0v_ p/0v_ Y MHz_XTL 0p/0V_ R M/F_ M_X M_X OLTON-M S PLUS S_ORE_EN RTLK INTRUER_LERT# VT_RT_G H F F E S_ORE_EN INTRUER_LERT# 0MIL R TP R _ *M/F_ 0.u/0V_ +V_RT RT_LK [] S_ORE_EN is necessary to connect enable pin of +VPU/+VPU regulator for S+ mode implementation INTRUER_LERT# Left not connected (FH has 0-kohm internal pull-up to VT). G +V_S *SHORT_P [,0,,] PLTRST# R0 _ 0p/0V RST# U *TSH0FU *0.u/0V RST#_R R *short_ Quanta omputer Inc. PROJET : Size ocument Number Rev FH /(PI/PI/LK) Wednesday, pril, 0 ate: Sheet of 0

U ST0 H ST SS [] [] [] [] [] [] [] [] ST_TXP0_ ST_TXN0_ ST_RXN0_R ST_RXP0_R ST_TXP ST_TXN ST_RXN ST_RXP PLE ST_L RES VERY LOSE TO LL OF HUSON-M/M K M L0 N0 N L H0 J0 J H M K H J N L L N J H N L K M L N L L H H ST_TX0P ST_TX0N ST_RX0N ST_RX0P ST_TXP ST_TXN ST_RXN ST_RXP ST_TXP ST_TXN ST_RXN ST_RXP ST_TXP ST_TXN ST_RXN ST_RXP ST_TXP ST_TXN ST_RXN ST_RXP ST_TXP ST_TXN ST_RXN ST_RXP N N N N N0 N HUSON-M SERIL T S R SPI ROM GE LN Part of S_LK/SLK_/GPIO S_M/SLO_/GPIO S_#/GPIO S_WP/GPIO S_T0/STI_/GPIO S_T/STO_/GPIO S_T/GPIO S_T/GPIO0 GE_OL GE_RS GE_MK GE_MIO GE_RXLK GE_RX GE_RX GE_RX GE_RX0 GE_RXTL/RXV GE_RXERR GE_TXLK GE_TX GE_TX GE_TX GE_TX0 GE_TXTL/TXEN GE_PHY_P GE_PHY_RST# GE_PHY_INTR SPI_I/GPIO SPI_O/GPIO SPI_LK/GPIO SPI_S#/GPIO ROM_RST#/SPI_WP#/GPIO VG_RE VG_GREEN VG_LUE L N J H K M H J W0 H F E G F G E W V V V T V L0 L M GE_PHY_INTR FH_SPI_SI FH_SPI_SO FH_SPI_LK FH_SPI_S0# FH_SPI_WP R 0K_ +V_S [] [] [] [] SPI_S SPI_SK SPI_SO SPI_SI FH_SPI_S0# FH_SPI_LK FH_SPI_SO FH_SPI_SI R R0 R R0 *short_ *short_ *short_ *short_ R0 _ +V_S R0 0K_ +V_S R 0K_ FH_SPI_SI_R *p/0v_ U E# SK SI SO WP# V HOL# WQIG(SOI) +V_S 0.u/0V_ R 0K_ SPI_HOL# [] +.V_V_ST R /F_ R K/F_ ST_LRP ST_LRN J J F F N N ST_LRP ST_LRN VG VG_HSYN/GPO VG_VSYN/GPO VG S/GPO0 VG SL/GPO VG RSET M N0 M N K FH_SPI_WP +V R0 *0K_ ST_LE# ST_T#/GPIO UX_VG_H_P UX_VG_H_N V V +V Initial IOS set internal pull down R R R R R R H@K_ K_ EV@K_ @K_ ELP@K_ K_ Integrated lock Mode: ST_X, ST_X leave unconnected. OR_I OR_I OR_I OR_I OR_I OR_I +V R R R R R R R *0K_ [] Remove Zero Power O funciton OR_I *NH@0K_ *0K_ UM@0K_ N@0K_ ELP@0K_ *0K_ OR_I FH_PROHOT#_ OR_I OR_I OR_I OR_I OR_I OR_I TEMPIN R 0K_ F G H M J K N L K K K M ST_X ST_X FNOUT0/GPIO FNOUT/GPIO FNOUT/GPIO FNIN0/GPIO FNIN/GPIO FNIN/GPIO TEMPIN0/GPIO TEMPIN/GPIO TEMPIN/GPIO TEMPIN/TLERT#/GPIO HW MONITOR VG MINLINK UXL ML_VG_L0P ML_VG_L0N ML_VG_LP ML_VG_LN ML_VG_LP ML_VG_LN ML_VG_LP ML_VG_LN ML_VG_HP/GPIO 0/GPIO /GPIO /STI_/GPIO /STO_/GPIO /SLO_/GPIO /SLK_/GPIO0 /GE_STT/GPIO /GE_LE/GPIO N N N N N U T T T T R R0 P P N M L N P P M M G H0 G L 0 TP0 R0 R R R R0 R0 R0 R 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ [] [,] OR_I OR_I OLTON-M +V_S R0 R0 R0 EV@K_ *K_ ELP@0K_ OR_I OR_I OR_I R R R *EV@0K_ 0K_ HYN@0K_ OR I SETTING oard I US harge No US harge I H L I I I I I Onorad RM SETTING Reserved VG SKU UM SKU No VRM G VRM G Non Touch Panel Touch Panel H H L H L H L H L <= P by cable I I I 0 0 0 0 0 0 0 HYNIX RL 00 G HTGFR-P ELPI RL G EJEG-J-F ELPI RL 00 G EJEFG-GNL-F isable Onorad RM Quanta omputer Inc. PROJET : Size ocument Number Rev FH /(ST/VG//SPI) Wednesday, pril, 0 ate: Sheet of 0

+V +V_S +FH_VPL SSUS_S +FH_VPL SUS_S +.V_UL L H0KF-T0_ L H0KF-T0_ L H0KF-T0_ +V_S +.V_UL L0 H0KF-T0_ +V 0.u/.V_ 0.u/.V_.u/.V_ R TRE WITH >=mil TRE WITH >=mil 0.u/0V_ L H0KF-T0_ *0.u/0V_ 0 *0.u/0V_ +FH_V SSUS_S *short_ +V_V_US 0u/.V_ L H0KF-T0_ L H0KF-T0_ R R0 *short_ *short_ PLE LL THE EOUPLING PS ON THIS SHEET LOSE TO S S POSSILE. +.V_FH_R VQ--.V I/O power U 0m 00m TRE WITH >=00mil HUSON-M Part of VIO PIGP_ VR T VIO PIGP_ VR T 0 E 0.u/0V_ 0.u/0V_ VIO PIGP_ VR T0 u/.v_ 0.u/0V_ 0 0 VIO PIGP_ VR U G 0.u/0V_ 0.u/0V_ VIO PIGP_ VR U VIO PIGP_ VR V VIO PIGP_ VR V VIO PIGP_ VR V0 VIO PIGP_ VR Y VIO PIGP_0 m 0m +VPL_.V H TRE WITH >=0mil VPL SYS VN LK_ H 0m V VPL VN LK_ J m U VPL ML VN LK_ K 00m T VN VN LK_ L +FH_VPL SSUS_S m L VPL SSUS_S VN LK_ M +FH_VPL SUS_S m 0.u/0V_ +FH_VPL PIE VPL US_S VN LK_ N 0.u/0V_ m H +FH_VPL ST VPL PIE VN LK_ N m G VPL ST VN LK_ P +.V R0 *0_ 0m TRE WITH >=00mil *.u/.v_ LO_P M LO_P VN PIE_ VN PIE_ Y m V VPL VN PIE_ E m VN PIE_ Y VN ML_ VN PIE_ *0.u/0V_ 0.u/0V_ V VN ML_ VN PIE_ V VN ML_ VN PIE_ F V VN ML_ VN PIE_ G L H0KF-T0_ TRE WITH >=0mil.u/.V_ 0 0u/.V_ u/0v_ u/0v_ 0.u/0V_ EMI +FH_VN US_S.u/.V_ 0.u/0V_ TRE WITH >=0mil 0 0.u/0V_ 0m +FH_VR US_S TRE WITH >=mil m 0 0.u/0V_ 0.u/0V_ 0u/.V_ +FH_VN SSUS_S +FH_VR SSUS_S u/0v_ 0m m m 0 0 G H J K K M M0 N N0 M N M U U T T P M N P P N N P M VIO GE_S VR GE_S_ VR GE_S_ VIO_GE_S_ VIO_GE_S_ VN US_S_ VN US_S_ VN US_S_ VN US_S_ VN US_S_ VN US_S_ VN US_S_ VN US_S_ VN US_S_ VN US_S_0 VN US_S_ VN US_S_ VN US_S_ VN US_S_ VR US_S_ VR US_S_ VN SSUS_S_ VN SSUS_S_ VN SSUS_S_ VN SSUS_S_ VN SSUS_S_ VR SSUS_S_ VR SSUS_S_ VR SSUS_S_ VR SSUS_S_ PI/GPIO I/O MIN GE LINK PI LN EXPRESS LKGEN I/O SERIL T US ORE S0.V_S I/O US SS VN ST_ VN ST_ VN ST_ VN ST_ VN ST_ VN ST_ VN ST_ VN ST_ VN ST_ VN ST_0 VIO S_ VIO S_ VIO S_ VIO S_ VIO S_ VIO S_ VIO S_ VIO S_ VXL S VR S_ VR S_ VPL SYS_S VN HWM_S VIO_Z_S Y0 0 0 m TRE WITH >=0mil *0.u/0V_ 0.u/0V_ u/0v_ +.V_V_FH_R +.V_KV u/0v_ +.V_PIE_VR u/0v_ +.V_V_ST u/0v_ u/0v_ u/0v_ 0 *u/0v_ u/0v_ +VIO S m TRE WITH >=0mil S_.--.v standby power N R +V_S L *SHORT_ M V 0 0 V u/0v_ u/0v_.u/.v_ Y Y W +VXL_.V m TRE WITH >=mil G +VR_.V m N0 TRE WITH >=mil M0 R +.V_UL *0.u/0V_.u/.V_ 0m *SHORT_ J m u/0v_ u/0v_ M S_.V--.V standby power m Trace width >=0 mil +VPL_.V V-- S/ ORE power R *short_ 0u/.V_ S plus mode +.V_UL +.V KV_.V-- Internal clock Generator I/O power L +.V H0KF-T_. u/.v_ heck +.V_KV leakage issues PIE_VR--PIE I/O power L H0KF-T_. u/.v_ V_ST--ST phy power L H0KF-T_. u/.v_ L H0KF-T0_ +.V +.V L H0KF-T0_ +V_S E E E E F F F F F F F F F F G G G H H H J J J0 J J J K K K K L L L L L L M M M M N N N N N P P P0 P P P R R R R T T T U 0 0 0 0 0 0 HUSON-M Part of N N_HWM PL_ N_ K XL NQ_ IO_ H PL_SYS EFUSE OLTON-M GROUN 0 0 0 00 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 0 T T U U U U0 U U0 U V V V W W W W Y Y Y 0 E E E E F F F F G0 G H H H H H H H H J J J K K L M M N N N N T L K N R 0 u/0v_ 0.u/0V_ 0.u/0V_ 0u/.V_ 0 u/0v_ 0.u/0V_ 0.u/0V_ POWER 0.u/0V_.u/.V_ OLTON-M +VN_.V_HWM +V_S L H0KF-T0_ +V +VPL_.V 0.u/0V_.u/.V_ L H0KF-T0.u/.V_ 0.u/0V_ +VIO_Z *0.u/0V_.u/.V_ heck to connect +.V -test R *0_ +V_S R *short_ +V R *0_ +.V Quanta omputer Inc. PROJET : Size ocument Number Rev FH /(POWER) Wednesday, pril, 0 ate: Sheet of 0 0

OVERLP OMMON PS WHERE POSSILE FOR UL-OP RESISTORS. +V +V +V +V_S +V_S +V_S +V_S STRPS PINS R00 0K_ R *0K_ R *0K_ R *0K_ R 0K_ R *0K_ R 0K_ FH PWRG KT [] PI_LK [] PI_LK PI_LK PI_LK +V +V [] PI_LK [,] LP_LK0 [,] LP_LK PI_LK LP_LK0 LP_LK R 0K_ *0.u/0V_ [] E_PWM [] RT_LK E_PWM RT_LK [] VRM_PWRG 0 R00V-0_00M *.u/.v_ U *SNLVGKR R *0_ FH_PWRG [,] R *0K_ R0 0K_ R 0K_ R 0K_ R0 *0K_ R.K_ R *.K_ E_PWM--> SPI ROM:.-KΩ % pull-down LP ROM: Pull-up to.v_s. External pull-up resistor is not required as FH has integrated 0-KΩ pull-up to.v_s. [] PWROK_E R00V-0_00M R 0_ Remove PI_LK function REQUIRE STRPS PULL HIGH -------- -------- PI_LK LLOW PIE Gen EFULT PI_LK -------- PI_LK USE EUG STRP PI_LK non_fusion LOK MOE LP_LK0 E ENLE LP_LK LKGEN ENLE EFULT E_PWM LP ROM RT_LK S PLUS MOE ISLE EFULT PULL LOW -------- FORE PIE Gen -------- IGNORE EUG STRP EFULT FUSION LOK MOE EFULT E ISLE EFULT LKGEN ISLE SPI ROM EFULT S PLUS MOE ENLE EUG STRPS FH HS K INTERNL PU FOR PI_[:] [] PI_ PI_ [] [] [] [] PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PULL HIGH PI_ USE PI PLL PI_ ISLE IL UTORUN PI_ USE F PLL PI_ USE EFULT PIE STRPS PI_ ISLE PI MEM OOT EFULT EFULT EFULT EFULT EFULT R *.K_ R *.K_ R *.K_ R *.K_ R *.K_ PULL LOW YPSS PI PLL ENLE IL UTORUN YPSS F PLL USE EEPROM PIE STRPS ENLE PI MEM OOT Quanta omputer Inc. PROJET : Size ocument Number Rev FH /(STRP & PWRG) Wednesday, pril, 0 ate: Sheet of 0

+V_JM000 +R_VREF +0.V_R_VTT_ PLK_SM PT_SM IMM0_S M 0 M S# M S# M S#0 M M0 M QSN0 M QSP0 M OT0 M OT M S# M RS# M WE# M S#0 M S# M LKN0 M LKP0 M LKN M LKP M KE M KE0 M M M M M M M M M M 0 M M M M M M Q M Q M Q M Q M Q M Q M Q M Q0 M Q0 M Q M Q M Q M Q M Q M M M M M M M M M M M M M M M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSN M QSN M QSN M QSN M QSN M QSN M QSN +R_VREF IMM0_S0 +R_VREF +R_VREF M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q0 M Q M Q M Q M Q M Q M Q[:0] [] M [:0] [] M S#[:0] [] M M[:0] [] M QSP[:0] [] M QSN[:0] [] M OT0 [] M OT [] PLK_SM [,,] PT_SM [,,] +.VSUS [,,,,,,0,] +0.V_R_VTT [,,0,] +V [,,,,,0,,,,,,0,,,,,,,,0,,,,,,,] M RS# [] M S# [] M WE# [] M S#0 [] M S# [] M LKP0 [] M LKN0 [] M LKP [] M LKN [] M KE0 [] M KE [] M RST# [] M EVENT# [] +.VSUS +.VSUS +.VSUS +.VSUS +.VSUS +SMR_VREF +.VSUS +.VSUS +V +.VSUS +0.V_R_VTT Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R SO-IMM 0 Wednesday, pril, 0 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R SO-IMM 0 Wednesday, pril, 0 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R SO-IMM 0 Wednesday, pril, 0 00 00 SM_MEM US RESS SO-IMM0 00 000 SO-IMM 00m m m Place these aps near So-imm R IMM- 0.u/0V_ 0.u/0V_ 000p/0V_ 000p/0V_ 0.u/0V_ 0.u/0V_ R 0K_ R 0K_ R K_ R K_ 000p/0V_ 000p/0V_ 0.u/0V_ 0.u/0V_ R K/F_ R K/F_ R 0K_ R 0K_ 0.u/0V_ 0.u/0V_ u/.v_ u/.v_ R *0_ R *0_ R0 *short_ R0 *short_ 0.u/.V_ 0.u/.V_.u/.V_.u/.V_ 0.u/0V_ 0.u/0V_ R K/F_ R K/F_.u/.V_.u/.V_ 0.u/0V_ 0.u/0V_ P00 R SRM SO-IMM (0P) N R-IMM_H=._ST P00 R SRM SO-IMM (0P) N R-IMM_H=._ST V V V V V V V V V V0 00 V 0 V 0 V V V V V V VSP N N NTEST EVENT# RESET# 0 VREF_Q VREF_ 0 0 0 0 0 0 0 0 0 VTT 0 VTT 0 0 0 0 0.u/0V_ 0 0.u/0V_ 0P/0V_ 0P/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ P00 R SRM SO-IMM (0P) N R-IMM_H=._ST P00 R SRM SO-IMM (0P) N R-IMM_H=._ST 0 0 0/P 0 /# 0 0 0 0 S0# S# K0 0 K0# 0 K 0 K# 0 KE0 KE S# RS# 0 WE# S0 S 0 SL 0 S 00 OT0 OT 0 M0 M M M M M M 0 M QS0 QS QS QS QS QS QS QS QS#0 0 QS# QS# QS# QS# QS# QS# QS# Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q 0 Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q 0 Q Q 0 Q Q0 Q Q Q Q Q Q Q 0 Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q Q 0.u/0V_ 0.u/0V_ u/.v_ u/.v_ u/.v_ u/.v_ R K/F_ R K/F_ R *short_ R *short_ 0.u/0V_ 0.u/0V_.u/.V_.u/.V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_.u/.V_.u/.V_ R K/F_ R K/F_ 0.u/0V_ 0.u/0V_.u/.V_.u/.V_ R *0_ R *0_

M M M M M 0 M M M M M M 0 M M M M M M M M M M 0 M M M M M M 0 M M M M M M S# M S#0 M S# M S# M S#0 M S# M S# M RS# M WE# M LKN0 M LKP0 M KE0 M S#0 M OT0 M RST# M ZQ M ZQ SMR_VREF_Q +SMR_VREF_IMM +SMR_VREF_IMM SMR_VREF_Q M ZQ M M M M M 0 M M M M M M 0 M M M M M +SMR_VREF_IMM SMR_VREF_Q M RST# M S# M S#0 M S# M S# M RS# M WE# M M M M M 0 M M M M M M 0 M M M M M M S# M S#0 M S# +SMR_VREF_IMM SMR_VREF_Q M S# M RS# M WE# M RST# M ZQ M QSP M QSN M QSP M QSN M LKN0 M LKP0 M KE0 M LKN0 M LKP0 M KE0 M S#0 M OT0 M S#0 M OT0 M QSP M QSN M QSP M QSN M QSN0 M QSP0 M QSP M QSN M Q M QSN M QSP M QSP M QSN M Q M Q M Q PT_SM PLK_SM M LKP0 M LKN0 SMR_VREF_Q +SMR_VREF_IMM M S# M S# M S#0 M RS# M WE# M S# M S#0 M KE0 M OT0 M M M M 0 M M M M M M M M M M 0 M M M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q +SMR_VREF_IMM SMR_VREF_Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q0 M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M [:0] [,] M LKP0 [] M LKN0 [] M KE0 [] M OT0 [] M S#0 [] M S# [,] M RS# [,] M WE# [,] M RST# [,] PLK_SM [,,] PT_SM [,,] M M0 [,] M M [,] M M [,] M M [,] M S#[:0] [,] M QSP[:0] [,] M QSN[:0] [,] M Q[:0] [,] +SMR_VREF_IMM [] SMR_VREF_Q [] M M [,] M M [,] M M [,] M M [,] +.VSUS +.VSUS +.VSUS +.VSUS +V +SMR_VREF +SMR_VREF +.VSUS +.VSUS +.VSUS +.VSUS +.VSUS +0.V_R_VTT +.VSUS +0.V_R_VTT +0.V_R_VTT +.VSUS Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R MEMORY OWNx - Wednesday, pril, 0 0 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R MEMORY OWNx - Wednesday, pril, 0 0 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R MEMORY OWNx - Wednesday, pril, 0 0 SO-IMM SP ddress is 0X SO-IMM TS ddress is 0X Place these aps near Memory own <R> Should be Ohms +-% Should be Ohms +-% Should be Ohms +-% Should be Ohms +-% address: WP = : WRITE ISLE YTE0_0- YTE_- YTE_- YTE_- YTE_- YTE_0- YTE_- YTE_- 00 KJGST00 KJGST0 R /F_ R /F_ 0.u/0V_ 0.u/0V_ R /F_ R /F_ 0.u/0V_ 0.u/0V_ 00-LL SRM R U RM_R 00-LL SRM R U RM_R WE L RS J S K S L KE K K J K K QSU 0 M N P N P P R R T R 0/P L R QL0 E QL F QL F QL F QL H QL H QL G QL H Q# # #E E # N#J J V# V# VQ# VQ# VQ# VQ# N#L L N#J J VQ#E E ZQ L RESET T QSL F MU ML E Q# Q# Q# Q#E E QSU Q#E E QSL G VQ#F F Q#F F Q#G G VQ#H H VQ#H H Q#G G VREF M #G G V#G G OT K 0 N P V#K K / N #J J V#K K QU QU QU QU QU QU QU QU0 T T M M VREFQ H N#L L V#N N V#N N V#R R V#R R #J J #M M #M M #P P #P P #T T #T T VQ# 0.u/0V_ 0.u/0V_ 0 0.u/0V_ 0 0.u/0V_ 0.u/0V_ 0.u/0V_ R /F_ R /F_ 0 0.u/0V_ 0 0.u/0V_ 0.u/0V_ 0.u/0V_ R /F_ R /F_ 0.u/0V_ 0.u/0V_ R /F_ R /F_ 0 0.u/0V_ 0 0.u/0V_ 0 0.u/0V_ 0 0.u/0V_ 0 0.u/0V_ 0 0.u/0V_ 0 0.u/0V_ 0 0.u/0V_ R0 /F_ R0 /F_ R /F_ R /F_ 0 0.u/0V_ 0 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ R /F_ R /F_ R /F_ R /F_ 0.u/0V_ 0.u/0V_ R /F_ R /F_ R /F_ R /F_ R /F_ R /F_ U *M0-WMNTP U *M0-WMNTP 0 V SL S WP R /F_ R /F_ 00-LL SRM R U RM_R 00-LL SRM R U RM_R WE L RS J S K S L KE K K J K K QSU 0 M N P N P P R R T R 0/P L R QL0 E QL F QL F QL F QL H QL H QL G QL H Q# # #E E # N#J J V# V# VQ# VQ# VQ# VQ# N#L L N#J J VQ#E E ZQ L RESET T QSL F MU ML E Q# Q# Q# Q#E E QSU Q#E E QSL G VQ#F F Q#F F Q#G G VQ#H H VQ#H H Q#G G VREF M #G G V#G G OT K 0 N P V#K K / N #J J V#K K QU QU QU QU QU QU QU QU0 T T M M VREFQ H N#L L V#N N V#N N V#R R V#R R #J J #M M #M M #P P #P P #T T #T T VQ# 0.u/0V_ 0.u/0V_ R /F_ R /F_ R /F_ R /F_ R K/F_ R K/F_ 0.u/0V_ 0.u/0V_ R /F_ R /F_ 00-LL SRM R U RM_R 00-LL SRM R U RM_R WE L RS J S K S L KE K K J K K QSU 0 M N P N P P R R T R 0/P L R QL0 E QL F QL F QL F QL H QL H QL G QL H Q# # #E E # N#J J V# V# VQ# VQ# VQ# VQ# N#L L N#J J VQ#E E ZQ L RESET T QSL F MU ML E Q# Q# Q# Q#E E QSU Q#E E QSL G VQ#F F Q#F F Q#G G VQ#H H VQ#H H Q#G G VREF M #G G V#G G OT K 0 N P V#K K / N #J J V#K K QU QU QU QU QU QU QU QU0 T T M M VREFQ H N#L L V#N N V#N N V#R R V#R R #J J #M M #M M #P P #P P #T T #T T VQ# R /F_ R /F_ 0.u/0V_ 0.u/0V_ R K/F_ R K/F_ R /F_ R /F_ 0.u/0V_ 0.u/0V_ R /F_ R /F_ R /F_ R /F_ R K/F_ R K/F_ R0 *0_ R0 *0_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ R /F_ R /F_ 0.u/0V_ 0.u/0V_ R K/F_ R K/F_ 0.u/0V_ 0.u/0V_ *0.u/0V_ *0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ R0 /F_ R0 /F_ 00-LL SRM R U RM_R 00-LL SRM R U RM_R WE L RS J S K S L KE K K J K K QSU 0 M N P N P P R R T R 0/P L R QL0 E QL F QL F QL F QL H QL H QL G QL H Q# # #E E # N#J J V# V# VQ# VQ# VQ# VQ# N#L L N#J J VQ#E E ZQ L RESET T QSL F MU ML E Q# Q# Q# Q#E E QSU Q#E E QSL G VQ#F F Q#F F Q#G G VQ#H H VQ#H H Q#G G VREF M #G G V#G G OT K 0 N P V#K K / N #J J V#K K QU QU QU QU QU QU QU QU0 T T M M VREFQ H N#L L V#N N V#N N V#R R V#R R #J J #M M #M M #P P #P P #T T #T T VQ# R0 /F_ R0 /F_ R /F_ R /F_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ R /F_ R /F_ 0 0.u/0V_ 0 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ R /F_ R /F_ R0 /F_ R0 /F_ 0 0.u/0V_ 0 0.u/0V_ R /F_ R /F_ R /F_ R /F_ R /F_ R /F_ 0.u/0V_ 0.u/0V_ R /F_ R /F_ 0.u/0V_ 0.u/0V_ R *0_ R *0_ 0 0.u/0V_ 0 0.u/0V_ 0.u/0V_ 0.u/0V_

M ZQ M QSP M QSN M RST# M QSN0 M QSP0 M QSP M QSN M ZQ M M M M M 0 M M M M M M 0 M M M M M M S# M RS# M WE# M QSP M QSN M S# M S#0 M S# M S# M S#0 M S# M QSP M QSN M S# M RS# M WE# M M M M M 0 M M M M M M 0 M M M M M M S# M S#0 M S# +SMR_VREF_IMM SMR_VREF_Q +SMR_VREF_IMM M LKN M LKP M KE M S# M OT M QSP M QSN SMR_VREF_Q +SMR_VREF_IMM M ZQ M QSP M QSN M RST# M M M M M 0 M M M M M M 0 M M M M M M RST# M ZQ SMR_VREF_Q M S# M S#0 M S# M S# M RS# M WE# +SMR_VREF_IMM SMR_VREF_Q M M M M M 0 M M M M M M 0 M M M M M M QSN M QSP M LKN M LKP M KE M OT M S# M LKN M LKP M KE M OT M S# M LKP M LKN M S# M KE M OT SMR_VREF_Q +SMR_VREF_IMM M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M M0 [,] M M [,] M M [,] M S#[:0] [,] M M [,] M [:0] [,] M LKP [] M LKN [] M KE [] M OT [] M S# [] M S# [,] M RS# [,] M WE# [,] M RST# [,] M QSP[:0] [,] M QSN[:0] [,] M Q[:0] [,] +SMR_VREF_IMM [] SMR_VREF_Q [] M M [,] M M [,] M M [,] M M [,] +.VSUS +.VSUS +.VSUS +.VSUS +.VSUS +.VSUS +0.V_R_VTT +0.V_R_VTT +.VSUS +.VSUS +.VSUS +0.V_R_VTT Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R MEMORY OWNx - Wednesday, pril, 0 0 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R MEMORY OWNx - Wednesday, pril, 0 0 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R MEMORY OWNx - Wednesday, pril, 0 0 <R> Should be Ohms +-% Should be Ohms +-% YTE_- YTE_0- YTE0_0- YTE_- YTE_- YTE_- SO-IMM SP ddress is 0X SO-IMM TS ddress is 0X Should be Ohms +-% YTE_- YTE_- Should be Ohms +-% Place these aps near Memory own 00 KJGST00 KJGST0 0 0.u/0V_ 0 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0 0.u/0V_ 0 0.u/0V_ 00-LL SRM R U RM_R 00-LL SRM R U RM_R WE L RS J S K S L KE K K J K K QSU 0 M N P N P P R R T R 0/P L R QL0 E QL F QL F QL F QL H QL H QL G QL H Q# # #E E # N#J J V# V# VQ# VQ# VQ# VQ# N#L L N#J J VQ#E E ZQ L RESET T QSL F MU ML E Q# Q# Q# Q#E E QSU Q#E E QSL G VQ#F F Q#F F Q#G G VQ#H H VQ#H H Q#G G VREF M #G G V#G G OT K 0 N P V#K K / N #J J V#K K QU QU QU QU QU QU QU QU0 T T M M VREFQ H N#L L V#N N V#N N V#R R V#R R #J J #M M #M M #P P #P P #T T #T T VQ# 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ R0 /F_ R0 /F_ 00-LL SRM R U RM_R 00-LL SRM R U RM_R WE L RS J S K S L KE K K J K K QSU 0 M N P N P P R R T R 0/P L R QL0 E QL F QL F QL F QL H QL H QL G QL H Q# # #E E # N#J J V# V# VQ# VQ# VQ# VQ# N#L L N#J J VQ#E E ZQ L RESET T QSL F MU ML E Q# Q# Q# Q#E E QSU Q#E E QSL G VQ#F F Q#F F Q#G G VQ#H H VQ#H H Q#G G VREF M #G G V#G G OT K 0 N P V#K K / N #J J V#K K QU QU QU QU QU QU QU QU0 T T M M VREFQ H N#L L V#N N V#N N V#R R V#R R #J J #M M #M M #P P #P P #T T #T T VQ# 00-LL SRM R U0 RM_R 00-LL SRM R U0 RM_R WE L RS J S K S L KE K K J K K QSU 0 M N P N P P R R T R 0/P L R QL0 E QL F QL F QL F QL H QL H QL G QL H Q# # #E E # N#J J V# V# VQ# VQ# VQ# VQ# N#L L N#J J VQ#E E ZQ L RESET T QSL F MU ML E Q# Q# Q# Q#E E QSU Q#E E QSL G VQ#F F Q#F F Q#G G VQ#H H VQ#H H Q#G G VREF M #G G V#G G OT K 0 N P V#K K / N #J J V#K K QU QU QU QU QU QU QU QU0 T T M M VREFQ H N#L L V#N N V#N N V#R R V#R R #J J #M M #M M #P P #P P #T T #T T VQ# 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ R0 /F_ R0 /F_ 0.u/0V_ 0.u/0V_ R /F_ R /F_ 0 0.u/0V_ 0 0.u/0V_ 0 0.u/0V_ 0 0.u/0V_ R /F_ R /F_ R0 /F_ R0 /F_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0 0.u/0V_ 0 0.u/0V_ 0.u/0V_ 0.u/0V_ R /F_ R /F_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0 0.u/0V_ 0 0.u/0V_ R /F_ R /F_ R /F_ R /F_ 0 0.u/0V_ 0 0.u/0V_ 00-LL SRM R U RM_R 00-LL SRM R U RM_R WE L RS J S K S L KE K K J K K QSU 0 M N P N P P R R T R 0/P L R QL0 E QL F QL F QL F QL H QL H QL G QL H Q# # #E E # N#J J V# V# VQ# VQ# VQ# VQ# N#L L N#J J VQ#E E ZQ L RESET T QSL F MU ML E Q# Q# Q# Q#E E QSU Q#E E QSL G VQ#F F Q#F F Q#G G VQ#H H VQ#H H Q#G G VREF M #G G V#G G OT K 0 N P V#K K / N #J J V#K K QU QU QU QU QU QU QU QU0 T T M M VREFQ H N#L L V#N N V#N N V#R R V#R R #J J #M M #M M #P P #P P #T T #T T VQ# 0 0.u/0V_ 0 0.u/0V_ 0.u/0V_ 0.u/0V_ R /F_ R /F_ 0.u/0V_ 0.u/0V_ 0 0.u/0V_ 0 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_

U PRT 0F [] [] [] [] PEG_TXP0 PEG_TXN0 PEG_TXP PEG_TXN Y Y W PIE_RX0P PIE_RX0N PIE_RXP PIE_RXN PIE_TX0P PIE_TX0N PIE_TXP PIE_TXN Y Y W W PEG_RXP0_ PEG_RXN0_ PEG_RXP_ PEG_RXN_ EV@0.u/0V_ EV@0.u/0V_ EV@0.u/0V_ EV@0.u/0V_ PEG_RXP0 [] PEG_RXN0 [] PEG_RXP [] PEG_RXN [] Thames(Pro,XT) and Mars Power-on sequence PX.0(no O) [] [] PEG_TXP PEG_TXN W V PIE_RXP PIE_RXN PIE_TXP PIE_TXN U U PEG_RXP_ PEG_RXN_ EV@0.u/0V_ EV@0.u/0V_ PEG_RXP [] PEG_RXN [] GPU_PWREN [] [] [] [] PEG_TXP PEG_TXN PEG_TXP PEG_TXN V U U T PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN U0 U T T PEG_RXP_ PEG_RXN_ PEG_RXP_ PEG_RXN_ 0 EV@0.u/0V_ EV@0.u/0V_ EV@0.u/0V_ EV@0.u/0V_ PEG_RXP [] PEG_RXN [] PEG_RXP [] PEG_RXN [] V/VI/.V_IO MVQ/+PIE_V VR 0ms max [] [] PEG_TXP PEG_TXN T R PIE_RXP PIE_RXN PIE_TXP PIE_TXN T0 T PEG_RXP_ PEG_RXN_ EV@0.u/0V_ EV@0.u/0V_ PEG_RXP [] PEG_RXN [] PE_PWRG [] [] [] [] PEG_TXP PEG_TXN PEG_TXP PEG_TXN R P P N PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN P P P0 P PEG_RXP_ PEG_RXN_ PEG_RXP_ PEG_RXN_ 0 EV@0.u/0V_ EV@0.u/0V_ EV@0.u/0V_ EV@0.u/0V_ PEG_RXP [] PEG_RXN [] PEG_RXP [] PEG_RXN [] PWRGOO PIE_RST# 00ms N M PIE_RXP PIE_RXN PIE_TXP PIE_TXN N N M L L K K J PIE_RXP PIE_RXN PIE_RX0P PIE_RX0N PIE_RXP PIE_RXN PI EXPRESS INTERFE PIE_TXP PIE_TXN PIE_TX0P PIE_TX0N PIE_TXP PIE_TXN N0 N L L L0 L +V_GFX EV@0.u/0V_ PIE lock J H H G PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN K K J J [] GPU_RST_L [] PIE_RST# U EV@TSH0FU(F) PERST#_UF R G F PIE_RXP PIE_RXN PIE_TXP PIE_TXN K0 K *EV@00K_ F E PIE_RXP PIE_RXN PIE_TXP PIE_TXN H H [] LK_PIE_VGP [] LK_PIE_VGN LOK PIE_REFLKP PIE_REFLKN LIRTION PIE_LR_TX Y0 PIE_LR_TX R EV@.K/F_ R EV@K_ TEST_PG H TEST_PG PIE_LR_RX Y PIE_LR_RX R EV@K/F_ +PIE_V_GFX PERST#_UF 0 PERST EV@GPU_M Quanta omputer Inc. PROJET : Size ocument Number Rev Thames_M/ PEG* ate: Wednesday, pril, 0 Sheet of 0

U PRT 0F TP TP GENLK_LK GENLK_VSYN MUTI GFX GENLK_LK GENLK_VSYN TXP_PP TXM_PN U V +V_GFX J K SWPLOK SWPLOK P TX0P_PP TX0M_PN TXP_PP TXM_PN T R U V R R EV@.K_ EV@.K_ GPU_SMLK GPU_SMT +V_GFX R R *EV@0K_ *EV@00_ PIE_REQ_GPU# +V_GFX / add.v GPIO +V_GFX R R *EV@.K_ *EV@.K_ GPU_SMLK GPU_SMT GPU_SL GPU_S R U P W R R U U W P W U R W U T V N V T R0 W0 U0 P0 V T R W U P J H K J VPNTL_MVP_0 VPNTL_MVP_ VPNTL_0 VPNTL_ VPNTL_ VPLK VPT_0 VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_0 VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_0 VPT_ VPT_ VPT_ SMLK SMus SMT SL I S P P P TXP_P0P TXM_P0N TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_P0P TXM_P0N TXP_PP TXM_PN TX0P_PP TX0M_PN TXP_PP TXM_PN TXP_P0P TXM_P0N TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_P0P TXM_P0N T R R0 T V U0 R T T U U V T R U V T R U0 T T R0 U V T R [] GPUT_LK [] GPUT_T Mars Thermal +V_GFX +V_GFX R EV@0K_ U GPUT_LK SLK V GPUT_T S XP LT#_GPIO LERT# XN OVERT# EV@G0PU EV@0.u/0V_ GPU_+ EV@00p/0V_ GPU_- [] GPU_PRSLPVR TP R TP EV@0K_ TP0 R *EV@0_ GPU_GPIO0 GPU_GPIO GPU_GPIO H0 H N GENERL PURPOSE I/O GPIO_0 GPIO_ GPIO_ R N# G N# E [] GPU #,,,] SYS_SHN# Q *EV@MEN00E_00M EV@N00K Q [] [] [] R *EV@0K_ [] [] TP TP TP TP TP PWRNTRL PWRNTRL0 PWRNTRL [] PWRNTRL PWRNTRL GPU # [] PWRNTRL TP TP PIE_REQ_GPU# TP R *EV@0K_ GPU_GPIO GPU_GPIO GPU_GPIO0 GPU_GPIO GPU_GPIO PWRNTRL TP R R R *short_ LT#_GPIO GPIO TF GPU_GPIO GPU_GPIO PIE_REQ_GPU# *short_ *short_ GPU_GENERI H J K J H J K L M M M K G0 N M L J K N G G J K J0 K0 J H H GPIO TT GPIO_ GPIO LON GPIO ROMSO GPIO ROMSI GPIO_0_ROMSK GPIO_ GPIO_ GPIO_ GPIO HP GPIO PWRNTL_0 GPIO_ GPIO THERML_INT GPIO HP GPIO TF GPIO_0_PWRNTL_ GPIO_ GPIO ROMS LKREQ GPIO_ GPIO_0 GENERI GENERI GENERI GENERI GENERIE_HP GENERIF_HP GENERIG_HP N# HSYN VSYN RSET V Q VI I N# N# N# N# N# N# N# N# N# N_TSQ F E E V U 0 F G F R GPU_HSYN_OM [] GPU_VSYN_OM [] EV@/F_ heck need or not +.V_GFX +.V_V nalog Power :.V@m L EV@LMSN_00M EV@0.u/0V_ EV@u/.V_ EV@0u/.V_ +.V_VI igital Power :.V@m L EV@LMSN_00M 00 0 EV@0.u/0V_ EV@u/.V_ EV@0u/.V_ +.V_GFX TP 0 E_ PS_0 M R *short_ PS_0 V_T V_T V_T +.V_GFX Place close to hip R EV@/F_ R EV@/F_ EV@0.u/0V_ +V_GFX PU:isable MLPS P:Enable MLPS R R0 R00 R R R0 R GPU_VREFG EV@0K_ on-die thermal sensor power :.V@m L EV@LMSN_00M 0 EV@0u/.V_ EV@u/.V_ R EV@K_ *EV@.K/F_ *EV@0K_ *EV@0K_ *EV@0K_ *EV@0K_ TP GPU_+ GPU_- +.V_TSV EV@0.u/0V_ *EV@.K_ TESTEN TP GPU_GPIO K H L M N K L M F G K L J J HP VREFG O PX_EN EUG TESTEN JTG_TRST JTG_TI JTG_TK JTG_TMS JTG_TO THERML PLUS MINUS GPIO FO TS_ TSV TS MLPS /UX EV@GPU_M PS_ PS_ PS_ LK T UXP UXN LK T UXP UXN LK_UXP T_UXN LK_UXP T_UXN LK_UXP T_UXN LK_UXP T_UXN VGLK VGT G M N M L M L N0 M0 L0 M0 L M N M K0 K J0 J MLPS PS_ PS_ PS_ [] R_pu R_pd its [:] N.K 000.K K 00.K.K.K.K.K.K K.K.K.K M N 00 0 00 0 0 PS_0 a Ra K.K.K.K.K.K.K.K.K M R_pu R_pd EV@n/V_ P/N S00F SF0 S0F0 SF0 SF SF SF SF0 SF S00F R_pu R_pu R R0 R EV@.K/F_ *EV@0_ *EV@0_ PS_ PS_ a R_pd a R_pd R R0 R *EV@0.u/0V_ EV@0n/.V_ EV@K/F_ EV@.K/F_ EV@.K/F_ MLPS it its [:] a its [:] P/N PS_0 000 0nF 00 HK00 PS_ 000 nf 0 HK00 PS_ 00000 0nF 0 H00K PS_ 00XXX N Quanta omputer Inc. PROJET : Size ocument Number Rev 0_Thames_M/ GPIO_P_RT_I Wednesday, pril, 0 ate: Sheet of 0

+.V_GFX L0 EV@PY00T-0Y-N_. m PLL_PV EV@0u/.V_ EV@u/.V_ EV@0.u/0V_ UI UG PRT 0F PRT 0F LVS ONTROL VRY_L IGON K R0 J R *EV@0K_ *EV@0K_ +PIE_V_GFX L 0m EV@PY00T-0Y-N_. EV@0u/.V_ EV@u/.V_ PLL_V EV@0.u/0V_ M N N PLL_PV PLL_V PLL_P XTLIN V XTLOUT U GPU_XTLIN GPU_XTLOUT R EV@M/F_ EV@.p/0V_ Y EV@MHz_XTL EV@.p/0V_ TXLK_UP_PFP TXLK_UN_PFN TXOUT_U0P_PFP TXOUT_U0N_PFN TXOUT_UP_PFP TXOUT_UN_PFN K L J K H J +.V_GFX L 0m EV@PY00T-0Y-N_. MPLL_PV EV@0u/.V_ EV@u/.V_ EV@0.u/0V_ H H M0 N MPLL_PV MPLL_PV SPLL_PV SPLL_V PLLS/XTL XO_IN W XO_IN W TP TP LVTMP TXOUT_UP_PF0P TXOUT_UN_PF0N TXOUT_UP TXOUT_UN TXLK_LP_PEP TXLK_LN_PEN TXOUT_L0P_PEP TXOUT_L0N_PEN G H F G P R W U +.V_GFX L EV@LMSN_00M m 00 EV@0u/.V_ EV@u/.V_ SPLL_PV 0 EV@0.u/0V_ N0 F0 F SPLL_P N_XTL_PV N_XTL_P LKTEST K0 LKTEST L0 LKTEST LKTEST TXOUT_LP_PEP TXOUT_LN_PEN TXOUT_LP_PE0P TXOUT_LN_PE0N TXOUT_LP TXOUT_LN R U P R N P *EV@0.u/0V_ *EV@0.u/0V_ EV@GPU_M +PIE_V_GFX L EV@PY00T-0Y-N_. 00m SPLL_V EV@GPU_M R *EV@./F_ R *EV@./F_ EV@0u/.V_ EV@u/.V_ EV@0.u/0V_ PLL_PV R R *EV@0_ *EV@0_ Quanta omputer Inc. PROJET : Size ocument Number Rev Thames_M/ XTL_LVS ate: Wednesday, pril, 0 Sheet of 0