ΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2017 ΔΙΑΛΕΞΗ 17: Κυκλώματα & Συστήματα Μνήμης ΧΑΡΗΣ ΘΕΟΧΑΡΙΔΗΣ (ttheocharides@ucy.ac.cy) (ack: Prof. Mary Jane Irwin and Vijay Narayanan) [Προσαρμογή από Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al. ]
Semiconductor Memories RWM NVRWM ROM Random Access Non-Random Access EPROM Maskprogrammed SRAM (cache, register file) FIFO/LIFO E 2 PROM DRAM Shift Register FLASH Electricallyprogrammed (PROM) CAM ΗΜΥ307 Δ17: Memory and Memory Circuitry.2 Θεοχαρίδης, ΗΜΥ, 2017
Growth in DRAM Chip Capacity 1000000 256,000 100000 64,000 Kbit capacity 10000 1000 256 1,000 4,000 16,000 100 64 10 1980 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 Year of introduction ΗΜΥ307 Δ17: Memory and Memory Circuitry.3 Θεοχαρίδης, ΗΜΥ, 2017
1D Memory Architecture m bits m bits S 0 Word 0 S 0 Word 0 S 1 Word 1 S 1 Word 1 S 2 S 3 Word 2 Storage Cell A 0 A 1 S 2 S 3 Word 2 Storage Cell A k-1 S n-2 Word n-2 S n-2 Word n-2 S n-1 Word n-1 S n-1 Word n-1 Input/Output n words n select signals Input/Output Decoder reduces # of inputs k = log 2 n ΗΜΥ307 Δ17: Memory and Memory Circuitry.4 Θεοχαρίδης, ΗΜΥ, 2017
2D Memory Architecture 2 k-j bit line word line A j A j+1 A k-1 storage (RAM) cell A 0 A 1 A j-1 Column Decoder Sense Amplifiers Read/Write Circuits m2 j selects appropriate word from memory row amplifies bit line swing Input/Output (m bits) ΗΜΥ307 Δ17: Memory and Memory Circuitry.5 Θεοχαρίδης, ΗΜΥ, 2017
3D Memory Architecture Row Address Column Address Block Address Control Circuitry Block Selector Global Amplifier/Driver I/O Global Data Bus Advantages: 1. Shorter wires within blocks 2. Block address activates only 1 block => power savings ΗΜΥ307 Δ17: Memory and Memory Circuitry.6 Θεοχαρίδης, ΗΜΥ, 2017
Read Only Memories (ROMs) ΗΜΥ307 Δ17: Memory and Memory Circuitry.7 Θεοχαρίδης, ΗΜΥ, 2017
Precharged MOS NOR ROM V dd precharge WL(0) WL(1) GND WL(2) GND WL(3) BL(0) BL(1) BL(2) BL(3) ΗΜΥ307 Δ17: Memory and Memory Circuitry.8 Θεοχαρίδης, ΗΜΥ, 2017
Precharged MOS NOR ROM V dd 0 1 precharge WL(0) 0 1 WL(1) GND WL(2) WL(3) GND BL(0) BL(1) BL(2) BL(3) 1 0 1 1 1 1 1 0 ΗΜΥ307 Δ17: Memory and Memory Circuitry.9 Θεοχαρίδης, ΗΜΥ, 2017
MOS NOR ROM Layout Metal1 on top of diffusion Basic cell 10l x 7 l WL(0) WL(1) WL(2) WL(3) GND (diffusion) Metal1 Polysilicon GND (diffusion) BL(0) BL(1) BL(2) BL(3) Only 1 layer (contact mask) is used to program memory array, so programming of the ROM can be delayed to one of the last process steps. ΗΜΥ307 Δ17: Memory and Memory Circuitry.10 Θεοχαρίδης, ΗΜΥ, 2017
Transient Model for NOR ROM WL precharge poly r word metal1 C bit BL c word Word line parasitics Resistance/cell: 35W Wire capacitance/cell: 0.65 ff Gate capacitance/cell: 5.10 ff Bit line parasitics Resistance/cell: 0.15W Wire capacitance/cell: 0.83 ff Drain capacitance/cell: 2.60 ff ΗΜΥ307 Δ17: Memory and Memory Circuitry.11 Θεοχαρίδης, ΗΜΥ, 2017
Propagation Delay of NOR ROM l Word line delay Delay of a distributed rc-line containing M cells t word = 0.38(r word x c word ) M 2 = 20 nsec for M = 512 l Bit line delay Assuming min size pull-down and 3*min size pull-up with reduced swing bit lines (5V to 2.5V) C bit = 1.7 pf and I avhl = 0.36 ma so t HL = t LH = 5.9 nsec ΗΜΥ307 Δ17: Memory and Memory Circuitry.12 Θεοχαρίδης, ΗΜΥ, 2017
Read-Write Memories (RAMs) l Static SRAM data is stored as long as supply is applied large cells (6 fets/cell) so fewer bits/chip fast so used where speed is important (e.g., caches) differential outputs (output BL and!bl) use sense amps for performance compatible with CMOS technology l Dynamic DRAM periodic refresh required small cells (1 to 3 fets/cell) so more bits/chip slower so used for main memories single ended output (output BL only) need sense amps for correct operation not typically compatible with CMOS technology ΗΜΥ307 Δ17: Memory and Memory Circuitry.13 Θεοχαρίδης, ΗΜΥ, 2017
Memory Timing Definitions Read Cycle Read Read Access Read Access Write Cycle Write Write Setup Write Hold Data Data Valid ΗΜΥ307 Δ17: Memory and Memory Circuitry.14 Θεοχαρίδης, ΗΜΥ, 2017
4x4 SRAM Memory 2 bit words read precharge bit line precharge enable!bl BL WL[0] A 1 WL[1] A 2 WL[2] WL[3] clocking and control A 0 Column Decoder sense amplifiers BL[i] BL[I+1] write circuitry ΗΜΥ307 Δ17: Memory and Memory Circuitry.15 Θεοχαρίδης, ΗΜΥ, 2017
2D Memory Configuration Sense Amps Sense Amps ΗΜΥ307 Δ17: Memory and Memory Circuitry.16 Θεοχαρίδης, ΗΜΥ, 2017
Decreasing Word Line Delay q Drive the word line from both sides WL driver polysilicon word line metal word line driver q Use a metal bypass WL polysilicon word line metal bypass ΗΜΥ307 Δ17: Memory and Memory Circuitry.17 Θεοχαρίδης, ΗΜΥ, 2017
Decreasing Bit Line Delay (and Energy) l Reduce the bit line voltage swing need sense amp for each column to sense/restore signal l Isolate memory cells from the bit lines after sensing (to prevent the cells from changing the bit line voltage further) - pulsed word line generation of word line pulses very critical too short - sense amp operation may fail too long - power efficiency degraded (because bit line swing size depends on duration of the word line pulse) use feedback signal from bit lines l Isolate sense amps from bit lines after sensing (to prevent bit lines from having large voltage swings) - bit line isolation ΗΜΥ307 Δ17: Memory and Memory Circuitry.18 Θεοχαρίδης, ΗΜΥ, 2017
Pulsed Word Line Feedback Signal Read Word line Dummy bit lines Bit lines Complete 10% populated l Dummy column height set to 10% of a regular column and its cells are tied to a fixed value capacitance is only 10% of a regular column ΗΜΥ307 Δ17: Memory and Memory Circuitry.19 Θεοχαρίδης, ΗΜΥ, 2017
Pulsed Word Line Timing Read Complete Word line Bit line Dummy bit line DV = 0.1V dd DV = V dd l Dummy bit lines have reached full swing and trigger pulse shut off when regular bit lines reach 10% swing ΗΜΥ307 Δ17: Memory and Memory Circuitry.20 Θεοχαρίδης, ΗΜΥ, 2017
Bit Line Isolation bit lines DV = 0.1V dd isolate sense Read sense amplifier DV = V dd sense amplifier outputs ΗΜΥ307 Δ17: Memory and Memory Circuitry.21 Θεοχαρίδης, ΗΜΥ, 2017
6-transistor SRAM Cell WL M5!Q M2 M4 Q M6 M1 M3!BL BL ΗΜΥ307 Δ17: Memory and Memory Circuitry.22 Θεοχαρίδης, ΗΜΥ, 2017
Review: 4x4 SRAM Memory 2 bit words read precharge bit line precharge enable!bl BL WL[0] A 1 WL[1] A 2 WL[2] WL[3] clocking and control A 0 Column Decoder sense amplifiers BL[i] BL[I+1] write circuitry ΗΜΥ307 Δ17: Memory and Memory Circuitry.23 Θεοχαρίδης, ΗΜΥ, 2017
6-transistor SRAM Cell WL M5!Q M2 M4 Q M6 M1 M3!BL BL ΗΜΥ307 Δ17: Memory and Memory Circuitry.24 Θεοχαρίδης, ΗΜΥ, 2017
SRAM Cell Analysis (Read) WL=1 M5!Q=0 M1 M4 Q=1 M6 C bit C bit!bl=1 BL=1 Read-disturb (read-upset): must carefully limit the allowed voltage rise on!q to a value that prevents the read-upset condition from occurring while simultaneously maintaining acceptable circuit speed and area constraints ΗΜΥ307 Δ17: Memory and Memory Circuitry.25 Θεοχαρίδης, ΗΜΥ, 2017
SRAM Cell Analysis (Read) WL=1 M5!Q=0 M1 M4 Q=1 M6 C bit C bit!bl=1 BL=1 Cell Ratio (CR) = (W M1 /L M1 )/(W M5 /L M5 ) V!Q = [(V dd - V Tn )(1 + CR ±Ö(CR(1 + CR))]/(1 + CR) ΗΜΥ307 Δ17: Memory and Memory Circuitry.26 Θεοχαρίδης, ΗΜΥ, 2017
Read Voltages Ratios 1.2 V dd = 2.5V V Tn = 0.5V 1 Voltage Rise on!q 0.8 0.6 0.4 0.2 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 Cell Ratio (CR) ΗΜΥ307 Δ17: Memory and Memory Circuitry.27 Θεοχαρίδης, ΗΜΥ, 2017
SRAM Cell Analysis (Write) WL=1 M5!Q=0 M1 M4 Q=1 M6!BL=1 BL=0 Pullup Ratio (PR) = (W M4 /L M4 )/(W M6 /L M6 ) V Q = (V dd - V Tn ) ±Ö((V dd V Tn ) 2 (µ p /µ n )(PR)((V dd V Tn - V Tp ) 2 ) ΗΜΥ307 Δ17: Memory and Memory Circuitry.28 Θεοχαρίδης, ΗΜΥ, 2017
Write Voltages Ratios 1 V dd = 2.5V V Tp = 0.5V µ p /µ n = 0.5 0.8 Write Voltage (VQ) 0.6 0.4 0.2 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 Pullup Ratio (PR) ΗΜΥ307 Δ17: Memory and Memory Circuitry.29 Θεοχαρίδης, ΗΜΥ, 2017
Cell Sizing l Keeping cell size minimized is critical for large caches l Minimum sized pull down fets (M1 and M3) Requires minimum width and longer than minimum channel length pass transistors (M5 and M6) to ensure proper CR But sizing of the pass transistors increases capacitive load on the word lines and limits the current discharged on the bit lines both of which can adversely affect the speed of the read cycle l Minimum width and length pass transistors Boost the width of the pull downs (M1 and M3) Reduces the loading on the word lines and increases the storage capacitance in the cell both are good! but cell size may be slightly larger ΗΜΥ307 Δ17: Memory and Memory Circuitry.30 Θεοχαρίδης, ΗΜΥ, 2017
6T-SRAM Layout V DD M2 M4 Q Q M1 M3 M5 M6 GND WL BL BL ΗΜΥ307 Δ17: Memory and Memory Circuitry.31 Θεοχαρίδης, ΗΜΥ, 2017
Multiple Read/Write Port Cell WL1 WL2 M7 M5!Q M2 M4 Q M6 M8 M1 M3!BL2!BL1 BL1 BL2 ΗΜΥ307 Δ17: Memory and Memory Circuitry.32 Θεοχαρίδης, ΗΜΥ, 2017
4x4 DRAM Memory 2 bit words enable read precharge A 1 BL bit line precharge WL[0] WL[1] A 2 WL[2] WL[3] clocking, control, and refresh A 0 BL[0] BL[1] BL[2] BL[3] Column Decoder sense amplifiers write circuitry ΗΜΥ307 Δ17: Memory and Memory Circuitry.33 Θεοχαρίδης, ΗΜΥ, 2017
3-Transistor DRAM Cell WWL RWL WWL write M3 BL1 V dd M1 X M2 X V dd -V t C s RWL read BL1 BL2 BL2 V dd -V t DV No constraints on device sizes (ratioless) Reads are non-destructive Value stored at node X when writing a 1 is V WWL - V tn ΗΜΥ307 Δ17: Memory and Memory Circuitry.34 Θεοχαρίδης, ΗΜΥ, 2017
3T-DRAM Layout BL2 BL1 GND RWL M3 M2 WWL M1 ΗΜΥ307 Δ17: Memory and Memory Circuitry.35 Θεοχαρίδης, ΗΜΥ, 2017
1-Transistor DRAM Cell WL WL write 1 read 1 C BL M1 C s X X V dd -V t BL BL V dd /2 V dd sensing Write: C s is charged (or discharged) by asserting WL and BL Read: Charge redistribution occurs between C BL and C s Read is destructive, so must refresh after read ΗΜΥ307 Δ17: Memory and Memory Circuitry.36 Θεοχαρίδης, ΗΜΥ, 2017
1-T DRAM Cell Capacitor Metal word line poly SiO 2 M1 word line n + n + Field Oxide poly Inversion layer induced by plate bias (a) Cross-section Diffused bit line Polysilicon gate Polysilicon plate (b) Layout Used Polysilicon-Diffusion Capacitance Expensive in Area ΗΜΥ307 Δ17: Memory and Memory Circuitry.37 Θεοχαρίδης, ΗΜΥ, 2017
DRAM Cell Observations l DRAM memory cells are single ended (complicates the design of the sense amp) l 1T cell requires a sense amp for each bit line due to charge redistribution read l 1T cell read is destructive; refresh must follow to restore data l 1T cell requires an extra capacitor that must be explicitly included in the design l A threshold voltage is lost when writing a 1 (can be circumvented by bootstrapping the word lines to a higher value than V dd ) ΗΜΥ307 Δ17: Memory and Memory Circuitry.38 Θεοχαρίδης, ΗΜΥ, 2017
Poly-diffusion capacitor 1T-DRAM ΗΜΥ307 Δ17: Memory and Memory Circuitry.39 Θεοχαρίδης, ΗΜΥ, 2017
Advanced 1T DRAM Cells Word line Insulating Layer Cell plate Capacitor dielectric layer Cell Plate Si Capacitor Insulator Refilling Poly Transfer gate Storage electrode Isolation Storage Node Poly 2nd Field Oxide Si Substrate Trench Cell Stacked-capacitor Cell ΗΜΥ307 Δ17: Memory and Memory Circuitry.40 Θεοχαρίδης, ΗΜΥ, 2017
Floating-gate transistor (FAMOS) Source Floating gate Gate Drain D t ox G t ox n + Substrate p n + S (a) Device cross-section (b) Schematic symbol ΗΜΥ307 Δ17: Memory and Memory Circuitry.41 Θεοχαρίδης, ΗΜΥ, 2017
Floating-Gate Transistor Programming 20 V 0 V 5 V 20 V 10 V 5 V -5 V 0 V -2.5 V 5 V S D S D S D Avalanche injection. Removing programming voltage leaves charge trapped. Programming results in higher V T. ΗΜΥ307 Δ17: Memory and Memory Circuitry.42 Θεοχαρίδης, ΗΜΥ, 2017
FLOTOX EEPROM Source Floating gate Gate Drain I n + 20-30 nm Substrate p 10 nm (a) Flotox transistor n + -10 V 10 V V GD (b) Fowler-Nordheim I-V characteristic BL WL V DD (c) EEPROM cell during a read operation ΗΜΥ307 Δ17: Memory and Memory Circuitry.43 Θεοχαρίδης, ΗΜΥ, 2017
Flash EEPROM Control gate Floating gate erasure Thin tunneling oxide n + source programming p-substrate n + drain ΗΜΥ307 Δ17: Memory and Memory Circuitry.44 Θεοχαρίδης, ΗΜΥ, 2017
Cross-sections of NVM cells Flash Courtesy Intel EPROM ΗΜΥ307 Δ17: Memory and Memory Circuitry.45 Θεοχαρίδης, ΗΜΥ, 2017
Peripheral Memory Circuitry l Row and column decoders l Sense amplifiers l Read/write circuitry l Timing and control ΗΜΥ307 Δ17: Memory and Memory Circuitry.46 Θεοχαρίδης, ΗΜΥ, 2017
Row Decoders l Collection of 2 M complex logic gates organized in a regular, dense fashion l (N)AND decoder WL(0) =!A 9!A 8!A 7!A 6!A 5!A 4!A 3!A 2!A 1!A 0 WL(511) =!A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 l NOR decoder WL(0) =!(A 9 +A 8 +A 7 +A 6 +A 5 +A 4 +A 3 +A 2 +A 1 +A 0 ) WL(511) =!(A 9 +!A 8 +!A 7 +!A 6 +!A 5 +!A 4 +!A 3 +!A 2 +!A 1 +!A 0 ) ΗΜΥ307 Δ17: Memory and Memory Circuitry.47 Θεοχαρίδης, ΗΜΥ, 2017
Dynamic NOR Row Decoder V dd WL 0 WL 1 WL 2 WL 3 precharge A 0!A 0 A 1!A 1 ΗΜΥ307 Δ17: Memory and Memory Circuitry.48 Θεοχαρίδης, ΗΜΥ, 2017
Dynamic NAND Row Decoder WL 0 WL 1 WL 2 WL 3!A 0 A 0!A 1 A 1 precharge ΗΜΥ307 Δ17: Memory and Memory Circuitry.49 Θεοχαρίδης, ΗΜΥ, 2017
Split Row Decoder!(!(!A 0!A 1!A 2 ) +!(!A 3!A 4!A 5 ) +!A 6 ) WL 0 WL 0 *128 *128 WL 127 WL 127!(!A 0!A 1!A 2 )...!(A 0 A 1 A 2 ) Address<6:0> *7 *7 *8 *8 ΗΜΥ307 Δ17: Memory and Memory Circuitry.50 Θεοχαρίδης, ΗΜΥ, 2017
Pass Transistor Based Column Decoder BL 3!BL 3 BL 2!BL 2 BL 1!BL 1 BL 0!BL 0 A 1 A 0 2 input NOR decoder S 3 S 2 S 1 S 0 Data!Data q Advantage: speed since there is only one extra transistor in the signal path q Disadvantage: large transistor count ΗΜΥ307 Δ17: Memory and Memory Circuitry.51 Θεοχαρίδης, ΗΜΥ, 2017
Tree Based Column Decoder BL 3!BL 3 BL 2!BL 2 BL 1!BL 1 BL 0!BL 0!A 0 A 0!A 1 A 1 Data!Data q Advantage: number of transistors drastically reduced q Disadvantage: delay increases quadratically with the number of sections (so prohibitive for large decoders) l fix with buffers, progressive sizing, combination of tree and pass transistor approaches ΗΜΥ307 Δ17: Memory and Memory Circuitry.52 Θεοχαρίδης, ΗΜΥ, 2017
Bit Line Precharging Static Pull-up Precharge Clocked Precharge clock BL!BL BL!BL equalization transistor - speeds up equalization of the two bit lines by allowing the capacitance and pull-up device of the nondischarged bit line to assist in precharging the discharged line ΗΜΥ307 Δ17: Memory and Memory Circuitry.53 Θεοχαρίδης, ΗΜΥ, 2017
Sense Amplifiers small t p = ( C * DV ) / I av large make D V as small as possible q Use sense amplifiers (SA) to amplify the small swing on the bit lines to the full rail-to-rail swing needed at the output SA input output ΗΜΥ307 Δ17: Memory and Memory Circuitry.54 Θεοχαρίδης, ΗΜΥ, 2017
Differential Sensing - SRAM V DD V DD V DD PC V DD y M3 M4 y BL EQ BL x M1 M2 SE M5 x x SE x WL i (b) Doubled-ended Current Mirror Amplifier SRAM cell i V DD Diff. x Sense x Amp y y D D x y SE y x (a) SRAM sensing scheme. (c) Cross-Coupled Amplifier ΗΜΥ307 Δ17: Memory and Memory Circuitry.55 Θεοχαρίδης, ΗΜΥ, 2017
Latch Based Sense Amplifier bit lines DV = 0.1V dd isolate sense sense amplifier outputs DV = V dd ΗΜΥ307 Δ17: Memory and Memory Circuitry.56 Θεοχαρίδης, ΗΜΥ, 2017
Alpha Differential Amplifier/Latch S 3 S 2 S 1 S 0 column decoder precharge 0->1 mux_out P1 P2!mux_out sense amplifier N3 N5 sense 0->1 P3 sense_out N2 N4 N1 Pre -> Closed) off->on DV = V dd ΗΜΥ307 Δ17: Memory and Memory Circuitry.57 Θεοχαρίδης, ΗΜΥ, 2017 P4!sense_out sense
Read/Write Circuitry!BL BL CS D W!R R SA Local R/W Precharge D: data (write) bus R: read bus W: write signal CS: column select (column decoder) Local W (write): BL = D,!BL =!D enabled by W & CS Local R (read): R = BL,!R =!BL enabled by!w & CS ΗΜΥ307 Δ17: Memory and Memory Circuitry.58 Θεοχαρίδης, ΗΜΥ, 2017
Approaches to Memory Timing SRAM Timing Self-Timed DRAM Timing Multiplexed Addressing msb s lsb s Address Bus Row Addr. Column Addr. Address Bus Address RAS Address transition initiates memory operation CAS RAS-CAS timing ΗΜΥ307 Δ17: Memory and Memory Circuitry.59 Θεοχαρίδης, ΗΜΥ, 2017
SRAM Address Transition Detection V DD A 0 DELAY t d ATD ATD A 1 DELAY t d A N-1 DELAY t d... ΗΜΥ307 Δ17: Memory and Memory Circuitry.60 Θεοχαρίδης, ΗΜΥ, 2017
DRAM Timing ΗΜΥ307 Δ17: Memory and Memory Circuitry.61 Θεοχαρίδης, ΗΜΥ, 2017
Caches as a side note l Address issued by the data path has to be mapped (in hardware) into a cache address tag which word in the cache block which cache block in the set l Cache block (aka line) unit of read/write information in cache l Cache mapping strategies Direct mapped A word can be in only one block in the cache, so only have to compare its tag against that block s tag Block set associative A word can be in two (or four or eight ), so have to compare its tag against the tags of those two (or four or eight ) cache blocks Fully associative A word can be in any block in the cache, so have to compare its tag against the tags of all of the blocks in the cache ΗΜΥ307 Δ17: Memory and Memory Circuitry.62 Θεοχαρίδης, ΗΜΥ, 2017
Two-Way Block Set Associative Cache Set 1 Set 2 Address issued by CPU Tag Data Tag Data = = Hit Desired word ΗΜΥ307 Δ17: Memory and Memory Circuitry.63 Θεοχαρίδης, ΗΜΥ, 2017
Translation Lookaside Buffers (TLBs) l Small caches used to speed up address translation in processors with virtual memory l All addresses have to be translated before cache access l I$ can be virtually indexed/virtually tagged ΗΜΥ307 Δ17: Memory and Memory Circuitry.64 Θεοχαρίδης, ΗΜΥ, 2017
TLB Structure Address issued by CPU (page size = index bits + byte select bits) VA Tag PA Tag Data Tag Data Hit Most TLBs are small (<= 256 entries) and thus fully associative content addressable memories (CAMs) = Hit = Desired word ΗΜΥ307 Δ17: Memory and Memory Circuitry.65 Θεοχαρίδης, ΗΜΥ, 2017
WL<0> WL<1> WL<2> CAM Design Hit match<0> match<1> word line<0> of data array WL<3> match<2> match<3> Read/Write Circuitry bit WL bit match/write data precharge/match match ΗΜΥ307 Δ17: Memory and Memory Circuitry.66 Θεοχαρίδης, ΗΜΥ, 2017
Reliability and Yield l Semiconductor memories trade-off noise margin for density and performance Thus, they are highly sensitive to noise (cross talk, supply noise) l High density and large die size causes yield problems Yield = 100 # of good chips/wafer # of chips/wafer Y = [(1 e AD )/(AD)] 2 l Increase yield using error correction and redundancy ΗΜΥ307 Δ17: Memory and Memory Circuitry.67 Θεοχαρίδης, ΗΜΥ, 2017
Alpha Particles a-particle WL V DD BL n + SiO 2 1 particle ~ 1 million carriers ΗΜΥ307 Δ17: Memory and Memory Circuitry.68 Θεοχαρίδης, ΗΜΥ, 2017
Redundancy in the Memory Structure Fuse bank Redundant row Row address Redundant columns Column address ΗΜΥ307 Δ17: Memory and Memory Circuitry.69 Θεοχαρίδης, ΗΜΥ, 2017
Redundancy and Error Correction ΗΜΥ307 Δ17: Memory and Memory Circuitry.70 Θεοχαρίδης, ΗΜΥ, 2017