Mohon Peak BETA BRD B1. Intel Corporation. 001_Cover Page. Mohon Peak CRB Wednesday, August 28, 2013 ODM PROJECT CODE : S

Μέγεθος: px
Εμφάνιση ξεκινά από τη σελίδα:

Download "Mohon Peak BETA BRD B1. Intel Corporation. 001_Cover Page. Mohon Peak CRB Wednesday, August 28, 2013 ODM PROJECT CODE : S"

Transcript

1 Mohon Peak ET R OM PROJET OE : S0-0 Intel orporation 00_over Page 000 W HNLER LV HNLER, Z Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

2 Note:VN = voton and RGY = Rangeley PGE INEX PGE INEX * over Page Page Index FUNTION LOK IGRM 0 RESET LOK IGRM ESRIPTIONS SMUS LOK IGRM POWER SEQUENE IGRM LOK IGRM POWER ISTRIUTION IGRM GPIO MP VN/RGY_LP_SM_MIS VN/RGY_R_HNNEL_ VN/RGY_R_HNNEL_ VN/RGY_PIE_GEN VN/RGY_GbE VN/RGY_ST_US VN/RGY_POWER_I VN/RGY_POWER_II VN/RGY_ VN/RGY_ITP_XP R_SLOT_IMM0_H R_SLOT_IMM0_H R_SLOT_IMM_H R_SLOT_IMM_H LK_GENERTOR LK_UFFER PORT0 TPM US_To_URT PIe_SW_INTERFE PIe_SW_PWR_ONFIG. PI_Mux US_SWITH QU_PHY_G_ PORTS QU_PHY_PWR_EOUPLING QU_PHY_X_G_LN_ONN_I QU_PHY_X_G_LN_ONN_II TWINVILLE_MI_ LES TWINVILLE_NSI_SM_FLSH TWINVILLE_PIe TWINVILLE_RSV_PINS TWINVILLE_MIS TWINVILLE_POWER_I TWINVILLE_POWER_II_ TWINVILLE_0G_LN ONNETOR TWINVILLE_PWR_PV TWINVILLE_PWR_PV TWINVILLE_PWR_P0V TWINVILLE_PWR_P0V PIE_SLOT ( X ) PIE_SLOT ( X ) PIE_SLOT ( X ) PIE_SLOT ( X) MGT_PIE_GF ( X ) SEQUENE REQUIREMENT ST_ONNETORS US_ONNETORS F_PNEL FN_ONNETOR TX_POWER PV_V_UX_SWITH PGE INEX ESRIPTIONS PV_STY VN/RGY_R_VREF VN/RGY_PVR VN/RGY_PVR_POWER STGE VN/RGY_PVTT_ VN/RGY_PVP_PVNN_I VN/RGY_PVP_PVNN_II VN/RGY_PV_STY VN/RGY_PV0 VN/RGY_PV0_PV0_STY VN/RGY_PV LK_PV_STY GbE_PV0_PV_PV PIe_SW_PV_SW PIe_SW_PV0_SW MOUNTING_HOLE_OUPON P_STK_UP_ME HNGE_LIST -EVTII HNGE_LIST -EVTII HNGE_LIST _EVTII HNGE_LIST -VTI HNGE_LIST -VTI HNGE_LIST--VTIII HNGE_LIST--VTIII HNGE_LIST--VTIII HNGE_LIST--VTIII HNGE_LIST-E-VTIII Intel orporation 00_Page Index 000 W HNLER LV HNLER, Z Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

3 Intel orporation 000 W HNLER LV HNLER, Z 00_FUNTION LOK IGRM Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

4 Intel orporation 000 W HNLER LV HNLER, Z 00_SMUS LOK IGRM Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

5 Intel orporation 000 W HNLER LV HNLER, Z 00_POWER SEQUENE IGRM Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

6 Intel orporation 000 W HNLER LV HNLER, Z 00_RESET LOK IGRM Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

7 Intel orporation 00_LOK IGRM 000 W HNLER LV HNLER, Z Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

8 Intel orporation 000 W HNLER LV HNLER, Z 00_POWER ISTRIUTION IGRM Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

9 Intel orporation 009_GPIO_MP 000 W HNLER LV HNLER, Z Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of 9

10 oard assignments _I_ PV_STY PV _I I_0 0 0 Lyon Peak SV 0 0 0K//X K//X.K/ 0K// K//.K/.K/.K/.K/.K/.K/ K//X K//X K//X 0K//.K/ SM_PV_HOST_T SM_PV_HOST_LK SM_SENSOR_R_T SM_SENSOR_R_LK SM_PEI_T SM_PEI_LK PLTRST_N R R R R9 R0 R R9 R R R R R R9 R R R GPIO_SUS_ GPIO_SUS_0 PMU PRESENT PMU_GPE_N PMU_WKE_N SM_SENSOR_R_T SM_SENSOR_R_LK SM_PEI_T SM_PEI_LK SM_PV_HOST_T SM_PV_HOST_LK ERROR_VN_ ERROR_VN_ ERROR_VN_0 LP_LKRUN_N SM_HOST_LRT_N PV JP Lyon Peak V Lyon Peak PPV Mohon Peak Tiger ove PH/*/K/./V/ U JP PH/*/K/./V/ JP PH/*/K/./V/ {9,0,,,,,0,} {9,0,,,,,0,} 0.u//XR/V/K/X SNLVG0GV/SOT- {} {} {} RST_PIE_SLOT_N {,} {,} {,} {,} {,} {9,,,,0,9,,} {9} {9} PV PV_STY ERROR_VN_ ERROR_VN_ ERROR_VN_0 ERROR_VN_ ERROR_VN_ ERROR_VN_0 FLEX_LK_SE0 : OOT Select, 0 = LP, = SPI FLEX_LK_SE : TOP SWP TIVE LP_L LP_L LP_L LP_L0 LP_FRME_N SM_PV_HOST_LK SM_PV_HOST_T {} {} {,,9,0} {,0,} PLTRST_N PWR_TN_VN_N RST_TN_VN_N PVTT EN_N SLP_LN_N SLP_S_N SLP_S_N LK_00M_VN_HFHPLL_P LK_00M_VN_HFHPLL_N {9} {,} SM_HOST_LRT_N {,9} {} {9} LP_LKOUT0 PMU_WKE_N LK_M_VN RST_VN_N PV0 {9} XP_VN_TK {9} XP_VN_TMS XP_VN_TRST_N {9} XP_VN_TI.K/.K//X.K//X.K//X R 0/ R 0/ R9 R R R K///X K///X K///X LP_L LP_L LP_L LP_L0 LP_LKOUT LP_LKOUT0 LP_LKRUN_N LP_FRME_N SM_PEI_LK SM_PV_HOST_LK SM_PEI_T SM_PV_HOST_T SM_HOST_LRT_N PLTRST_N PWR_TN_VN_N RST_TN_VN_N PVTT EN_N SLP_LN_N SLP_S_N SLP_S_N PMU_SUSLK PMU_WKE_N LK_00M_VN_HFHPLL_P LK_00M_VN_HFHPLL_N LK_M_VN RST_VN_N RST_PIE_SLOT_N {9,0,,} R R R XP_VN_TK XP_VN_TMS XP_VN_TRST_N XP_VN_TI _I I I_0 FLEX_LK_SE FLEX_LK_SE0 PMU_SUSLK R9 R9 R9 RST_VN_N K//X K//X K//X R / R / R / / R / R _I_ {} _I_0 {} FLEX_LK_SE FLEX_LK_SE0 SPI_VN_R_S0_N _I_ GPIO_SUS_ GPIO_SUS_0 FLEX_LK_SE FLEX_LK_SE0 R / R9 SM_SENSOR_R_LK SM_SENSOR_R_T PMU PRESENT PMU_GPE_N PLTRST_R_N PWRTN_IN_N RESETOTTOM_IN_N 0 0.u//XR/V/K/X TTRIGINOUT TTRIGOUT PV_STY.K//X R0.K//X L L L T W V G H9 G9 L M G M9 G H H R R N N N P L E 9 M Y0 F V L J M Y M L R9 R9 UF ERROR ERROR ERROR0 GPIO_SUS GPIO_SUS GPIO_SUS0 LP_ LP_ LP_ LP_0 SMLRT_N0 PV PV_STY FLEX_LK_SE FLEX_LK_SE0 LP_LKOUT LP_LKOUT0 LP_LKRUN LP_FRME SM_LK SM_LK SM_LK0 SM_T SM_T SM_T0 SYM OF VOTON/G/S/X JP Mode - Normal - VOTON/RNGELEY PMU PRESENT PMU_GPE PMU_PLTRST PMU_PWRTN PMU_RESETUTTON PMU_SLP_RVTT PMU_SLP_LN PMU_SLP_S PMU_SLP_S PMU_SUSLK PMU_WKE HPLL_REFP HPLL_REFN LK_IN PU_RESET TTRIGINOUT TTRIGOUT TK TMS TRST TI 0K// 0K// SPI_VN_R_LK SPI_VN_R_S0_N SPI_VN_R_MOSI SPI_VN_MISO PV_STY 0.u//YV/V/Z RTX_P RTX_P VRT_EXTP OREPWROK X_PRY X_PREQ IERR IL_SERIRQ INTRUER MERR MEMHOT NMI PROHOT ROMP_ORE_LVT RSMRST RTEST SPI_LK SPI_S SPI_S0 SPI_MISO SPI_MOSI SRTRST SUS_STT SUSPWRNK SVI_LERT SVI_LK SVI_T THERMTRIP URT_RX URT_TX TO SPI_VN S0_N SPI_VN MISO SPI programming J J H0 W Y M T0 L L L 9 G 0 F Y 9 9 Y 0 W T G0 H0 F R 9 0 RTX RTX U XP_VN_PRY_N XP_VN_PREQ_N IERR_VN IRQ_IL_SEIRQ_VN INTRUER_N R 0K/ MERR_VN H_MEMHOT_O_R_N NMI_VN Z Z Z Z V JP H_PROHOT_O_N ROMP_ORE_LVT RSMRST_R_N RTEST_VN_N SPI_VN_LK SPI_VN_S_N SPI_VN_S0_N SPI_VN_MISO SPI_VN_MOSI -SRTRST SLP_SUS_STT_N SUSPWRNK SVI_LERT_VN_N SVI_VN_LK SVI_VN_T SPI_EMUL LV0PW/TSSOP/S VN_THERMTRIP_N URT_VN_RX URT_VN_TX XP_VN_TO K// PH/*/K/./V//GF Y Y Y Y E E E E PH/*/K/./V/ JP SPI_FLSH_HOL SPI_VN LK SPI_VN MOSI JP PV_STY SPI_VN LK SPI_VN S0_N SPI_VN MOSI SPI_VN MISO SPI_SW_EN JP/*/K/OH/./O/GF::[-]LOSE R 0/ PWRG_OREPWR PV_RT R0 0/ R RSMRST_N R9 0/ R9 0/ R9 0/ URT_VN_RX {} URT_VN_TX {} PH/*/K/./V/ PV_STY XP_VN_PRY_N {9} XP_VN_PREQ_N {9} IRQ_IL_SEIRQ_VN {} H_PROHOT_O_N {} R SVI_LERT_N SVI_LK SVI_T XP_VN_TO {9} SPI_VN MISO 9.9// PV_STY PWRG_OREPWR {9,} RSMRST_N {9,} 0.u//YV/V/Z R.K/ R9 0.u//XR/V/K K// 0.u//XR/V/K RTEST_VN_N {9} RN 0/PR/.K/ PV_RT SPI_VN_R_LK SPI_VN_R_S0_N SPI_VN_R_MOSI PV_STY PV SVI_LERT_N {,} SVI_LK {,} SVI_T {,} R R SPI_FLSH_HOL SPI_VN_IOS_S0_N R0 / SPI_VN_R_MISO U SNLVG0VR/SOT-.K/ K///X p//npo/0v/j IOS HOLn V N N N N Sn/Sn SO/Q RT LOK Test points for probing only. PLTRST_R_N PWRTN_IN_N SPI_VN_S_N SUSPWRNK NMI signal- PU to support Interposer and P to support VN. NMI_VN IOS_SPI_PORT_N H_MEMHOT_O_R_N VN_THERMTRIP_N H_PROHOT_O_N MERR_VN PWRG_OREPWR SPI_VN_S0_N IERR_VN VN_THERMTRIP_N LP_LKOUT SLP_SUS_STT_N H_MEMHOT_O_N {0,,,} SPI-SK//S/GF XP_VN_PREQ_N SVI_LERT_N SVI_LK SVI_T SPI_VN_IOS_S0_N SPI_VN_IOS_S0_N IRQ_IL_SEIRQ_VN LK/ SI/ N N N N 0 9 WPn R 0M/ X X N[0] N[] R0 SPI_VN LK SPI_VN MOSI IOS_SPI_PORT_N R990 R99 R0 RTX RTX p//npo/0v/j X.K/.p/ppm/*./0K/S R 0/ R 9.9// R 0/ R0 R0 R0 R0 R.// R9 R0 R R R R 0//X R 00// R R9 0K//X R9 0K/ R0 R // K//X 0K//X 0K//X 0K//X 0K//X.K/.K/ PV0 PV0 PV_STY.K//X.K//X K//X 0K//.K//X.K//X.K//X K// PV IOS_SPI_PORT_N {} PV_STY R 0K/ ~ms 0 u//xr/.v/k U LVGGV/SOT PV_STY 0.u//XR/V/K R0 / RSMRST_N R0 0K/ VT TTERY R WT/*/IV/./V/S/SN/M TTERY R0 + R0/0mm/. K// PV_STY T/SOT/00m u//xr/.v/m PV_RT PV_RT R 0K// -SRTRST S u//xr/.v/k JP RTEST_VN_N PH/*/K/./V/ JP JP/*/K/OH/./O/GF::[-]LOSE LR MOS JUMP PV_STY 0.u//YV/V/Z SPI_VN_IOS_S0_N SPI_VN S0_N SPI_VN_IOS_S0_N MXI MXI SPI_FLSH_HOL SPI_VN_IOS_S0_N SPI_VN_R_MISO IOS MP-VMFTP/S/[0HL--0R] IOS MP-VMFTP/S/[0HL--0R] JP PH/*/K/./V/ IOS HOLn V N N N N Sn/Sn SO/Q SPI-SK//S/GF/X MXI LK/ SI/ N N N N 0 9 WPn JP JP/*/K/OH/./O/GF::[-]LOSE Intel orporation SPI_VN LK SPI_VN MOSI IOS_SPI_PORT_N 00_VN/RGY_LP_SM_MIS 000 W HNLER LV HNLER, Z Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of 0

11 U M Q[..0] M M[..0] {0,} M Q[..0] VOTON/RNGELEY M Q L F M M M M[..0] {0,} M Q K R_0_Q_ R_0_M_ M M M Q L R_0_Q_ R_0_M_ M M M Q0 M R_0_Q_ R_0_M_ M M M Q9 M R_0_Q_0 R_0_M_ G M M M Q N R_0_Q_9 R_0_M_ N0 M M0 M Q K R_0_Q_ R_0_M_0 M M9 M Q N R_0_Q_ R_0_M_9 M M M Q P R_0_Q_ R_0_M_ H M M M Q M R_0_Q_ R_0_M_ 0 M M M Q N R_0_Q_ R_0_M_ M M M M Q L R_0_Q_ R_0_M_ M M M Q N R_0_Q_ R_0_M_ G M M M Q0 L R_0_Q_ R_0_M_ G M M M Q9 P R_0_Q_0 R_0_M_ L M M M Q M R_0_Q_9 R_0_M_ H M M0 M Q N9 R_0_Q_ R_0_M_0 M E[..0] M E[..0] {0,} M Q P9 R_0_Q_ M E M Q P R_0_Q_ R_0_QE_ M E M Q M R_0_Q_ R_0_QE_ Y M E M Q N R_0_Q_ R_0_QE_ W M E M Q L R_0_Q_ R_0_QE_ M E M Q L R_0_Q_ R_0_QE_ M E M Q0 L R_0_Q_ R_0_QE_ Y M E M Q9 G0 R_0_Q_0 R_0_QE_ Y M E0 M Q G9 R_0_Q_9 R_0_QE_0 M Q Y0 R_0_Q_ 9 M K_P M Q R_0_Q_ R_0_K_ G9 M K_P M K_P {} M Q 0 R_0_Q_ R_0_K_ F M K_P M K_P {} M Q F0 R_0_Q_ R_0_K_ M K_P0 M K_P {0} M Q 0 R_0_Q_ R_0_K_0 M K_P0 {0} M Q R_0_Q_ 9 M K_N M Q R R_0_Q_ R_0_K H9 M K_N M K_N {} M Q0 R R_0_Q_ R_0_K G M K_N M K_N {} M Q9 L R_0_Q_0 R_0_K M K_N0 M K_N {0} M Q L R_0_Q_9 R_0_K0 M K_N0 {0} M Q U R_0_Q_ H M KE M Q U R_0_Q_ R_0_KE_ G M KE M KE {} M Q N R_0_Q_ R_0_KE_ H M KE M KE {} M Q N R_0_Q_ R_0_KE_ G M KE0 M KE {0} M Q W R_0_Q_ R_0_KE_0 M KE0 {0} M Q Y R_0_Q_ G M S_N M Q Y R_0_Q_ R_0_S M S_N M S_N {} M Q0 W R_0_Q_ R_0_S M S_N M S_N {} M Q9 W R_0_Q_0 R_0_S E M S_N0 M S_N {0} M Q Y R_0_Q_9 R_0_S0 M S_N0 {0} M Q Y R_0_Q_ G M OT M Q Y9 R_0_Q_ R_0_OT_ H M OT M OT {} M Q R0 R_0_Q_ R_0_OT_ M OT M OT {} M Q T R_0_Q_ R_0_OT_ M OT0 M OT {0} M Q T R_0_Q_ R_0_OT_0 M OT0 {0} M S[..0] M Q R R_0_Q_ M S M S[..0] {0,} M Q R R_0_Q_ R_0_S_ L0 M S M Q0 T0 R_0_Q_ R_0_S_ L M S0 M Q9 T R_0_Q_0 R_0_S_0 R 00///X M Q R R_0_Q_9 M Q M9 R_0_Q_ R_0_MONP P R9 00// M Q M R_0_Q_ R_0_MONN P R0 00///X PVR M Q L R_0_Q_ R_0_MONP K R 00// M Q M R_0_Q_ R_0_MONN K M Q M R_0_Q_ M MPU M Q L R_0_Q_ R_0_MPU R.// M QPU R 0.// M Q M R_0_Q_ R_0_QPU W M QS_N R M Q0 M R_0_Q_ R_0_QSE_0 M QS_P M QS_N {0,} K//X R_0_Q_0 R_0_QSE_0 M QS_P {0,} {0,} M QS_P[..0] M QS_P P M R_RESET_N R M QS_P N R_0_QS_ R_0_RMRST M_OTPU R 0/ M QS_P M R_0_QS_ R_0_OTPU W0 // M QS_P 9 R_0_QS_ M S_N M QS_P P R_0_QS_ R_0_S H M RS_N M S_N {0,} M QS_P W R_0_QS_ R_0_RS G M WE_N M RS_N {0,} M QS_P T R_0_QS_ R_0_WE M WE_N {0,} R M QS_P0 L R_0_QS_ LK_00M_VN_MPLL0_P LK_00M_VN_MPLL0_P {} 00K/ R_0_QS_0 R_0_REFP N LK_00M_VN_MPLL0_N {0,} M QS_N[..0] LK_00M_VN_MPLL0_N {} M QS_N M R_0_REFN M M QS_N L R_0_QS M_RM_PWROK 0//X R M QS_N N R_0_QS R_0_RM_PWROK G PWRG_R_V PWRG_R_V {} M QS_N 9 R_0_QS R_0_V_PWROK E M QS_N P R_0_QS Y9 M VREF M VREF M QS_N W R_0_QS R_0_VREF M QS_N R R_0_QS M QS_N0 L R_0_QS P//NPO/0V/J/X 0.u//XR/V/K/X R_0_QS0 M RESET_N {0,} PVR R0 00///X R 00// SYM OF VOTON/G/S/X PLE LOSE TO PIN Y9 PVR PVR PV {} VR_PVR PWRG {0,0,} SLP_S_N VR_PVR PWRG SLP_S_N R R K/ K//X 0.u//XR/V/K 0 0.u//XR/V/K/X PV_STY R0 / U9 SNHGVR/SOT- PV_STY R K//X G R K/ S M_RM_PWROK Q N00/SOT/pF/ 0.u//XR/V/K/X {} {} LKPWRG_R LKPWRG_L 0.u//XR/V/K M_RM_PWROK {} R0 0//X R 0K/ R0 0K/.u//XR/0V/K PV_STY 0 0.u//XR/V/K R0 / U99 SNHGVR/SOT- PV_STY R K//X R K/ PWRG_R_V Q G S N00/SOT/0pF/./.V 0 0.u//XR/V/K/X G R9 K/ LKPWRG_ELYE S Q N00/SOT/0pF/./.V Intel orporation LKPWRG_ELYE {} 00_VN/RGY_LP_SM_MIS 000 W HNLER LV HNLER, Z Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

12 U M Q[..0] M M[..0] {,} M Q[..0] VOTON/RNGELEY M Q H M M M M[..0] {,} M Q R Q_ R M_ G M M M Q 9 R Q_ R M_ G M M M Q0 R Q_ R M_ G M M M Q9 R Q_0 R M_ P M M M Q R Q_9 R M_ L M M0 M Q R Q_ R M_0 M M M9 M Q R Q_ R M_9 H M M M Q Y0 R Q_ R M_ J M M M Q W R Q_ R M_ J M M M Q Y R Q_ R M_ H M M M Q Y R Q_ R M_ M M M M Q Y R Q_ R M_ P M M M Q0 W0 R Q_ R M_ G M M M Q9 W R Q_0 R M_ G M M M Q W R Q_9 R M_ H M M0 M Q Y R Q_ R M_0 M E[..0] M Q Y R Q_ M E[..0] {,} M E M Q T R Q_ R QE_ M E M Q T R Q_ R QE_ M E M Q R Q_ R QE_ M E M Q R Q_ R QE_ E M E M Q U R Q_ R QE_ M E M Q0 U R Q_ R QE_ M E M Q9 U R Q_0 R QE_ M E0 M Q R R Q_9 R QE_0 M Q U R Q_ J M K_P M Q T R Q_ R K_ H0 M K_P M K_P {} M Q R R Q_ R K_ G9 M K_P M K_P {} M Q R9 R Q_ R K_ 9 M K_P0 M K_P {} M Q R R Q_ R K_0 M K_P0 {} M Q R R Q_ L M K_N M Q P0 R Q_ R K G0 M K_N M K_N {} M Q0 M0 R Q_ R K H9 M K_N M K_N {} M Q9 J0 R Q_0 R K M K_N0 M K_N {} M Q H R Q_9 R K0 M K_N0 {} M Q L R Q_ L M KE M Q N R Q_ R KE_ L M KE M KE {} M Q H9 R Q_ R KE_ N M KE M KE {} M Q H0 R Q_ R KE_ N M KE0 M KE {} M Q R Q_ R KE_0 M KE0 {} M Q R Q_ K M S_N M Q R Q_ R S L M S_N M S_N {} M Q0 R Q_ R S N M S_N M S_N {} M Q9 9 R Q_0 R S K M S_N0 M S_N {} M Q 9 R Q_9 R S0 M S_N0 {} M Q R Q_ L M OT M Q R Q_ R OT_ N M OT M OT {} M Q R Q_ R OT_ N M OT M OT {} M Q R Q_ R OT_ L M OT0 M OT {} M Q R Q_ R OT_0 M OT0 {} M S[..0] M Q E R Q_ H M S M S[..0] {,} M Q R Q_ R S_ H M S M Q0 R Q_ R S_ N M S0 M Q9 R Q_0 R S_0 R 00///X M Q R Q_9 R 00// M Q R MONP E R Q_ R9 00///X M Q R MONN R Q_ M Q R MONP R90 00// 0 R Q_ M Q R MONN 9 R Q_ M Q R Q_ M MPU R9.// M Q R Q_ R MPU T M QPU M Q R QPU T R9 0.// 9 R Q_ M QS_N M Q0 9 R Q_ R QSE_0 M QS_P M QS_N {,} R Q_0 R QSE_0 M QS_P {,} {,} M QS_P[..0] M QS_P N M R_RESET_N R9 M QS_P Y R QS_ R RMRST M OTPU 0/ M QS_P R OTPU T R9 W R QS_ // M QS_P U R QS_ M S_N M QS_P R S H M9 R QS_ M RS_N M S_N {,} M QS_P R RS L R QS_ M WE_N M RS_N {,} M QS_P R WE N 0 R QS_ M WE_N {,} R9 M QS_P0 R QS_ LK_00M_VN_MPLL_P R QS_0 R REFP J LK_00M_VN_MPLL_P {} 00K/ LK_00M_VN_MPLL_N {,} M QS_N[..0] LK_00M_VN_MPLL_N {} M QS_N R REFN L M QS_N W R QS M_RM_PWROK M_RM_PWROK {} M QS_N R QS R RM_PWROK L W PWRG_R_V PWRG_R_V {} M QS_N R V_PWROK N U R QS M QS_N L9 R QS R9 M VREF M QS_N R QS R VREF M QS_N 0 R QS M QS_N0 R QS R QS0 R9 K//X PVR M RESET_N {,} SYM OF VOTON/G/S/X PVR M VREF 0.u//XR/V/K/X R9 00///X R9 00// PLE LOSE TO PIN R9 Intel orporation 00_VN/RGY_LP_SM_MIS 000 W HNLER LV HNLER, Z Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

13 U {9} {9} {9} {9} {9} {9} {9} {9} {9} {9} {9} {9} {9} {9} {9} {9} PE_VN_SW_TX_P PE_VN_SW_TX_N PE_VN_SW_TX_P PE_VN_SW_TX_N PE_VN_SW_TX_P PE_VN_SW_TX_N PE_VN_SW_TX_P PE_VN_SW_TX_N PE_VN_SW_TX_P PE_VN_SW_TX_N PE_VN_SW_TX_P PE_VN_SW_TX_N PE_VN_SW_TX_P PE_VN_SW_TX_N PE_VN_SW_TX_P0 PE_VN_SW_TX_N0 {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} PE_VN_MUX_RX_P PE_VN_MUX_RX_N PE_VN_MUX_RX_P PE_VN_MUX_RX_N PE_VN_MUX_RX_P PE_VN_MUX_RX_N PE_VN_MUX_RX_P PE_VN_MUX_RX_N PE_VN_SLOT_RX_P PE_VN_SLOT_RX_N PE_VN_SLOT_RX_P PE_VN_SLOT_RX_N PE_VN_SLOT_RX_P PE_VN_SLOT_RX_N PE_VN_SLOT_RX_P0 PE_VN_SLOT_RX_N0 0.u//XR/V/K 0.u//XR/V/K 0.u//XR/V/K 0.u//XR/V/K 0.u//XR/V/K 0.u//XR/V/K 0.u//XR/V/K 0.u//XR/V/K 0.u//XR/V/K 0.u//XR/V/K 0.u//XR/V/K 0.u//XR/V/K 0.u//XR/V/K 0.u//XR/V/K 0.u//XR/V/K 0.u//XR/V/K PE_VN_SW_R_TX_P PE_VN_SW_R_TX_N PE_VN_SW_R_TX_P PE_VN_SW_R_TX_N PE_VN_SW_R_TX_P PE_VN_SW_R_TX_N PE_VN_SW_R_TX_P PE_VN_SW_R_TX_N PE_VN_SW_R_TX_P PE_VN_SW_R_TX_N PE_VN_SW_R_TX_P PE_VN_SW_R_TX_N PE_VN_SW_R_TX_P PE_VN_SW_R_TX_N PE_VN_SW_R_TX_P0 PE_VN_SW_R_TX_N0 E G F F G E G G H F G F G9 H9 E0 G0 F G F G H G H J K J H E E VOTON/RNGELEY PIE_RXP_ PIE_TXP_ PIE_RXN_ PIE_TXN_ PIE_RXP_ PIE_TXP_ PIE_RXN_ PIE_TXN_ PIE_RXP_ PIE_TXP_ PIE_RXN_ PIE_TXN_ PIE_RXP_ PIE_TXP_ PIE_RXN_ PIE_TXN_ PIE_RXP_ PIE_TXP_ PIE_RXN_ PIE_TXN_ PIE_RXP_0 PIE_TXP_0 PIE_RXN_0 PIE_TXN_0 PIE_RXP_9 PIE_TXP_9 PIE_RXN_9 PIE_TXN_9 PIE_RXP_ PIE_TXP_ PIE_RXN_ PIE_TXN_ PIE_RXP_ PIE_TXP_ PIE_RXN_ PIE_TXN_ PIE_RXP_ PIE_TXP_ PIE_RXN_ PIE_TXN_ PIE_RXP_ PIE_TXP_ PIE_RXN_ PIE_TXN_ PIE_RXP_ PIE_TXP_ PIE_RXN_ PIE_TXN_ PIE_RXP_ PIE_TXP_ PIE_RXN_ PIE_TXN_ PIE_RXP_ PIE_TXP_ PIE_RXN_ PIE_TXN_ PIE_RXP_ PIE_TXP_ PIE_RXN_ PIE_TXN_ PIE_RXP_0 PIE_TXP_0 PIE_RXN_0 PIE_TXN_0 PIE_OSP PIE_OSN N9 L9 M0 K0 L N P M N L N L N L P9 M9 N0 L0 L M N L M K L N L N L9 M K0 L PE_VN_SW_R_RX_P 0.u//XR/V/K PE_VN_SW_R_RX_N 0.u//XR/V/K PE_VN_SW_R_RX_P 0.u//XR/V/K PE_VN_SW_R_RX_N 0.u//XR/V/K PE_VN_SW_R_RX_P 0.u//XR/V/K PE_VN_SW_R_RX_N 0.u//XR/V/K PE_VN_SW_R_RX_P 0.u//XR/V/K PE_VN_SW_R_RX_N 0.u//XR/V/K PE_VN_SW_R_RX_P 0 0.u//XR/V/K PE_VN_SW_R_RX_N 0.u//XR/V/K PE_VN_SW_R_RX_P 0.u//XR/V/K PE_VN_SW_R_RX_N 0 0.u//XR/V/K PE_VN_SW_R_RX_P 0.u//XR/V/K PE_VN_SW_R_RX_N 0.u//XR/V/K PE_VN_SW_R_RX_P0 0.u//XR/V/K PE_VN_SW_R_RX_N0 0.u//XR/V/K PE_VN_MUX_TX_P {} PE_VN_MUX_TX_N {} PE_VN_MUX_TX_P {} PE_VN_MUX_TX_N {} PE_VN_MUX_TX_P {} PE_VN_MUX_TX_N {} PE_VN_MUX_TX_P {} PE_VN_MUX_TX_N {} PE_VN_SLOT_TX_P {} PE_VN_SLOT_TX_N {} PE_VN_SLOT_TX_P {} PE_VN_SLOT_TX_N {} PE_VN_SLOT_TX_P {} PE_VN_SLOT_TX_N {} PE_VN_SLOT_TX_P0 {} R 00///X PE_VN_SLOT_TX_N0 {} PIE_OSP R99 0// PIE_OSN PE_VN_SW_RX_P {9} PE_VN_SW_RX_N {9} PE_VN_SW_RX_P {9} PE_VN_SW_RX_N {9} PE_VN_SW_RX_P {9} PE_VN_SW_RX_N {9} PE_VN_SW_RX_P {9} PE_VN_SW_RX_N {9} PE_VN_SW_RX_P {9} PE_VN_SW_RX_N {9} PE_VN_SW_RX_P {9} PE_VN_SW_RX_N {9} PE_VN_SW_RX_P {9} PE_VN_SW_RX_N {9} PE_VN_SW_RX_P0 {9} PE_VN_SW_RX_N0 {9} PIE_REFLKP PIE_REFLKN 9 9 LK_00M_LKUF_PIE_P0 {} LK_00M_LKUF_PIE_N0 {} SYM OF VOTON/G/S/X Intel orporation 0_VN/RGY_PIE_GEN 000 W HNLER LV HNLER, Z Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

14 U {} {} {} {} {} {} {} {} SGMII_RX_P SGMII_RX_N SGMII_RX_P SGMII_RX_N SGMII_RX_P SGMII_RX_N SGMII_RX_P0 SGMII_RX_N0 SGMII_RX_P SGMII_RX_N SGMII_RX_P SGMII_RX_N SGMII_RX_P SGMII_RX_N SGMII_RX_P0 SGMII_RX_N n//XR/V/K.n//XR/V/K.n//XR/V/K.n//XR/V/K.n//XR/V/K.n//XR/V/K.n//XR/V/K.n//XR/V/K SGMII_RX_R_P SGMII_RX_R_N SGMII_RX_R_P SGMII_RX_R_N SGMII_RX_R_P SGMII_RX_R_N SGMII_RX_R_P0 SGMII_RX_R_N0 G H J L J L H K GE_RXP_ GE_RXN_ GE_RXP_ GE_RXN_ GE_RXP_ GE_RXN_ GE_RXP_0 GE_RXN_0 VOTON/RNGELEY GE_TXP_ GE_TXN_ GE_TXP_ GE_TXN_ GE_TXP_ GE_TXN_ GE_TXP_0 GE_TXN_0 SGMII_TX_R_P SGMII_TX_R_N SGMII_TX_R_P SGMII_TX_R_N SGMII_TX_R_P SGMII_TX_R_N SGMII_TX_R_P0 SGMII_TX_R_N0 SGMII_TX_R_P {} SGMII_TX_R_N {} SGMII_TX_R_P {} SGMII_TX_R_N {} SGMII_TX_R_P {} SGMII_TX_R_N {} SGMII_TX_R_P0 {} SGMII_TX_R_N0 {} {} {} {} LK_00M_VN_GbE_P LK_00M_VN_GbE_N {} PHY_M_I_LK PHY_MIO_I_T 0K// 0K// 0K// 0K// R00 R0 R0 R0 R0 0// LK_00M_VN_GbE_P LK_00M_VN_GbE_N SM_GE_MIO_LK SM_GE_MIO_T PHY_M_I_LK PHY_MIO_I_T LE_GE_ LE_GE_ LE_GE_ LE_GE_0 GE_OSP GE_OSN R P W0 P G0 H0 0 0 Y Y W W9 GE_LE GE_LE GE_LE GE_LE0 GE_OSP GE_OSN GE_REFLKP GE_REFLKN GE_MIO_I_LK GE_MIO_I_T GE_MIO0_I_LK GE_MIO0_I_T GE_SP0_ GE_SP0_0 GE_SMLRT GE_SMLK GE_SM GE_EE_S GE_EE_I GE_EE_O GE_EE_SK GE_WOL T T T P0 T9 R9 W W0 T0 V GE_SPO_ SPI_S_R_GE_N SPI_MOSI_R_GE SPI_MISO_GE SPI_LK_R_GE GE_WOL SM_LRT_GbE_LN_N SM_LK_GbE_LN SM_T_GbE_LN TP TP9 RN 0//X GE_SPO_ R0 0K/ SPI_S_GE_N SPI_MOSI_GE SPI_LK_GE 0/PR/ PMU_WKE_N R9 PV_STY PMU_WKE_N {0,9} PV0 TP0 U TP TP RSV0 RSV9 T TP TP L RSV RSV0 T TP TP J RSV RSV G0 INTVRMEN_VN R 0/ TP P RSV RSV Y9 RSV TP0 TP9 P0 RSV RSV R TP / R R RSV RSV P TP RSV //X R R RSV RSV L TP / R R RSV RSV J TP / R9 RSV RSV R0 0K/ R0 0K//X PV_STY SYM OF VOTON/G/S/X PV_STY PV_RT SM_LRT_GbE_LN_N SM_T_GbE_LN SM_LK_GbE_LN GE_WOL R0 K// R0 0K//X R0 0K//X R0 K///X INTVRMEN_VN R0 90K//X R09 0K//X PV_STY R00 0K// R0 0K// R0 0K// PV_STY SM_LRT_GbE_LN_N SM_T_GbE_LN SM_LK_GbE_LN JP0 0K/ R0 0K/ R0 SM_GE_MIO_T SM_GE_MIO_LK JP PH/*/K/./V/ PH/*/K/./V/ U PV_STY GbE debugged circuit for EV SPI_S_GE_N SPI_MISO_GE SPI_WP_GE_N R09 / SO_GE S# SO WP# V HOL# SK SPI_GE_HOL_N SPI_LK_GE 9 u//yv/v/z SI SPI_MOSI_GE PV0 R00 0/ 0.u//XR/V/K SMP M9-WMNTP/SO/S/[0HP-0-00R] MiniSMP/New/X R00 R009 0///X 0///X GE_OSP GE_OSN PV_STY K/ R0 SPI_GE_HOL_N R00 R0 0///X 0///X R0 0/ 0.u//XR/V/K SMP MiniSMP/New/X.K/ R SPI_WP_GE_N Intel orporation 0_VN/RGY_GbE 000 W HNLER LV HNLER, Z Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

15 UE {} {} {} {} {} {} {} {} STG_RX_P STG_RX_N STG_RX_P STG_RX_N STG_RX_P STG_RX_N STG_RX_P0 STG_RX_N0 STG_RX_P STG_RX_N STG_RX_P STG_RX_N STG_RX_P STG_RX_N STG_RX_P0 STG_RX_N0 0 0 E G G H H VOTON/RNGELEY ST_RXP_ ST_TXP_ ST_RXN_ ST_TXN_ ST_RXP_ ST_TXP_ ST_RXN_ ST_TXN_ ST_RXP_ ST_TXP_ ST_RXN_ ST_TXN_ ST_RXP_0 ST_TXP_0 ST_RXN_0 ST_TXN_0 E E STG_TX_P STG_TX_N STG_TX_P STG_TX_N STG_TX_P STG_TX_N STG_TX_P0 STG_TX_N u//XR/0V/K 0.0u//XR/0V/K 0.0u//XR/0V/K 0.0u//XR/0V/K 0.0u//XR/0V/K 0.0u//XR/0V/K 0.0u//XR/0V/K 0.0u//XR/0V/K STG TX_P {} STG TX_N {} STG TX_P {} STG TX_N {} STG TX_P {} STG TX_N {} STG TX_P0 {} STG TX_N0 {} {} {} {} {} STG_RX_P STG_RX_N STG_RX_P0 STG_RX_N0 STG_RX_P STG_RX_N STG_RX_P0 STG_RX_N0 L L M M ST_RXP_ ST_RXN_ ST_RXP_0 ST_RXN_0 ST_TXP_ ST_TXN_ ST_TXP_0 ST_TXN_0 R R R T STG_TX_P STG_TX_N STG_TX_P0 STG_TX_N u//XR/0V/K 0.0u//XR/0V/K 0.0u//XR/0V/K 0.0u//XR/0V/K STG TX_P {} STG TX_N {} STG TX_P0 {} STG TX_N0 {} {9} R 00///X R 0// XP_FX_PORT[0..] {0} _I_0 {} LE_ST_T_N {} LK_00M_LKUF_ST_P {} LK_00M_LKUF_ST_N XP_FX_PORT[0..] {9} XP_FX_PORT_LK {9} XP_FX_PORT_LK0 _I_0 LE_ST_T_N ST_OSP ST_OSN LK_00M_LKUF_ST_P LK_00M_LKUF_ST_N XP_FX_PORT XP_FX_PORT XP_FX_PORT XP_FX_PORT XP_FX_PORT XP_FX_PORT0 XP_FX_PORT9 XP_FX_PORT XP_FX_PORT XP_FX_PORT XP_FX_PORT XP_FX_PORT XP_FX_PORT XP_FX_PORT XP_FX_PORT XP_FX_PORT0 XP_FX_PORT_LK XP_FX_PORT_LK0 T L9 J L J L R9 Y W W T9 T0 Y9 W Y Y T R W Y V V ST_GP0 ST_LEN ST_OSP ST_OSN ST_REFLKP ST_REFLKN FX_PORT FX_PORT FX_PORT FX_PORT FX_PORT FX_PORT0 FX_PORT9 FX_PORT FX_PORT FX_PORT FX_PORT FX_PORT FX_PORT FX_PORT FX_PORT FX_PORT0 FX_PORT_LK FX_PORT_LK0 ST_GP0 ST_LEN ST_OSP ST_OSN ST_REFLKP ST_REFLKN US_P_ US_N_ US_P_ US_N_ US_P_ US_N_ US_P_0 US_N_0 US_OSP US_O0 H H R R L L9 Y R ST_OSP ST_OSN US_P_P US_P_N US_P_P US_P_N US_P_P US_P_N US_P0_P US_P0_N USO_F_N R0.0K// _I_ LE_SS_T_N LK_00M_VN_ST_P LK_00M_VN_ST_N _I_ {0} LE_SS_T_N {} LK_00M_VN_ST_P {} LK_00M_VN_ST_N {} US_P_P {} US_P_N {} US_P_P {} US_P_N {} US_P_P {} US_P_N {} US_P0_P {} US_P0_N {} USO_F_N {} R9 00///X R 0// US_ROMPI US_ROMPO T T _US_RIS R.// US_REFLKP US_REFLKN 0 0 LK_9M_VN_US_P {} LK_9M_VN_US_N {} SYM OF VOTON/G/S/X Intel orporation 0_VN/RGY_ST_US 000 W HNLER LV HNLER, Z Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

16 000 W HNLER LV HNLER, Z Intel orporation VR_PVP_VN_VSEN VR_PVP_VN_RTN VR_PV0_SENSE PV0_STY PVNN PV0_STY PV0 PV0 PV0 PV0 VKR PV0 PV0 PV0 PV0 V_PLLR0_VN V_PLLR_VN PV0_STY PV0 PV0 PV0 VKR0 PV0 PV0 V_PLLR_VN VKR0 VKR PV0_STY V_PLLR0_VN PV0 PV0 PV0 PV0 PV0 VR_PVP_VN_VSEN {} VR_PVP_VN_RTN {} VR_PV0_SENSE {0} Size ocument Number Rev ate: Sheet of Mohon Peak R eta 0_VN/RGY_POWER_I Wednesday, ugust, 0 Size ocument Number Rev ate: Sheet of Mohon Peak R eta 0_VN/RGY_POWER_I Wednesday, ugust, 0 Size ocument Number Rev ate: Sheet of Mohon Peak R eta 0_VN/RGY_POWER_I Wednesday, ugust, 0 0 u//xr/v/m 0 u//xr/v/m F 0///S F 0///S u//xr/v/m u//xr/v/m 0 u//xr/v/m 0 u//xr/v/m 9 u//xr/v/m 9 u//xr/v/m u//xr/.v/k u//xr/.v/k u//xr/v/m u//xr/v/m F0 0///S F0 0///S u//xr/v/m u//xr/v/m u//xr/v/m u//xr/v/m u//xr/v/m u//xr/v/m F 0///S F 0///S.u//XR/.V/M.u//XR/.V/M u//xr/v/m u//xr/v/m u//xr/.v/m u//xr/.v/m.u//xr/.v/m.u//xr/.v/m u//xr/v/m u//xr/v/m u//xr/v/m u//xr/v/m u//xr/.v/k u//xr/.v/k u//xr/v/k u//xr/v/k VOTON/RNGELEY SYM OF UH VOTON/G/S/X VOTON/RNGELEY SYM OF UH VOTON/G/S/X VR P0 W VR P0 W VR P0 W VR_0_P0 T VR_0_P0 T VR_0_P0 T VR_0_P0 T VR_0_P0 T VLLR P0 V0 VLLR P0 V VLLR P0 V VLLR P0 V VLLR P0 V VLLR_0_P0 U VLLR_0_P0 U VLLR_0_P0 U VLLR_0_P0 U VLLR_0_P0 U VR P0 VPUVISI0_P0_SENSE E VRMPUSI_P0_SENSE F PUVISI0_P0_SENSE F RMPUSI_P0_SENSE F VR P0 W V_ST_P0 K V_PIE_P0 W V_PIE_P0 W9 V_ST_P0 N VKR P0 W VKR_0_P0 U VKR_0_P0 T V_ST_P0 P V_ST_P0 N V_ST_P0 L V_PIE_P0 U9 V_PIE_P0 U V_PIE_P0 T V_PIE_P0 T V_PIE_P0 U V_PIE_P0 W V_ST_P0 L V_ST_P0 P VKR P0 V V_GE_P0 W V_GE_P0 V V_GE_P0 T VNN M VNN M VNN M9 VNN M VNN M VNN M9 VNN M VNN M VNN M VNN M VNN J9 VNN L VNN L9 VNN M VNN M VNN F9 VNN F VNN G VNN G9 VNN J VNN VNN 9 VPLLR P0 W VPLLR_0_P0 U VUS_P0 U VUS_P0 W VUS_P0 T VUSSUS_P0 T VPLL_ST_P0 T VPLL_ST_P0 R VPLL_ST_P0 R VPLL_GE_P0 W VPLL_GE_P0 V VPLL_PIE_P0 VPLL_PIE_P0 Y VPLL_ST_P0 T VREF_GE_HVGEN V9 VREF_GE_HVGEN T9 VREF_PIE_HVGEN T9 VREF_ST_HVGEN V VREF_ST_HVGEN W VREF_ST_HVGEN W VN_HS VN_HS_SK/X VN_HS VN_HS_SK/X R9 00K/ R9 00K/ u//xr/v/k u//xr/v/k F 0///S F 0///S u//xr/v/m u//xr/v/m u//xr/.v/k u//xr/.v/k.u//xr/.v/m.u//xr/.v/m u//xr/v/m u//xr/v/m 9 u//xr/v/m 9 u//xr/v/m u//xr/.v/k u//xr/.v/k u//xr/v/m u//xr/v/m u//xr/.v/k u//xr/.v/k u//xr/v/m u//xr/v/m.u//xr/.v/m.u//xr/.v/m u//xr/v/m u//xr/v/m u//xr/v/m u//xr/v/m.u//xr/.v/m.u//xr/.v/m u//xr/.v/k u//xr/.v/k.u//xr/.v/m.u//xr/.v/m u//xr/.v/k u//xr/.v/k u//xr/v/m u//xr/v/m 9 u//xr/v/m 9 u//xr/v/m u//xr/v/m u//xr/v/m 0 u//xr/.v/k 0 u//xr/.v/k u//xr/v/m u//xr/v/m 0 u//xr/v/m 0 u//xr/v/m

17 PLE T OTTOM OF THE OR 000 W HNLER LV HNLER, Z Intel orporation PVP PV0 PV0_STY PV0_STY PV_STY PV0 PV0 PV0 PV_RT PV_STY PV_STY PV PVR PVR PV_STY PV PV_STY PV PV PV PVR VLKR0 PVR VLKR VLKR0 VLKR PV PV0 Size ocument Number Rev ate: Sheet of Mohon Peak R eta 0_VN/RGY_POWER_II Wednesday, ugust, 0 Size ocument Number Rev ate: Sheet of Mohon Peak R eta 0_VN/RGY_POWER_II Wednesday, ugust, 0 Size ocument Number Rev ate: Sheet of Mohon Peak R eta 0_VN/RGY_POWER_II Wednesday, ugust, 0 u//xr/v/m u//xr/v/m u//xr/.v/m u//xr/.v/m F 0///S F 0///S u//xr/.v/k u//xr/.v/k 0 u//xr/v/m 0 u//xr/v/m u//xr/v/m u//xr/v/m u//xr/.v/m u//xr/.v/m u//xr/v/m u//xr/v/m 9 u//xr/v/m 9 u//xr/v/m TP TP u//xr/v/m u//xr/v/m SYM OF VOTON/RNGELEY UG VOTON/G/S/X SYM OF VOTON/RNGELEY UG VOTON/G/S/X VR P K VR P K VR P K VR P K VR P E VUSSUS_P U VUSSUS_P U VPXXXSUS_P F VPXXXSUS_P F VPXXXSUS_P VPXXXSI0_P J VRT_P G VPXXXSI0_P J VPXXXSI0_P L VR P E9 VR P J VR P H VR P G VR P G VR P H VR P K0 VR P N VR P L VR P L VR P L VR P M VR P P VR P N VR P P VR P P VR P P VR P R VR P R VR_0_P Y9 VR_0_P Y VR_0_P Y VR_0_P VR_0_P VR_0_P 0 VR_0_P VR_0_P VPUVISI0_P0 VPUVISI0_P0 E VPUVISI0_P0 VPUVISI0_P0 VPUVISI0_P0 VIGXXXSI0_P0 VIGXXXSI0_P0 F VIGXXXSI0_P0 G VIGXXXSI0_P0 J VIGXXXSUS_P0 VIGXXXSUS_P0 9 VIGXXXSUS_P0 VR_0_P F VR_0_P E VR_0_P VR_0_P VR_0_P E9 VR_0_P J VR_0_P H VR_0_P F VR_0_P G9 VR_0_P G VR_0_P L VR_0_P K VR_0_P K9 VR_0_P K VR_0_P K VR_0_P M9 VLKR P V9 VLKR P W9 VLKR_0_P T9 VLKR_0_P U9 VSFRPLLR P V VSFRPLLR_0_P T VSFRXXXSI0_P V VSFRXXXSI0_P W VSFRXXXSI0_P VSFRXXXSI0_P VIGXXXSUS_P0 VIGXXXSUS_P0 9 VIGXXXSUS_P0 VRMPUSI_P0 VRMPUSI_P0 VRMPUSI_P0 F9 VRMPUSI_P0 F VOREVISI0GT_P0 L VOREVISI0GT_P0 L VFHVPUSI0_MO_P0 J9 VFHVPUSI0_MO_P0 9 VFHVPUSI0_MO_P0 L VFHVPUSI0_MO0_P0 VRMPUSI0GT_MO_P0 J VFHVSOSI0_P0 VFHVSOSI0_P0 VUSSUS_P U VPXXXSUS_P VUSSUS_P W VPUVISI0_P0 F VPUVISI0_P0 F VPUVISI0_P0 F0 VPUVISI0_P0 F VPUVISI0_P0 E VPUVISI0_P0 G VPUVISI0_P0 G VPUVISI0_P0 G VPUVISI0_P0 F VPUVISI0_P0 F VPUVISI0_P0 G VPUVISI0_P0 G9 VPUVISI0_P0 G VPUVISI0_P0 G VPUVISI0_P0 G VPUVISI0_P0 H VPUVISI0_P0 H VPUVISI0_P0 H VPUVISI0_P0 H VPUVISI0_P0 H VPUVISI0_P0 H9 VPUVISI0_P0 H VPUVISI0_P0 H VPUVISI0_P0 H VPUVISI0_P0 H0 VPUVISI0_P0 J VPUVISI0_P0 J VPUVISI0_P0 J VPUVISI0_P0 J VPUVISI0_P0 J VPUVISI0_P0 L VPUVISI0_P0 J VPUVISI0_P0 L VPUVISI0_P0 K0 VPUVISI0_P0 J VPUVISI0_P0 L VPUVISI0_P0 L VRMPUSI_P0 G9 VRMPUSI_P0 G VRMPUSI_P0 G u//xr/.v/k u//xr/.v/k u//xr/.v/m u//xr/.v/m 9 u//xr/.v/k 9 u//xr/.v/k 90 u//xr/v/m 90 u//xr/v/m 0 u//xr/v/m 0 u//xr/v/m u//xr/.v/m u//xr/.v/m 9 u//xr/v/m 9 u//xr/v/m 0 u//xr/.v/k 0 u//xr/.v/k 0 u//xr/.v/k 0 u//xr/.v/k 0 u//xr/v/m 0 u//xr/v/m 9 u//xr/v/m 9 u//xr/v/m 99 u//xr/v/m 99 u//xr/v/m 9 u//xr/.v/k 9 u//xr/.v/k u//xr/.v/k u//xr/.v/k u//xr/.v/m u//xr/.v/m 00 u//xr/v/m 00 u//xr/v/m 9 0u//XR/.V/M 9 0u//XR/.V/M 0 u//xr/v/m 0 u//xr/v/m u//xr/v/m u//xr/v/m u//xr/.v/k u//xr/.v/k 0.u//XR/.V/K 0.u//XR/.V/K 0 u//xr/.v/k 0 u//xr/.v/k u//xr/v/m u//xr/v/m 9 u//xr/v/m 9 u//xr/v/m 9 u//xr/.v/k 9 u//xr/.v/k u//xr/.v/k u//xr/.v/k 0 u//xr/.v/k 0 u//xr/.v/k 09 u//xr/.v/k 09 u//xr/.v/k 0.u//XR/.V/K 0.u//XR/.V/K u//xr/.v/m u//xr/.v/m 0 0.u//XR/V/K 0 0.u//XR/V/K u//xr/v/m u//xr/v/m TP TP 9 u//xr/v/m 9 u//xr/v/m 0.u//XR/V/K 0.u//XR/V/K u//xr/.v/k u//xr/.v/k u//xr/v/m u//xr/v/m u//xr/v/m u//xr/v/m 9 u//xr/v/m 9 u//xr/v/m F 0///S F 0///S TP TP u//xr/v/m u//xr/v/m u//xr/v/m u//xr/v/m 0 u//xr/.v/k 0 u//xr/.v/k u//xr/v/m u//xr/v/m 9 u//xr/.v/k 9 u//xr/.v/k 0u//XR/.V/M 0u//XR/.V/M u//xr/.v/k u//xr/.v/k 0 u//xr/v/m 0 u//xr/v/m

18 000 W HNLER LV HNLER, Z Intel orporation Size ocument Number Rev ate: Sheet of Mohon Peak R eta 0_VN/RGY_ Wednesday, ugust, 0 Size ocument Number Rev ate: Sheet of Mohon Peak R eta 0_VN/RGY_ Wednesday, ugust, 0 Size ocument Number Rev ate: Sheet of Mohon Peak R eta 0_VN/RGY_ Wednesday, ugust, 0 SYM 0 OF VOTON/RNGELEY UJ VOTON/G/S/X SYM 0 OF VOTON/RNGELEY UJ VOTON/G/S/X U V V V W W9 W W9 W W W W W0 W W P R R R R9 R0 R R0 R T T T T T9 T U P P P P P P9 P P P P P P9 P P P L0 L9 L L L L L9 L K K K K K J J J J J H H H H H G G G G G G G G G G G G G0 G G F F M M9 N N P L L L L0 M M M0 M M M M M0 L L9 T T T T G N F E E SYM OF VOTON/RNGELEY UK VOTON/G/S/X SYM OF VOTON/RNGELEY UK VOTON/G/S/X G 0 0 W Y Y Y Y Y9 Y Y Y Y0 W V V V W W W W9 W W9 W W W T0 T T T R R R U U U U V V T T T T T T U9 9 W W H R R0 R R P R R P P P P9 N N N N0 N N N0 N N M M0 M M M M M M M M L0 L L L0 K K T T T9 T T T K K K J J J J9 H H H H9 H H M9 H H H H H H H M G G9 G VOTON/RNGELEY SYM OF UL VOTON/G/S/X VOTON/RNGELEY SYM OF UL VOTON/G/S/X E E E0 E L0 E E E E9 E E E E E E E0 E E E E E0 E9 E E E E E E9 E0 E E9 E E E E F F F F F G G G E _US W _US U VOTON/RNGELEY SYM 9 OF UI VOTON/G/S/X VOTON/RNGELEY SYM 9 OF UI VOTON/G/S/X W W W W9 W0 W W Y W9 Y J Y Y Y Y Y K K K K K K K9 K K K K0 K K J K K K P E E E E9 E E F F F F9 G F G G G G G H H H H0 H0 L K K K K K K K K9 K K K K K K9 K L9 K0 P P N N0 N M M M M M M M M M L L L L0 L P P P P P9 P P P P P0 P P P P P0

19 Need placed within 0. inches of the XP connector PV0_STY XP_VN_TO R // PV0 R 0/ XP_VN_TMS R // PV0 Need placed within. inches from VN/RGY XP_VN_PREQ_N OSFN_0 OSFN_0 R9 0/ XP_FX_PORT_LK0 {0} XP_VN_PREQ_N XP_VN_PRY_N OSFN_ XP_FX_PORT_LK0 {} {0} XP_VN_PRY_N OSFN_ R 0/ XP_FX_PORT_LK XP_FX_PORT_LK {} XP_FX_PORT0 OST_0 9 0 OST_0 XP_FX_PORT {} XP_FX_PORT0 XP_FX_PORT OST_ XP_FX_PORT {} OST_ XP_FX_PORT9 {} XP_FX_PORT XP_FX_PORT9 {} XP_FX_PORT OST_ OST_ XP_FX_PORT0 {} XP_FX_PORT XP_FX_PORT0 {} XP_FX_PORT OST_ OST_ XP_FX_PORT {} XP_FX_PORT XP_FX_PORT {} 9 0 XP_FX_PORT_LK R9 0//X OSFN_0 OSFN_0 OSFN_ OSFN_ XP_FX_PORT OST_0 OST_0 XP_FX_PORT {} XP_FX_PORT XP_FX_PORT {} XP_FX_PORT OST_ 9 0 OST_ XP_FX_PORT {} XP_FX_PORT XP_FX_PORT {} XP_FX_PORT OST_ OST_ XP_FX_PORT {} XP_FX_PORT XP_FX_PORT {} XP_FX_PORT OST_ OST_ XP_FX_PORT {} XP_FX_PORT XP_FX_PORT {} RSMRST_N R K/ RSMRST N HOOK0 9 0 HOOK LK_00M_XP_R_P {0,} RSMRST_N LK_00M_XP_R_P {} PWR_TN_XP_R HOOK HOOK LK_00M_XP_R_N V_OS_ V_OS_ LK_00M_XP_R_N {} {0,} PWRG_OREPWR PWRG_OREPWR R K/ XP_PWRG_IN HOOK HOOK XP_PU_RESET R0 K// RST_VN_N RTEST_VN_N HOOK HOOK RST_TN_XP_R R0 K///X PLTRST_N {0} RTEST_VN_N 9 0 SM_PV_HOST_T R 0/ S TO XP_VN_TO {0,0,,,,,0,} SM_PV_HOST_T XP_VN_TO {0} {0,0,,,,,0,} SM_PV_HOST_LK SM_PV_HOST_LK R 0/ SL TRST# XP_VN_TRST_N XP_VN_TRST_N {0} TP TP_XP0_TK TK TI XP_VN_TI XP_VN_TI {0} XP_VN_TK TK0 TMS XP_VN_TMS {0} XP_VN_TK XP_VN_TMS {0} 9 0 PU_XP T/*0/IV/0./V/S/GF/F/[0NH-0000-R] XP_VN_TI XP_VN_TK XP_VN_TRST_N RST_VN_N {0} PLTRST_N {0,,,,0,9,,} R // R9 // R0 // u//xr/.v/k XP_PU_RESET 0.u//XR/V/K/X PV_STY PV_STY PV_STY PV_STY R K/ 0.u//XR/V/K 0.u//XR/V/K 0.u//YV/V/Z/X U PWR_TN_XP_R R 00// XP_PWR_TN_R_N 0.u//XR/V/K R 00// U SNHGVR/SOT- R9 00// U SNHGVR/SOT- PWR_TN_XP_N SNLVG0GV/SOT- PWR_TN_VN_N {0} {} PWR_FP_TN_N_GTE PV PV PV PV R K/ 0.u//XR/V/K 0.u//XR/V/K 0.u//YV/V/Z/X U90 RST_TN_XP_R R 00// XP_RST_TN_R_N 0.u//XR/V/K R 00// U SNHGVR/SOT- R 00// U9 SNHGVR/SOT- RST_TN_XP_N SNLVG0GV/SOT- RST_TN_VN_N {0} {} RST_FP_TN_N_GTE Intel orporation 09_VN/RGY_XP 000 W HNLER LV HNLER, Z Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of 9

20 LUE OLOR SOKET HNNEL IMM 0 - LUE ONN RESS = 0x0 PLE LOSE TO PIN Y9 000 W HNLER LV HNLER, Z Intel orporation M QS_N[0:] M QS_P[0:] M QS_P M QS_P M QS_P M QS_P M QS_N M QS_N M QS_N M QS_N M QS_P M QS_P M QS_N M QS_N M QS_P M QS_P M QS_P M QS_P M QS_N M QS_N M QS_N M QS_N M QS_P M QS_P M QS_P M QS_P M QS_N M QS_N M QS_P M QS_P M QS_N0 M QS_N0 M QS_P0 M QS_P0 M QS_N M QS_N M QS_N M QS_N M RESET_N M E0 M M0 M M M S M M M M M M M M M M M M M M0 M M9 M M M M M M M M M M M M M S M S0 M Q[0:] M K_N M K_P M S_N M S_N0 M KE0 M KE M WE_N M OT0 M OT M RS_N M S_N M E[0:] M Q0 M Q M Q M Q M Q M Q M Q M S[..0] M Q M Q M Q M Q9 M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q0 M Q M Q M Q9 M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q9 M Q M Q M Q M Q M Q M Q M Q9 M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M M[0:] SM_PV_HOST_T SM_PV_HOST_LK M E M E M E M E M E M E M E M K_P0 M K_N0 H_MEMHOT_O_N PV_R_VREF_H_Q0 PV_R_VREF_H_ PV_R_VREF_H_ H_MEMHOT_O_N PV PVR PVTT_ PVR PVTT_ PVR PV_R_VREF_H_Q0 PVTT_ PV M K_P0 {} M S_N {,} M Q[0:] {,} M K_N {} M RESET_N {,} M K_P {} M S[..0] {,} M M[0:] {,} M KE0 {} SM_PV_HOST_T {0,9,,,,,0,} M KE {} M OT0 {} M S_N0 {} M E[0:] {,} SM_PV_HOST_LK {0,9,,,,,0,} M K_N0 {} M WE_N {,} M OT {} M S_N {} M RS_N {,} M QS_P[0:] {,} M QS_N[0:] {,} H_MEMHOT_O_N {0,,,} PV_R_VREF_H_ {} M QS_P {,} M QS_N {,} Size ocument Number Rev ate: Sheet of Mohon Peak R eta 00_R_SLOT_IMM0_H 0 Wednesday, ugust, 0 Size ocument Number Rev ate: Sheet of Mohon Peak R eta 00_R_SLOT_IMM0_H 0 Wednesday, ugust, 0 Size ocument Number Rev ate: Sheet of Mohon Peak R eta 00_R_SLOT_IMM0_H 0 Wednesday, ugust, 0 0u//XR/.V/M 0u//XR/.V/M 0u//XR/.V/M 0u//XR/.V/M u//xr/v/k u//xr/v/k 0u//XR/.V/M 0u//XR/.V/M 0u//XR/.V/M 0u//XR/.V/M R 00// R 00// R.K/ R.K/ 0.u//XR/V/K 0.u//XR/V/K R9 0//X R9 0//X R 00// R 00// R / R_ R/0/U/V//G R / R_ R/0/U/V//G <> <> <> <> <> <> <> 0 <> <0> <9> 9 <> <> <> <> <> <> <> 0 <> <0> <9> 9 <> 9 <> 9 <> 9 <> 0 <> 0 <> 0 <> 0 <> <0> <9> <> <> <> 0 <> <> <> 9 <> <> <0> <9> <> <> <> 0 <> <> <> 99 <> 0 <> 0 <0> 0 <9> <> <> <> 0 <> <> <> 9 <> <> <0> 9 V<> V<0> V<9> V<> 0 V<> V<> V<> V<> 9 V<> V<> V<> V<0> 0 V<9> V<> V<> 9 V<> V<> V<> V<> 9 V<> 9 V<> 9 V<0> 9 VTT<> 9 VTT<> VTT<> 0 VTT<0> 0 N_TEST R / R_ R/0/U/V//G R / R_ R/0/U/V//G _(I) <>(I) <>(I) <>(I) 9 <>(I) <>(I) <0>(I) 0 <9>(I) <>(I) <>(I) <>(I) <>(I) <>(I) 9 <>(I) 0 <>(I) <>(I) <0>(I) Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<0>(I/O) Q<9>(I/O) Q<>(I/O) Q<>(I/O) 09 Q<>(I/O) 0 Q<>(I/O) Q<>(I/O) Q<>(I/O) 9 Q<>(I/O) Q<>(I/O) 0 Q<0>(I/O) 0 Q<9>(I/O) 00 Q<>(I/O) 99 Q<>(I/O) Q<>(I/O) Q<>(I/O) 0 Q<>(I/O) 09 Q<>(I/O) 9 Q<>(I/O) 9 Q<>(I/O) 9 Q<0>(I/O) 90 Q<9>(I/O) 0 Q<>(I/O) 0 Q<>(I/O) 0 Q<>(I/O) 00 Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<0>(I/O) Q<9>(I/O) 0 Q<>(I/O) 9 Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<>(I/O) 0 Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<0>(I/O) 0 Q<9>(I/O) Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<>(I/O) 9 Q<0>(I/O) Q<9>(I/O) Q<>(I/O) Q<>(I/O) 9 Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<>(I/O) 0 Q<>(I/O) 9 Q<>(I/O) Q<0>(I/O) <>(I) 90 <0>(I) N_KP(I) N_KN(I) K0P(I) K0N(I) S<>(I) 9 S<>(I) 9 S<>(I) S<0>(I) 9 KE<>(I) 9 KE<0>(I) 0 WE_N(I) RS_N(I) 9 S_N(I) OT<>(I) OT<0>(I) 9 PR_IN_N(I) ERR_OUT_N(O) <>(I/O) <>(I/O) <>(I/O) 9 <>(I/O) <>(I/O) <>(I/O) <>(I/O) 0 <0>(I/O) 9 RESET_N(I) VSP S<>(I) 9 S<>(I) S<0>(I) S(I/O) SL(I) EVENT_N_N(O) VREFQ VREF 0.u//XR/V/K 0.u//XR/V/K R / R_ R/0/U/V//G R / R_ R/0/U/V//G QSP_M(I/O) QSN_N(I/O) QSP_M(I/O) 0 QSN_N(I/O) QSP_M(I/O) QSN_N(I/O) QSP_M(I/O) QSN_N(I/O) QSP_M(I/O) 0 QSN_N(I/O) 0 QSP_M(I/O) QSN_N(I/O) QSP_M(I/O) QSN_N(I/O) QS0P_M(I/O) QS0N_N(I/O) QS9P_M0(I/O) QS9N_N(I/O) QSP(I/O) QSN(I/O) QSP(I/O) QSN(I/O) QSP(I/O) 0 QSN(I/O) 0 QSP(I/O) 9 QSN(I/O) 9 QSP(I/O) QSN(I/O) QSP(I/O) QSN(I/O) QSP(I/O) QSN(I/O) QSP(I/O) QSN(I/O) QS0P(I/O) QS0N(I/O) u//xr/v/k u//xr/v/k

21 HNNEL IMM 0 - LUE ONN RESS = 0x LUE OLOR SOKET PLE LOSE TO PIN Y9 000 W HNLER LV HNLER, Z Intel orporation M QS_N[0:] M QS_P[0:] M QS_P M QS_N M QS_P M QS_P M QS_N M QS_P M QS_P M QS_N M QS_P M QS_N M QS_N M QS_P M QS_P M QS_P0 M QS_N M QS_N0 M QS_N M QS_N M E M E M E M E M RESET_N M M M S M M M E0 M M M M M M M M M M0 M M0 M M9 M M M M M M M M M M M M M M M S0 M S M Q[0:] M K_P0 M K_N0 M E M K_N M K_P M WE_N M OT0 M OT M RS_N M S_N M KE0 M KE M Q M E[0:] M Q M Q M Q M S[..0] M Q0 M Q M Q M Q M Q9 M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q9 M Q M Q M Q M Q M Q9 M Q M Q0 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q9 M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M M[0:] SM_PV_HOST_T SM_PV_HOST_LK M E M E H_MEMHOT_O_N PV_R_VREF_H_Q0 PV_R_VREF_H_ M S_N M S_N0 PV_R_VREF_H_ PV PVR PVTT_ PVR PVTT_ PV_R_VREF_H_Q0 PVR PVTT_ M OT0 {} M M[0:] {,} M KE {} M E[0:] {,} M OT {} M WE_N {,} M RS_N {,} M S_N {,} SM_PV_HOST_T {0,9,0,,,,0,} SM_PV_HOST_LK {0,9,0,,,,0,} M K_N0 {} M RESET_N {,} M K_P0 {} M Q[0:] {,} M K_N {} M S[..0] {,} M K_P {} M KE0 {} M QS_P[0:] {,} M QS_N[0:] {,} H_MEMHOT_O_N {0,0,,} PV_R_VREF_H_ {} M QS_P {,} M QS_N {,} M S_N0 {} M S_N {} Size ocument Number Rev ate: Sheet of Mohon Peak R eta 0_R_SLOT_IMM0_H Wednesday, ugust, 0 Size ocument Number Rev ate: Sheet of Mohon Peak R eta 0_R_SLOT_IMM0_H Wednesday, ugust, 0 Size ocument Number Rev ate: Sheet of Mohon Peak R eta 0_R_SLOT_IMM0_H Wednesday, ugust, 0 9 u//xr/v/k 9 u//xr/v/k R9 0//X R9 0//X R / R_ R/0/U/V//G R / R_ R/0/U/V//G _(I) <>(I) <>(I) <>(I) 9 <>(I) <>(I) <0>(I) 0 <9>(I) <>(I) <>(I) <>(I) <>(I) <>(I) 9 <>(I) 0 <>(I) <>(I) <0>(I) Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<0>(I/O) Q<9>(I/O) Q<>(I/O) Q<>(I/O) 09 Q<>(I/O) 0 Q<>(I/O) Q<>(I/O) Q<>(I/O) 9 Q<>(I/O) Q<>(I/O) 0 Q<0>(I/O) 0 Q<9>(I/O) 00 Q<>(I/O) 99 Q<>(I/O) Q<>(I/O) Q<>(I/O) 0 Q<>(I/O) 09 Q<>(I/O) 9 Q<>(I/O) 9 Q<>(I/O) 9 Q<0>(I/O) 90 Q<9>(I/O) 0 Q<>(I/O) 0 Q<>(I/O) 0 Q<>(I/O) 00 Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<0>(I/O) Q<9>(I/O) 0 Q<>(I/O) 9 Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<>(I/O) 0 Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<0>(I/O) 0 Q<9>(I/O) Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<>(I/O) 9 Q<0>(I/O) Q<9>(I/O) Q<>(I/O) Q<>(I/O) 9 Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<>(I/O) 0 Q<>(I/O) 9 Q<>(I/O) Q<0>(I/O) <>(I) 90 <0>(I) N_KP(I) N_KN(I) K0P(I) K0N(I) S<>(I) 9 S<>(I) 9 S<>(I) S<0>(I) 9 KE<>(I) 9 KE<0>(I) 0 WE_N(I) RS_N(I) 9 S_N(I) OT<>(I) OT<0>(I) 9 PR_IN_N(I) ERR_OUT_N(O) <>(I/O) <>(I/O) <>(I/O) 9 <>(I/O) <>(I/O) <>(I/O) <>(I/O) 0 <0>(I/O) 9 RESET_N(I) VSP S<>(I) 9 S<>(I) S<0>(I) S(I/O) SL(I) EVENT_N_N(O) VREFQ VREF 0 u//xr/v/k 0 u//xr/v/k R 00// R 00// 0.u//XR/V/K 0.u//XR/V/K 0u//XR/.V/M 0u//XR/.V/M 0.u//XR/V/K 0.u//XR/V/K R 00// R 00// 0u//XR/.V/M 0u//XR/.V/M 9 0u//XR/.V/M 9 0u//XR/.V/M R / R_ R/0/U/V//G R / R_ R/0/U/V//G <> <> <> <> <> <> <> 0 <> <0> <9> 9 <> <> <> <> <> <> <> 0 <> <0> <9> 9 <> 9 <> 9 <> 9 <> 0 <> 0 <> 0 <> 0 <> <0> <9> <> <> <> 0 <> <> <> 9 <> <> <0> <9> <> <> <> 0 <> <> <> 99 <> 0 <> 0 <0> 0 <9> <> <> <> 0 <> <> <> 9 <> <> <0> 9 V<> V<0> V<9> V<> 0 V<> V<> V<> V<> 9 V<> V<> V<> V<0> 0 V<9> V<> V<> 9 V<> V<> V<> V<> 9 V<> 9 V<> 9 V<0> 9 VTT<> 9 VTT<> VTT<> 0 VTT<0> 0 N_TEST R / R_ R/0/U/V//G R / R_ R/0/U/V//G QSP_M(I/O) QSN_N(I/O) QSP_M(I/O) 0 QSN_N(I/O) QSP_M(I/O) QSN_N(I/O) QSP_M(I/O) QSN_N(I/O) QSP_M(I/O) 0 QSN_N(I/O) 0 QSP_M(I/O) QSN_N(I/O) QSP_M(I/O) QSN_N(I/O) QS0P_M(I/O) QS0N_N(I/O) QS9P_M0(I/O) QS9N_N(I/O) QSP(I/O) QSN(I/O) QSP(I/O) QSN(I/O) QSP(I/O) 0 QSN(I/O) 0 QSP(I/O) 9 QSN(I/O) 9 QSP(I/O) QSN(I/O) QSP(I/O) QSN(I/O) QSP(I/O) QSN(I/O) QSP(I/O) QSN(I/O) QS0P(I/O) QS0N(I/O) 0 0u//XR/.V/M 0 0u//XR/.V/M

22 LK OLOR SOKET HNNEL IMM - LK ONN RESS = 0x 000 W HNLER LV HNLER, Z Intel orporation M RESET_N M E0 M M0 M M M S M M M M M M M M M M M M M M0 M M9 M M M M M M M M M M M M M S M S0 M Q[0:] M K_N M K_P M KE M KE M WE_N M OT M OT M RS_N M S_N M E[0:] M Q0 M Q M Q M Q M Q M Q M Q M S[..0] M Q M Q M Q M Q9 M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M QS_P[0:] M QS_N[0:] M QS_P M Q M Q0 M Q0 M Q M Q M QS_N M QS_P M QS_P M QS_N M QS_N M QS_P M Q9 M Q M Q M Q M Q M QS_P M QS_N M QS_P M QS_N M QS_N M Q9 M Q0 M Q M Q M Q M Q M QS_P M QS_P M QS_P0 M QS_N0 M Q M Q M Q M Q M Q M Q M Q M Q0 M Q9 M Q M QS_N M QS_N M Q M Q M Q M Q M Q M Q9 M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M M[0:] SM_PV_HOST_T SM_PV_HOST_LK M E M E M E M E M E M E M E M K_P M K_N H_MEMHOT_O_N PV_R_VREF_H_Q PV_R_VREF_H_ M S_N M S_N PV PVTT_ PVR PVR PVTT_ PV_R_VREF_H_Q M K_P {} M K_N {} M K_P {} M OT {} M S[..0] {,0} M M[0:] {,0} M K_N {} M Q[0:] {,0} SM_PV_HOST_T {0,9,0,,,,0,} SM_PV_HOST_LK {0,9,0,,,,0,} M S_N {,0} M WE_N {,0} M RS_N {,0} M RESET_N {,0} M KE {} M E[0:] {,0} M KE {} M OT {} M QS_P[0:] {,0} M QS_N[0:] {,0} H_MEMHOT_O_N {0,0,,} PV_R_VREF_H_ {0} M QS_P {,0} M QS_N {,0} M S_N {} M S_N {} Size ocument Number Rev ate: Sheet of Mohon Peak R eta 0_R_SLOT_IMM_H Wednesday, ugust, 0 Size ocument Number Rev ate: Sheet of Mohon Peak R eta 0_R_SLOT_IMM_H Wednesday, ugust, 0 Size ocument Number Rev ate: Sheet of Mohon Peak R eta 0_R_SLOT_IMM_H Wednesday, ugust, 0 R / R_ R/0/K/V//G R / R_ R/0/K/V//G _(I) <>(I) <>(I) <>(I) 9 <>(I) <>(I) <0>(I) 0 <9>(I) <>(I) <>(I) <>(I) <>(I) <>(I) 9 <>(I) 0 <>(I) <>(I) <0>(I) Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<0>(I/O) Q<9>(I/O) Q<>(I/O) Q<>(I/O) 09 Q<>(I/O) 0 Q<>(I/O) Q<>(I/O) Q<>(I/O) 9 Q<>(I/O) Q<>(I/O) 0 Q<0>(I/O) 0 Q<9>(I/O) 00 Q<>(I/O) 99 Q<>(I/O) Q<>(I/O) Q<>(I/O) 0 Q<>(I/O) 09 Q<>(I/O) 9 Q<>(I/O) 9 Q<>(I/O) 9 Q<0>(I/O) 90 Q<9>(I/O) 0 Q<>(I/O) 0 Q<>(I/O) 0 Q<>(I/O) 00 Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<0>(I/O) Q<9>(I/O) 0 Q<>(I/O) 9 Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<>(I/O) 0 Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<0>(I/O) 0 Q<9>(I/O) Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<>(I/O) 9 Q<0>(I/O) Q<9>(I/O) Q<>(I/O) Q<>(I/O) 9 Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<>(I/O) 0 Q<>(I/O) 9 Q<>(I/O) Q<0>(I/O) <>(I) 90 <0>(I) N_KP(I) N_KN(I) K0P(I) K0N(I) S<>(I) 9 S<>(I) 9 S<>(I) S<0>(I) 9 KE<>(I) 9 KE<0>(I) 0 WE_N(I) RS_N(I) 9 S_N(I) OT<>(I) OT<0>(I) 9 PR_IN_N(I) ERR_OUT_N(O) <>(I/O) <>(I/O) <>(I/O) 9 <>(I/O) <>(I/O) <>(I/O) <>(I/O) 0 <0>(I/O) 9 RESET_N(I) VSP S<>(I) 9 S<>(I) S<0>(I) S(I/O) SL(I) EVENT_N_N(O) VREFQ VREF 0.u//XR/V/K 0.u//XR/V/K 0u//XR/.V/M 0u//XR/.V/M 0u//XR/.V/M 0u//XR/.V/M R / R_ R/0/K/V//G R / R_ R/0/K/V//G QSP_M(I/O) QSN_N(I/O) QSP_M(I/O) 0 QSN_N(I/O) QSP_M(I/O) QSN_N(I/O) QSP_M(I/O) QSN_N(I/O) QSP_M(I/O) 0 QSN_N(I/O) 0 QSP_M(I/O) QSN_N(I/O) QSP_M(I/O) QSN_N(I/O) QS0P_M(I/O) QS0N_N(I/O) QS9P_M0(I/O) QS9N_N(I/O) QSP(I/O) QSN(I/O) QSP(I/O) QSN(I/O) QSP(I/O) 0 QSN(I/O) 0 QSP(I/O) 9 QSN(I/O) 9 QSP(I/O) QSN(I/O) QSP(I/O) QSN(I/O) QSP(I/O) QSN(I/O) QSP(I/O) QSN(I/O) QS0P(I/O) QS0N(I/O) 0u//XR/.V/M 0u//XR/.V/M 0u//XR/.V/M 0u//XR/.V/M R / R_ R/0/K/V//G R / R_ R/0/K/V//G <> <> <> <> <> <> <> 0 <> <0> <9> 9 <> <> <> <> <> <> <> 0 <> <0> <9> 9 <> 9 <> 9 <> 9 <> 0 <> 0 <> 0 <> 0 <> <0> <9> <> <> <> 0 <> <> <> 9 <> <> <0> <9> <> <> <> 0 <> <> <> 99 <> 0 <> 0 <0> 0 <9> <> <> <> 0 <> <> <> 9 <> <> <0> 9 V<> V<0> V<9> V<> 0 V<> V<> V<> V<> 9 V<> V<> V<> V<0> 0 V<9> V<> V<> 9 V<> V<> V<> V<> 9 V<> 9 V<> 9 V<0> 9 VTT<> 9 VTT<> VTT<> 0 VTT<0> 0 N_TEST

23 LK OLOR SOKET HNNEL IMM - LK ONN RESS = 0x 000 W HNLER LV HNLER, Z Intel orporation M QS_N[0:] M QS_P[0:] M QS_P M QS_N M QS_P M QS_P M QS_N M QS_N0 M QS_N M QS_P0 M QS_P M QS_P M QS_P M QS_P M QS_N M QS_N M QS_N M QS_P M QS_N M QS_N M E M E M E M E M RESET_N M M M S M M M E0 M M M M M M M M M M0 M M0 M M9 M M M M M M M M M M M M M M M S0 M S M Q[0:] M K_P M K_N M E M K_N M K_P M WE_N M OT M OT M RS_N M S_N M KE M KE M Q M E[0:] M Q M Q M Q M S[..0] M Q0 M Q M Q M Q M Q9 M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q9 M Q M Q M Q M Q M Q9 M Q M Q0 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q9 M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M M[0:] SM_PV_HOST_T SM_PV_HOST_LK M E M E H_MEMHOT_O_N PV_R_VREF_H_Q PV_R_VREF_H_ M S_N M S_N PV PVR PVTT_ PVR PVTT_ PV_R_VREF_H_Q M K_N {} M K_P {} M K_N {} M KE {} M K_P {} M M[0:] {,} M S[..0] {,} M OT {} M E[0:] {,} M KE {} M Q[0:] {,} SM_PV_HOST_T {0,9,0,,,,0,} SM_PV_HOST_LK {0,9,0,,,,0,} M OT {} M WE_N {,} M RESET_N {,} M RS_N {,} M S_N {,} M QS_P[0:] {,} M QS_N[0:] {,} H_MEMHOT_O_N {0,0,,} M S_N {} M S_N {} PV_R_VREF_H_ {} M QS_P {,} M QS_N {,} Size ocument Number Rev ate: Sheet of Mohon Peak R eta 0_R_SLOT_IMM_H Wednesday, ugust, 0 Size ocument Number Rev ate: Sheet of Mohon Peak R eta 0_R_SLOT_IMM_H Wednesday, ugust, 0 Size ocument Number Rev ate: Sheet of Mohon Peak R eta 0_R_SLOT_IMM_H Wednesday, ugust, 0 R / R_ R/0/K/V//G R / R_ R/0/K/V//G <> <> <> <> <> <> <> 0 <> <0> <9> 9 <> <> <> <> <> <> <> 0 <> <0> <9> 9 <> 9 <> 9 <> 9 <> 0 <> 0 <> 0 <> 0 <> <0> <9> <> <> <> 0 <> <> <> 9 <> <> <0> <9> <> <> <> 0 <> <> <> 99 <> 0 <> 0 <0> 0 <9> <> <> <> 0 <> <> <> 9 <> <> <0> 9 V<> V<0> V<9> V<> 0 V<> V<> V<> V<> 9 V<> V<> V<> V<0> 0 V<9> V<> V<> 9 V<> V<> V<> V<> 9 V<> 9 V<> 9 V<0> 9 VTT<> 9 VTT<> VTT<> 0 VTT<0> 0 N_TEST 0u//XR/.V/M 0u//XR/.V/M R / R_ R/0/K/V//G R / R_ R/0/K/V//G QSP_M(I/O) QSN_N(I/O) QSP_M(I/O) 0 QSN_N(I/O) QSP_M(I/O) QSN_N(I/O) QSP_M(I/O) QSN_N(I/O) QSP_M(I/O) 0 QSN_N(I/O) 0 QSP_M(I/O) QSN_N(I/O) QSP_M(I/O) QSN_N(I/O) QS0P_M(I/O) QS0N_N(I/O) QS9P_M0(I/O) QS9N_N(I/O) QSP(I/O) QSN(I/O) QSP(I/O) QSN(I/O) QSP(I/O) 0 QSN(I/O) 0 QSP(I/O) 9 QSN(I/O) 9 QSP(I/O) QSN(I/O) QSP(I/O) QSN(I/O) QSP(I/O) QSN(I/O) QSP(I/O) QSN(I/O) QS0P(I/O) QS0N(I/O) R / R_ R/0/K/V//G R / R_ R/0/K/V//G _(I) <>(I) <>(I) <>(I) 9 <>(I) <>(I) <0>(I) 0 <9>(I) <>(I) <>(I) <>(I) <>(I) <>(I) 9 <>(I) 0 <>(I) <>(I) <0>(I) Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<0>(I/O) Q<9>(I/O) Q<>(I/O) Q<>(I/O) 09 Q<>(I/O) 0 Q<>(I/O) Q<>(I/O) Q<>(I/O) 9 Q<>(I/O) Q<>(I/O) 0 Q<0>(I/O) 0 Q<9>(I/O) 00 Q<>(I/O) 99 Q<>(I/O) Q<>(I/O) Q<>(I/O) 0 Q<>(I/O) 09 Q<>(I/O) 9 Q<>(I/O) 9 Q<>(I/O) 9 Q<0>(I/O) 90 Q<9>(I/O) 0 Q<>(I/O) 0 Q<>(I/O) 0 Q<>(I/O) 00 Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<0>(I/O) Q<9>(I/O) 0 Q<>(I/O) 9 Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<>(I/O) 0 Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<0>(I/O) 0 Q<9>(I/O) Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<>(I/O) 9 Q<0>(I/O) Q<9>(I/O) Q<>(I/O) Q<>(I/O) 9 Q<>(I/O) Q<>(I/O) Q<>(I/O) Q<>(I/O) 0 Q<>(I/O) 9 Q<>(I/O) Q<0>(I/O) <>(I) 90 <0>(I) N_KP(I) N_KN(I) K0P(I) K0N(I) S<>(I) 9 S<>(I) 9 S<>(I) S<0>(I) 9 KE<>(I) 9 KE<0>(I) 0 WE_N(I) RS_N(I) 9 S_N(I) OT<>(I) OT<0>(I) 9 PR_IN_N(I) ERR_OUT_N(O) <>(I/O) <>(I/O) <>(I/O) 9 <>(I/O) <>(I/O) <>(I/O) <>(I/O) 0 <0>(I/O) 9 RESET_N(I) VSP S<>(I) 9 S<>(I) S<0>(I) S(I/O) SL(I) EVENT_N_N(O) VREFQ VREF 9 0u//XR/.V/M 9 0u//XR/.V/M 0 0u//XR/.V/M 0 0u//XR/.V/M 0u//XR/.V/M 0u//XR/.V/M 0.u//XR/V/K 0.u//XR/V/K

24 PV_STY PV_STY F PV_LK_XTL F 0///S 0///S R./ PV_LK_PI 0.u//XR/V/K 0u//XR/V/K 9 XTL_LK_GEN_OUT PV_STY R./ R9./ R./ 0u//XR/V/K 0u//XR/V/K PV_STY PV_LK_V R PV_LK_V_ORE_ 0.u//XR/V/K F 0.u//XR/V/K 0///S PV_LK_VIF PV_LK_SR {,,} {,,} 0u//XR/V/K R.// SM_PV_STY_HOST_T SM_PV_STY_HOST_LK {0} 0.u//XR/V/K 0 0u//XR/V/K LK_M_VN 0.u//XR/V/K 0.u//XR/V/K LKPWRG LKPWRG_L SM_PV_STY_HOST_T SM_PV_STY_HOST_LK LK_M_VN R0 0.u//XR/V/K 0.u//XR/V/K 0//X R0 0K///X PV_LK_V PV_LK_V_ORE_ PV_LK_VIF PV_LK_SR ddress : 0x R9 / R9 K/ 0.u//XR/V/K R K/ LK_M_VN_ R9 K//X R 0//X 0 0 U V V V_ORE_. V_ORE_. VSR_LVIO PI_STOP#_. 9 PI_F_x 0 PI_x LKREQ#/PI_x vsel_pi/m_pi_x 9 VREF VPI_. VIF_ORE_. ST_. SLK_. LKREQ# LKPWRG/P#_. vref0_x/fsl US_Mhz_x TPad IT9VRS0 X X SR_LRS 9 SR#_LRS SR_LRS SR#_LRS SR_LRS SR#_LRS SR_LRS 9 SR#_LRS SR_LRS SR#_LRS OT9_LRS/SR_LRS 9 OT9#_LRS/SR#_LRS 0 ST_LRS ST#_LRS IF0_LRS IF0#_LRS IF_LRS IF#_LRS IF_STOP#_. PI ST SR SR IF REF R X XTL_LK_GEN_IN 9 p//npo/0v/j.m/0p/0ppm/*./0/s/[0xt--0r] LK_00M_XP_R_P LK_00M_XP_R_P {9} LK_00M_XP_R_N LK_00M_XP_R_N {9} To XP LK_00M_VN_HFHPLL_P LK_00M_VN_HFHPLL_P {0} LK_00M_VN_HFHPLL_N LK_00M_VN_HFHPLL_N {0} To VN/RGY HFHPLL LK_00M_VN_MPLL0_P LK_00M_VN_MPLL0_P {} LK_00M_VN_MPLL0_N LK_00M_VN_MPLL0_N {} To VN/RGY MPLL0 LK_00M_VN_MPLL_P LK_00M_VN_MPLL_P {} LK_00M_VN_MPLL_N LK_00M_VN_MPLL_N {} ToVN/RGY MPLL LK_00M_LKUFF_P LK_00M_LKUFF_P {} LK_00M_LKUFF_N LK_00M_LKUFF_N {} To LOK UFFER LK_9M_VN_US_P LK_9M_VN_US_P {} LK_9M_VN_US_N LK_9M_VN_US_N {} To VN/RGY US LK_00M_VN_ST_P LK_00M_VN_ST_P {} LK_00M_VN_ST_N LK_00M_VN_ST_N {} To VN/RGY ST LK_00M_VN_GbE_P LK_00M_VN_GbE_P {} LK_00M_VN_GbE_N LK_00M_VN_GbE_N {} To VN/RGY GbE PV_STY R.K/ 0/ 0 p//npo/0v/j 0u//XR/V/K 0.u//XR/V/K 9VRS0KLFT-IN0/QFN/S PV PV U0 0.u//XR/V/K R.K/ PV_STY u//xr/.v/k LVGGV/SOT LKPG R0 / LKPWRG LKPWRG {} R0 0.K/ PV LK_M_VN JP R0 PH/*/K/./V/ 9 0.u//XR/V/K 0K/ JP LKPG R0 00/ R0 0/ U0 R0 0/ LKPWRG_L LKPWRG_L {} JP GbE_LK - MHz -(default) 00MHz JP/*/K/OH/./O/GF::[-]LOSE LVGGV/S- Intel orporation 0_LK_GENERTOR 000 W HNLER LV HNLER, Z Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

25 If it is 00 ohms then the ohm resistors. If it is ohms use ohm series PV_TX R9 {} {} {} PV_V_LK_UF PV_VR_LK_UF PV_V_IFF_LK_UF PV_LK_UFF_V_ORE_ LK_00M_LKUFF_P LK_00M_LKUFF_P LK_00M_LKUFF_N LK_00M_LKUFF_N R ///X LKPWRG LKPWRG U V VR V V V VIO VIO VIO VIO IF_IN IF_IN# F_OUT_N F_OUT_N# KPWRG_P# HIW_YPM_LOW# IF_0 IF_0# IF_ IF_# IF_ IF_# IF_ IF_# IF_ IF_# 0 LK_00M_LKUF_PIE_R_P0 LK_00M_LKUF_PIE_R_N0 LK_00M_LKUF_ST_R_P LK_00M_LKUF_ST_R_N LK_00M_LKUF_TV_R_P LK_00M_LKUF_TV_R_N LK_00M_LKUF_SW_R_P LK_00M_LKUF_SW_R_N LK_00M_LKUF_SLOT_R_P LK_00M_LKUF_SLOT_R_N R / R9 / R0 / R / R / R / R / R / R / R / LK_00M_LKUF_PIE_P0 LK_00M_LKUF_PIE_N0 LK_00M_LKUF_ST_P LK_00M_LKUF_ST_N LK_00M_LKUF_TV_P LK_00M_LKUF_TV_N LK_00M_LKUF_SW_P LK_00M_LKUF_SW_N LK_00M_LKUF_SLOT_P LK_00M_LKUF_SLOT_N LK_00M_LKUF_PIE_P0 {} LK_00M_LKUF_PIE_N0 {} LK_00M_LKUF_ST_P {} LK_00M_LKUF_ST_N {} LK_00M_LKUF_TV_P {9} LK_00M_LKUF_TV_N {9} LK_00M_LKUF_SW_P {0} LK_00M_LKUF_SW_N {0} LK_00M_LKUF_SLOT_P {9} LK_00M_LKUF_SLOT_N {9}.K/ SM_PV_HOST_LK {0,9,0,,,,0,} SM_PV_HOST_LK SM_PV_HOST_T {0,9,0,,,,0,} SM_PV_HOST_T There OE# pin have an internal pull-down resistors. R.K//X PV_TX R 0//X R 0//X R 0//X R 0//X PV_TX R9 0//X R9 0//X R9 0//X R9 0//X R9.K/ R9.K/ R9.K/ PV_TX R99.K/ SMLK SMT N voe0# voe# voe# voe# voe# voe# voe# voe# voe# voe9# voe0# voe# IF_ IF_# IF_ IF_# IF_ IF_# IF_ IF_# IF_9 IF_9# 9 0 LK_00M_LKUF_SLOT_R_P LK_00M_LKUF_SLOT_R_N LK_00M_LKUF_SLOT_R_P LK_00M_LKUF_SLOT_R_N LK_00M_LKUF_SLOT_R_P LK_00M_LKUF_SLOT_R_N R0 / R / R / R / R9 / R90 / LK_00M_LKUF_SLOT_P LK_00M_LKUF_SLOT_N LK_00M_LKUF_SLOT_P LK_00M_LKUF_SLOT_N LK_00M_LKUF_SLOT_P LK_00M_LKUF_SLOT_N LK_00M_LKUF_SLOT_P {0} LK_00M_LKUF_SLOT_N {0} LK_00M_LKUF_SLOT_P {} LK_00M_LKUF_SLOT_N {} LK_00M_LKUF_SLOT_P {} LK_00M_LKUF_SLOT_N {} PV_TX R0.K/ SM_0_tri SM tr Tpad IF_0 IF_0# IF_ IF_# 00M_M# 9 0 OUTPUT_SELET.K/ R0 PV_TX RESS = 0xE 9ZXLKLFT/QFN/S R0 0//X PV_TX LOSE LK UF F R0./ PV_V_LK_UF <- V FOR PLL 0///S u//xr/v/k 9 0.u//XR/V/K R0./ PV_VR_LK_UF <- V FOR INPUT REEIVER 0 u//xr/v/k 0.u//XR/V/K PV_V_IFF_LK_UF 0u//XR/V/K 0.u//XR/V/K 0.u//XR/V/K 0.u//XR/V/K 0.u//XR/V/K 0.u//XR/V/K 0.u//XR/V/K PV_TX F PV_LK_UFF_V_ORE_ 0///S 0u//XR/V/K 0.u//XR/V/K 9 0.u//XR/V/K Intel orporation 0_LK_UFFER 000 W HNLER LV HNLER, Z Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

26 PV LP_FRME_N {0,} TMS_0P R0 TI_0P R0 TK_0P R0 {0,} {0,} {0,} {0,} LP_L0 LP_L PV LP_L LP_L PV TI_0P L0 L L L TK_0P LP_FRME_N LE_H_0 LE_H_ LE_H_ LE_H_ LE_H_ LE_H_ LE_H_ LE_L_0 LE_L_ LE_L_ TMS_0P PV PV LE_H0 LE_H LE_H LE_H LE_H LE_H LE_H LE_L0 LE_L LE_L LE_L LE_L LE_L LE_L H_OT L_OT PFMRST_N LP_LKOUT0 LE_L_ LE_L_ LE_L_ LE_L_ {0,} LP_LKOUT0 R09 0//X PV {0,9,,,0,9,,} PLTRST_N LE_H LE_H LE_H0 LE_H LE_L LE_L LE_L0 LE_L F G F G LE 0-SURKW-F0/RE/S PV E E LE_H LE_H LE_H H_OT LE_L LE_L LE_L L_OT P 0 9 E E.K/.K/.K/ 9 0 TI 0 _0 VIO_0 0 TK V 0/GOE0 LK0 LK /GOE LK LK U9 L0V-TN/TQFP//[0HP-00-0R] 0 p//npo/0v/j/x PLTRST_N P//NPO/0V/J/X PFMRST_N P//NPO/0V/J/X R0 00K/ G 0 9 F G F V TO 0 0 VIO_ 9 _ 0 TMS RN 0/PR/ LE_H_0 LE_H_ LE_H_ LE_H_ RN 0/PR/ LE_H_ LE_H_ LE_H_ LE_L_0 RN 0/PR/ LE_L_ LE_L_ LE_L_ LE_L_ RN 0/PR/ LE_L_ LE_L_ PFMRST_N PFMRST_N P U0 SNLVG0GV/SOT- 0U//YV/0V/Z 0U//YV/0V/Z 0.0u//XR/V/K 0.u//XR/V/K u//xr/.v/k 0.u//XR/V/K Intel orporation 0_PORT0 000 W HNLER LV HNLER, Z Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

27 PV {0} IRQ_IL_SEIRQ_VN {0,9,,,0,9,,} PLTRST_N {0,} LP_LKOUT0 {0,} LP_FRME_N {0,} LP_L0 {0,} LP_L {0,} LP_L {0,} LP_L PV IRQ_IL_SEIRQ_VN PLTRST_N LP_LKOUT0 LP_FRME_N LP_L0 LP_L LP_L LP_L R.K/ R.K/ U LPP# SERIRQ LRESET# LLK LFRME# L0 0 L L L PP 0 VPS VPS GPIO GPIO GPIO 9 GPIO GPIO VN N N N N N N 9 N ST9NPERPVMK/TSSOP/S/[0T-E9-0R] Intel orporation 0_TPM 000 W HNLER LV HNLER, Z Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

28 V_P U V N N 9 {0} {0} URT_VN_TX URT_VN_RX URT_VN_TX URT_VN_RX Y Y Y 0 Y URT_P0_TX URT_P0_RX {0,9,,,0,9,,} PLTRST_N PLTRST_N OE OE OE OE R09.K/ ITQSVHQG/QSOP U9 PVUS_US US_SW_P US_SW_N Z099-0S/SOT-L V_P U 0 TS_EI RTS_EI N / _EI / VPP GPIO.0_EI / TR_EI GPIO._EI / SR_EI SUSPEN#/ RI_EI RX_EI TX_EI V VIO VUS - + PVUS_US_R US_SW_N US_SW_P R9 0/ PVUS_US PVUS_US EUG_US Vbus - + I 9 9 TS_SI RTS_SI GPIO.0_SI / _SI GPIO._SI / TR_SI GPIO._SI/SR_SI SUSPEN#/RI_SI REGIN 9 RST# R99.K/ PVUS_US M-US//P/K/OS/R/S/ URT_P0_TX URT_P0_RX 0 RX_SI TX_SI Epad 0.u//XR/V/K P0/QFN/S US_SW_N US_SW_P V_P 0p//NPO/0V/J/X 9 0p//NPO/0V/J/X 0.0u//XR/0V/K 9 0.0u//XR/0V/K Intel orporation 0_US_To_URT 000 W HNLER LV HNLER, Z Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

29 PV_TX R 00/ R 00/ R 00/ R9 00/ For Hot plug Function PORT0_LE LE/G/00/S PORT_LE LE/G/00/S PORT_LE LE/G/00/S PORT_LE LE/G/00/S PV_SW R0.K//X R.K//X R K/ R K/ PV_SW R9.K/ R K//X PV_SW R R R R R R SW_PORT_G0# SW_PORT_G# SW_PORT_G# SW_PORT_G9# R.K/ R.K/ R K/ R.K/ R K/ TP TP TP.K/.K/.K/ R0 0/.K// REXT_0.K// REXT_.K// REXT_ U U R HP_UTTON_# V HP_MRL_# V HP_PRSNT_# R HP_PWRFLT_# U HP_PWR_GOO_ V HP_TNLE_# V HP_LKEN_# U HP_PERST_# T HP_PWREN_ HP_PWRLE_# M L HP_UTTON_# M HP_MRL_# M HP_PRSNT_# K HP_PWRFLT_# K HP_PWR_GOO_ R HP_TNLE_# N HP_LKEN_# M HP_PERST_# N HP_PWREN_ HP_PWRLE_# HP_UTTON_# HP_MRL_# HP_PRSNT_# HP_PWRFLT_# HP_PWR_GOO_ HP_TNLE_# HP_LKEN_# HP_PERST_# HP_PWREN_ HP_PWRLE_# GPIO U GPIO R GPIO V GPIO T GPIO U GPIO P GPIO L GPIO9 L GPIO H GPIO J GPIO R GPIO T GPIO0 GPIO G F PEX_PORT_GOO0# H PEX_PORT_GOO# H PEX_PORT_GOO# R PEX_PORT_GOO# T PEX_PORT_GOO# PEX_PORT_GOO9# J P STRP_RESERVE0 K STRP_RESERVE E STRP_RESERVE V STRP_RESERVE F STRP_RESERVE E STRP_RESERVE STRP_RESERVE V P THERML_IOEp THERML_IOEn G K SPRE0 K SPRE L SPRE R SPRE T SPRE STRP_RESERVE N R N/ P REXT_0 REXT_0 F N/ N/ N/ E REXT_ REXT_ J J N/ J N/ J N/ J REXT_ REXT_ PEX PEX_PETp0 PEX_PETn0 PEX_PERp0 PEX_PERn0 PEX_PETp PEX_PETn PEX_PERp PEX_PERn PEX_PETp PEX_PETn PEX_PERp PEX_PERn PEX_PETp PEX_PETn PEX_PERp PEX_PERn PEX_PETp PEX_PETn PEX_PERp PEX_PERn PEX_PETp PEX_PETn PEX_PERp PEX_PERn PEX_PETp PEX_PETn PEX_PERp PEX_PERn PEX_PETp PEX_PETn PEX_PERp PEX_PERn PEX_PETp PEX_PETn PEX_PERp PEX_PERn PEX_PETp PEX_PETn PEX_PERp PEX_PERn PEX_PETp PEX_PETn PEX_PERp PEX_PERn PEX_PETp PEX_PETn PEX_PERp PEX_PERn PEX_PETp PEX_PETn PEX_PERp PEX_PERn PEX_PETp9 PEX_PETn9 PEX_PERp9 PEX_PERn9 PEX_PETp0 PEX_PETn0 PEX_PERp0 PEX_PERn0 PEX_PETp PEX_PETn PEX_PERp PEX_PERn PEX_PETp PEX_PETn PEX_PERp PEX_PERn PEX_PETp PEX_PETn PEX_PERp PEX_PERn PEX_PETp PEX_PETn PEX_PERp PEX_PERn PEX_PETp PEX_PETn PEX_PERp PEX_PERn PEX_PETp PEX_PETn PEX_PERp PEX_PERn PEX_PETp PEX_PETn PEX_PERp PEX_PERn PEX_PETp PEX_PETn PEX_PERp PEX_PERn PEX_PETp9 PEX_PETn9 PEX_PERp9 PEX_PERn9 U V P R U V P R U V P R U V P R U V P R U9 V9 P9 R9 U0 V0 P0 R0 U V P R E E E E E 9 9 E E0 0 E N N N N M M M M L L L L K K K K H H H H G G G G F F F F E E E E PE_VN_SW_TX_P0 {} PE_VN_SW_TX_N0 {} PE_VN_SW_RX_P0 {} PE_VN_SW_RX_N0 {} PE_VN_SW_TX_P {} PE_VN_SW_TX_N {} PE_VN_SW_RX_P {} PE_VN_SW_RX_N {} PE_VN_SW_TX_P {} PE_VN_SW_TX_N {} PE_VN_SW_RX_P {} PE_VN_SW_RX_N {} PE_VN_SW_TX_P {} PE_VN_SW_TX_N {} PE_VN_SW_RX_P {} PE_VN_SW_RX_N {} PE_VN_SW_TX_P {} PE_VN_SW_TX_N {} PE_VN_SW_RX_P {} PE_VN_SW_RX_N {} PE_VN_SW_TX_P {} PE_VN_SW_TX_N {} PE_VN_SW_RX_P {} PE_VN_SW_RX_N {} PE_VN_SW_TX_P {} PE_VN_SW_TX_N {} PE_VN_SW_RX_P {} PE_VN_SW_RX_N {} PE_VN_SW_TX_P {} PE_VN_SW_TX_N {} PE_VN_SW_RX_P {} PE_VN_SW_RX_N {} PE_SW_TV_TX_P0 {9} PE_SW_TV_TX_N0 {9} PE_SW_TV_RX_P0 {9} PE_SW_TV_RX_N0 {9} PE_SW_TV_TX_P {9} PE_SW_TV_TX_N {9} PE_SW_TV_RX_P {9} PE_SW_TV_RX_N {9} PE_SW_TV_TX_P {9} PE_SW_TV_TX_N {9} PE_SW_TV_RX_P {9} PE_SW_TV_RX_N {9} PE_SW_TV_TX_P {9} PE_SW_TV_TX_N {9} PE_SW_TV_RX_P {9} PE_SW_TV_RX_N {9} PE_SW_TV_TX_P {9} PE_SW_TV_TX_N {9} PE_SW_TV_RX_P {9} PE_SW_TV_RX_N {9} PE_SW_TV_TX_P {9} PE_SW_TV_TX_N {9} PE_SW_TV_RX_P {9} PE_SW_TV_RX_N {9} PE_SW_TV_TX_P {9} PE_SW_TV_TX_N {9} PE_SW_TV_RX_P {9} PE_SW_TV_RX_N {9} PE_SW_TV_TX_P {9} PE_SW_TV_TX_N {9} PE_SW_TV_RX_P {9} PE_SW_TV_RX_N {9} PE_SLOT_TX_P0 {9} PE_SLOT_TX_N0 {9} PE_SLOT_RX_P0 {9} PE_SLOT_RX_N0 {9} PE_SW_SLOT_TX_P {9} PE_SW_SLOT_TX_N {9} PE_SW_SLOT_RX_P {9} PE_SW_SLOT_RX_N {9} PE_SW_SLOT_TX_P {9} PE_SW_SLOT_TX_N {9} PE_SW_SLOT_RX_P {9} PE_SW_SLOT_RX_N {9} PE_SW_SLOT_TX_P {9} PE_SW_SLOT_TX_N {9} PE_SW_SLOT_RX_P {9} PE_SW_SLOT_RX_N {9} PE_SW_MUX_TX_P0 {} PE_SW_MUX_TX_N0 {} PE_SW_MUX_RX_P0 {} PE_SW_MUX_RX_N0 {} PE_SW_MUX_TX_P {} PE_SW_MUX_TX_N {} PE_SW_MUX_RX_P {} PE_SW_MUX_RX_N {} PE_SW_MUX_TX_P {} PE_SW_MUX_TX_N {} PE_SW_MUX_RX_P {} PE_SW_MUX_RX_N {} PE_SW_MUX_TX_P {} PE_SW_MUX_TX_N {} PE_SW_MUX_RX_P {} PE_SW_MUX_RX_N {} Upstream Port from VN/RGY PI-e GEN X ownstream Port to TwinVille PI-e GEN X To PIe Mux To PIe Mux To Manage onn. To PIe Slot PI-e GEN X ownstream Port To PIe Slot PI-e GEN X PEX-0R F/G/S/[0H--0R] Intel orporation 000 W HNLER LV HNLER, Z 09_PIe_SW_INTERFE Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of 9

30 PV0_SW U G G9 G H H0 H J J9 J K K0 K L L9 L M M0 M F F0 F G H K L M N9 N PV_SW STRP_UPSTRM_PORTSEL SEL L L H STRP_STN_PORTFG/0 STN0 STN STN SEL L H L R R U V HOL# WP# T00-SSHL-T/SO/S SEL L L L SK E# SI SO SEL0 H = PORT0 =X, PORT= disable L = PORT =X, PORT= disable H = PORT =X, PORT 9= disable L H L = PORT =X, PORT 9=X L.K/.K/ PORT# PORT0 PORT PORT SW_EE_SK SW_EE_S# SW_EE_SI SW_EE_SO {} JP0 Slot # Slot # [-] X None [-] (default) MUX_SEL X MUX_SEL X {0,9,,,,9,,} {} {} PLTRST_N LK_00M_LKUF_SW_P LK_00M_LKUF_SW_N JP0 JP0 PH/*/K/./V/ JP/*/K/OH/./O/GF::[-]LOSE {0,9,0,,,,,} {0,9,0,,,,,} PV_SW LK_00M_LKUF_SW_P LK_00M_LKUF_SW_N Slave ddress : 0 SM_PV_HOST_LK SM_PV_HOST_T PV_SW PV_TX R.K/ 90 9 RP K/PR/ PV_SW R9 R0 R R R R 0.u//XR/V/K 0.u//XR/V/K R.K/.K/.K/.K/.K/ JTG_SW_TK JTG_SW_TMS JTG_SW_TI JTG_SW_TRST# 0//X.K/ LK_00M_LKUF_SW P LK_00M_LKUF_SW N R R R R9 R0 RP K/PR/ R R R R R SM_PV_HOST_LK SM_PV_HOST_T SW_PROE_MOE# SW_SERES_MOE_EN# SW_PLL_P# SW_F_ERR# SW_EE_S# SW_EE_SI SW_EE_SO SW_EE_SK R9 0/ R0 0/ R 0/ R 0/.K/.K/.K/.K/.K/.K/.K/ R 0K/ R 0K/ R 0K/.K/.K/.K/ F E M V U V R R T V J U N H H J G G U U U P P P V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 JTG_TMS JTG_TRST# JTG_TK JTG_TI JTG_TO PEX_PERST# PEX_NT_RESET# PEX_REFLKp PEX_REFLKn EE_S# EE_I EE_O EE_SK STRP_UPSTRM_PORTSEL0 STRP_UPSTRM_PORTSEL STRP_UPSTRM_PORTSEL STRP_UPSTRM_PORTSEL STRP_NT_ENLE# STRP_NT_UPSTRM_PORTSEL0 STRP_NT_UPSTRM_PORTSEL STRP_STN0_PORTFG STRP_STN_PORTFG0 STRP_STN_PORTFG STRP_TESTMOE0 STRP_TESTMOE STRP_TESTMOE STRP_TESTMOE STRP_EUG_SEL0 STRP_EUG_SEL I_0 I_ I_ I_SL0 I_S0 I_SL I_S SHP_INT# STRP_RESERVE# STRP_PROE_MOE# STRP_SERES_MOE_EN# STRP_PLL_YPSS# STRP_FST_RINGUP# PEX V V V V V V V V F F N N T F K N J J J0 J J K K9 K K L L L0 L L M M9 M M M N N N0 N N P P P T T T T T T T9 T0 T T T PV_SW STRP_TESTMOE R.K/ PEX_INT# L G N/ PEX_INT# FTL_ERR# SEL H SEL L SEL H SEL0 H PORT# PEX_PORT_GOO[9,,,,,0]# default to the PORT_GOO output function. GPIO[:0,,:] are GPIO input GPIO[9:] are input, with values reflected in the GPIO_9 input data register(offset 0h) PEX-0R F/G/S/[0H--0R] 9 0 E E F F9 F F G G G0 G G H H9 H H H J H H H H PEX_PORT_GOO[9,,,,,0]# and GPIO[:0,,:]default to GPIO input, with values reflected in the GPIO 0_ input data register(offset h) GPIO[9:] are input, with values reflected in the GPIO_9 input data register(offset 0h) PV0_SW 9 0.0u//XR/0V/K 9 0.0u//XR/0V/K 9 0.0u//XR/0V/K 9 0.0u//XR/0V/K 9 0.0u//XR/0V/K 9 0.0u//XR/0V/K u//XR/0V/K u//XR/0V/K PV0_SW u//xr/.v/m 9 u//xr/.v/m 0 u//xr/.v/m u//xr/.v/m 0 n//xr/v/k 0 n//xr/v/k 0 0.0u//XR/.V/K 0 0.0u//XR/.V/K 0 0.u//XR/.V/K 0 0.u//XR/.V/K 0 0.u//XR/.V/K PV_SW 0 0.0u//XR/0V/K u//XR/0V/K 0 0.0u//XR/0V/K 0.0u//XR/0V/K 0.0u//XR/.V/K 0.0u//XR/.V/K n//xr/v/k 0.u//XR/.V/K 0.u//XR/.V/K 0.u//XR/.V/K 0U//XR/V/K 0U//XR/V/K 0U//XR/V/K Intel orporation 000 W HNLER LV HNLER, Z 00_PIe_SW_PWR_ONFIG. Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of 0

31 PIe MUX PIe MUX {9} {9} {9} {9} {9} {9} {9} {9} PE_SW_MUX_TX_P0 PE_SW_MUX_TX_N0 PE_SW_MUX_TX_P PE_SW_MUX_TX_N PE_SW_MUX_TX_P PE_SW_MUX_TX_N PE_SW_MUX_TX_P PE_SW_MUX_TX_N {0} MUX_SEL MUX_SEL PV_PIE_MUX U9 I+ I- Oa+ I+ Oa- I- Oa+ 0 Oa- I+ I- Ob+ I+ Ob- I- Ob+ 0 Ob- SEL 9 Oa+ 9 V Oa- V Oa+ V Oa- V V Ob+ 9 V Ob- V Ob+ V Ob PIPIEZHE/QFN/[0T-0-0R] PE_MUX_SLOT_TX_P0 {0} PE_MUX_SLOT_TX_N0 {0} PE_MUX_SLOT_TX_P {0} PE_MUX_SLOT_TX_N {0} PE_MUX_SLOT_TX_P {9} PE_MUX_SLOT_TX_N {9} PE_MUX_SLOT_TX_P {9} PE_MUX_SLOT_TX_N {9} PE_MUX_SLOT_TX_P {0} PE_MUX_SLOT_TX_N {0} PE_MUX_SLOT_TX_P {0} PE_MUX_SLOT_TX_N {0} PE_MUX_SLOT_TX_P {9} PE_MUX_SLOT_TX_N {9} PE_MUX_SLOT_TX_P {9} PE_MUX_SLOT_TX_N {9} {} PE_VN_MUX_TX_P {} PE_VN_MUX_TX_N {} PE_VN_MUX_TX_P {} PE_VN_MUX_TX_N {} PE_VN_MUX_TX_P {} PE_VN_MUX_TX_N {} PE_VN_MUX_TX_P {} PE_VN_MUX_TX_N JP JP/*/K/OH/./O/GF::[-]LOSE JP PRSNT_SLOT PH/*/K/./V/ MUX_SEL PV_PIE_MUX PV_PIE_MUX R99.K/ MUX_SEL Q N00P/SOT/0pF/ G S U0 I+ I- Oa+ I+ Oa- I- Oa+ 0 Oa- I+ I- Ob+ I+ Ob- I- Ob+ 0 Ob- SEL 9 Oa+ 9 V Oa- V Oa+ V Oa- V V Ob+ 9 V Ob- V Ob+ V Ob PIPIEZHE/QFN/[0T-0-0R] PE_MUX_SLOT_TX_P {} PE_MUX_SLOT_TX_N {} PE_MUX_SLOT_TX_P {} PE_MUX_SLOT_TX_N {} PE_MUX_SLOT_TX_P0 {} PE_MUX_SLOT_TX_N0 {} PE_MUX_SLOT_TX_P {} PE_MUX_SLOT_TX_N {} PE_MUX_SLOT_TX_P {} PE_MUX_SLOT_TX_N {} PE_MUX_SLOT_TX_P {} PE_MUX_SLOT_TX_N {} PE_MUX_SLOT_TX_P {} PE_MUX_SLOT_TX_N {} PE_MUX_SLOT_TX_P {} PE_MUX_SLOT_TX_N {} G S {} PRSNT_SLOT R90.K/ u//xr/.v/k/x JP Slot # [-] None [-] (default) X Slot # X X {9} {9} {9} {9} {9} {9} {9} {9} PE_SW_MUX_RX_P0 PE_SW_MUX_RX_N0 PE_SW_MUX_RX_P PE_SW_MUX_RX_N PE_SW_MUX_RX_P PE_SW_MUX_RX_N PE_SW_MUX_RX_P PE_SW_MUX_RX_N MUX_SEL PV_PIE_MUX I+ I- I+ I- U I+ I- Oa+ I+ Oa- I- Oa+ 0 Oa- I+ I- Ob+ I+ Ob- I- Ob+ 0 Ob- SEL 9 Oa+ 9 V Oa- V Oa+ V Oa- V V Ob+ 9 V Ob- V Ob+ V Ob PIPIEZHE/QFN/[0T-0-0R] PE_MUX_SLOT_RX_P0 {0} PE_MUX_SLOT_RX_N0 {0} PE_MUX_SLOT_RX_P {0} PE_MUX_SLOT_RX_N {0} PE_MUX_SLOT_RX_P {9} PE_MUX_SLOT_RX_N {9} PE_MUX_SLOT_RX_P {9} PE_MUX_SLOT_RX_N {9} PE_MUX_SLOT_RX_P {0} PE_MUX_SLOT_RX_N {0} PE_MUX_SLOT_RX_P {0} PE_MUX_SLOT_RX_N {0} PE_MUX_SLOT_RX_P {9} PE_MUX_SLOT_RX_N {9} PE_MUX_SLOT_RX_P {9} PE_MUX_SLOT_RX_N {9} PV_TX {} {} {} {} {} {} {} {} F PE_VN_MUX_RX_P PE_VN_MUX_RX_N PE_VN_MUX_RX_P PE_VN_MUX_RX_N PE_VN_MUX_RX_P PE_VN_MUX_RX_N PE_VN_MUX_RX_P PE_VN_MUX_RX_N MUX_SEL PV_PIE_MUX PV_PIE_MUX 0 0 U SEL 9 9 V V V V V 9 V V V Ob+ Ob- Ob+ Ob- Ob+ Ob- Ob+ Ob- I+ I- I+ I- Oa+ Oa- Oa+ Oa- Oa+ Oa- Oa+ Oa PIPIEZHE/QFN/[0T-0-0R] PE_MUX_SLOT_RX_P {} PE_MUX_SLOT_RX_N {} PE_MUX_SLOT_RX_P {} PE_MUX_SLOT_RX_N {} PE_MUX_SLOT_RX_P0 {} PE_MUX_SLOT_RX_N0 {} PE_MUX_SLOT_RX_P {} PE_MUX_SLOT_RX_N {} PE_MUX_SLOT_RX_P {} PE_MUX_SLOT_RX_N {} PE_MUX_SLOT_RX_P {} PE_MUX_SLOT_RX_N {} PE_MUX_SLOT_RX_P {} PE_MUX_SLOT_RX_N {} PE_MUX_SLOT_RX_P {} PE_MUX_SLOT_RX_N {} PV_PIE_MUX 0///S 0.0u//XR/0V/K 0.0u//XR/0V/K 0.0u//XR/0V/K PV_TX F 0///S 0.0u//XR/0V/K 0.0u//XR/0V/K 0.0u//XR/0V/K 9 0.u//XR/V/K 0 0.u//XR/V/K 0U//XR/V/K 0.u//XR/V/K 0.u//XR/V/K 0U//XR/V/K Intel orporation 0_PIe_Mux 000 W HNLER LV HNLER, Z Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

32 Intel orporation 0_US_SWITH 000 W HNLER LV HNLER, Z Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

33 9 PV_STY PHY_MIO_I_T PHY_M_I_LK {} PHY_MIO_I_T {} PHY_M_I_LK PHY_MIO_I_T PHY_M_I_LK {} {} {} {} {} {} {} {} SGMII_TX_R_P SGMII_TX_R_N SGMII_RX_P SGMII_RX_N SGMII_RX_N0 SGMII_RX_P0 SGMII_TX_R_N0 SGMII_TX_R_P0 9.n//XR/V/K SGMII_TX_P 9.n//XR/V/K SGMII_TX_N SGMII_RX_P SGMII_RX_N SGMII_RX_N0 SGMII_RX_P0 0.n//XR/V/K SGMII_TX_N0 00.n//XR/V/K SGMII_TX_P0 RST_QU_PHY_N SGMII_TX_P.n//XR/V/K 90 SGMII_TX_N.n//XR/V/K SGMII_RX_P SGMII_RX_N SGMII_RX_N SGMII_RX_P SGMII_TX_N.n//XR/V/K 9 SGMII_TX_P.n//XR/V/K 9 SGMII_TX_R_P {} SGMII_TX_R_N {} SGMII_RX_P {} SGMII_RX_N {} SGMII_RX_N {} SGMII_RX_P {} SGMII_TX_R_N {} SGMII_TX_R_P {} PV_GE PV_GE {} {} LE_NI_P0_000_N LE_NI_P0_00_N LE_NI_P0_000_N LE_NI_P0_00_N PV_GE PV0_GE {} LE_NI_P0_T_N LE_NI_P0_T_N PV_GE {} {} {} {} {} {} {} {} {} LE_NI_P_000_N LE_NI_P_00_N LE_NI_P_T_N LE_NI_P_000_N LE_NI_P_00_N LE_NI_P_T_N LE_NI_P_000_N LE_NI_P_00_N LE_NI_P_T_N LE_NI_P_000_N LE_NI_P_00_N LE_NI_P_T_N LE_NI_P_000_N LE_NI_P_00_N LE_NI_P_T_N LE_NI_P_000_N LE_NI_P_00_N LE_NI_P_T_N LE_NI_P0_00_N R00 0//X R0 0/ PV_GE PV0_GE U P0_LE_ V P_LE_0 P_LE_ P_LE_ P_LE_ V VOL P_LE_0 P_LE_ V V_EN_L P_LE_ P_LE_ VOL P_LE_0 P_LE_ P_LE_ P_LE_ ONFIG_0 ONFIG_ ONFIG_ ONFIG_ P0_MIP_0 P0_MIN_0 V E _QFP_SGMII E0-LKJ000/LQFP/S VOR V TRST TO 0 RLK 9 RLK TI V VOR TMS TK V LK_SEL_ LK_SEL_0 0 XTL_OUT XTL_IN 9 V SLK TSTPT HSP HSN V RSET P_MIP_0 0 P_MIN_0 9 V PV_GE PHY_XTL_OUT PHY_XTL_IN PV_GE V P0_MIP_ P0_MIN_ P0_MIP_ P0_MIN_ V P0_MIP_ P0_MIN_ P_MIN_ P_MIP_ V P_MIN_ P_MIP_ V P_MIN_ P_MIP_ V P_MIN_0 P_MIP_0 P_MIP_0 P_MIN_0 V P_MIP_ P_MIN_ V P_MIP_ P_MIN_ V P_MIP_ P_MIN_ P_MIN_ P_MIP_ V P_MIN_ P_MIP_ P_MIN_ P_MIP_ V JP9 K/ R K/ R PH/*/K/./V/ TP R9 K/ R0 0//X R 0/ R0 0//X R0 0/ R0 0//X R09 0/ R0 0/ R0 0/ 0 P0_LE_ 0 P0_LE_ 00 P0_LE_0 99 INTn 9 VOL 9 RESETn 9 P0_S_INP P0_S_INN 9 9 VF 9 P0_S_OUTP P0_S_OUTN 9 P_S_OUTN 9 90 P_S_OUTP 9 VF P_S_INN P_S_INP V TEST_0 TEST_ VOM M MIO 0 TSTPTF V 9 VQ P_S_INP P_S_INN VF P_SOUTP P_SOUTN P_SOUTN P_SOUTP 0 VF P_SIN_N 9 P_SIN_P REF_LK_P REF_LK_N FM FM FM FM R.99K// R R9 9.9// R0 0/ R.K/ 0//X R0 9.9// R 0/ R 0//X R 0/ R 0//X 9 EP PV_GE PV_GE {} {} {} {} {} {} {} {} NI_P0_MI_P0 NI_P0_MI_N0 NI_P0_MI_P NI_P0_MI_N NI_P0_MI_P NI_P0_MI_N NI_P0_MI_P NI_P0_MI_N NI_P_MI_P0 {} NI_P_MI_N0 {} NI_P_MI_P {} NI_P_MI_N {} NI_P_MI_P {} NI_P_MI_N {} NI_P_MI_P {} NI_P_MI_N {} {} {} {} {} {} {} {} {} NI_P_MI_N NI_P_MI_P NI_P_MI_N NI_P_MI_P NI_P_MI_N NI_P_MI_P NI_P_MI_N0 NI_P_MI_P0 NI_P_MI_N {} NI_P_MI_P {} NI_P_MI_N {} NI_P_MI_P {} NI_P_MI_N {} NI_P_MI_P {} NI_P_MI_N0 {} NI_P_MI_P0 {} 0p//NPO/0V/J PHY_XTL_IN PV_GE M/0p/0ppm/.*./0/S X R9 M/ 0.u//YV/V/Z/X 0p//NPO/0V/J PHY_XTL_OUT U {0,9} {} RSMRST_N LN_PHY_EN RSMRST_N LN_PHY_EN R0 0/ HG0GV/SOT- RST_QU_PHY_N Intel orporation 000 W HNLER LV HNLER, Z 0_QU_PHY_G_ PORTS Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

34 EOUPLING PV_GE 0.u//XR/V/K 0.u//XR/V/K 9 0.u//XR/V/K 0 0.u//XR/V/K 0.u//XR/V/K 0.u//XR/V/K 0.u//XR/V/K PV_GE 0.u//XR/V/K 0.u//XR/V/K 0.u//XR/V/K 0.u//XR/V/K 0.u//XR/V/K 9 0.u//XR/V/K 0 0.u//XR/V/K PV0_GE PV0_GE 0.u//XR/V/K 0.u//XR/V/K 0.u//XR/V/K 0.u//XR/V/K 0.u//XR/V/K 0.u//XR/V/K 0.u//XR/V/K 0.u//XR/V/K 9 0.u//XR/V/K 0 0.u//XR/V/K 0.u//XR/V/K PV_GE PV_GE 0.u//XR/V/K 0.u//XR/V/K 0.u//XR/V/K 0.u//XR/V/K 0.u//XR/V/K 0.u//XR/V/K 0.u//XR/V/K 9 0.u//XR/V/K 0 0.u//XR/V/K 0.u//XR/V/K 0U//XR/V/K Intel orporation 000 W HNLER LV HNLER, Z 0_QU_PHY_PWR_EOUPLING Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

35 {} {} {} {} {} {} {} {} NI_P0_MI_N NI_P0_MI_P NI_P0_MI_N NI_P0_MI_P NI_P0_MI_N NI_P0_MI_P NI_P0_MI_N0 NI_P0_MI_P0 NI_P0_MI_N NI_P0_MI_P NI_P0_MI_N NI_P0_MI_P NI_P0_MI_N NI_P0_MI_P NI_P0_MI_N0 NI_P0_MI_P0 R PV_GE 0.u//XR/V/K 0//X 0.u//XR/V/K GLN_ LE_NI_P0_00_R_N TR- G- LE_NI_P0_000_R_N TR+ Y- TR- 0 TR+ SH 9 OM- SH OM SH TR- SH TR+ LE_NI_P0_T_R_N TR- UG- LE_NI_P0_LINK_R_N TR+ UY- LN/G/GY,GY/S/R///G0/[NR-00-00R] R 0/ 0.u//XR/V/K 0.u//XR/V/K R 0/ R 0/ R 0/ LE_NI_P0_00_N LE_NI_P0_000_N LE_NI_P0_T_N LE_NI_P0_00_N {} LE_NI_P0_000_N {} LE_NI_P0_T_N {} NI_P0_MI_P0 NI_P0_MI_P NI_P0_MI_P NI_P0_MI_P NI_P_MI_N0 U Z099-0S/SOT-L EMI Suggest U Z099-0S/SOT-L EMI Suggest U NI_P0_MI_N0 NI_P0_MI_N NI_P0_MI_N NI_P0_MI_N NI_P_MI_P0 PV_GE PV_GE PV_GE 0.u//XR/V/K 0.u//XR/V/K 9 0.u//XR/V/K R 0//X PV_GE NI_P_MI_P Z099-0S/SOT-L EMI Suggest NI_P_MI_N 0.u//XR/V/K {} {} {} {} {} {} {} {} NI_P_MI_N NI_P_MI_P NI_P_MI_N NI_P_MI_P NI_P_MI_N NI_P_MI_P NI_P_MI_N0 NI_P_MI_P0 NI_P_MI_N NI_P_MI_P NI_P_MI_N NI_P_MI_P NI_P_MI_N NI_P_MI_P NI_P_MI_N0 NI_P_MI_P0 0 0.u//XR/V/K GLN_ TR- G- TR+ Y- TR- 0 TR+ 9 OM- OM TR- TR+ TR- UG- TR+ UY- LE_NI_P_00_R_N LE_NI_P_000_R_N LE_NI_P_T_R_N LE_NI_P_LINK_R_N R 0/ R 0/ R9 0/ LE_NI_P_00_N LE_NI_P_000_N LE_NI_P_T_N LE_NI_P_00_N {} LE_NI_P_000_N {} LE_NI_P_T_N {} NI_P_MI_P NI_P_MI_N U9 Z099-0S/SOT-L EMI Suggest NI_P_MI_N NI_P_MI_P PV_GE 0.u//XR/V/K R90 0/ LN/G/GY,GY/S/R///G0/[NR-00-00R] 0.u//XR/V/K 0.u//XR/V/K PV_GE EMI suggest F9 0///S LE_NI_P0_000_R_N LE_NI_P0_00_R_N LE_NI_P0_LINK_R_N LE_NI_P0_T_R_N 0p//XR/0V/K/X 0p//XR/0V/K/X 0p//XR/0V/K/X 0p//XR/0V/K/X R9 0/ R9 0/ R9 0/ R9 0/ LE_NI_P0_T_R_N LE_NI_P0_LINK_R_N LE_NI_P0_00_R_N LE_NI_P0_000_R_N PV_GE EMI suggest F0 0///S LE_NI_P_000_R_N LE_NI_P_00_R_N LE_NI_P_LINK_R_N LE_NI_P_T_R_N p//XR/0V/K/X 0p//XR/0V/K/X 0p//XR/0V/K/X 0p//XR/0V/K/X R9 0/ R9 0/ R9 0/ R9 0/ LE_NI_P_T_R_N LE_NI_P_LINK_R_N LE_NI_P_00_R_N LE_NI_P_000_R_N Intel orporation 000 W HNLER LV HNLER, Z 0_QU_PHY_X_G_LN_ONN_I Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

36 {} {} {} {} {} {} {} {} NI_P_MI_N NI_P_MI_P NI_P_MI_N NI_P_MI_P NI_P_MI_N NI_P_MI_P NI_P_MI_N0 NI_P_MI_P0 NI_P_MI_N NI_P_MI_P NI_P_MI_N NI_P_MI_P NI_P_MI_N NI_P_MI_P NI_P_MI_N0 NI_P_MI_P0 R0 0/ 0.u//XR/V/K 9 0.u//XR/V/K 9 0.u//XR/V/K u//XR/V/K R99 PV_GE 0//X U0 0 9 GLN_ G- Y- TR- TR+ TR- TR+ OM- OM TR- TR+ TR- TR+ UG- UY- LE_NI_P_00_R_N LE_NI_P_000_R_N LE_NI_P_T_R_N LE_NI_P_LINK_R_N LN/G/GY,GY/S/R///G0/[NR-00-00R] R0 0/ R00 0/ R0 0/ LE_NI_P_00_N LE_NI_P_000_N LE_NI_P_T_N LE_NI_P_00_N {} LE_NI_P_000_N {} LE_NI_P_T_N {} NI_P_MI_P0 NI_P_MI_P NI_P_MI_P NI_P_MI_P NI_P_MI_N0 Z099-0S/SOT-L EMI Suggest EMI Suggest U Z099-0S/SOT-L U NI_P_MI_N0 NI_P_MI_N NI_P_MI_N NI_P_MI_N NI_P_MI_P0 PV_GE PV_GE PV_GE 9 0.u//XR/V/K 9 0.u//XR/V/K 99 0.u//XR/V/K R0 0//X PV_GE NI_P_MI_P Z099-0S/SOT-L EMI Suggest NI_P_MI_N 9 0.u//XR/V/K {} {} {} {} {} {} {} {} NI_P_MI_N NI_P_MI_P NI_P_MI_N NI_P_MI_P NI_P_MI_N NI_P_MI_P NI_P_MI_N0 NI_P_MI_P0 NI_P_MI_N NI_P_MI_P NI_P_MI_N NI_P_MI_P NI_P_MI_N NI_P_MI_P NI_P_MI_N0 NI_P_MI_P u//XR/V/K GLN_ TR- G- TR+ Y- TR- 0 TR+ 9 OM- OM TR- TR+ TR- UG- TR+ UY- LE_NI_P_00_R_N LE_NI_P_000_R_N LE_NI_P_T_R_N LE_NI_P_LINK_R_N R0 0/ R0 0/ R0 0/ LE_NI_P_00_N LE_NI_P_000_N LE_NI_P_T_N LE_NI_P_00_N {} LE_NI_P_000_N {} LE_NI_P_T_N {} NI_P_MI_P NI_P_MI_N U Z099-0S/SOT-L EMI Suggest NI_P_MI_N NI_P_MI_P PV_GE 0 0.u//XR/V/K R0 0/ LN/G/GY,GY/S/R///G0/[NR-00-00R] 0 0.u//XR/V/K 0 0.u//XR/V/K PV_GE EMI suggest F 0///S LE_NI_P_000_R_N LE_NI_P_00_R_N LE_NI_P_LINK_R_N LE_NI_P_T_R_N p//XR/0V/K/X 0p//XR/0V/K/X 0p//XR/0V/K/X 0p//XR/0V/K/X R09 0/ R0 0/ R 0/ R 0/ LE_NI_P_T_R_N LE_NI_P_LINK_R_N LE_NI_P_00_R_N LE_NI_P_000_R_N PV_GE EMI suggest F 0///S LE_NI_P_000_R_N LE_NI_P_00_R_N LE_NI_P_LINK_R_N LE_NI_P_T_R_N p//XR/0V/K/X 0p//XR/0V/K/X 0p//XR/0V/K/X 0p//XR/0V/K/X R 0/ R 0/ R 0/ R 0/ LE_NI_P_T_R_N LE_NI_P_LINK_R_N LE_NI_P_00_R_N LE_NI_P_000_R_N Intel orporation 000 W HNLER LV HNLER, Z 0_QU_PHY_X_G_LN_ONN_II Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

37 PV_TV U X0 LE_LINK0_LINKUP H MI0_P0 {} LE_LINK0_LINKUP MI0_P0 {} LE_LINK0_0G J LE0_0 MI0_P0 MI0_N0 {} LE_LINK0_0G MI0_N0 {} LE_LINK0_T J LE0_ MI0_N0 {} LE_LINK0_T LE_LINK0_G K LE0_ MI0_P {} LE_LINK0_G LE0_ MI0_P MI0_P {} MI0_N MI0_N MI0_N {} R R R9 R0 K//X K//X K//X K//X SP0_0 SP0_ SP0_ SP0_ R P T R SP0_0 SP0_ SP0_ SP0_ MI0_P MI0_N MI0_P MI0_N 9 9 MI0_P MI0_N MI0_P MI0_N MI0_P {} MI0_N {} MI0_P {} MI0_N {} PV_TV {} {} {} {} LE_LINK_LINKUP LE_LINK_0G LE_LINK_T LE_LINK_G LE_LINK_LINKUP LE_LINK_0G LE_LINK_T LE_LINK_G J J K K LE_0 LE_ LE_ LE_ MI0_P MI0_N MI_P0 MI_N0 MI0_THP MI0_THN MI_P0 MI_N0 MI0_THP {} MI0_THN {} MI_P0 {} MI_N0 {} R R R R K//X K//X K//X K//X SP_0 SP_ SP_ SP_ T T U U SP_0 SP_ SP_ SP_ MI_P MI_N MI_P MI_N 0 0 MI_P MI_N MI_P MI_N MI_P {} MI_N {} MI_P {} MI_N {} MI_P MI_N MI_P MI_N MI_P {} MI_N {} MI_P MI_N MI_THP MI_THN MI_THP {} MI_THN {} / JLX0T/G/S Intel orporation 000 W HNLER LV HNLER, Z 0_TWINVILLE_MI_ LES Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

38 PV_TV R.K/ R.K/ R.K/ 0.u//XR/V/K FLSH_HOL_N FLSH_WP_N FLSH_E_N SERIL FLSH U V HOL_N WP_N S_N O IO PV_UX LK R R9 0K/ 0K/ R0 0K/ PULL UP/OWN RESISTORS REQUIRE WHETHER N-SI USE S: SINGL ROP MULTIPLE ROP OR EVEN IF N-SI IS NOT USE R R0 0K/ 0K/ PV_UX R R R 0K//X 0K//X 0K//X IF SMUS IS NOT USE SM_LK N SM_T JUSTE Y SYSTEM STILL NEE TO E PULLE UP TO V. SM_PV_STY_HOST_T_R SM_PV_STY_HOST_LK_R SM_PV_STY_HOST_LERT_R {,,} {,,} {} SM_PV_STY_HOST_T SM_PV_STY_HOST_LK SM_PV_STY_HOST_LERT M/SPI/SO/0mil/LOWV/S/[0HP--0R] R 0/ R 0/ R 0/ FLSH_SO FLSH_SI FLSH_E_N FLSH_SK SM_PV_STY_HOST_T_R SM_PV_STY_HOST_LK_R SM_PV_STY_HOST_LERT_R K K J J L L M U FLSH_SO FLSH_SI FLSH_E_N FLSH_SK SM SMLK SMLRT_N X0 NSI_RX0 NSI_RX NSI_TX0 NSI_TX NSI_TX_EN NSI_LK_IN H G H G G G NSI_RX0 NSI_RX NSI_TX0 NSI_TX NSI_TX_EN NSI_LK_IN TRE L < 0 MIL XTL_0M_O_R R 0/ XTL_0M_I XTL_0M_O XTL 0M/p/ppm/*./0/S/[0XT R] XTL_I XTL_O / JLX0T/G/S NSI_RS_V NSI_R_IN NSI_R_OUT G_REXT TM_REXT H F F NSI_RS_V NSI_R_IN TP_NSI_R_OUT P_G_REXT PU_TM_REXT TRE L < 000 MIL PV_TV TP9 R9 0K/ R 0K/ R 0K/ p//npo/0v/j p//npo/0v/j R 0// R K// XTL (L) (R) X0 0MHz pf pf Intel orporation 000 W HNLER LV HNLER, Z 0_TWINVILLE_NSI_SM_FLSH Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

39 {9} {9} PE_SW_TV_TX_P0 PE_SW_TV_TX_N0 TRE Z = ohm PE_SW_TV_TX_P0 PE_SW_TV_TX_N0 TRE Z = ohm PLE LOSE TO X0 PLE LOSE TO PU U X0 0.u//XR/V/K PE_SW_TV_R_TX_P0 PE_SW_TV_R_RX_P0 0.u//XR/V/K 0.u//XR/V/K PE_SW_TV_R_TX_N0 PER_0_P PET_0_P PE_SW_TV_R_RX_N0 0.u//XR/V/K PER_0_N PET_0_N PE_SW_TV_RX_P0 PE_SW_TV_RX_N0 PE_SW_TV_RX_P0 {9} PE_SW_TV_RX_N0 {9} {9} {9} PE_SW_TV_TX_P PE_SW_TV_TX_N PE_SW_TV_TX_P PE_SW_TV_TX_N 9 0.u//XR/V/K 0.u//XR/V/K PE_SW_TV_R_TX_P PE_SW_TV_R_TX_N PER P PER N PET P PET N PE_SW_TV_R_RX_P PE_SW_TV_R_RX_N 0 0.u//XR/V/K 0.u//XR/V/K PE_SW_TV_RX_P PE_SW_TV_RX_N PE_SW_TV_RX_P {9} PE_SW_TV_RX_N {9} {9} {9} PE_SW_TV_TX_P PE_SW_TV_TX_N PE_SW_TV_TX_P PE_SW_TV_TX_N 0.u//XR/V/K PE_SW_TV_R_TX_P PE_SW_TV_R_RX_P 0.u//XR/V/K 0.u//XR/V/K PE_SW_TV_R_TX_N PER P PET P 9 PE_SW_TV_R_RX_N 0.u//XR/V/K PER N PET N 9 PE_SW_TV_RX_P PE_SW_TV_RX_N PE_SW_TV_RX_P {9} PE_SW_TV_RX_N {9} {9} {9} PE_SW_TV_TX_P PE_SW_TV_TX_N PE_SW_TV_TX_P PE_SW_TV_TX_N 9 0.u//XR/V/K 0.u//XR/V/K PE_SW_TV_R_TX_P PE_SW_TV_R_TX_N PER P PER N PET P PET N 0 0 PE_SW_TV_R_RX_P PE_SW_TV_R_RX_N 0 0.u//XR/V/K 0.u//XR/V/K PE_SW_TV_RX_P PE_SW_TV_RX_N PE_SW_TV_RX_P {9} PE_SW_TV_RX_N {9} {9} {9} PE_SW_TV_TX_P PE_SW_TV_TX_N PE_SW_TV_TX_P PE_SW_TV_TX_N 0.u//XR/V/K 0.u//XR/V/K PE_SW_TV_R_TX_P PE_SW_TV_R_TX_N PER P PER N PET P PET N PE_SW_TV_R_RX_P PE_SW_TV_R_RX_N 0.u//XR/V/K 0.u//XR/V/K PE_SW_TV_RX_P PE_SW_TV_RX_N PE_SW_TV_RX_P {9} PE_SW_TV_RX_N {9} {9} {9} PE_SW_TV_TX_P PE_SW_TV_TX_N PE_SW_TV_TX_P PE_SW_TV_TX_N 0.u//XR/V/K 0.u//XR/V/K PE_SW_TV_R_TX_P PE_SW_TV_R_TX_N PER P PER N PET P PET N PE_SW_TV_R_RX_P PE_SW_TV_R_RX_N 0.u//XR/V/K 0.u//XR/V/K PE_SW_TV_RX_P PE_SW_TV_RX_N PE_SW_TV_RX_P {9} PE_SW_TV_RX_N {9} {9} {9} PE_SW_TV_TX_P PE_SW_TV_TX_N PE_SW_TV_TX_P PE_SW_TV_TX_N 9 0.u//XR/V/K PE_SW_TV_R_TX_P 9 PE_SW_TV_R_RX_P 0 0.u//XR/V/K 0.u//XR/V/K PE_SW_TV_R_TX_N 9 PER P PET P PE_SW_TV_R_RX_N 0.u//XR/V/K PER N PET N PE_SW_TV_RX_P PE_SW_TV_RX_N PE_SW_TV_RX_P {9} PE_SW_TV_RX_N {9} {9} {9} PE_SW_TV_TX_P PE_SW_TV_TX_N PE_SW_TV_TX_P PE_SW_TV_TX_N 0.u//XR/V/K 0.u//XR/V/K PE_SW_TV_R_TX_P PE_SW_TV_R_TX_N PER P PER N PET P PET N PE_SW_TV_R_RX_P PE_SW_TV_R_RX_N 0.u//XR/V/K 0.u//XR/V/K PE_SW_TV_RX_P PE_SW_TV_RX_N PE_SW_TV_RX_P {9} PE_SW_TV_RX_N {9} {} {} LK_00M_LKUF_TV_P LK_00M_LKUF_TV_N LK_00M_LKUF_TV_P LK_00M_LKUF_TV_N Y Y PE_LK_P PE_LK_N {0,9,,,,0,,} PLTRST_N PLTRST_N P_PE_RIS0 P_PE_RIS R 0/ RST_PERST_R V V W PE_RIS0 PE_RIS PE_RST_N PE_WKE_N W PV_STY / JLX0T/G/S R000.K/ TRE L < 000 MIL RST_PERST_R NI PV_UX P_PE_RIS0 P_PE_RIS p//npo/0v/j/x {9,0,,} PMU_WKE_N_UX PMU_WKE_N_UX R.K/ S G G S Q MOSFET m N00W II N-HNNEL UL SOT- N00W/SOT/0pF/./[0IF-00-0R] R.0K// R9.0K// PMU_WKE_N {0,} Intel orporation 09_TWINVILLE_PIe 000 W HNLER LV HNLER, Z Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of 9

40 TP0 RSVU_N U U RSVU_N L RSV_N L RSVL_N L RSVL_N RSVL_N RSV_N RSV_N RSV_N RSV_N RSV_N E RSV_N E RSVE_N F RSVE_N M RSVF_N RSVM_N L M RSVL_N N RSVM_N N RSVN_N N RSVN_N N RSVN_N N RSVN_N N RSVN_N M RSVN_N M RSVM_N M RSVM_N P RSVM_N F RSVP_N RSVF_N RSV_N Y RSV_N RSVY_N X0 RSV_N RSV_N RSV0_N RSV_N RSV_N RSVE_N RSVV_N RSVR_N RSVG_N RSVY0_N RSVF_N RSVR_N RSVN_N RSVL_N RSVU_N RSVP_N RSVP_N RSVP_N RSVR_N RSVR_N RSVR_N RSVT_N RSVU_N RSVU_N RSVU_N RSVU_N RSVV_N RSVV_N 0 E V R G Y0 F R N L U P P P R R R T U U U U V V PVL_EV_OFF_N I0_NSI_LK_OUT R0 TP 0K//X PV_STY / JLX0T/G/S PV_TV R.K/ R.K/ P_RSVK_ R.K/ UE W RSV_ N RSVW_ G RSVN_ H RSVG_ J RSVH_ N RSVJ_ W RSVN_ K RSVW_ T RSVK_ RSVT_ P RSV_ Y RSVP_ RSVY_ X0 RSVT_VP RSVM_VP RSVJ_ RSVY_ RSVT_ RSVH_ RSVV_ RSVP_ RSVG_ RSV_ RSV_ RSVM_ RSVH_ T M J Y T H V P G M H PU_RSVT_VP PU_RSVM_VP / JLX0T/G/S Intel orporation 000 W HNLER LV HNLER, Z 00_TWINVILLE_RSV_PINS Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of 0

41 PV_TV PV_TV PV_TV UF X0 P_PHY0_RVSL P_PHY_RVSL R R 0K//X 0K//X R R 0K/ SE_EN M TP_THERM P SE_EN THERM P G TP 0K/ TP_THERM N R0 PHY0_RVSL UX_PWR FUNTION PWRG_LN L THERM N G TP R9 R 0K/ PHY_RVSL LN_PWR_GOO.K/.K//X T P_PHY0_RVSL HI UX POWER IS VILLE UX_PWR P PHY0_RVSL HI X0 SUPPORT OL POWER STTE UX_PWR PV R 0K/ V P_PHY_RVSL LOW UX IS NOT VILLE PV_UX R 0K//X PWRG_MIN R PHY_RVSL LOW MIN_PWR_OK JTG_TK PV_TV LN_IS K TK Y R R 0K/ LN_IS_N 0K//X W JTG_TI R 0K/ LN0_IS K TI LN0_IS_N JTG_TO YPSS_POR H TO V R 0K/ YPSS_POR JTG_TMS TMS W / JLX0T/G/S TRST_N W JTG_TRST_N PHY MI LNE SWPSL MI LNE ORER:,,, MI LNE ORER:,,, PV_TV JTG_TI JTG_TO JTG_TMS JTG_TK JTG_TRST_N R 0K/ R.K/ R9 0K/ R0 0/ R 0/ IF JTG IS NOT USE JTRST_N SHOUL E PULL-OWN Intel orporation 0_TWINVILLE_MIS 000 W HNLER LV HNLER, Z Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

42 PLE ULK UNER THE G PLE ULK UNER THE G PLE uf UNER THE G Intel orporation 000 W HNLER LV HNLER, Z P0V_TV PV_UX P0V_TV P0V_TV P0V_TV P0V_TV P0V_TV PV_UX Size ocument Number Rev ate: Sheet of Mohon Peak R eta 0_TWINVILLE_POWER_I Wednesday, ugust, 0 Size ocument Number Rev ate: Sheet of Mohon Peak R eta 0_TWINVILLE_POWER_I Wednesday, ugust, 0 Size ocument Number Rev ate: Sheet of Mohon Peak R eta 0_TWINVILLE_POWER_I Wednesday, ugust, 0 u//xr/.v/k u//xr/.v/k u//xr/.v/m u//xr/.v/m u//xr/.v/k u//xr/.v/k u//xr/.v/k u//xr/.v/k 9 u//xr/.v/k 9 u//xr/.v/k 9 u//xr/.v/k 9 u//xr/.v/k u//xr/.v/k u//xr/.v/k u//xr/.v/k u//xr/.v/k 9 u//xr/.v/k 9 u//xr/.v/k u//xr/.v/k u//xr/.v/k 0 u//xr/.v/m 0 u//xr/.v/m u//xr/.v/k u//xr/.v/k u//xr/.v/k u//xr/.v/k u//xr/.v/k u//xr/.v/k u//xr/.v/m u//xr/.v/m u//xr/.v/m u//xr/.v/m u//xr/.v/k u//xr/.v/k 0 u//xr/.v/k 0 u//xr/.v/k u//xr/.v/k u//xr/.v/k 9 u//xr/.v/m 9 u//xr/.v/m u//xr/.v/k u//xr/.v/k u//xr/.v/k u//xr/.v/k u//xr/.v/k u//xr/.v/k u//xr/.v/m u//xr/.v/m u//xr/.v/k u//xr/.v/k 0 u//xr/.v/m 0 u//xr/.v/m u//xr/.v/k u//xr/.v/k u//xr/.v/k u//xr/.v/k u//xr/.v/m u//xr/.v/m u//xr/.v/m u//xr/.v/m u//xr/.v/m u//xr/.v/m u//xr/.v/k u//xr/.v/k 9 u//xr/.v/k 9 u//xr/.v/k u//xr/.v/m u//xr/.v/m 9 u//xr/.v/m 9 u//xr/.v/m 0 u//xr/.v/k 0 u//xr/.v/k u//xr/.v/k u//xr/.v/k u//xr/.v/k u//xr/.v/k u//xr/.v/m u//xr/.v/m 0 u//xr/.v/k 0 u//xr/.v/k 0 u//xr/.v/k 0 u//xr/.v/k u//xr/.v/k u//xr/.v/k 90 u//xr/.v/k 90 u//xr/.v/k u//xr/.v/k u//xr/.v/k X0 / UK JLX0T/G/S X0 / UK JLX0T/G/S V0P_J J V0P_M M V0P_G G V0P_L L V0P_R R V0P_U U V0P_W W V0P_H H V0P_K K V0P_M M V0P_P P V0P_T T V0P_V V V0P_G G V0P_J J V0P_L L V0P_N N V0P_R R V0P_U U V0P_W W V0P_H H V0P_K K V0P_M M V0P_P P V0P_T T V0P_V V V0P_G G V0P_T T V0P_V V V0P_G9 G9 V0P_J9 J9 V0P_L9 L9 V0P_H0 H0 V0P_K0 K0 V0P_P P V0P_J J V0P_L L V0P_N N V0P_R R V0P_U U V0P_W W V0P_H H V0P_K K VP_L L VP_N N VP_M M V0P_K K V0P_G G V0P_J J V0P_L L V0P_N N V0P_R R V0P_U U V0P_W W V0P_H H V0P_K K V0P_M M V0P_P P V0P_T T V0P_V V V0P_G9 G9 V0P_J9 J9 V0P_L9 L9 V0P_N9 N9 V0P_R9 R9 V0P_U9 U9 V0P_W9 W9 V0P_H0 H0 V0P_K0 K0 V0P_M0 M0 V0P_P0 P0 V0P_T0 T0 V0P_V0 V0 V0P_H H V0P_J J V0P_L L V0P_N N V0P_R R V0P_U U V0P_W W V0P_K K V0P_P P V0P_T T V0P_V V V0P_G G V0P_H H V0P_J J u//xr/.v/k u//xr/.v/k u//xr/.v/k u//xr/.v/k u//xr/.v/k u//xr/.v/k u//xr/.v/m u//xr/.v/m u//xr/.v/k u//xr/.v/k u//xr/.v/k u//xr/.v/k u//xr/.v/k u//xr/.v/k u//xr/.v/k u//xr/.v/k TV_HS TV_HS/[SF-00-00R] TV_HS TV_HS/[SF-00-00R] u//xr/.v/k u//xr/.v/k u//xr/.v/k u//xr/.v/k u//xr/.v/k u//xr/.v/k u//xr/.v/k u//xr/.v/k u//xr/.v/m u//xr/.v/m 9 u//xr/.v/k 9 u//xr/.v/k

43 PLE ULK UNER THE G T PHY RE PLE ULK UNER THE G T PIE RE PLE ULK UNER THE G T PHY RE PLE ULK UNER THE G T PIE RE Stuff For X0 Stuff For X0 Intel orporation 000 W HNLER LV HNLER, Z PV_ISO_E PV_ISO_ PV_ISO_E PV_TV PV_TV PV_TV PV_TV PV_TV PV_TV PV_TV PV_TV PV_TV Size ocument Number Rev ate: Sheet of Mohon Peak R eta 0_TWINVILLE_POWER_II_ Wednesday, ugust, 0 Size ocument Number Rev ate: Sheet of Mohon Peak R eta 0_TWINVILLE_POWER_II_ Wednesday, ugust, 0 Size ocument Number Rev ate: Sheet of Mohon Peak R eta 0_TWINVILLE_POWER_II_ Wednesday, ugust, 0 0 u//xr/.v/k 0 u//xr/.v/k u//xr/.v/k u//xr/.v/k 9 u//xr/.v/k 9 u//xr/.v/k 00 u//xr/.v/k 00 u//xr/.v/k 0 u//xr/.v/m 0 u//xr/.v/m F 00///S F 00///S u//xr/.v/m u//xr/.v/m 0 u//xr/.v/k 0 u//xr/.v/k u//xr/.v/k u//xr/.v/k 9 u//xr/.v/k 9 u//xr/.v/k u//xr/.v/k u//xr/.v/k 0 u//xr/.v/k 0 u//xr/.v/k u//xr/.v/k u//xr/.v/k 9 u//xr/.v/k 9 u//xr/.v/k u//xr/.v/k u//xr/.v/k 0 u//xr/.v/k 0 u//xr/.v/k 0 u//xr/.v/k 0 u//xr/.v/k u//xr/.v/k u//xr/.v/k u//xr/.v/m u//xr/.v/m u//xr/.v/k u//xr/.v/k u//xr/.v/k u//xr/.v/k F 00///S F 00///S F 00///S F 00///S u//xr/.v/k u//xr/.v/k X0 9/ UI JLX0T/G/S X0 9/ UI JLX0T/G/S _K K _F F _F F _F F _9 9 _F F _E0 E0 _F F F9 F9 E E _F F _F0 F0 _F F _F F _F F _F F _G G _G G _G0 G0 _G G _H H _H H _H9 H9 _H H _J J _J J _J0 J0 _L0 L0 _K K _K9 K9 _L L _L L _M M _M M _F F _F F _F F _L L _F F _F F _F9 F9 _F0 F0 _G G _G G _E E _G G _G0 G0 _H H _E E _H H _H H _H9 H9 _E E _J J _9 9 _J J _E0 E0 _J J _E E _J J _J0 J0 _E E _K K K K _E E _K K K K _E E _K9 K9 _L L _L L _L L _L0 L0 _ u//xr/.v/k u//xr/.v/k 9 u//xr/.v/k 9 u//xr/.v/k / X0 UH JLX0T/G/S / X0 UH JLX0T/G/S 0 0 E E _ _0 0 _9 9 _ u//xr/.v/m u//xr/.v/m X0 / UG JLX0T/G/S X0 / UG JLX0T/G/S VP_Y Y VP_Y Y VP_Y Y VP_Y0 Y0 VP_Y Y VP_Y Y VP_ VP_ VP_ VP_0 0 VP_ VP_ VP_0 0 VP_E E VP_E E VP_E E VP_E9 E9 VP_E E VP_E E VP_E E VP_E E VP_E9 E9 VP_E E VP_Y Y VP_ VP_ VP_ VP_ VP_ VP_ VP_ VP_0 0 VP_ VP_ VP_ VP_ VP_9 9 VP_ VP_ VP_ VP_ VP_ VP_ VP_0 0 VP_ VP_ VP_9 9 VP_ VP_ VP_0 0 VP_P P VP_P0 P0 VP_R R VP_R9 R9 VP_T T VP_T0 T0 VP_U U VP_U9 U9 VP_V V VP_W W VP_W9 W9 VP_ VP_M0 M0 VP_N9 N9 VP_V0 V0 VP_ VP_ VP_ VP_ 9 u//xr/.v/k 9 u//xr/.v/k u//xr/.v/k u//xr/.v/k u//xr/.v/k u//xr/.v/k u//xr/.v/m u//xr/.v/m 0 u//xr/.v/k 0 u//xr/.v/k 0 u//xr/.v/k 0 u//xr/.v/k 09 u//xr/.v/k 09 u//xr/.v/k 0 u//xr/.v/k 0 u//xr/.v/k 9 u//xr/.v/k 9 u//xr/.v/k u//xr/.v/m u//xr/.v/m u//xr/.v/m u//xr/.v/m 9 u//xr/.v/k 9 u//xr/.v/k u//xr/.v/k u//xr/.v/k 0/ X0 UJ JLX0T/G/S 0/ X0 UJ JLX0T/G/S _W0 W0 _M M _M9 M9 _T T _V V _Y Y _T T _T T _V U _V V _V V _N N _V9 V9 _R R _W W _M9 M9 _U U _P9 P9 _W W _T9 T9 _V9 V9 _P P _T T _V V _N N _R R _M M _U U _M M _W W _N N _P P _P P _P P _R R _Y Y _Y Y _Y9 Y9 _Y9 Y9 _N0 N0 _M M _Y Y _Y Y _Y Y _W W _Y Y _N N _N N _N N _N0 N0 _W W _W0 W0 _P P _P P _P9 P9 _U0 U0 _R0 R0 _R R _R R _R R _R0 R0 _T T _T T _T9 T9 _U U _U U _U U _U0 U0 _V V _V V _W W _W W _Y Y 9 u//xr/.v/k 9 u//xr/.v/k u//xr/.v/m u//xr/.v/m u//xr/.v/k u//xr/.v/k 99 u//xr/.v/k 99 u//xr/.v/k 0 u//xr/.v/k 0 u//xr/.v/k u//xr/.v/m u//xr/.v/m u//xr/.v/k u//xr/.v/k u//xr/.v/k u//xr/.v/k 0 u//xr/.v/k 0 u//xr/.v/k u//xr/.v/m u//xr/.v/m 9 u//xr/.v/m 9 u//xr/.v/m u//xr/.v/k u//xr/.v/k 9 u//xr/.v/k 9 u//xr/.v/k u//xr/.v/k u//xr/.v/k 0 u//xr/.v/k 0 u//xr/.v/k 9 u//xr/.v/k 9 u//xr/.v/k

44 PV_TV 9.u//XR/.V/K.u//XR/.V/K.u//XR/.V/K.u//XR/.V/K.u//XR/.V/K R 0/ LE_LINK0_LINKUP_R LE_LINK0_T_R EMI suggest 0p//XR/0V/K/X 0p//XR/0V/K/X PV_UX R R R R 0//X 0//X 0//X 0//X LE_LINK0_LINKUP_R LE_LINK0_T_R LE_LINK0_0G_UF_R LE_LINK0_G_UF_R {} {} {} {} {} {} MI0_P0 MI0_N0 MI0_P MI0_N MI0_P MI0_N MI0_P0 MI0_N0 MI0_P MI0_N MI0_P MI0_N 0GLN R R R9 J R R R R R R YELLOW J L L L L LE_LINK0_T_R LE_LINK0_LINKUP_R LE_LINK0_0G_UF_R LE_LINK0_G_UF_R R 0//X R 0/ R9 0/ R0 0/ R 0/ LE_LINK0_LINKUP LE_LINK0_T LE_LINK0_LINKUP LE_LINK0_0G_UFF LE_LINK0_G_UFF LE_LINK0_T {} LE_LINK0_LINKUP {} {} MI0_THP MI0_THP L nh//00m//s.p//npo/0v//hq L {} {} L L MI0_P MI0_N nh//00m//s.p//npo/0v//hq MI0_P MI0_N MI0_THP_FILT p//npo/0v//hq R0 R 9 R GREEN R G R GREEN G R LN/0G/GY,G/O/R///G0/[NR-00-0R_NR-00-0R] {} MI0_THN MI0_THN nh//00m//s nh//00m//s MI0_THN_FILT MI0_THP_FILT PLE N ROUTE S LNE IFFERENTILLY LOTE LOSE TO X0 R 9.9///X MI0_THN_FILT R 9.9///X PV_UX PV_UX PV_UX PV_UX cap +/- 0.% Stuff For I0-T R 0/ R 0/ R 0/ R 0/ U {} LE_LINK0_0G LE_LINK0_0G Y LE_LINK0_0G_UFF {} LE_LINK0_G LE_LINK0_G Y LE_LINK0_G_UFF {} LE_LINK_0G LE_LINK_0G Y LE_LINK_0G_UFF {} LE_LINK_G LE_LINK_G 9 Y LE_LINK_G_UFF Y 0 Y PV_UX 0p//XR/0V/K 9 0p//XR/0V/K 0 0p//XR/0V/K 0p//XR/0V/K V PV_TV LV0 LV0PW/TSSOP 0TT-000-R 0.u//XR/V/K R 0/ EMI suggest PV_UX R9 0//X LE_LINK_LINKUP_R 0.u//XR/.V/K.u//XR/.V/K.u//XR/.V/K.u//XR/.V/K.u//XR/.V/K LE_LINK_LINKUP_R LE_LINK_T_R 0p//XR/0V/K/X 0p//XR/0V/K/X R90 R9 R9 0//X 0//X 0//X LE_LINK_T_R LE_LINK_0G_UF_R LE_LINK_G_UF_R {} {} {} {} {} {} MI_P MI_N MI_P MI_N MI_P MI_N MI_P MI_N MI_P MI_N MI_P MI_N 0GLN R R R9 J R R R R R R YELLOW J L L L L LE_LINK_T_R LE_LINK_LINKUP_R LE_LINK_0G_UF_R LE_LINK_G_UF_R R9 0//X R9 0/ R9 0/ R9 0/ R9 0/ LE_LINK_LINKUP LE_LINK_T LE_LINK_LINKUP LE_LINK_0G_UFF LE_LINK_G_UFF LE_LINK_T {} LE_LINK_LINKUP {} {} {} MI_THP MI_THN MI_THP MI_THN cap +/- 0.% L nh//00m//s p//npo/0v//hq L nh//00m//s PLE N ROUTE S LNE IFFERENTILLY LOTE LOSE TO X0 {} {} L L MI_P0 MI_N0 nh//00m//s.p//npo/0v//hq nh//00m//s MI_P0 MI_N0 MI_THP_FILT p//npo/0v//hq MI_THN_FILT R0 R 9 R GREEN R G R GREEN G R LN/0G/GY,G/O/R///G0/[NR-00-0R_NR-00-0R] MI_THP_FILT MI_THN_FILT R9 R99 9.9///X 9.9///X Stuff For I0-T 0 TR+ 0 T 09 TR- 0 TR+ 0 T 0 TR- 0 TR+ 0 T 0 TR- 0 TR+ T TR- M SENSE+ M T M SENSE- GREEN YELLOW GREEN 9 LINK/TIVITY 0 GbE OLOR GREEN GREEN - GREEN GREEN YELLOW YELLOW - Intel orporation LIGHT ON LINK OFF ON LINK ON LINK OFF TION LN LINK / NO ESS LN ESS ILE 0 Gbps ONNETION IENTIFIT 0 Gbps ONN. Gbps ONNETION IENTIFIT Gbps ONN. 0 Mbps OR 00 Mbps ONNETION 000 W HNLER LV HNLER, Z 0_TWINVILLE_0G_LN ONNETOR Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

45 PV_TV_LN_X0 VR VR SPEIFITION VOUT =. V, +/- % VOUT =. V, +/- % VOUT RIPPLE = +/-0.% IOUT = PEK(PG) IOUT =. T(PG) IOUT STEP SIZE = 0. IOUT I/T = /us SW FREQ = 00 KHz {} PWRG_P_V_LN EN Level need > V PWRG_P_V_LN 0 p P_V_LN_ n//xr/0v/k c 9 p//npo/0v/j/x Rc P_V_LN_OMP_R PV_UX The ompensation parts need close to I R0 R0.K/ R0 0/ R0 0.u//XR/V/K/X.K// PV_UX.K// heck R0.K/ P_V_LN_PG P_V_LN_EN P_V_LN_OMP P_V_LN_F_R R NP0 P_V_LN_ R0 RF K// P_V_LN_F_R R09 U PG EN OMP F F P.K// VIN VSW Vin :.V~V P_V_LN_PH NP0RG/SOI/S 0.0u//XR/V/K P_V_LN_VIN 0.u//XR/V/K R0./ P n//xr/0v/k 0u//XR/V/M 0.u//XR/V/K R00 0/ P Reserve L9.uH//S/[0L-00-0R_0L-00-0R] PV_UX 00 hange to use 00 size for layout. Output HOKE Spec. MHI000-R0M-S L :.0uH +/- 0% Idc : () Isat : () R : 0m OHMS MX 0u//XR/.V/M u//xr/.v/m u//xr/.v/m u//xr/.v/m 009 hange to use SMT EP. P_V_LN_F E9 Reserve PV_TV R0 0/ P_V_LN_.n//XR/0V/K/X R0 0/ Vout = 0. * ( +.K /.K ) =.V Vout = 0. * (+R/R) P_V_LN_ Intel orporation 000 W HNLER LV HNLER, Z 0_TWINVILLE_PWR_PV Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

46 VR SPEIFITION VOUT =.V, +/- % VOUT =.V, +/- % VOUT RIPPLE = +/-0.% IOUT = PEK(PG) IOUT =. T(PG) IOUT STEP SIZE = 0.9 IOUT I/T = /us SW FREQ = 00 KHz {} {} PWRG_P_V_LN PWRG_P_V_LN EN Level need > V PWRG_P_V_LN PWRG_P_V_LN R 0/ R.K/ R 0/ PV_UX 0.u//XR/V/K/X PV_UX heck R.K//X P_V_LN_PG P_V_LN_EN PV_TV VR U PG EN NP0 VIN VSW Vin :.V~V P_V_LN_PH P_V_LN_VIN 0.u//XR/V/K P 0u//XR/V/M R 0/ P Reserve L0.uH//S/[0L-00-0R_0L-00-0R] PV_UX Output HOKE Spec. MHI000-R0M-S L :.0uH +/- 0% Idc : () Isat : () R : 0m OHMS MX PV_TV 9 p P_V_LN_ n//xr/0v/k c 00p//NPO/0V/J/X R 0K// Rc P_V_LN_OMP_R The ompensation parts need close to I R0.K// P_V_LN_OMP P_V_LN_F_R OMP F P_V_LN_ R9 RF K// P_V_LN_F_R R R F P.K// NP0RG/SOI/S 0.0u//XR/V/K R./ n//xr/0v/k 0 0.u//XR/V/K 0 0u//XR/.V/M u//xr/.v/m u//xr/.v/m u//xr/.v/m 9 P_V_LN_F R 0/ P_V_LN_.n//XR/0V/K/X R 0/ Vout = 0. * ( +.K /.K ) =.9V Vout = 0. * (+R/R) P_V_LN_ Intel orporation 000 W HNLER LV HNLER, Z 0_TWINVILLE_PWR_PV Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

47 P_0V_TV_LN VR PV_UX TPS VIN voltage range = V to V, and V voltage range =. to V u//xr/.v/m u//xr/.v/m u//xr/.v/m P0V_TV_VREG R R 9 u//xr/v/k R R 00K///X K// R 00K// R.u//XR/.V/K PV_UX VR_P0V_TV_MOE VR_P0V_TV_TRIP VR_P0V_TV_RF R 9.K// R 00K///X R 9 0 VIN VIN V VREG MOE TRIP RF P VF EN VIN PG VIN VIN VST VIN LL LL LL LL LL LL U9 TPS/QFN/S uH/0/S L=0nH+/-0% I = 0 Iset =0 R =. (mω) SP 0.u//XR/V/K VR_P0V_Vripple_P L 0.uH/0/S/[0L-00-R_0L-00-0R] Short P/X SP VR_P0V_Vripple_N Short P/X 0.u//XR/V/K u//xr/.v/m u//xr/.v/m u//xr/.v/m u//xr/.v/m u//xr/.v/m u//xr/.v/m 9 P0V_TV R 0/ R0 VR_P_0V_VST./ VR_P_0V_VST_R R9.K// VR_P_0V_F_ n//xr/0v/k 0 0.u//XR/V/K {} PWRG_P_V_LN VR_P0V_TV_EN_R R K// R VR_P_0V_F R R.K// VR_P_0V_F_R Vout= 0.*(R+R)/R = 0.9V PV_UX K// R R 0K// {} PWRG_P0V_TV PWRG_P0V_TV Intel orporation 000 W HNLER LV HNLER, Z 0_TWINVILLE_PWR_P0V Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

48 P_0V_TV_LN VR PV_UX TPS VIN voltage range = V to V, and V voltage range =. to V 0 u//xr/.v/m u//xr/.v/m u//xr/.v/m P0V_VREG R R R 00K///X R K// u//xr/v/k R 00K// R.u//XR/.V/K PV_UX VR_P0V_TV_MOE VR_P0V_TV_TRIP VR_P0V_TV_RF R9 9.K// R0 00K///X R 9 0 VIN VIN V VREG MOE TRIP RF P VF EN VIN PG VIN VIN VST VIN LL LL LL LL LL LL U0 TPS/QFN/S uH/0/S L=0nH+/-0% I = 0 Iset =0 R =. (mω) SP 0.u//XR/V/K VR_P0V_Vripple_P L 0.uH/0/S/[0L-00-R_0L-00-0R] Short P/X SP VR_P0V_Vripple_N Short P/X 0.u//XR/V/K u//xr/.v/m u//xr/.v/m u//xr/.v/m u//xr/.v/m u//xr/.v/m u//xr/.v/m P0V_TV R 0/ R VR_P_0V_VST./ VR_P_0V_VST_R R.K// VR_P_0V_F_ n//xr/0v/k 0.u//XR/V/K {} PWRG_P0V_TV PV_UX VR_P0V_TV_EN_R R K// R VR_P_0V_F R R.K// VR_P_0V_F_R Vout= 0.*(R+R)/R = 0.V K// R R 0K// {} PWRG_P0V_TV PWRG_P0V_TV Intel orporation 000 W HNLER LV HNLER, Z 0_TWINVILLE_PWR_P0V Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

49 PV_PIE_SLOT PV_PIE_SLOT PIE SLOT {0,,,} {0,,,} SM_PV_STY_HOST LK SM_PV_STY_HOST T {9,0,,} PMU_WKE_N_UX {9} PE_SLOT_TX_P0 {9} PE_SLOT_TX_N0 {9} PE_SW_SLOT_TX_P {9} PE_SW_SLOT_TX_N {9} PE_SW_SLOT_TX_P {9} PE_SW_SLOT_TX_N {9} PE_SW_SLOT_TX_P {9} PE_SW_SLOT_TX_N {} PE_MUX_SLOT_TX_P {} PE_MUX_SLOT_TX_N {} PE_MUX_SLOT_TX_P {} PE_MUX_SLOT_TX_N {} PE_MUX_SLOT_TX_P {} PE_MUX_SLOT_TX_N {} PE_MUX_SLOT_TX_P {} PE_MUX_SLOT_TX_N SM_PV_STY_HOST LK R 0/ SM_PV_STY_HOST T R0 0/ R.K/ PMU_WKE_N_UX PE_SLOT_TX_P0 9 0.u//XR/V/K PE_SLOT_TX_N0 0 0.u//XR/V/K PE_SW_SLOT_TX_P 0.u//XR/V/K PE_SW_SLOT_TX_N 0.u//XR/V/K PE_SW_SLOT_TX_P 0.u//XR/V/K PE_SW_SLOT_TX_N 0.u//XR/V/K PE_SW_SLOT_TX_P 0.u//XR/V/K PE_SW_SLOT_TX_N 0.u//XR/V/K PE_MUX_SLOT_TX_P 0.u//XR/V/K PE_MUX_SLOT_TX_N 0.u//XR/V/K PE_MUX_SLOT_TX_P 9 0.u//XR/V/K PE_MUX_SLOT_TX_N 90 0.u//XR/V/K PE_MUX_SLOT_TX_P 9 0.u//XR/V/K PE_MUX_SLOT_TX_N 9 0.u//XR/V/K PE_MUX_SLOT_TX_P 9 0.u//XR/V/K PE_MUX_SLOT_TX_N 9 0.u//XR/V/K PV_TX PV_UX SM_LK_PIE_SLOT SM_T_PIE_SLOT P_PE_SLOT_JTG PE_SLOT TX_P0 PE_SLOT TX_N0 PE_SW_SLOT TX_P PE_SW_SLOT TX_N PE_SW_SLOT TX_P PE_SW_SLOT TX_N PE_SW_SLOT TX_P PE_SW_SLOT TX_N PE_MUX_SLOT TX_P PE_MUX_SLOT TX_N PE_MUX_SLOT TX_P PE_MUX_SLOT TX_N PE_MUX_SLOT TX_P PE_MUX_SLOT TX_N PE_MUX_SLOT TX_P PE_MUX_SLOT TX_N PI-E_ PI_EXPRESS X +V PRSNT# +V +V +V +V SMLK(I) JTG/TK SMT(I/O) JTG/TI JTG/TO 9 +.V JTG/TMS 0 JTG/TRST# +.V 9 +.VUX +.V 0 WKE#(O) PE_RST# ( I ) KEY RSV REFLK+(I) PETP0(I) REFLK-(I) PETN0(I) PERP0(O) PRSNT# PERN0(O) X 9 0 PETP(I) RSV 9 PETN(I) 0 PERP(O) PERN(O) PETP(I) PETN(I) PERP(O) PERN(O) PETP(I) 9 PETN(I) 9 0 PERP(O) 0 RSV PERN(O) PRSNT# RSV X PETP(I) RSV PETN(I) PERP(O) PERN(O) PETP(I) 9 PETN(I) 9 0 PERP(O) 0 PERN(O) PETP(I) PETN(I) PERP(O) PERN(O) PETP(I) PETN(I) PERP(O) 9 PRSNT# PERN(O) X 9 PV_TX P_PE_SLOT_JTG R9 PU_PE_SLOT_JTG R PU_PE_SLOT_JTG R PE_SLOT_RST# R LK_00M_LKUF_SLOT_P LK_00M_LKUF_SLOT_N PE_SLOT_RX_P0 PE_SLOT_RX_N0 PE_SW_SLOT_RX_P PE_SW_SLOT_RX_N PE_SW_SLOT_RX_P PE_SW_SLOT_RX_N PE_SW_SLOT_RX_P PE_SW_SLOT_RX_N PE_MUX_SLOT_RX_P PE_MUX_SLOT_RX_N PE_MUX_SLOT_RX_P PE_MUX_SLOT_RX_N PE_MUX_SLOT_RX_P PE_MUX_SLOT_RX_N PE_MUX_SLOT_RX_P PE_MUX_SLOT_RX_N.K/@SX@S.K/@SX@S.K/@SX@S 0/@SX@S 0p//NPO/0V LK_00M_LKUF_SLOT_P {} LK_00M_LKUF_SLOT_N {} PE_SLOT_RX_P0 {9} PE_SLOT_RX_N0 {9} PE_SW_SLOT_RX_P {9} PE_SW_SLOT_RX_N {9} PE_SW_SLOT_RX_P {9} PE_SW_SLOT_RX_N {9} PE_SW_SLOT_RX_P {9} PE_SW_SLOT_RX_N {9} PE_MUX_SLOT_RX_P {} PE_MUX_SLOT_RX_N {} PE_MUX_SLOT_RX_P {} PE_MUX_SLOT_RX_N {} PE_MUX_SLOT_RX_P {} PE_MUX_SLOT_RX_N {} PE_MUX_SLOT_RX_P {} PE_MUX_SLOT_RX_N {} PV_TX RST_PIE_SLOT_N {0,0,,} PI-E/X-9P/K/OL/OPEN PV_PIE_SLOT PV_TX PV_PIE_SLOT PV_TX PV_UX + E 0u/FP//V/9/0m + E 0u/FP//V/9/0m 9 u//xr/v/k 9 0.u//XR/V/K 9.u//XR/V/K 9 0.u//XR/V/K 9 u//xr/v/k Intel orporation 000 W HNLER LV HNLER, Z 09_PIE_SLOT ( X ) Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of 9

50 PV_PIE_SLOT PIE SLOT PV_PIE_SLOT {9,,,} {9,,,} {} {} {} {} {} {} {} {} SM_PV_STY_HOST LK SM_PV_STY_HOST LK SM_PV_STY_HOST T SM_PV_STY_HOST T PMU_WKE_N_UX {9,9,,} PMU_WKE_N_UX PE_MUX_SLOT_TX_P0 PE_MUX_SLOT_TX_P0 PE_MUX_SLOT_TX_N0 PE_MUX_SLOT_TX_N0 PE_MUX_SLOT_TX_P PE_MUX_SLOT_TX_P PE_MUX_SLOT_TX_N PE_MUX_SLOT_TX_N PE_MUX_SLOT_TX_P PE_MUX_SLOT_TX_P PE_MUX_SLOT_TX_N PE_MUX_SLOT_TX_N PE_MUX_SLOT_TX_P PE_MUX_SLOT_TX_P PE_MUX_SLOT_TX_N PE_MUX_SLOT_TX_N R 0/ R 0/.K/ R u//XR/V/K 0 0.u//XR/V/K 0 0.u//XR/V/K 0 0.u//XR/V/K 0 0.u//XR/V/K 0 0.u//XR/V/K 0 0.u//XR/V/K 0 0.u//XR/V/K PV_TX PV_UX SM_LK_PIE_SLOT SM_T_PIE_SLOT P_PE_SLOT_JTG PE_MUX_SLOT TX_P0 PE_MUX_SLOT TX_N0 PE_MUX_SLOT TX_P PE_MUX_SLOT TX_N PE_MUX_SLOT TX_P PE_MUX_SLOT TX_N PE_MUX_SLOT TX_P PE_MUX_SLOT TX_N PI-E_ PI_EXPRESS X +V PRSNT# +V +V +V +V SMLK(I) JTG/TK SMT(I/O) JTG/TI JTG/TO 9 +.V JTG/TMS 0 JTG/TRST# +.V 9 +.VUX +.V 0 WKE#(O) PE_RST# ( I ) KEY RSV REFLK+(I) PETP0(I) REFLK-(I) PETN0(I) PERP0(O) PRSNT# PERN0(O) X 9 0 PETP(I) RSV 9 PETN(I) 0 PERP(O) PERN(O) PETP(I) PETN(I) PERP(O) PERN(O) PETP(I) 9 PETN(I) 9 0 PERP(O) 0 RSV PERN(O) PRSNT# RSV X PV_TX P_PE_SLOT_JTG PU_PE_SLOT_JTG PU_PE_SLOT_JTG PE_SLOT_RST# R R R9 99 LK_00M_LKUF_SLOT_P LK_00M_LKUF_SLOT_N PE_MUX_SLOT_RX_P0 PE_MUX_SLOT_RX_N0 PE_MUX_SLOT_RX_P PE_MUX_SLOT_RX_N PE_MUX_SLOT_RX_P PE_MUX_SLOT_RX_N PE_MUX_SLOT_RX_P PE_MUX_SLOT_RX_N.K/.K/.K/ R / 0p//NPO/0V/J PV_TX RST_PIE_SLOT_N LK_00M_LKUF_SLOT_P {} LK_00M_LKUF_SLOT_N {} PE_MUX_SLOT_RX_P0 {} PE_MUX_SLOT_RX_N0 {} PE_MUX_SLOT_RX_P {} PE_MUX_SLOT_RX_N {} PE_MUX_SLOT_RX_P {} PE_MUX_SLOT_RX_N {} PE_MUX_SLOT_RX_P {} PE_MUX_SLOT_RX_N {} RST_PIE_SLOT_N {0,9,,} PI-E/X-P/K/OL/OPEN PV_PIE_SLOT PV_UX 0 0.u//XR/V/K 09 0.u//XR/V/K 0 0.u//XR/V/K 0.u//XR/V/K u//xr/v/k PV_TX 0.u//XR/V/K 0.u//XR/V/K u//xr/v/k Intel orporation 000 W HNLER LV HNLER, Z 00_PIE_SLOT ( X ) Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of 0

51 PV_PIE_SLOT PV_PIE_SLOT PIE SLOT {9,0,,} {9,0,,} SM_PV_STY_HOST LK SM_PV_STY_HOST LK SM_PV_STY_HOST T SM_PV_STY_HOST T PMU_WKE_N_UX {9,9,0,} PMU_WKE_N_UX R / R /.K/ R PV_TX PV_UX SM_LK_PIE_SLOT SM_T_PIE_SLOT P_PE_SLOT_JTG PI-E_ PI_EXPRESS X +V PRSNT# +V +V +V +V SMLK(I) JTG/TK SMT(I/O) JTG/TI JTG/TO 9 +.V JTG/TMS 0 JTG/TRST# +.V 9 +.VUX +.V 0 WKE#(O) PE_RST# ( I ) KEY PV_TX P_PE_SLOT_JTG PU_PE_SLOT_JTG PU_PE_SLOT_JTG PE_SLOT_RST# R R R.K/.K/.K/ R9 / PV_TX RST_PIE_SLOT_N RST_PIE_SLOT_N {0,9,0,} {} {} {} {} {} {} {} {} PE_MUX_SLOT_TX_P0 PE_MUX_SLOT_TX_N0 PE_MUX_SLOT_TX_P PE_MUX_SLOT_TX_N PE_MUX_SLOT_TX_P PE_MUX_SLOT_TX_N PE_MUX_SLOT_TX_P PE_MUX_SLOT_TX_N PE_MUX_SLOT_TX_P0 PE_MUX_SLOT_TX_N0 PE_MUX_SLOT_TX_P PE_MUX_SLOT_TX_N PE_MUX_SLOT_TX_P PE_MUX_SLOT_TX_N PE_MUX_SLOT_TX_P PE_MUX_SLOT_TX_N u//XR/0V/K 0.u//XR/0V/K 0.u//XR/0V/K 0.u//XR/0V/K 0.u//XR/0V/K 0.u//XR/0V/K 0.u//XR/0V/K 0.u//XR/0V/K PE_MUX_SLOT TX_P0 PE_MUX_SLOT TX_N0 PE_MUX_SLOT TX_P PE_MUX_SLOT TX_N PE_MUX_SLOT TX_P PE_MUX_SLOT TX_N PE_MUX_SLOT TX_P PE_MUX_SLOT TX_N RSV PETP0(I) PETN0(I) PRSNT# PETP(I) PETN(I) PETP(I) PETN(I) PETP(I) PETN(I) RSV PRSNT# X X REFLK+(I) REFLK-(I) PERP0(O) PERN0(O) RSV PERP(O) PERN(O) PERP(O) PERN(O) PERP(O) PERN(O) RSV LK_00M_LKUF_SLOT_P LK_00M_LKUF_SLOT_N PE_MUX_SLOT_RX_P0 PE_MUX_SLOT_RX_N0 PE_MUX_SLOT_RX_P PE_MUX_SLOT_RX_N PE_MUX_SLOT_RX_P PE_MUX_SLOT_RX_N PE_MUX_SLOT_RX_P PE_MUX_SLOT_RX_N 0p//NPO/0V/J LK_00M_LKUF_SLOT_P {} LK_00M_LKUF_SLOT_N {} PE_MUX_SLOT_RX_P0 {} PE_MUX_SLOT_RX_N0 {} PE_MUX_SLOT_RX_P {} PE_MUX_SLOT_RX_N {} PE_MUX_SLOT_RX_P {} PE_MUX_SLOT_RX_N {} PE_MUX_SLOT_RX_P {} PE_MUX_SLOT_RX_N {} PI-E/X-P/K/OL/OPEN PV_PIE_SLOT PV_UX 0.u//XR/V/K 0.u//XR/V/K 0.u//XR/V/K 0.u//XR/V/K 9 u//xr/v/k PV_TX 0 0.u//XR/V/K 0.u//XR/V/K u//xr/v/k Intel orporation 000 W HNLER LV HNLER, Z 0_PIE_SLOT ( X ) Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

52 PV_PIE_SLOT PV_TX PI-E_ PIE SLOT PV_PIE_SLOT PV_TX PV_TX {9,0,,} SM_PV_STY_HOST LK {9,0,,} SM_PV_STY_HOST T {9,9,0,} PMU_WKE_N_UX SM_PV_STY_HOST LK SM_PV_STY_HOST T PMU_WKE_N_UX 0/ R 0/ R.K/ R SM_LK_PIE_SLOT SM_T_PIE_SLOT P_PE_SLOT_JTG PV_UX 9 0 PI_EXPRESS X +V PRSNT# +V +V +V +V SMLK(I) JTG/TK SMT(I/O) JTG/TI JTG/TO +.V JTG/TMS JTG/TRST# +.V 9 +.VUX +.V 0 WKE#(O) PE_RST# ( I ) KEY P_PE_SLOT_JTG PU_E_SLOT_JTG PU_PE_SLOT_JTG PE_SLOT_RST# R R R R 0/.K/.K/.K/ RST_PIE_SLOT_N RST_PIE_SLOT_N {0,9,0,} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} PE_VN_SLOT_TX_P0 PE_VN_SLOT_TX_N0 PE_VN_SLOT_TX_P PE_VN_SLOT_TX_N PE_VN_SLOT_TX_P PE_VN_SLOT_TX_N PE_VN_SLOT_TX_P PE_VN_SLOT_TX_N PE_MUX_SLOT_TX_P PE_MUX_SLOT_TX_N PE_MUX_SLOT_TX_P PE_MUX_SLOT_TX_N PE_MUX_SLOT_TX_P PE_MUX_SLOT_TX_N PE_MUX_SLOT_TX_P PE_MUX_SLOT_TX_N PE_VN_SLOT_TX_P0 PE_VN_SLOT_TX_N0 PE_VN_SLOT_TX_P PE_VN_SLOT_TX_N PE_VN_SLOT_TX_P PE_VN_SLOT_TX_N PE_VN_SLOT_TX_P PE_VN_SLOT_TX_N PE_MUX_SLOT_TX_P PE_MUX_SLOT_TX_N PE_MUX_SLOT_TX_P PE_MUX_SLOT_TX_N PE_MUX_SLOT_TX_P PE_MUX_SLOT_TX_N PE_MUX_SLOT_TX_P PE_MUX_SLOT_TX_N u//XR/0V/K 0.u//XR/0V/K 0.u//XR/0V/K 0.u//XR/0V/K 0.u//XR/0V/K 0.u//XR/0V/K 0.u//XR/0V/K 0.u//XR/0V/K 0.u//XR/0V/K 0.u//XR/0V/K 0.u//XR/0V/K 0.u//XR/0V/K 0.u//XR/0V/K 0.u//XR/0V/K 0.u//XR/0V/K 0.u//XR/0V/K PE_VN_SLOT TX_P0 PE_VN_SLOT TX_N0 PE_VN_SLOT TX_P PE_VN_SLOT TX_N PE_VN_SLOT TX_P PE_VN_SLOT TX_N PE_VN_SLOT TX_P PE_VN_SLOT TX_N PE_MUX_SLOT TX_P PE_MUX_SLOT TX_N PE_MUX_SLOT TX_P PE_MUX_SLOT TX_N PE_MUX_SLOT TX_P PE_MUX_SLOT TX_N PE_MUX_SLOT TX_P PE_MUX_SLOT TX_N RSV PETP0(I) PETN0(I) PRSNT# PETP(I) PETN(I) PETP(I) PETN(I) PETP(I) PETN(I) RSV PRSNT# PETP(I) PETN(I) PETP(I) PETN(I) PETP(I) PETN(I) PETP(I) PETN(I) PRSNT# PETP(I) PETN(I) PETP9(I) PETN9(I) PETP0(I) PETN0(I) PETP(I) PETN(I) PETP(I) PETN(I) PETP(I) PETN(I) PETP(I) PETN(I) PETP(I) PETN(I) PRSNT# RSV X X X X REFLK+(I) REFLK-(I) PERP0(O) PERN0(O) RSV PERP(O) PERN(O) PERP(O) PERN(O) PERP(O) PERN(O) RSV RSV PERP(O) PERN(O) PERP(O) PERN(O) PERP(O) PERN(O) PERP(O) PERN(O) RSV PERP(O) PERN(O) PERP9(O) PERN9(O) PERP0(O) PERN0(O) PERP(O) PERN(O) PERP(O) PERN(O) PERP(O) PERN(O) PERP(O) PERN(O) PERP(O) PERN(O) LK_00M_LKUF_SLOT_P LK_00M_LKUF_SLOT_N PE_VN_SLOT_RX_P0 PE_VN_SLOT_RX_N0 PE_VN_SLOT_RX_P PE_VN_SLOT_RX_N PE_VN_SLOT_RX_P PE_VN_SLOT_RX_N PE_VN_SLOT_RX_P PE_VN_SLOT_RX_N PE_MUX_SLOT_RX_P PE_MUX_SLOT_RX_N PE_MUX_SLOT_RX_P PE_MUX_SLOT_RX_N PE_MUX_SLOT_RX_P PE_MUX_SLOT_RX_N PE_MUX_SLOT_RX_P PE_MUX_SLOT_RX_N LK_00M_LKUF_SLOT_P {} LK_00M_LKUF_SLOT_N {} PE_VN_SLOT_RX_P0 {} PE_VN_SLOT_RX_N0 {} PE_VN_SLOT_RX_P {} PE_VN_SLOT_RX_N {} PE_VN_SLOT_RX_P {} PE_VN_SLOT_RX_N {} PE_VN_SLOT_RX_P {} PE_VN_SLOT_RX_N {} PE_MUX_SLOT_RX_P {} PE_MUX_SLOT_RX_N {} PE_MUX_SLOT_RX_P {} PE_MUX_SLOT_RX_N {} PE_MUX_SLOT_RX_P {} PE_MUX_SLOT_RX_N {} PE_MUX_SLOT_RX_P {} PE_MUX_SLOT_RX_N {} n//xr/0v/k/x PE_SLOT_RST# PI-E/X-P/K/OL/GF/[-0-LR_-0-0R] PV_PIE_SLOT PV_TX 9 0.u//XR/V/K 90.u//XR/V/K 0 0.u//XR/V/K 0.u//XR/V/K 0.u//XR/V/K.u//XR/V/K 0.u//XR/V/K.u//XR/V/K PV_PIE_SLOT PV_TX PV_UX + E 0u/FP//V/9/0m + E 0u/FP//V/9/0m u//xr/v/k Intel orporation 000 W HNLER LV HNLER, Z 0_PIE_SLOT ( X) Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

53 PV_STY.K/ R.K/ R.K/ R9.K/ R90 SM_PV_STY_HOST T SM_PV_STY_HOST LK SM_PV_STY_HOST_T SM_PV_STY_HOST_LK {9,0,,} {9,0,,} H_PROHOT_O_N R00 0/ VR_PVP_PNN_VRHOT_N {0} H_PROHOT_O_N VR_PVP_PNN_VRHOT_N {,} SM_PV_STY_HOST T R 0//X SM_PV_STY_HOST_T SM_PV_STY_HOST T SM_PV_STY_HOST LK SM_PV_STY_HOST LK R 0//X SM_PV_STY_HOST_LK SM_HOST_LRT_N {0} SM_HOST_LRT_N.K/ R9 PRSNT_SLOT PV_STY PV_STY U9 PV_STY R9.K/ _F0 _F LN_PHY_EN {} LN_PHY_EN IOS_SPI_PORT_N {0} IOS_SPI_PORT_N PV_STY In In OUT OUT U 0 I/O0 I/O I/O I/O V S SL /INT I/O I/O 0 I/O 9 I/O P9PW/TSSOP/S ddress :0x In In 0.u//XR/V/K SM_PV_HOST_T SM_PV_HOST_LK R9 0/ PU_SV RT_MOS_LER MNFTURING_NORML SM_PV_HOST_T {0,9,0,,,,,0} SM_PV_HOST_LK {0,9,0,,,,,0} PRSNT_SLOT PRSNT_SLOT {} SM_PV_HOST_T SM_PV_HOST_LK SM_HOST_LRT_N V OE OE OE OE N N 9 Y Y Y 0 Y SM_PV_STY_HOST_T SM_PV_STY_HOST_T {,,} SM_PV_STY_HOST_LK SM_PV_STY_HOST_LK {,,} SM_PV_STY_HOST_LERT SM_PV_STY_HOST_LERT {} PV_STY SM_PV_STY_HOST_LERT 0K/ R0.K/ R9.K//X R9.K//X R9 LN_PHY_EN MNFTURING_NORML PU_SV {0,9,,,,0,9,} PLTRST_N PLTRST_N R0.K/ ITQSVHQG/QSOP R9 0/ R9 0/ R9 0//X PV_STY PV_STY.K/ R0.K//X R0 Fab I _F _F0 0 0 Fab 0 Fab 0 Fab Fab R0 0/ R0 0//X _F0 _F RT_MOS_LER R9 0K// R9 0/ JP JP PH/*/K/./V/ JP/*/K/OH/./O/GF::[-]LOSE RT_MOS_LER 0 - Normal Mode - RT/MOS LER Intel orporation 000 W HNLER LV HNLER, Z 0_MGT_PIE_GF ( X ) Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

54 PV_STY PV_STY 0 0.u//YV/V/Z/X {} {} PWRG_P0V_TV PWRG_PV0_SW PWRG_OREPWR PWRG_OREPWR {0,9} {} LKPWRG_ELYE R0 0/ {} LKPWRG_R PV_STY U00 {0,,9,0} SLP_S_N R0 0K// R09 K/ MT90WTG/SOT/00m/00 MT90W PV_STY PV.u//XR/.V/K R0 0//X G S Q PM00-TRL/SOT/0pF/0m PV PV_STY 9 0.u//XR/V/K 0 0.u//XR/V/K 0.u//XR/V/K Q N00P/SOT/0pF/ G S PV_STY {9} PWRG_PV0 G S Ic > Ib R.K/ Q9 PM00-TRL/SOT/0pF/0m G S PV_STY PV R.K/ 0.u//XR/V/K 0.u//XR/V/K PV PV_VSTY_UX PV Q MMT/SOT/00m/0 E G S 0.u//XR/V/K G S R09.K/ G S Q N00/SOT/pF/ G S G S Q0 N00/SOT/pF/ G S 0 0.u//YV/V/Z/X U SNLVG0GV/SOT- U SNLVG0GV/SOT- R00.K/ R0.K/ u//xr/.v/k/x R0.K/ 0.u//XR/V/K u//xr/.v/k/x PV R.K/ PV_STY SR/SM/ FOR PVR 0.u//XR/V/K/X SR/SM/ Vf=0.V@ Intel orporation 000 W HNLER LV HNLER, Z 0_SEQUENE REQUIREMENT Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

55 ST Gbps ST T {} {} {} {} STG_RX_P0 STG_RX_N0 STG TX_N0 STG TX_P0 STG_RX_P0 STG_RX_N0 STG TX_N0 STG TX_P u//XR/0V/K STG RX_P0 0.0u//XR/0V/K STG RX_N0 ST RX+ RX- TX- TX+ T RX+ RX- 0 TX- 9 TX+ STG RX_P STG RX_N 0.0u//XR/0V/K 0.0u//XR/0V/K ST 0 STG_RX_P STG_RX_N STG TX_N STG TX_P STG_RX_P {} STG_RX_N {} STG TX_N {} STG TX_P {} White ST//WH/H/OP/R///[NR-0-R_NR-0-R] ST T {} {} {} {} STG_RX_P STG_RX_N STG TX_N STG TX_P STG_RX_P STG_RX_N STG TX_N STG TX_P 0.0u//XR/0V/K 0.0u//XR/0V/K STG RX_P STG RX_N RX+ RX- TX- TX+ RX+ RX- 0 TX- 9 TX+ STG RX_P STG RX_N ST T ST 0.0u//XR/0V/K 0.0u//XR/0V/K 9 STG_RX_P STG_RX_N STG TX_N STG TX_P STG_RX_P {} STG_RX_N {} STG TX_N {} STG TX_P {} White ST//WH/H/OP/R///[NR-0-R_NR-0-R] ll PS NER TO ONNETOR ST Gbps ST {} STG_RX_P0 {} STG_RX_N0 {} STG TX_N0 {} STG TX_P0 STG_RX_P0 STG_RX_N0 STG TX_N0 STG TX_P u//XR/0V/K 0.0u//XR/0V/K STG RX_P0 STG RX_N0 9 T RX+ RX- TX- TX+ T ST//K/H/OP/V////G ST {} STG_RX_P {} STG_RX_N {} STG TX_N {} STG TX_P STG_RX_P STG_RX_N STG TX_N STG TX_P u//XR/0V/K 0.0u//XR/0V/K STG RX_P STG RX_N 9 T RX+ RX- TX- TX+ T ST//K/H/OP/V////G lack Intel orporation 000 W HNLER LV HNLER, Z 0_ST_ONNETORS Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

56 Rear_US US.0 O PV_UX PV_R_US PV_UX PV_R_US 0MIL LOSE TO US ONNETOR FS minism0f-/0./s 0MIL 0MIL LOSE TO US ONNETOR FS minism0f-/0./s 0MIL PV_R_US PV_R_US 0 0.u//XR/V/K 0 0.u//XR/V/K + E 0u/FP//V/9/0m + E 0u/FP//V/9/0m U R_US {} {} {} {} US_P_P US_P_N US_P_P US_P_N US_R_P_P US_R_P_N US_R_P_P US_R_P_N L 90OHM/00m//S/[0L R_0L R] US_R_P_P US_R_P_P Z099-0S/SOT-L US_R_P_N US_R_P_N 0 0.u//XR/V/K PV_UX US_R_P_N US_R_P_P 0 9 US//K/S/R///GF US_R_P_N US_R_P_P PV_R_US PV_STY PV_R_US 0 0.u//YV/V/Z/X R 0K// R 0K// U HG0GV/SOT- USO_R_US_N Front_US {} {} {} {} US_P0_P US_P0_N US_P_P US_P_N FRONT US (US HEER) L US_P0_P US_F_P0_P US_P0_N US_F_P0_N US_P_P US_F_P_P US_P_N US_F_P_N 90OHM/00m//MU/S US_F_P_P US_F_P0_P U9 Z099-0S/SOT-L US_F_P_N US_F_P0_N 0 0.u//XR/V/K PV_UX EMI Suggest PV_UX PV_F_US0 PV_UX PV_F_US PV_F_US0 (VI= or VI=) PV_F_US 0MIL LOSE TO US ONNETOR FS nanosm0f/0./s 0MIL 0MIL LOSE TO US ONNETOR FS nanosm0f/0./s 0MIL US_F_P_N US_F_P_P F_US 0 US_F_P0_N US_F_P0_P 0 0.u//XR/V/K 0 0.u//XR/V/K E + PH/*K9/YL/./V/S + E PV_F_US0 PV_STY PV_STY 0u/FP/S/.V//m/[0O-00-0R_0O-00-0R] 0u/FP/S/.V//m/[0O-00-0R_0O-00-0R] PV_F_US 09 0.u//YV/V/Z/X 0 0.u//YV/V/Z/X R 0K// R 0K// U HG0GV/SOT- USO_R_US_N USO_F_US0_N U0 USO_F_R_N HG0GV/SOT- R 0/ USO_F_N R9 K//X USO_F_N {} 0.u//XR/V/K Intel orporation 000 W HNLER LV HNLER, Z 0_US_ONNETRORS Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

57 PV R./ R0 PV_TX PV_UX R.K/ 0/ G G S S PWR_LE Q N00/SOT/pF/ FP_PWR_TN_N R9./ FP_PWR_TN N 0.u//XR/V/K F_PNEL 9 PH/*K0/K/./V/ FP_RST_TN N LE_H_TIVITY R./ R9./ FP_RST_TN_N R./ 0.u//XR/V/K PV_TX R 0/ R90./ Q MMT/SOT/00m/0 u//xr/.v/k/x LE_H_TIVITY E PV PV {0,,9,0} SLP_S_N SLP_S_N R.K/ u//xr/.v/k/x {0,9,,,,0,9,} PLTRST_N {} LE_ST_T_N {} LE_SS_T_N PLTRST_N LE_ST_T_N LE_SS_T_N T/SOT/00m R 0/ R.K/ R.K/ 0.u//XR/V/K U LE_H_T_N LE_ST_T_N R.K/ PV SNLVG0GV/SOT- R9 0/ LE_H_TIVITY PV Q G S N00/SOT/0pF/./.V/[*0IF-00-0R] R0 H_LE_0R_N G S.K/ H_LE_0R_N Power button PV_STY PV_STY PV_STY PV_STY PV_STY FP_PWR_TN_N PWR_SW SW/HH/STS-/[0NH-0000-F0R] R.K/ 0.u//XR/V/K R.K//X 0.u//XR/V/K R.K//X "EV hook" R9 0//X R 00// FP_PWR_TN_R_N R 00// R 00// PWR_FP_TN_N_GTE {9} 0.u//XR/V/K/X 0 0.u//XR/V/K U SNHGVR/SOT- u//xr/.v/k U SNHGVR/SOT- Reset button "EV hook" FP_RST_TN_N R9 0//X RST_SW SW/HH/STS-/[0NH-0000-F0R] PV PV PV PV R.K/ R9 0.u//XR/V/K.K//X 0.u//XR/V/K PV R.K//X R 00// FP_RST_TN_R_N R 00// R 00// RST_FP_TN_N_GTE {9} 0.u//XR/V/K/X 0.u//XR/V/K U SNHGVR/SOT- u//xr/.v/k U SNHGVR/SOT- Intel orporation 0_F_PNEL 000 W HNLER LV HNLER, Z Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

58 V S EFULT TURN ON PV SYSTEM FRONT FN PV_SYS_FN_FUSE G V S V S FS 0SFS00F// + E9 00u/OS//V//m 9 0u//XR/V/K FRONT_FN FN/*/WH//./V//SN EFULT TURN ON PV SYSTEM SIE OOR FN FS PV_SYS_FN_FUSE 0SFS00F// + E0 00u/OS//V//m EFULT TURN ON PV SYSTEM RER FN FS P_SYS_FN_FUSE 0SFS00F// 9 0u//XR/V/K G 9 0u//XR/V/K G SYS_FN FN/*/WH//./V//SN + E 00u/OS//V//m RER_FN FN/*/WH//./V//SN PU FN LN FN PV FS PV_PU_FN_FUSE PU_FN PV FS9 PV_LN_FN_FUSE LN_FN 0SFS00F// + E 00u/OS//V//m 9 0u//XR/V/K FN/*/WH//./V//SN + E 00u/OS//V//m 0SFS00F// 9 0u//XR/V/K FN/*/WH//./V//SN Intel orporation 0_FN_ONNETOR 000 W HNLER LV HNLER, Z Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

59 Golden Finger PV_PIE_SLOT PIE_GF {0,,} PWRG_PS PV_STY PWRG_PS 0.u//XR/V/K PWRG_PS_R 0/ R9 PV R 0K// PV_TX PV_TX PV_TX PV_TX 0.u//XR/V/K 9.u//XR/V/K 9.u//XR/V/K 0.u//XR/V/K PV_TX PI_EXPRESS X GF +_PIE +_PIE +_PIE +_PIE +_PIE +_PIE +_PIE +_PIE +_PIE 9 +_PIE 0 +_PIE KEY +.V +.V +.V +.V +.V +.V +.V +.V +.V 9 X 0 +V PS_ON# +V +V +V +V +V 9 0 PWROK X +VSTY +VSTY +VSTY +VSTY +V +VSTY +V 9 +VSTY +V 0 +V +V +V +V +V +V +V +V +V +V +V +V +.V +.V X +.V 9 PV_PIE_SLOT PV_TX PV_TX 0.n//XR/0V/K PV_TX 0.u//XR/V/K PV_STY 9.u//XR/V/K R K//X Power supply has internal pull-up resistor inside. PS_EN_PSU_N 0.u//XR/V/K S S G G R0 0K/ Q N00/SOT/0pF/./.V/[*0IF-00-0R] 0/ R SLP_S_N {0,,,0} PI-E/9/GF/X PWRG_PS_R PV_PIE_SLOT PV_TX 0 0.u//XR/V/K/X 0.0u//XR/V/K/X 0.0u//XR/V/K/X Intel orporation 09_TX_POWER 000 W HNLER LV HNLER, Z Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of 9

60 PV_UX SWITH PM0 : -. ; -0V Rds(on) : mohms (max),vgs = -. V Rds(on) : mohms (max),vgs = -0 V VSS = -0 V ; VGSS = +/- V VGS(th) = -.V (typ.) P MOS U9 PM0-TRG/TSOP/00pF/m/[0IF-00-0R] PV_UX TO PV_STY US PV_STY 0.0u//XR/0V/K Soft Start VS_RV_R R 0K//X G S PV_STY 00 0u//XR/V/K G S N MOS Q9 EMN0/TO/9pF/m/[0IF-0-00R_0IF-0-00R_0IF-09-00R] PV_TX + E 00u/OS//V//m 99 0u//XR/V/K PV_TX R 0/ 0.u//XR/V/K up0_v PV R K/ 0.u//XR/V/K V_RV 9 0.u//XR/V/K/X PV_STY PV_STY R R 0/.K/ > 0mil up0_vs up0_moe U0 V VS MOE V_RV VS_RV S# S# VS_RV up0_s# up0_s# R 0/ R 0/ R 0/ VS_RV_R SLP_S_N SLP_S_N SLP_S_N {0,,} SLP_S_N {0,,,9} up0/sot- MOE : HI = S/S PV_UX FROM PV_STY LOW = S/S SHUTOWN PV_UX SWITH PV_STY PV_TX 0u//XR/V/K PV_UX PV U PMK-TRG/SO/N990pF/P0pF//[0IF-0-00R] R.K/ PV_UX_SW_EN PV_TX S G N PV_STY R.K/ R99 0/ G G S S Q0 N00/SOT/pF/ R00 0/ PV_STY u//xr/.v/k/x S G P - 0 0u//XR/V/K 0 0.u//XR/V/K 0.u//XR/V/K + E 00u/OS//V//m 0.u//XR/V/K/X Q N00P/SOT/0pF/ G S u//xr/.v/k/x G S 0 0u//XR/V/K R9.K//X 9 0u//XR/V/K R0 0/ R.K/ {9,,} PWRG_PS Pull-up resistor is R@page u//xr/.v/k/x Intel orporation 000 W HNLER LV HNLER, Z 00_PV_V_UX_SWITH Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of 0

61 R 0//X PV_UX PV_UX PV_UX R 0//X R 0/ VR_FET_SW_PV_STY 0 0u//XR/V/K P0 u//xr/v/k F 0///S R 0/ 0.u//XR/V/K PV_STY PV_UX _PV_STY _PV_STY U {0} PWRG_PV0_STY R90 0/ 0 u//xr/v/k/x R9 K///X R9 K///X VR_PV_STY_VIN VR_EN_PV_STY PWRG_PV_STY_R VR_PV_STY_RLLM VR_PV_STY_SS VIN PVIN PVIN LLM_SYN PVIN0 ENLE VOUT VOUT POK VOUT 9 VOUT RLLM VOUT 0 VOUT SS VOUT u//XR/.V/M u//xr/.v/m P 00u//XR/.V/M/X {} PWRG_PV_STY R9 0/ PV_UX R9 0K// R9 K//X _PV_STY _PV_STY 0 0.0u//XR/V/K VF 9 THP ENQI/QFN/S P P P P P P0 _PV_STY R9 0/ VR_PV_STY_VF p//xr/0v/k VR_PV_STY_VF_R R9 9K// R9 00K// _PV_STY R9 0/ _PV_STY Intel orporation 0_PV_STY 000 W HNLER LV HNLER, Z Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

62 PV_STY PV_R_VREF_H_Q PV_STY PVR 0.u//XR/V/K PVR 0.u//XR/V/K {,,} SM_PV_STY_HOST_LK {,,} SM_PV_STY_HOST_T SM_PV_STY_HOST_LK SM_PV_STY_HOST_T R99 0/ R0 0/ U V ISL90 SL S RW RH ISL90WIEZ-TK/S0- VREF_Q RW R0.K/ U + - VREF_Q OP_F R00 00///X R0./ VREF_Q INT R0 0/ PV_R_VREF_H_Q0 PV_R_VREF_H_Q "EV hook" "EV hook" R9 0//X R9 0//X RESS = 0x R0.K/ R0 00// u//xr/.v/k/x R0 0/ LMVIVR/SOT-/[0T-00-0R_0T-0-R] PV_R_VREF_H_Q PV_STY PVR VREF_Q RW U9 + - VREF_Q OP_F R0 00///X R09./ VREF_Q INT R0 0/ PV_R_VREF_H_Q0 PV_R_VREF_H_Q "EV hook" "EV hook" R9 0//X R9 0//X R 00// u//xr/.v/k/x R 0/ LMVIVR/SOT-/[0T-00-0R_0T-0-R] Intel orporation 000 W HNLER LV HNLER, Z 0_VN/RGY_R_VREF Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

63 PV_STY VR_FET_SW_PV_ VR_PVR F R 0/ R / R9 0//X SVI_LERT_N SVI_LK SVI_T R9 0//X R99.// R90 00// PV0 PV0 PV_STY PV_STY R R R.K///X 0K// K///X R 0/ VR_PVR VIN 0.u//XR/V/K VR_PVR VP U//XR/V/K U//XR/V/K VR_PVR V PVR compensate 0 n//xr/0v/k R.K// EV hooks VR_PVR VW {0,,0} SLP_S_N {} VR_PVR PWRG {0,} SVI_T {0,} SVI_LERT_N {0,} SVI_LK {,} VR_PVP_PNN_VRHOT_N R0 0/ R9 0/ R0 0/ R 0/ 9 n//xr/0v/k TP VR_PWREN_PVR_ VR_PVR PWRG SVI_IO_ SVI LERT_N SVI_LK_ VR_PVP_PNN_VRHOT_N VR_PVR VW VR_PVR OMP TP_PVR F VR_PVR F VR_PVR VSEN VSENSE_PVR VRTN VR_PVR_ISUMP 9 U V 0 0 ISEN OMP ISEN F ISEN F PWM VSEN 9 VR_ON PGOO S LERT# SLK VR_HOT# VW RTN ISUMP VIN 9 VP ISLRTZ-T/QFN0/[0T-0-0R] VR_PVR OOT OOT VR_PVR GH UG VR_PVR PHSE PH VR_PVR GL LG OOT UG PH LG VSET VSET 0 TP_PVR OOT TP_PVR UG TP_PVR PH TP_PVR LG ISENSE_PVR ISEN VR_PVR ISEN TP_PVR ISEN VR_PVR PWM VR_PVR VUTO VR_PVR IUTO TP TP TP TP TP9 VR_PVR OOT {} VR_PVR GH {} VR_PVR PHSE {} VR_PVR GL {} R 0/ R 0/ R 0K//X PVR R9 K///X.n//XR/0V/K R K// p//npo/0v/j VR_PVR OMP VR_PVR SUMN VR_PVR OVP VR_PVR SVI_R 9 0 ISUMN OVP R NT n//xr/0v/k/x VR_PVR NT R 0/ R 0/ n//xr/0v/k/x VR_PVR NT_R R.K// R 9//.n//XR/0V/K VR_PVR F VR_PVR IMON VR_PVR PROG VR_PVR PROG VR_PVR PSI IMON PROG PROG PSI P P n//xr/0v/k/x R9.K// R0 0K// T RT 00K///S VR_PVR VSEN R 0/ VSENSE_PVR VSEN VSENSE_PVR VSEN {} R 0K// R // n//xr/0v/k R K// R.0K// R.0K// R9 0/ OTTOM P ONNET TO Through VIs Place close to VR_ inductor R0.M///X n//xr/v/k/x VSENSE_PVR VRTN VSENSE_PVR VRTN {} R=.0K, Imax= R=.0K, R Voltage=.V PVR Isense compensate VR_PVR_ISUMP VR_PVR_ISUMP VR_PVR_ISUMP {} VR_PVR SUMN 0p//XR/0V/K 00// 0 R R // 9 0.0u//XR/V/K VR_PVR_ISUMN R K// 0.u//XR/V/K 9 0.u//XR/0V/K 0.u//XR/V/K R.K// RT 0K///S T VR_PVR_ISUMN {} ISENSE_PVR ISEN ISENSE_PVR_ISEN {} Intel orporation 000 W HNLER LV HNLER, Z 0_VN/RGY_PVR Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

64 9 PV_VSTY_UX L 0.uH//S/[0L-00-0R] VR_FET_SW_PV_ E 0u/FP//V/9/0m INPUT HOKE VR_FET_SW_PV_ {} VR_PVR OOT {} VR_PVR GH {} VR_PVR PHSE {} VR_PVR GL 0.u//XR/V/K VR_PVR OOT U VR_PVR GH_R R R HG 0/ 0K// VR_PVR GH VR_PVR PHSE R9 PH 0/ VR_PR GL VR_PVR GL_R LG S0Q/SON/S/[0T-0-00R] R 0K// P VIN(,) VSW VSW VSW R./ VR_PVR SNU.n//XR/0V/K 0.u//XR/V/K 0.uH//S/.m/I L SP SP Short P/X Short P/X 0 0u//XR/V/K VR_PVR_R_ISUMN VR_PVR_R_IS 0 0u//XR/V/K PVR 0 u//xr/.v/m R 0// R 0K// HOKE Spec. MGI : PLT0P-R0M-L. L : 0. uh +/- 0% Idc : 0 () Isat : 0 () R :.m type /.m max VR_PVR_ISUMN ISENSE_PVR_ISEN VR_PVR_ISUMN {} ISENSE_PVR_ISEN {} PVR Vsense VR_PVR VTT PVR REMOTE Sense R.K// VR_PVR_ISUMP VR_PVR_ISUMP {} {} VSENSE_PVR VSEN VSENSE_PVR VSEN R 0/ R 0/ R.99K///X Place close to controller {} VSENSE_PVR VRTN VSENSE_PVR VRTN R 0/ PLE NER SENSE LOTION PVR PVR PVR OUTPUT P 0U + JP PH/*/K/./V/ E 0u/S/V/X/m E 0u/S/V/X/m EV hooks PVR PVR PVR OUTPUT P u*9 0u//XR/.V/M 0u//XR/.V/M 0u//XR/.V/M 0u//XR/.V/M 0 u//xr/.v/m 0 u//xr/.v/m 09 u//xr/.v/m 0 u//xr/.v/m u//xr/.v/m u//xr/.v/m u//xr/.v/m u//xr/.v/m u//xr/.v/m 0u//XR/.V/M 9 0u//XR/.V/M 0 0u//XR/.V/M 0u//XR/.V/M PVR OUTPUT P 00U * PVR P 00u//XR/.V/M/X P 00u//XR/.V/M/X Intel orporation 000 W HNLER LV HNLER, Z 0_VN/RGY_PVR_POWER STGE Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

65 {0} PVTT EN_N PVTT EN_N PVR PVR PV_STY EN pull high <.V PV_STY PV_STY R0 0K// R 0/ R9 0K// U TPS00 Vcc <.V PG pull high <.V R 0/ R 00K// PVTT_ n//xr/0v/k R 0K// R 0//X 0u//XR/.V/M 0u//XR/.V/M R 0/ VR_PVTT VREFIN VR_PVTT EN VR_PVTT VLOIN VR_PVTT REFOUT 0.u//XR/V/K REFIN EN VLOIN REFOUT P THERML P VIN 0 PGOO 9 Vo VOSNS VR_PVTT V PWRG_PVTT_ VSENSE_PVTT_ R 0/ 0.u//XR/V/K 0u//XR/.V/M 9 0u//XR/.V/M 0 0u//XR/.V/M u//xr/.v/m R.// ummy Resistor as for VOUT ischarge when VIN is not present but VNTL is present n//xr/0v/k/x TPS00RR/SON0/./[0GLK-0-00R] lose to the controller PVTT_ VSENSE_PVTT_ VSENSE_PVTT_ R9 0//X R99 0//X R9 0//X EV hooks PVTT_ EV hooks EV hooks R99 0//X PVTT EN_N PVR PVR PV_STY EN pull high <.V PV_STY PV_STY EV hooks R0 0K// R 0/ R9 0K///X U9 TPS00 Vcc <.V PG pull high <.V R 0/ R 00K// PVTT_ n//xr/0v/k R 0K// R 0//X 9 0u//XR/.V/M 9 0u//XR/.V/M R 0/ 90 VR_PVTT VREFIN VR_PVTT EN VR_PVTT VLOIN VR_PVTT REFOUT 0.u//XR/V/K REFIN EN VLOIN REFOUT P THERML P VIN 0 PGOO 9 Vo VOSNS VR_PVTT V PWRG_PVTT_ VSENSE_PVTT_ R 0/ 0.u//XR/V/K 0u//XR/.V/M 0u//XR/.V/M 9 0u//XR/.V/M u//xr/.v/m R.// ummy Resistor as for VOUT ischarge when VIN is not present but VNTL is present TPS00RR/SON0/./[0GLK-0-00R] 9 n//xr/0v/k/x lose to the controller Intel orporation 0_VN/RGY_PVTT_ 000 W HNLER LV HNLER, Z Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

66 P_VP compensate VR_PVP_VW 9 n//xr/0v/k R.0K// VR_PVP_OMP 9 0p//NPO/0V/J R K// 99 9p//NPO/0V/J VR_PVP_F VR_PVP_VNN_VP PV_STY R9 R0 0/ / RT.K///S T RT.K///S VR_PVP_VSEN_R R9.K// VR_PVP_VSEN P_VNN compensate VR_PVNN_VW R90 K// VR_PVNN_VSEN_R R K// 0 n//xr/0v/k 0 0p//NPO/0V/J R00 K// R0 K// T R9 K// 0 0p//NPO/0V/J R 99// R9.0K// VR_PVNN_OMP 0 9p//NPO/0V/J VR_PVNN_F 0 0p//NPO/0V/J R0 99// R0.K// VR_PVNN_VSEN {,} {9,0,} PWRG_PS {0,} SVI_T {0,} SVI_LERT_N {0,} SVI_LK {0} PWRG_PVP_PVNN VR_PVP_PNN_VRHOT_N VR_PVP_F 0p//NPO/0V/J/X R9 99///X R 0// PV_STY SVI_T SVI_LERT_N SVI_LK VR_PVNN_F 0p//NPO/0V/J/X R9 99///X R99 0///X R 0/ R 0/ R 0/ R 0/ R9 0/ R9 0/ {} {} {} {} VR_PVP_VSEN VR_PVP_RTN VR_PVNN_VSEN VR_PVNN_RTN VR_FET_SW_PV_PVP_PVNN R0 VR_P_VP_PVNN_EN_R SVI_T_R SVI_LERT_R_N SVI_LK_R VR_PVP_PWRG_R VR_PVNN_PWRG_R VR_PVP_PNN_VRHOT_N VR_PVP_VW VR_PVP_OMP VR_PVP_VSEN VR_PVP_RTN VR_PVNN_VW VR_PVNN_OMP VR_PVNN_VSEN VR_PVNN_RTN VR_PVP_ISUMP VR_PVP_ISUMN_R VR_PVNN_ISUMP VR_PVNN_ISUMN_R VR_PVP_PROG 9.K// R 0/ VR_PVNN_PROG R0.K// VR_PVP_PVNN_VIN 00 0.u//XR/V/K 0 U0 VR_ON S LERT# SLK PGOO PGOOG VR_HOT# VWG OMPG FG ISPG ISNG PROG VP V 9 U//XR/V/K ISL9/TQFN/S VR_PVP_OOT OOT UG PH ISEN OMP 9 0 VW F VSEN RTN VSENG RTNG ISUMP ISUMN PROG VIN LG OOT UG PH LG ISEN PWM ISEN_F 0 PHG P 9 OOTG 0 UGG 9 LGG P IMON 9 IMONG NT NTG 9 9 U//XR/V/K VR_PVP_GH VR_PVP_PHSE VR_PVP_GL VR_PVP_VNN_V R9 0/ VR_P_VR_ISEN_R 0.u//XR/V/K 0 TP_PVP_OOT TP_PVP_UGTE TP_PVP_PHSE TP_PVP_LGTE VR_PVP_ISEN VR_PVP_PWM TP_PVP_ISEN_F VR_PVNN_OOT VR_PVNN_GH VR_PVNN_PHSE VR_PVNN_GL VR_PVP_IMON VR_PVNN_IMON VR_PVP_NT VR_PVNN_NT OTTOM P ONNET TO Through VIs TP0 TP TP TP R9 0/ R9 0/ TP VR_PVNN_OOT {} VR_PVNN_GH {} VR_PVNN_PHSE {} VR_PVNN_GL {} VR_PVP_OOT {} VR_PVP_GH {} VR_PVP_PHSE {} VR_PVP_GL {} VR_PVP_ISEN VR_PVP_ISUMN VR_PVP_VNN_V VR_PVP_ISEN {} VR_PVP_ISUMN {,} n//xr/0v/k/x n//xr/0v/k/x P_VP IMON VR_PVP_IMON VR_PVP_RTN P_VNN_IMON VR_PVNN_IMON VR_PVNN_RTN P_VP TSENSE VR_PVP_NT VR_PVP_NT_R R99 PVNN TSENSE VR_PVNN_NT R0 9 0.u//XR/0V/K 0 0.u//XR/0V/K R9.K//.9K//.K// VR_PVNN_NT_R R0.9K// R 0.K// R9.K// T Place close to VG inductor T RT 00K///S RT 00K///S Place close to VORE inductor PVP Isenes compensate P_VNN Isense compensate VR_PVP_ISUMP VR_PVP_ISUMP {} VR_PVNN_ISUMP VR_PVNN_ISUMP {} 0p//XR/0V/K 0 00// R0 0 0.u//XR/0V/K R0.K// 0p//NPO/0V/J 00// R 09 0.u//XR/V/K R09 K// VR_PVP_ISUMN_R VR_PVP_ISUMN VR_PVP_ISUMN {,} VR_PVNN_ISUMN_R VR_PVNN_ISUMN VR_PVNN_ISUMN {} R 9// 0.u//XR/V/K R 9// 0.u//XR/V/K Intel orporation 000 W HNLER LV HNLER, Z 0_VN/RGY_PVP_PVNN_I Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

67 PVP VR_FET_SW_PV_PVP_PVNN {} VR_PVP_OOT VR_PVP_OOT 0.u//XR/V/K {} VR_PVP_PHSE VR_PVP_PHSE R 0K// U 0.u//XR/V/K 0u//XR/V/K 0 0u//XR/V/K 0u//XR/V/K 9 0u//XR/V/K PVP Vsense {} VR_PVP_VSEN {} VR_PVP_RTN VR_PVP_VSEN VR_PVP_RTN R9 0// R 0// PVP 0.0u//XR/V/K/X {} {} R0 0/ R 0/ 0.0u//XR/0V/K PLE NER SENSE LOTION VR_PVP_GH VR_PVP_GL REMOTE Sense VR_PVP_GH VR_PVP_GL VR_PVP_VN_VSEN {} VR_PVP_VN_RTN {} R 0/ R 0/ VR_PVP_GL_R VR_PVP_GH_R IRFH9TRPF/PPK/00pF/.m/[0IF R] R 0K// HG N LG S S S S S VSW VSW VSW VSW 9 VSW 0 R./ VR_PVP_SNU.n//XR/0V/K SP VR_PP_ISUMP_R 0.uH//S/F L Short P/X Place close to controller Short P/X VR_P_VP_ISUMN_R SP9 R 0// R 0K// R / R.K// E9 0u/S/V/X/m VR_PVP_ISUMN VR_PVP_ISEN VR_PVP_ISUMP E0 0u/S/V/X/m VR_PVP_ISUMN {} VR_PVP_ISEN {} VR_PVP_ISUMP {} PVP E 0u/S/V/X/m/X PVP P_VP OUTPUT P u*+ u//xr/.v/m u//xr/.v/m u//xr/.v/m u//xr/.v/m u//xr/.v/m u//xr/.v/m u//xr/.v/m 9 u//xr/.v/m 0 u//xr/.v/m/x PV VR_FET_SW_PV_PVP_PVNN L 0.uH//S/[0L-00-0R] E INPUT HOKE 00u/FP//V//m PVNN {} VR_PVNN_OOT VR_PVNN_OOT 9 0.u//XR/V/K VR_FET_SW_PV_PVP_PVNN {} VR_PVNN_PHSE VR_PVNN_PHSE {} VR_PVNN_GH VR_PVNN_GH R0 0/ R 0K// VR_PVNN_GH_R U HG LG VIN VIN VIN VIN 9 VSW u//XR/V/K 0u//XR/V/K 0.uH/./S/I L 0u//XR/V/K PVNN PVNN Vsense {} VR_PVNN_VSEN VR_PVNN_VSEN PVNN R 0// R 0/ REMOTE Sense PVNN {} VR_PVNN_GL VR_PVNN_GL R 0/ FM00/POWER/0pF/9.m/[0IF R] R 0K// P P P R./ VR_PVNN_SNU.n//XR/0V/K SP0 VR_PNN_ISUMP_R Short P//X Short P/X VR_P_VNN_ISUMN_R SP R 0// R / E 0u/S/V/X/m VR_PVNN_ISUMN E 0u/S/V/X/m/X VR_PVNN_ISUMN {} {} VR_PVNN_RTN VR_PVNN_RTN 0// R9 n//xr/v/k R 0/ 0.u//XR/V/K PLE NER SENSE LOTION PVNN P_VNN OUTPUT P u*+ Place close to controller R0 0K// VR_PVNN_ISUMP VR_PVNN_ISUMP {} u//xr/.v/m u//xr/.v/m u//xr/.v/m u//xr/.v/m u//xr/.v/m/x Intel orporation 000 W HNLER LV HNLER, Z 0_VN/RGY_PVP_PVNN_II Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

68 PV_STY R 0//X PV_STY PV_STY PV_STY R K//X R 0/ VR_FET_SW_PV_STY 0u//XR/V/K u//xr/v/m F 0///S R 0/ 0.u//XR/V/K PV_STY PV_STY _PV_STY _PV_STY U 0 u//xr/v/k/x R 0.K// R.K// VR_EN_PV_STY VR_PV_STY_VIN PWRG_PV_STY_R VR_PV_STY_RLLM VR_PV_STY_SS VIN PVIN PVIN LLM_SYN PVIN0 ENLE VOUT VOUT POK VOUT 9 VOUT RLLM VOUT 0 VOUT SS VOUT u//XR/.V/M P u//xr/.v/m P 00u//XR/.V/M/X {0} PWRG_PV_STY R 0/ PV_STY R 0K// R K//X _PV_STY _PV_STY 0.0u//XR/V/K VF 9 THP ENQI/QFN/S P P P P P P0 _PV_STY R9 0/ VR_PV_STY_VF p//xr/0v/k VR_PV_STY_VF_R R0 0K// R 00K// _PV_STY R 0/ _PV_STY Intel orporation 000 W HNLER LV HNLER, Z 0_VN/RGY_PV_STY Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

69 PV0 lose to PVin PIN V < PVin < V PV VR_PV0_PVIN F 9 0.u//XR/V/K P9 0u//XR/V/M P0 u//xr/v/k 0///S PV_STY EN: use V level (don't exceed.9v) PG: don't exceed V R 00K///X R 0/ lose to Vin PIN PV0 {} PWRG_PV {} PWRG_PV0 PV_STY R 0/ R9 0/ PV_STY R 9.9K// R0 0/ R 0.K///X PWRG_PV0_VR VR_PV0_Sctrl VR_PV0_EN_R.u//XR/V/K VR_PV0_VREF 0 n//xr/0v/k/x P_V0_PH_RT_0 0 U Vp PGood S_trl ENLE V/LO_OUT VREF RT_SYN VIN 9 VR_PV0_VIN IR99MTRPF/QFN/S PVIN P oot SW VSNS F OMP VR_PV0_oot VR_PV0_SW VR_PV0_SNS VR_PV0_OMP u//xr/v/k 0.0u//XR/0V/K/X 0p//NPO/0V/J 0.u//XR/V/K VR_PV0_F _PV0 R R R R.//X R.K//0..K//0. R=R R=R VR_PV0_SN 0.uH/9/S/[0L-90-0R] L R //.n//xr/0v/k/x VR_PV0_FR R.K//0. 0.u//XR/V/K.n//XR/0V/K HOKE Spec. 0.uH/9/S L=0.uH +/-0% Idc = 9 Iset = R max =.mohm 9 u//xr/.v/m VR_PV0_F_SNS 0 u//xr/.v/m VR_PV0_FR P P 00u//XR/.V/M 00u//XR/.V/M R 0// PV0 P 00u//XR/.V/M[0M-000-R_0M-000-R_0M-000-R_0M-000-R] 00u//XR/.V/M[0M-000-R_0M-000-R_0M-000-R_0M-000-R] P R 0// 9 0.u//XR/V/K R 9.K// R u//XR/V/K VR_PV0_OMPR R9.K// R.K//0. Rb Ra Vout = 0. * (+Ra/Rb) Vout = 0. * ( +.K /.K ) =.00V VR_PV0_F R90 0//X _PV0 0/ 0.0u//XR/0V/K/X _PV0 PV0 R 0/ PV0 _PV0 JP9 u//xr/v/m EV hooks PH/*/K/./V/ EV hooks VSENSE FTER SWITH IF LOSE PV0 R 0/ P P P P9 00u//XR/.V/M/[0M-000-R] _PV0 00u//XR/.V/M 00u//XR/.V/M 00u//XR/.V/M Place these 00uF as close to the VN/RGY as possible Intel orporation 09_VN/RGY_PV0 000 W HNLER LV HNLER, Z Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of 9

70 PV_STY PV_STY PV0_STY R 0K// R 0/ u//xr/.v/m VR_FET_SW_PV0_STY 9 0P//XR/0V/K PWRG_PV0_STY PWRG_PV0_STY {} PV0_STY R 0/ U PVIN PVIN0 EP VOUT VOUT0 0 VIN POK VR_PV0_STY_V 0 u//xr/0v/k VIN EN VF 9 u//xr/.v/m u//xr/.v/m/x EPFQI/QFN/S/[0T-00-00R] _PV0_STY _PV0_STY R9 {} PWRG_PV_STY R 0/ u//xr/v/k/x PV0_STY_EN VR_PV0_STY_F R0 K// R K// VR_PV0_STY_F_R 0/ R _PV0_STY p//npo/0v/ Using external divider Vout programming Ra must be chosen as K ohmto maintain loop gain. Vout=(.K/Rb)+0.. =(./)+0. =.0 V 0/ _PV0_STY PV0 PV_TX PV_TX R0 0//X PV_TX R0 K//X R0 0/ VR_FET_SW_PV0 0 0u//XR/V/K u//xr/0v/m F 0///S R0 0/ 0.u//XR/V/K PV0 PV_TX _PV0 _PV0 U9 R9 0K///X VR_FET_SW_PV0 VIN LLM_SYN PVIN PVIN PVIN0 9 0 {} PWRG_PVP_PVNN R9 0/ u//xr/v/k/x R9 0K///X PV0_EN POK_PV0 VR_PV0_RLLM VR_PV0_SS 9 0 ENLE POK RLLM SS VOUT VOUT VOUT VOUT VOUT VOUT VOUT u//XR/.V/M P u//xr/.v/m P 00u//XR/.V/M/X {} PWRG_PV0 R09 0/ PV_TX R9 0K// R0 K//X _PV0 _PV u//XR/V/K VF 9 THP ENQI/QFN/S P P P P P P0 _PV0 R9 0/ R90 0/ VR_PV0_VF 90 0p//NPO/0V/J VR_PV0_VF_R _PV0 R _PV0 R00 0K// R0 00K// R R9 0/ VR_PV0_SENSE {} Intel orporation 000 W HNLER LV HNLER, Z 00_VN/RGY_PVRM_PV0_STY Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of 0

71 PV PV_STY R 0K///X {0} PWRG_PV0 R 0/ VR_PV_EN_R PV_STY 0.0u//XR/V/K R 0/ VR_PV_IN u//xr/.v/m u//xr/.v/m PV_STY PV U IN TPS0 OUT 0 {9} PWRG_PV 0.0u//XR/V/K R.K// R IN 0/ EN PWRG_PV PG VR_PV_IS IS 0u//XR/.V/M THERML P TPS0RR/SON0/S/[0GLK-0-00R] 9 OUT F SS 0pF//XR/V/K 0.0u//XR/V/K R.K// R.K// Ra Rb R 0/ 0u//XR/.V/M 0u//XR/.V/M 0u//XR/.V/M u//xr/.v/m Vout=0.X(+(Ra/Rb)) =0.X(+(./.)) =. V Intel orporation 0_VN/RGY_PV 000 W HNLER LV HNLER, Z Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

72 PV_STY PV_UX R9 0K// R90 0/ VR_FET_SW_PV_STY u//xr/v/m 9 0P//XR/0V/K PV_STY R9 0/ U PVIN PVIN0 EP VOUT VOUT0 PV_STY VR_PV_STY_V 0 u//xr/0v/k 0 VIN POK VIN 9 EN VF EPFQI/QFN/S/[0T-00-00R] PWRG_PV_STY _PV_STY u//xr/.v/m 9 u//xr/.v/m R9 0K///X _PV_STY VR_PV_STY_F R9 K// VR_PV_STY_F_R R9 {} PWRG_PV_STY R9 0/ VR_PV_STY_EN 0/ u//xr/v/k/x R9 0K///X R9 K// R9 p//npo/0v/ _PV_STY 0/ _PV_STY Using external divider Vout programming Ra must be chosen as Kohmto maintain loop gain. Vout=(.K/Rb)+0.. =(./)+0. =.00 V Intel orporation 0_LK_PV_STY 000 W HNLER LV HNLER, Z Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

73 PV_STY PV_UX VR_FET_SW_PV0_GE PWRG_PV0_GE PV0_GE U PVIN PVIN0 EP VOUT VOUT0 0 VIN POK PV_STY VR_PV0_GE_V u//xr/0v/k VIN EN VF 9 u//xr/.v/m EPFQI/QFN/S/[0T-00-00R] _PV0_GE PWRG_PV_GE _PV0_GE VR_PV0_GE_F VR_PV0_GE_F_R R0 K// Using external divider Vout programming Ra must be chosen as Kohmto maintain loop gain. Vout=(.K/Rb)+0.. =(./)+0. =.0 V R0 K//.P//XR/0V/K R0 0/ _PV0_GE _PV0_GE PV_GE PV_GE PV_STY PV_UX R0 0K// PV_STY PV_STY R99 0K// R00 0/ 0 u//xr/.v/m 0P//XR/0V/K R0 0/ u//xr/.v/m R0 0K///X R0 0/ R0 0K///X 0.u//XR/V/K R9.K/ P-MOSFET. U9 G VR_FET_SW_PV_GE R09 0/ 0.u//XR/V/K S 0P//XR/0V/K u//xr/.v/m PM0-TRG/TSOP/00pF/m/[0IF-00-0R] PWRG_PV_GE u//xr/v/k/x PV_GE R9.K/ G G S S Q N00/SOT/pF/ R0 0/ U9 PVIN PVIN0 0 VIN EP VOUT VOUT0 POK PV_GE VR_PV_GE_V u//xr/0v/k VIN EN VF 9 u//xr/.v/m u//xr/.v/m EPFQI/QFN/S/[0T-00-00R] _PV_GE {0} SLP_LN_N PV_STY R.K/ SLP_LN_N u//xr/v/k/x R 0K// R 0K// _PV_GE VR_PV_GE_EN ENLE Voltage : Logic High=.~Vin VR_PV_GE_F R K// VR_PV_GE_F_R R K// R 0/ R.P//XR/0V/K 0/ _PV_GE Using external divider Vout programming Ra must be chosen as Kohmto maintain loop gain. Vout=(.K/Rb)+0.. =(./)+0. =.0 V _PV_GE Intel orporation 0_GbE_PV0_PV 000 W HNLER LV HNLER, Z Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

74 PV_SW PV_TX R 0K///X VR_PV_STY_SW_EN_R PV_TX R9 0/ {9,0,} PWRG_PS R0 0/ VR_PV_STY_SW_IN 0.0u//XR/V/K u//xr/.v/m u//xr/.v/m PV_TX PV_TX PV_SW {} PWRG_VR_PV_STY_SW PWRG_VR_PV_STY_SW 0.0u//XR/V/K R.K// R 0/ VR_PV_STY_SW_IS 0u//XR/.V/M U0 IN IN IN IN EN 9 PG 0 IS N N N N N OUT 0 OUT 9 OUT OUT TPS0 THERML P F SS 9 0.0u//XR/V/K 0pF//XR/V/K/X R.K// R.9K// R 0/ 0 0u//XR/.V/M 0u//XR/.V/M 0u//XR/.V/M u//xr/.v/m TPS0RGWR/QFN0/. Intel orporation 000 W HNLER LV HNLER, Z 0_PIe_SW_PV_SW Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

75 PV0_SW_VR PV_TX TPS VIN voltage range = V to V, and V voltage range =. to V 9 u//xr/.v/m 0 u//xr/.v/m u//xr/.v/m 0.uH/0/S PV_TX L=0nH+/-0% I = 0 Iset =0 U.u//XR/V/K TPS/QFN/S R =. (mω) L9 PV0_SW_VREG 0.uH/0/S/[0L-00-R_0L-00-0R] VIN 9 LL V 0 SP SP LL VREG 9 R R 00K///X VR_PV0_SW_MOE 0 LL MOE 0.u//XR/V/K VR_PV0_SW_TRIP LL R TRIP R K// VR_PV0_SW_RF LL 0.u//XR/V/K u//xr/.v/m u//xr/.v/m u//xr/.v/m RF u//xr/.v/m u//xr/.v/m u//xr/.v/m LL 9 P u//xr/v/k R R9 R0 00K///X 00K//.9K// R R VIN VF VIN EN VIN PG VIN VIN VST VR_PV0_SW_Vripple_P Short P/X VR_PV0_SW_Vripple_N Short P/X PV0_SW R 0/ R VR_PV0_SW_VST./ VR_PV0_SW_VST_R R.K// VR_PV0_SW_F_ n//xr/0v/k 0 0.u//XR/V/K {} PWRG_VR_PV_STY_SW PV_TX VR_PV0_SW_EN_R R K// R VR_PV0_SW_F R R.K// VR_PV0_SW_F_R Vout= 0.*(R+R)/R =.00V K// R R 0K// {} PWRG_PV0_SW PWRG_PV0_SW Intel orporation 000 W HNLER LV HNLER, Z 0_PIe_SW_PV0_SW Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

76 K K K K K K I I I I Fiducial_Point/X Fiducial_Point/X Fiducial_Point/X Fiducial_Point/X Fiducial_Point/X Fiducial_Point/X POSITION/X POSITION/X POSITION/X POSITION/X SK SK SK SK SK SK Fiducial_Point/X Fiducial_Point/X Fiducial_Point/X Fiducial_Point/X Fiducial_Point/X Fiducial_Point/X H M_HOLE/X 9 H M_HOLE/X 9 H M_HOLE/X 9 H M_HOLE/X 9 H M_HOLE/X 9 H M_HOLE/X 9 Top layer :. :0. :. (width : space : width) For LN Zd=00ohm +/-.% Top layer :. :. :. (width : space : width) For PI-Express/ST/US Zd=ohm +/-.% TOP_.S0._00_P TOP_.S0._00_N OUPON_ OUPON/X _L TOP_.S. P TOP_.S. N OUPON_ OUPON/X _R TOP_9_ Top layer :mil,0ohm +/-0% OUPON OUPON/X OT layer :mil,0ohm +/-0% _L TOP_._0 Top layer :.mil,0ohm +/-0% OUPON OUPON/X OT layer :.mil,0ohm +/-0% _R Top layer : :. : (width : space : width) For LN Zd=00ohm +/-.% OUPON_ IN_S._00_P OUPON/X IN_S._00_N Top layer : : : (width : space : width) For PI-Express/ST Zd=ohm +/-.% OUPON_ IN_S P OUPON/X IN_S N TM_._ IN OUPON OUPON/X IN layer :.mil,0ohm +/-0% OUPON _L TM_._0 IN 0 OUPON OUPON/X IN layer:mil,ohm +/-0% OUPON _R _L _R OUPON/X OUPON/X Top layer :. :. :. (width : space : width) For LN Zd=00ohm +/-.% IN IN layer :.mil,0ohm +/-0% OUPON _L IN 0 IN layer :mil,ohm +/-0% OUPON _R IN_S._00_P IN_S._00_N OUPON_ OUPON/X IN_S P IN_S N OUPON_ OUPON/X OUPON/X _L OUPON/X _R _L _R Top layer :. :0 :. (width : space : width) For LN Zd=00ohm +/-.% OUPON_ TM_.S0_00_P OUPON/X TM_.S0_00_N TM layer : :. : (width : space : width) For PI-Express/QPI/ESI/SS/ST/US Zd=ohm +/- 0% TM_S P TM_S N OUPON_ OUPON/X _L _R Intel orporation 000 W HNLER LV HNLER, Z 0_MOUNTING_HOLE_OUPON Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

77 P Vender calculate ate:00 ME Provide ate: Intel orporation 000 W HNLER LV HNLER, Z 0_P_STK_UP_ME Size ocument Number Rev eta Mohon Peak R Wednesday, ugust, 0 ate: Sheet of

COMPONENTS LIST BASE COMPONENTS

COMPONENTS LIST BASE COMPONENTS ITLIN TEHNOLOGY grifo PPENIX : R SSEMLY The GP F can be ordered in two different mode: completely mounted, tested and ready to use or in assembly kit. In this final condition the user can directly use

Διαβάστε περισσότερα

intel <MCH Processor> intel <PCH>

intel <MCH Processor> intel <PCH> IV@ For UM EV@ For Pure is. SP@ For special setting SPI@ For Optimus & UM special setting SPE@ For Pure is.special setting V@ For udio version setting V@ For udio version setting @G For G setting PIV@

Διαβάστε περισσότερα

ΑΓΓΕΛΗΣ ΧΡΗΣΤΟΣ ΠΑΝΑΓΙΩΤΗΣ 6 OO ΑΓΓΕΛΙΔΗΣ ΧΑΡΙΛΑΟΣ ΧΡΗΣΤΟΣ 4 OO ΑΓΓΟΥ ΑΝΑΣΤΑΣΙΑ ΔΗΜΗΤΡΙΟΣ 6 OO ΑΔΑΜΙΔΟΥ ΕΥΑΓΓΕΛΙΑ ΑΒΡΑΑΜ 3 OO ΑΛΕΒΙΖΟΥ ΠΑΝΑΓΙΩΤΑ

ΑΓΓΕΛΗΣ ΧΡΗΣΤΟΣ ΠΑΝΑΓΙΩΤΗΣ 6 OO ΑΓΓΕΛΙΔΗΣ ΧΑΡΙΛΑΟΣ ΧΡΗΣΤΟΣ 4 OO ΑΓΓΟΥ ΑΝΑΣΤΑΣΙΑ ΔΗΜΗΤΡΙΟΣ 6 OO ΑΔΑΜΙΔΟΥ ΕΥΑΓΓΕΛΙΑ ΑΒΡΑΑΜ 3 OO ΑΛΕΒΙΖΟΥ ΠΑΝΑΓΙΩΤΑ ΕΠΩΝΥΜΙΑ ΠΕΡΙΟΔΟΣ ΜΕΣΟ ΑΓΓΕΛΗΣ ΧΡΗΣΤΟΣ ΠΑΝΑΓΙΩΤΗΣ 6 OO ΑΓΓΕΛΙΔΗΣ ΧΑΡΙΛΑΟΣ ΧΡΗΣΤΟΣ 4 OO ΑΓΓΟΥ ΑΝΑΣΤΑΣΙΑ ΔΗΜΗΤΡΙΟΣ 6 OO ΑΔΑΜΙΔΟΥ ΕΥΑΓΓΕΛΙΑ ΑΒΡΑΑΜ 3 OO ΑΛΕΒΙΖΟΥ ΠΑΝΑΓΙΩΤΑ ΔΗΜΗΤΡΙΟΣ 7 OO ΑΝΑΓΝΩΣΤΟΠΟΥΛΟΥ ΖΩΙΤΣΑ

Διαβάστε περισσότερα

+3V3 Supply. +3V0 Flash + VCCPGMy +2V5 FPGA VCC + FPGA I/O +1V1 FPGA Core. Overview. abaxor engineering GmbH

+3V3 Supply. +3V0 Flash + VCCPGMy +2V5 FPGA VCC + FPGA I/O +1V1 FPGA Core. Overview. abaxor engineering GmbH 6 7 8 Supply +V0 Flash + PGMy +V FPG + FPG I/O +V FPG ore Overview 6 7 8 6 7 8 I0NK_ IO H IO P IO L IO J VRFN0 N IO/IFFIO_TX_L9N/IFFOUT_L9N IO/IFFIO_RX_L0N/IFFOUT_L0N/QL J IO/IFFIO_TX_L9P/IFFOUT_L9P/QL

Διαβάστε περισσότερα

ο ο 3 α. 3"* > ω > d καΐ 'Ενορία όλις ή Χώρί ^ 3 < KN < ^ < 13 > ο_ Μ ^~~ > > > > > Ο to X Η > ο_ ο Ο,2 Σχέδι Γλεγμα Ο Σ Ο Ζ < o w *< Χ χ Χ Χ < < < Ο

ο ο 3 α. 3* > ω > d καΐ 'Ενορία όλις ή Χώρί ^ 3 < KN < ^ < 13 > ο_ Μ ^~~ > > > > > Ο to X Η > ο_ ο Ο,2 Σχέδι Γλεγμα Ο Σ Ο Ζ < o w *< Χ χ Χ Χ < < < Ο 18 ρ * -sf. NO 1 D... 1: - ( ΰ ΐ - ι- *- 2 - UN _ ί=. r t ' \0 y «. _,2. "* co Ι». =; F S " 5 D 0 g H ', ( co* 5. «ΰ ' δ". o θ * * "ΰ 2 Ι o * "- 1 W co o -o1= to»g ι. *ΰ * Ε fc ΰ Ι.. L j to. Ι Q_ " 'T

Διαβάστε περισσότερα

ss rt çã r s t Pr r Pós r çã ê t çã st t t ê s 1 t s r s r s r s r q s t r r t çã r str ê t çã r t r r r t r s

ss rt çã r s t Pr r Pós r çã ê t çã st t t ê s 1 t s r s r s r s r q s t r r t çã r str ê t çã r t r r r t r s P P P P ss rt çã r s t Pr r Pós r çã ê t çã st t t ê s 1 t s r s r s r s r q s t r r t çã r str ê t çã r t r r r t r s r t r 3 2 r r r 3 t r ér t r s s r t s r s r s ér t r r t t q s t s sã s s s ér t

Διαβάστε περισσότερα

Modbus basic setup notes for IO-Link AL1xxx Master Block

Modbus basic setup notes for IO-Link AL1xxx Master Block n Modbus has four tables/registers where data is stored along with their associated addresses. We will be using the holding registers from address 40001 to 49999 that are R/W 16 bit/word. Two tables that

Διαβάστε περισσότερα

( )( ) ( )( ) 2. Chapter 3 Exercise Solutions EX3.1. Transistor biased in the saturation region

( )( ) ( )( ) 2. Chapter 3 Exercise Solutions EX3.1. Transistor biased in the saturation region Chapter 3 Exercise Solutios EX3. TN, 3, S 4.5 S 4.5 > S ( sat TN 3 Trasistor biased i the saturatio regio TN 0.8 3 0. / K K K ma (a, S 4.5 Saturatio regio: 0. 0. ma (b 3, S Nosaturatio regio: ( 0. ( 3

Διαβάστε περισσότερα

ΠΑΝΕΠΙΣΤΗΜΙΟ ΑΙΓΑΙΟΥ ΣΧΟΛΗ ΘΕΤΙΚΩΝ ΕΠΙΣΤΗΜΩΝ ΤΜΗΜΑ ΜΑΘΗΜΑΤΙΚΩΝ ΜΕ ΚΑΤΕΥΘΥΝΣΗ ΣΤΑΤΙΣΤΙΚΗ ΚΑΙ ΧΡΗΜΑΤΟΟΙΚΟΝΟΜΙΚΑ ΜΑΘΗΜΑΤΙΚΑ

ΠΑΝΕΠΙΣΤΗΜΙΟ ΑΙΓΑΙΟΥ ΣΧΟΛΗ ΘΕΤΙΚΩΝ ΕΠΙΣΤΗΜΩΝ ΤΜΗΜΑ ΜΑΘΗΜΑΤΙΚΩΝ ΜΕ ΚΑΤΕΥΘΥΝΣΗ ΣΤΑΤΙΣΤΙΚΗ ΚΑΙ ΧΡΗΜΑΤΟΟΙΚΟΝΟΜΙΚΑ ΜΑΘΗΜΑΤΙΚΑ ΠΑΝΕΠΙΣΤΗΜΙΟ ΑΙΓΑΙΟΥ ΣΧΟΛΗ ΘΕΤΙΚΩΝ ΕΠΙΣΤΗΜΩΝ ΤΜΗΜΑ ΜΑΘΗΜΑΤΙΚΩΝ ΜΕ ΚΑΤΕΥΘΥΝΣΗ ΣΤΑΤΙΣΤΙΚΗ ΚΑΙ ΧΡΗΜΑΤΟΟΙΚΟΝΟΜΙΚΑ ΜΑΘΗΜΑΤΙΚΑ ΑΣΚΗΣΕΙΣ ΧΡΗΜΑΤΟΟΙΚΟΝΟΜΙΚΩΝ ΜΑΘΗΜΑΤΙΚΩΝ ΙΩΑΝΝΗΣ Σ. ΣΤΑΜΑΤΙΟΥ ΣΑΜΟΣ, ΧΕΙΜΕΡΙΝΟ ΕΞΑΜΗΝΟ

Διαβάστε περισσότερα

Intel Calpella BlOCK DIAGRAM

Intel Calpella BlOCK DIAGRAM Intel alpella lok IGRM POWER /TT ONNETOR R-SOIMM H R-SOIMM H ST-O ST-H UIO/MP L SYSTEM RESET IRUIT TT HRGER RUN POWER SW +V_S/+V_S +V_SUS/+V_SUS +V_RUN/+V_RUN/+.V_RUN ual hannel R 0.V INTEL ISRETE SYSTEM

Διαβάστε περισσότερα

Econ 2110: Fall 2008 Suggested Solutions to Problem Set 8 questions or comments to Dan Fetter 1

Econ 2110: Fall 2008 Suggested Solutions to Problem Set 8  questions or comments to Dan Fetter 1 Eon : Fall 8 Suggested Solutions to Problem Set 8 Email questions or omments to Dan Fetter Problem. Let X be a salar with density f(x, θ) (θx + θ) [ x ] with θ. (a) Find the most powerful level α test

Διαβάστε περισσότερα

UM8 UMA SYSTEM DIAGRAM

UM8 UMA SYSTEM DIAGRAM +V/+V PG. PG. +.0V/+.V PG. PU ore PG. VG ore/+.v PG. +.V/+0.V PG. +.0VTT PG. UM VGORE harger LN PG. LNE theros/r 0/00 K ITE 0 PG. UM UM SYSTEM IGRM SOIMM Max. G PG. SOIMM Max. G PG. M ROM PG. LNEO WWN

Διαβάστε περισσότερα

QUANTA COMPUTER. Page Title of schematic page Rev. Date

QUANTA COMPUTER. Page Title of schematic page Rev. Date Page of schematic page Rev. ate 0 0 0 0 0 0 0 0 0 0 0 Index lock iagram hange ist OK NRTOR PROSSOR /(MI&HOST&PI) PROSSOR /(R) PROSSOR /(POWR) PROSSOR /() PH / (MI&VIO) PH / (ST/P/zalia) PH / (PI/PI/K/US)

Διαβάστε περισσότερα

DC-DC Constant Current Step-Down LED driver LDD-300L LDD-350L LDD-500L LDD-600L LDD-700L CURRENT RANGE

DC-DC Constant Current Step-Down LED driver LDD-300L LDD-350L LDD-500L LDD-600L LDD-700L CURRENT RANGE SPECIFICATION ORDER NO. LDD-00L LDD-0L LDD-00L LDD-00L LDD-700L CURRENT RANGE 00mA 0mA 00mA 00mA VOLTAGE RANGE Note. ~ VDC for LDD-00~700L/LW ; ~ 8VDC for LDD-00~700LS CURRENT ACCURACY (Typ.) ±% at VDC

Διαβάστε περισσότερα

DISPLAY SUPPLY: FILTER STANDBY

DISPLAY SUPPLY: FILTER STANDBY ircuit iagrams and PW Layouts. ircuit iagrams and PW Layouts J.0 P. 0 isplay Supply P: ilter Standby MNS NPUT -Vac 00 P-V- V_OT 0 0 0 0 0 0 0 0 SPLY SUPPLY: LT STNY 0 M0 V 0 T,/0V MSU -VOLTS NOML... STNY

Διαβάστε περισσότερα

DC-DC Constant Current Step-Down LED driver LDD-300L LDD-350L LDD-500L LDD-600L LDD-700L CURRENT RANGE

DC-DC Constant Current Step-Down LED driver LDD-300L LDD-350L LDD-500L LDD-600L LDD-700L CURRENT RANGE SPECIFICATION ORDER NO. LDD-00L LDD-0L LDD-00L LDD-00L LDD-700L CURRENT RANGE 00mA 0mA 00mA VOLTAGE RANGE Note. ~ VDC for LDD-00~700L/LW ; ~ 8VDC for LDD-00~700LS CURRENT ACCURACY (Typ.) ±% at VDC input

Διαβάστε περισσότερα

LS01-15B09SS LS01-15B12SS LS01-15B15SS LS01-15B24SS LS03-15B03SR2S LS03-15B05SR2S LS03-15B09SR2S LS03-15B12SR2S LS03-15B15SR2S LS03-15B24SR2S

LS01-15B09SS LS01-15B12SS LS01-15B15SS LS01-15B24SS LS03-15B03SR2S LS03-15B05SR2S LS03-15B09SR2S LS03-15B12SR2S LS03-15B15SR2S LS03-15B24SR2S LS0 SS & LS0RS _ onverter. W SIP economic LS series.... W High performance & compact size series.... W ~0V wide input voltage LH series.... W 0 Low temperature & high reliability L0_LT series.... 00W LH

Διαβάστε περισσότερα

AMD Champlain S1G4 Processor 35mm X 35mm 638P (PGA) 35W PAGE 2,3,4 NORTH BRIDGE RS880M A11

AMD Champlain S1G4 Processor 35mm X 35mm 638P (PGA) 35W PAGE 2,3,4 NORTH BRIDGE RS880M A11 P STK UP LYER : TOP LYER : GN LYER : IN LYER : IN LYER : V LYER : OT IV@ -----> igpu EV@ -----> dgpu SPE@ -----> Option Notice MHz LN ROOM PIE-LN M RJ P (//) R- SOIMM R- SOIMM PGE PGE PGE PGE Mini PI-E

Διαβάστε περισσότερα

M p f(p, q) = (p + q) O(1)

M p f(p, q) = (p + q) O(1) l k M = E, I S = {S,..., S t } E S i = p i {,..., t} S S q S Y E q X S X Y = X Y I X S X Y = X Y I S q S q q p+q p q S q p i O q S pq p i O S 2 p q q p+q p q p+q p fp, q AM S O fp, q p + q p p+q p AM

Διαβάστε περισσότερα

ZRI/ZQI Block Diagram

ZRI/ZQI Block Diagram lock iagram RIII-SOIMM RM P Mb**pcs/ = G P, hannel (00 MHZ) hannel R PU Richland PU (W) mm X mm FP pin G P,,, GFX P P P0 PEG0~(PI-E x ) ep PNEL P HMI ONN TXP/N,0/ P GPU Mars XT(W) mm X mm P~ X'TL.0MHz

Διαβάστε περισσότερα

IXBH42N170 IXBT42N170

IXBH42N170 IXBT42N170 High Voltage, High Gain BIMOSFET TM Monolithic Bipolar MOS Transistor IXBH42N17 IXBT42N17 S 9 = 1 = 42A (sat) 2.8V Symbol Test Conditions Maximum Ratings TO-247 (IXBH) S = 25 C to 15 C 17 V V CGR = 25

Διαβάστε περισσότερα

r r t r r t t r t P s r t r P s r s r r rs tr t r r t s ss r P s s t r t t tr r r t t r t r r t t s r t rr t Ü rs t 3 r r r 3 rträ 3 röÿ r t

r r t r r t t r t P s r t r P s r s r r rs tr t r r t s ss r P s s t r t t tr r r t t r t r r t t s r t rr t Ü rs t 3 r r r 3 rträ 3 röÿ r t r t t r t ts r3 s r r t r r t t r t P s r t r P s r s r P s r 1 s r rs tr t r r t s ss r P s s t r t t tr r 2s s r t t r t r r t t s r t rr t Ü rs t 3 r t r 3 s3 Ü rs t 3 r r r 3 rträ 3 röÿ r t r r r rs

Διαβάστε περισσότερα

Page Title of schematic page Rev. Date Page Title of schematic page Rev. Date

Page Title of schematic page Rev. Date Page Title of schematic page Rev. Date Page Title of schematic page Rev. ate Page ist lock iagram hange ist SN /(HOST&PIE) SN /(R I/F) SN /(POWER) SN /(/Strap) PH /(MI/FI/VIEO) PH /(ST/RT/H/P) PH /(PIE/US/K/NV) PH /(GPIO/PU/STRP) PH /(POWER)

Διαβάστε περισσότερα

[3.2] 38.0[4.3] [12.9] , [.71] [.00021].8[.09] 13.2[6.0] 230

[3.2] 38.0[4.3] [12.9] , [.71] [.00021].8[.09] 13.2[6.0] 230 Series TORQUE RANGE: 38-116.2 IN-LBS 4.3-13.1 Nm Motor Data (Trap) Motor Parameters Units 1140ATG**** 1140BTG**** 1141ATG**** 1141BTG**** *ontinuous Rated Torque @ Rated Speed *ontinuous Stall Torque ontinuous

Διαβάστε περισσότερα

Network Neutrality Debate and ISP Inter-Relations: Traffi c Exchange, Revenue Sharing, and Disconnection Threat

Network Neutrality Debate and ISP Inter-Relations: Traffi c Exchange, Revenue Sharing, and Disconnection Threat Network Neutrality Debate and ISP Inter-Relations: Traffi c Exchange, Revenue Sharing, and Disconnection Threat Pierre Coucheney, Patrick Maillé, runo Tuffin To cite this version: Pierre Coucheney, Patrick

Διαβάστε περισσότερα

Low ESR Tantalum Capacitors (TCR Series)

Low ESR Tantalum Capacitors (TCR Series) Low SR Tnlum pciors (TR Series) Pr Numer Srucure Feures: RoHS omplin nd Hlogen Free Lower SR hn sndrd Tnlum xcellen frequency chrcerisics nd impednce Lser mrking for esy idenificion Volge rnge: 4V o 50V

Διαβάστε περισσότερα

α/α Α.Μ. Ονοματεπώνυμο Σύλλογος Βαθμοί Έτος Πόλη1 Κτγ1

α/α Α.Μ. Ονοματεπώνυμο Σύλλογος Βαθμοί Έτος Πόλη1 Κτγ1 1 30537 ΒΟΛΤΥΡΑΚΗΣ ΒΑΣΙΛΗΣ Ο.Α.ΧΑΝΙΩΝ 117,0 2003 ΗΡΑ b12 2 32680 ΦΩΤΕΙΝΟΠΟΥΛΟΣ ΑΘΑΝΑΣΙΟΣ Α.Ο.Α.ΗΛΙΟΥΠΟΛΗΣ 110,5 2003 ΗΡΑ b12 3 30776 ΖΕΡΒΟΣ ΓΕΩΡΓΙΟΣ Ο.Α.ΧΑΝΙΩΝ 71,5 2003 ΗΡΑ b12 4 33545 ΛΥΜΠΕΡΗΣ ΑΡΗΣ-ΠΑΝΑΓΙΩΤΗΣ

Διαβάστε περισσότερα

Tablet SYSTEM BLOCK DIAGRAM

Tablet SYSTEM BLOCK DIAGRAM VER : OM P/N escription Tablet SYSTEM LOK IGRM Memory own Max. G P M* R III /00 MHZ IM FI Ivy ridge G 0 W P,,,, MI ep US- ep onn. TOUH PNEL P MI(x) mst - H P0 ST FI MI Gyroscope P ST LG0 e-compass/ G sensor

Διαβάστε περισσότερα

ΚΥΠΡΙΑΚΗ ΕΤΑΙΡΕΙΑ ΠΛΗΡΟΦΟΡΙΚΗΣ CYPRUS COMPUTER SOCIETY ΠΑΓΚΥΠΡΙΟΣ ΜΑΘΗΤΙΚΟΣ ΔΙΑΓΩΝΙΣΜΟΣ ΠΛΗΡΟΦΟΡΙΚΗΣ 19/5/2007

ΚΥΠΡΙΑΚΗ ΕΤΑΙΡΕΙΑ ΠΛΗΡΟΦΟΡΙΚΗΣ CYPRUS COMPUTER SOCIETY ΠΑΓΚΥΠΡΙΟΣ ΜΑΘΗΤΙΚΟΣ ΔΙΑΓΩΝΙΣΜΟΣ ΠΛΗΡΟΦΟΡΙΚΗΣ 19/5/2007 Οδηγίες: Να απαντηθούν όλες οι ερωτήσεις. Αν κάπου κάνετε κάποιες υποθέσεις να αναφερθούν στη σχετική ερώτηση. Όλα τα αρχεία που αναφέρονται στα προβλήματα βρίσκονται στον ίδιο φάκελο με το εκτελέσιμο

Διαβάστε περισσότερα

CD-308MP/FM. Service Manual - CD-308MP/FM

CD-308MP/FM. Service Manual - CD-308MP/FM CD-308MP/FM R Service Manual - CD-308MP/FM Bill of Materials NO ITEM CODE DESCRIPTION QTY SYMBOL 1 001-3300D-A90 P.C.B ISO BOARD 1 2 001-3912S-W00 P.C.B MAIN BOARD 1 3 002-01140-A09 I.C LA1140 IF SIP 1

Διαβάστε περισσότερα

ΑΣΚΗΣΗ 2: Σχεδίαση και προσομοίωση κυκλωμάτων καταχωρητών και μετρητών

ΑΣΚΗΣΗ 2: Σχεδίαση και προσομοίωση κυκλωμάτων καταχωρητών και μετρητών ΑΣΚΗΣΗ 2: Σχεδίαση και προσομοίωση κυκλωμάτων καταχωρητών και μετρητών Θέμα Β.1: Απλός καταχωρητής 1 bit (D Flip-Flop) preset D D Q Q clk clear Σχήμα 2.1: D Flip-Flop με εισόδους preset και clear Με τη

Διαβάστε περισσότερα

INT_LVDS. Pineview. Graphics Interfaces CPU P4,5,6,7 CRT DMI DMI. PCI-Express(Port1~4) Tigerpoint PCI-E P8,9,10,11,12,13 PN : AJSLGXX0T14 LPC LPC

INT_LVDS. Pineview. Graphics Interfaces CPU P4,5,6,7 CRT DMI DMI. PCI-Express(Port1~4) Tigerpoint PCI-E P8,9,10,11,12,13 PN : AJSLGXX0T14 LPC LPC ZE lock iagram 0 K0 RIII-SOIMM P MT/s R SYSTEM MEMORY Pineview PU P,,, MI Graphics Interfaces INT_LVS RT 0. "Panel Up to 0*00 or * P RT P P N0.G: JSLXEVT0 N.G: JSLXUT0 N.G: JSLXVT0 MI(x) harger P US port*

Διαβάστε περισσότερα

ASL BS ,00 ASL BS ,00 ASL BS ,80 ASL BS ,60 ASL TP SET 1 817,20 ASL TP SET 2 997,20 ASL TP SET ,20

ASL BS ,00 ASL BS ,00 ASL BS ,80 ASL BS ,60 ASL TP SET 1 817,20 ASL TP SET 2 997,20 ASL TP SET ,20 www.asl-inter.com BASIC SERIES ASL BS 217 Κεντρική μονάδα intercom 2 καναλιών. Κάθε κανάλι διαθέτει φωτιζόμενο κουμπί Talk και Call και volume για τον έλεγχο της έντασης. Στην πίσω πλευρά διαθέτει μια

Διαβάστε περισσότερα

(#5 5::%%%$ " (#5 5::%%%$" %

(#5 5::%%%$  (#5 5::%%%$ % !" "#! " # $ "! "#" "" ""! % %! % " &"#!! "' (%)* (% (%! "' + "',! "' $% " %! "'% " %!"! #!" " $ #!" #$ #! #!#!" -%$!"#!".! "!"#!"! "!" " " "!!" "! %!"!#/ "%! %! #! )0+! *.." )0)!- % 67&* 6**&7*0.8 67&*67&*90&0.8

Διαβάστε περισσότερα

Current Sense Metal Strip Resistors (CSMS Series)

Current Sense Metal Strip Resistors (CSMS Series) Features: Range: 1mΩ to 100mΩ Low TCR as low as 75PPM High power rating Custom Values available RoHS Compliant and Halogen Free Operating Temperature: -55 C to +170 C Part Number Structure CSMS 0805 -

Διαβάστε περισσότερα

Potential Dividers. 46 minutes. 46 marks. Page 1 of 11

Potential Dividers. 46 minutes. 46 marks. Page 1 of 11 Potential Dividers 46 minutes 46 marks Page 1 of 11 Q1. In the circuit shown in the figure below, the battery, of negligible internal resistance, has an emf of 30 V. The pd across the lamp is 6.0 V and

Διαβάστε περισσότερα

Electrical Specifications at T AMB =25 C DC VOLTS (V) MAXIMUM POWER (dbm) DYNAMIC RANGE IP3 (dbm) (db) Output (1 db Comp.) at 2 f U. Typ.

Electrical Specifications at T AMB =25 C DC VOLTS (V) MAXIMUM POWER (dbm) DYNAMIC RANGE IP3 (dbm) (db) Output (1 db Comp.) at 2 f U. Typ. Surface Mount Monolithic Amplifiers High Directivity, 50Ω, 0.5 to 5.9 GHz Features 3V & 5V operation micro-miniature size.1"x.1" no external biasing circuit required internal DC blocking at RF input &

Διαβάστε περισσότερα

No item Digit Description Series Reference (1) Meritek Series SI Signal Inductor LI: Leaded Inductor PI: Power Inductor

No item Digit Description Series Reference (1) Meritek Series SI Signal Inductor LI: Leaded Inductor PI: Power Inductor PART NUMBERING SYSTEM SI F 0805 K 780 F (1) (2) (3) (4) (5) (6) No item Digit Description Series Reference (1) Meritek Series SI Signal Inductor LI: Leaded Inductor PI: Power Inductor (2) Type F Ferrite

Διαβάστε περισσότερα

1. ΧΗΜΙΚΟΙ ΕΣΜΟΙ ΣΤΑ ΣΤΕΡΕΑ

1. ΧΗΜΙΚΟΙ ΕΣΜΟΙ ΣΤΑ ΣΤΕΡΕΑ 1. ΧΗΜΙΚΟΙ ΕΣΜΟΙ ΣΤΑ ΣΤΕΡΕΑ ΓΕΝΙΚΑ Η στερεά, η υγρή και η αέρια κατάσταση αποτελούν τις τρεις, συνήθεις στο γήινο περιβάλλον, καταστάσεις της ύλης. ιαφέρουν η µία από την άλλη σε κάποια απλά γνωρίσµατα:

Διαβάστε περισσότερα

❷ s é 2s é í t é Pr 3

❷ s é 2s é í t é Pr 3 ❷ s é 2s é í t é Pr 3 t tr t á t r í í t 2 ➄ P á r í3 í str t s tr t r t r s 3 í rá P r t P P á í 2 rá í s é rá P r t P 3 é r 2 í r 3 t é str á 2 rá rt 3 3 t str 3 str ýr t ý í r t t2 str s í P á í t

Διαβάστε περισσότερα

Monolithic Crystal Filters (M.C.F.)

Monolithic Crystal Filters (M.C.F.) Monolithic Crystal Filters (M.C.F.) MCF (MONOLITHIC CRYSTAL FILTER) features high quality quartz resonators such as sharp cutoff characteristics, low loss, good inter-modulation and high stability over

Διαβάστε περισσότερα

NEC Silicon RFIC Amplifiers Low Power, Wideband & SiGe/SiGeC

NEC Silicon RFIC Amplifiers Low Power, Wideband & SiGe/SiGeC NEC Silicon RFIC Amplifiers Low Power, Wideband & SiGe/SiGeC Low Power Amplifiers ELECTRICAL CHARACTERISTICS (TA = 25 C) Range VCC ICC NF Gain RLIN RLOUT PdB ISOL @ 3dB (V) (ma) (dbm) Part down Package

Διαβάστε περισσότερα

AT Surface Mount Package SOT-363 (SC-70) I I Y. Pin Connections B 1 C 1 E 1 E 2 C 2 B , 7:56 PM

AT Surface Mount Package SOT-363 (SC-70) I I Y. Pin Connections B 1 C 1 E 1 E 2 C 2 B , 7:56 PM AT-3263 Surface Mount Package SOT-363 (SC-7) I I Y Pin Connections B 1 C 1 E 1 E 2 C 2 B 2 Page 1 21.4., 7:6 PM Absolute Maximum Ratings [1] Absolute Thermal Resistance [2] : Symbol Parameter Units Maximum

Διαβάστε περισσότερα

38BXCS STANDARD RACK MODEL. DCS Input/Output Relay Card Series MODEL & SUFFIX CODE SELECTION 38BXCS INSTALLATION ORDERING INFORMATION RELATED PRODUCTS

38BXCS STANDARD RACK MODEL. DCS Input/Output Relay Card Series MODEL & SUFFIX CODE SELECTION 38BXCS INSTALLATION ORDERING INFORMATION RELATED PRODUCTS DCS Input/Output Relay Card Series STANDARD RACK MODEL 38BXCS MODEL & SUFFIX CODE SELECTION 38BXCS MODEL CONNECTOR Y1 :Yokogawa KS2 cable use Y2 :Yokogawa KS9 cable use Y6 :Yokogawa FA-M3/F3XD32-3N use

Διαβάστε περισσότερα

jqa=mêççìåíë=^âíáéåöéëéääëåü~ñí= =p~~êäêωåâéå= =déêã~åó

jqa=mêççìåíë=^âíáéåöéëéääëåü~ñí= =p~~êäêωåâéå= =déêã~åó L09 cloj=klk=tsvjmosopa jqa=mêççìåíë=^âíáéåöéëéääëåü~ñí= =p~~êäêωåâéå= =déêã~åó 4 16 27 38 49 60 71 82 93 P Éå Ñê ÇÉ áí dbq=ql=hklt=vlro=^mmif^k`b mo pbkq^qflk=ab=slqob=^mm^obfi ibokbk=pfb=feo=dboûq=hbkkbk

Διαβάστε περισσότερα

ON THE MEASUREMENT OF

ON THE MEASUREMENT OF ON THE MEASUREMENT OF INVESTMENT TYPES: HETEROGENEITY IN CORPORATE TAX ELASTICITIES HENDRIK JUNGMANN, SIMON LORETZ WORKING PAPER NO. 2016-01 t s r t st t t2 s t r t2 r r t t 1 st t s r r t3 str t s r ts

Διαβάστε περισσότερα

rs r r â t át r st tíst Ó P ã t r r r â

rs r r â t át r st tíst Ó P ã t r r r â rs r r â t át r st tíst P Ó P ã t r r r â ã t r r P Ó P r sã rs r s t à r çã rs r st tíst r q s t r r t çã r r st tíst r t r ú r s r ú r â rs r r â t át r çã rs r st tíst 1 r r 1 ss rt q çã st tr sã

Διαβάστε περισσότερα

1. For each of the following power series, find the interval of convergence and the radius of convergence:

1. For each of the following power series, find the interval of convergence and the radius of convergence: Math 6 Practice Problems Solutios Power Series ad Taylor Series 1. For each of the followig power series, fid the iterval of covergece ad the radius of covergece: (a ( 1 x Notice that = ( 1 +1 ( x +1.

Διαβάστε περισσότερα

RECIPROCATING COMPRESSOR CALCULATION SHEET

RECIPROCATING COMPRESSOR CALCULATION SHEET Gas properties, flowrate and conditions 1 Gas name Air RECIPRCATING CMPRESSR CALCULATIN SHEET WITH INTERCLER ( Sheet : 1. f 4.) Item or symbol Quantity Unit Item or symbol Quantity Unit 2 Suction pressure,

Διαβάστε περισσότερα

Digital motor protection relays

Digital motor protection relays Digital motor protection relays Specification DMP -S & DMP -Sa DMP -T & DMP -Ta Model No. DMP06-S/Sa DMP60-S/Sa DMP06-T/Ta DMP60-T/Ta Wiring Screw type Tunnel type Panel mount Unit or Extension Note1)

Διαβάστε περισσότερα

CPU Merom 478 PIN (micro FC-PGA) P3,4. FSB 667 MHz(166X4) FSB 800MHz(200X4) UNBUFFERED DDRII SODIMM DDRII 533/667 UNBUFFERED DDRII SODIMM P11

CPU Merom 478 PIN (micro FC-PGA) P3,4. FSB 667 MHz(166X4) FSB 800MHz(200X4) UNBUFFERED DDRII SODIMM DDRII 533/667 UNBUFFERED DDRII SODIMM P11 WK lock iagram.mhz VRM GR P- Mx PS PU Merom PIN (micro F-PG) P, LOK GEN ISLPR P VI P FS MHz(X) FS MHz(X) TI M P- LVS R/G/ L P RT P PIE Lanes LVS R/G/ restline GM/PM PIN (micro FG) mm x mm P- RII / RII

Διαβάστε περισσότερα

P P Ó P. r r t r r r s 1. r r ó t t ó rr r rr r rí st s t s. Pr s t P r s rr. r t r s s s é 3 ñ

P P Ó P. r r t r r r s 1. r r ó t t ó rr r rr r rí st s t s. Pr s t P r s rr. r t r s s s é 3 ñ P P Ó P r r t r r r s 1 r r ó t t ó rr r rr r rí st s t s Pr s t P r s rr r t r s s s é 3 ñ í sé 3 ñ 3 é1 r P P Ó P str r r r t é t r r r s 1 t r P r s rr 1 1 s t r r ó s r s st rr t s r t s rr s r q s

Διαβάστε περισσότερα

GigaDevice Semiconductor Inc. GD32150R-EVAL Evaluation Board. User Manual

GigaDevice Semiconductor Inc. GD32150R-EVAL Evaluation Board. User Manual GigaDevice Semiconductor Inc. GD0R-EVAL Evaluation Board User Manual GD0R-EVAL Table of Contents List of Figures... Introduction... Function pin assignment... Getting started... Hardware layout overview....

Διαβάστε περισσότερα

Q π (/) ^ ^ ^ Η φ. <f) c>o. ^ ο. ö ê ω Q. Ο. o 'c. _o _) o U 03. ,,, ω ^ ^ -g'^ ο 0) f ο. Ε. ιη ο Φ. ο 0) κ. ο 03.,Ο. g 2< οο"" ο φ.

Q π (/) ^ ^ ^ Η φ. <f) c>o. ^ ο. ö ê ω Q. Ο. o 'c. _o _) o U 03. ,,, ω ^ ^ -g'^ ο 0) f ο. Ε. ιη ο Φ. ο 0) κ. ο 03.,Ο. g 2< οο ο φ. II 4»» «i p û»7'' s V -Ζ G -7 y 1 X s? ' (/) Ζ L. - =! i- Ζ ) Η f) " i L. Û - 1 1 Ι û ( - " - ' t - ' t/î " ι-8. Ι -. : wî ' j 1 Τ J en " il-' - - ö ê., t= ' -; '9 ',,, ) Τ '.,/,. - ϊζ L - (- - s.1 ai

Διαβάστε περισσότερα

Advanced Subsidiary Unit 1: Understanding and Written Response

Advanced Subsidiary Unit 1: Understanding and Written Response Write your name here Surname Other names Edexcel GE entre Number andidate Number Greek dvanced Subsidiary Unit 1: Understanding and Written Response Thursday 16 May 2013 Morning Time: 2 hours 45 minutes

Διαβάστε περισσότερα

HORIZON QUANTUM. Logging

HORIZON QUANTUM. Logging HORIZON QUANTUM High Capacity Packet Microwave System FEATURES NETWORK MANAGEMENT (NMS) Capacity w/accelerator Variable from 10 to 2000 Mbps full duplex CIR Management Access In or out of band 2x capacity

Διαβάστε περισσότερα

ΚΑΤΑΛΟΓΟΣ ΠΡΟΪΟΝΤΩΝ. www.valcom.gr ΚΑΤΑΛΟΓΟΣ ΠΡΟΪΟΝΤΩΝ. βιοµηχανικός ηλεκτρολογικός εξοπλισµός

ΚΑΤΑΛΟΓΟΣ ΠΡΟΪΟΝΤΩΝ. www.valcom.gr ΚΑΤΑΛΟΓΟΣ ΠΡΟΪΟΝΤΩΝ. βιοµηχανικός ηλεκτρολογικός εξοπλισµός ΚΑΤΑΛΟΓΟΣ ΠΡΟΪΟΝΤΩΝ Μείνετε ενηµερωµένοι για όσα κάνουµε. Συναναστραφείτε µαζί µας στο facebook. βιοµηχανικός ηλεκτρολογικός εξοπλισµός ΚΑΤΑΛΟΓΟΣ ΠΡΟΪΟΝΤΩΝ 2015 www.valcom.gr ΌΡΟΙ ΠΩΛΗΣΗΣ Οι τιμές τιμοκαταλόγου

Διαβάστε περισσότερα

Sheet H d-2 3D Pythagoras - Answers

Sheet H d-2 3D Pythagoras - Answers 1. 1.4cm 1.6cm 5cm 1cm. 5cm 1cm IGCSE Higher Sheet H7-1 4-08d-1 D Pythagoras - Answers. (i) 10.8cm (ii) 9.85cm 11.5cm 4. 7.81m 19.6m 19.0m 1. 90m 40m. 10cm 11.cm. 70.7m 4. 8.6km 5. 1600m 6. 85m 7. 6cm

Διαβάστε περισσότερα

A/m

A/m G anada Ltd. MTERI ROSS REFERENE Ferronics V G FTF T G FKF G F82F G G FF1G J G F52J K G F01H P G F21 Units Initial Permeability (µi) 15,000 15,000 10,000 10,000 5,000 5,000 1,500 1,500 850 850 125 125

Διαβάστε περισσότερα

FM9 XXXX Intel Discrete GFX

FM9 XXXX Intel Discrete GFX FM XXXX Intel iscrete GFX VER : PW: PW: POWER /TT ONNETOR PG R-SOIMM PG R-SOIMM SYSTEM RESET IRUIT TT HRGER RUN POWER SW +.V_SUS/+V_SUS +V/+.V/+.V PG PG PG ual hannel R //.V uburndale/ larksfield ( rpg

Διαβάστε περισσότερα

DIS._eDP. edp N13P-GS N13P-GL N13M-GS PEG TX/RX GPU. Display P15~P19. DMI(x4) INT_LVDS INT_CRT. Display INT_HDMI USB3.0/2.0 USB3-2/USB2-1.

DIS._eDP. edp N13P-GS N13P-GL N13M-GS PEG TX/RX GPU. Display P15~P19. DMI(x4) INT_LVDS INT_CRT. Display INT_HDMI USB3.0/2.0 USB3-2/USB2-1. IS._eP OM IV@ : igpu EV@ : dgpu OP@ : Optimus O@ : iscrete only SP@ : Special SNP@: NPGS/GL IV@: UM GL@: NPGL GS@: NP/MGS ep on. P RIII-SOIMM RIII-SOIMM P, INT._eP ual hannel R III 0//00 MHZ ep IM FI IVY

Διαβάστε περισσότερα

ITU-R BT.2033 (2013/01) / 0) ( )

ITU-R BT.2033 (2013/01) / 0) ( ) ITU-R BT. (/) & ' ( & " #$%! - ".,(UHF) ) * + (VHF) ( / ) ( ) BT ITU-R BT.8-9 ii.. (IPR) (ITU-T/ITU-R/ISO/IEC).ITU-R http://www.itu.int/itu-r/go/patents/en. (http://www.itu.int/publ/r-rec/en ) ( ) () BO

Διαβάστε περισσότερα

BM1385. Bitcoin Hash ASIC Datasheet. Bitmain Technologies Limited

BM1385. Bitcoin Hash ASIC Datasheet. Bitmain Technologies Limited BM1385 Bitcoin Hash ASIC Datasheet Bitmain Technologies Limited Page 1 of 14 Contents Contents... 1 Revision History... 2 1 Overview... 3 1.1 Features... 3 1.2 Applications... 3 2 Pin Description... 4

Διαβάστε περισσότερα

Fourier Series. MATH 211, Calculus II. J. Robert Buchanan. Spring Department of Mathematics

Fourier Series. MATH 211, Calculus II. J. Robert Buchanan. Spring Department of Mathematics Fourier Series MATH 211, Calculus II J. Robert Buchanan Department of Mathematics Spring 2018 Introduction Not all functions can be represented by Taylor series. f (k) (c) A Taylor series f (x) = (x c)

Διαβάστε περισσότερα

SMBJ SERIES. SMBG Plastic-Encapsulate Diodes. Transient Voltage Suppressor Diodes. Peak pulse current I PPM A with a 10/1000us waveform See Next Table

SMBJ SERIES. SMBG Plastic-Encapsulate Diodes. Transient Voltage Suppressor Diodes. Peak pulse current I PPM A with a 10/1000us waveform See Next Table SMBJ SERIES SMBG Plastic-Encapsulate Diodes HD BK 7 Transient Suppressor Diodes Features P PP 6W V RWM 5.V- 44V Glass passivated chip Applications Clamping Marking SMBJ XXCA/XXA/XX XX : From 5. To 44 SMBG

Διαβάστε περισσότερα

2. Μηχανικό Μαύρο Κουτί: κύλινδρος με μια μπάλα μέσα σε αυτόν.

2. Μηχανικό Μαύρο Κουτί: κύλινδρος με μια μπάλα μέσα σε αυτόν. Experiental Copetition: 14 July 011 Proble Page 1 of. Μηχανικό Μαύρο Κουτί: κύλινδρος με μια μπάλα μέσα σε αυτόν. Ένα μικρό σωματίδιο μάζας (μπάλα) βρίσκεται σε σταθερή απόσταση z από το πάνω μέρος ενός

Διαβάστε περισσότερα

070-A

070-A 764 070-A543-50 www.tektronix.com Copyright Tektronix Japan, Ltd. All rights reserved. 141 0001 5 9 31 TektronixTek Tektronix, Inc. i v ix xi 1 11 12 12 12 13 19 110 110 2 21 21 22 23 24 24 26 211

Διαβάστε περισσότερα

7. Schematic Diagram. 7-1 Overall Block Diagram FRONT MAIN MAIN CD SMPS (MAX-A54U)...

7. Schematic Diagram. 7-1 Overall Block Diagram FRONT MAIN MAIN CD SMPS (MAX-A54U)... 7. Schematic Diagram 7- Overall Block Diagram... 7-7- FRONT... 7-7- MAIN-... 7-7- MAIN-... 7-5 7-5 CD... 7-7- SM (MAX-A5U)... 7-7 7-7 SM (MAX-A55U)... 7- Samsung Electronics This Document can not be used

Διαβάστε περισσότερα

Metal Oxide Varistors (MOV) Data Sheet

Metal Oxide Varistors (MOV) Data Sheet Φ SERIES Metal Oxide Varistors (MOV) Data Sheet Features Wide operating voltage (V ma ) range from 8V to 0V Fast responding to transient over-voltage Large absorbing transient energy capability Low clamping

Διαβάστε περισσότερα

Example Sheet 3 Solutions

Example Sheet 3 Solutions Example Sheet 3 Solutions. i Regular Sturm-Liouville. ii Singular Sturm-Liouville mixed boundary conditions. iii Not Sturm-Liouville ODE is not in Sturm-Liouville form. iv Regular Sturm-Liouville note

Διαβάστε περισσότερα

Couplage dans les applications interactives de grande taille

Couplage dans les applications interactives de grande taille Couplage dans les applications interactives de grande taille Jean-Denis Lesage To cite this version: Jean-Denis Lesage. Couplage dans les applications interactives de grande taille. Réseaux et télécommunications

Διαβάστε περισσότερα

Σχεδίαση Ψηφιακών Συστημάτων

Σχεδίαση Ψηφιακών Συστημάτων ΕΛΛΗΝΙΚΗ ΔΗΜΟΚΡΑΤΙΑ Ανώτατο Εκπαιδευτικό Ίδρυμα Πειραιά Τεχνολογικού Τομέα Σχεδίαση Ψηφιακών Συστημάτων Ενότητα 2: Βασικές Μονάδες Κυριάκης - Μπιτζάρος Ευστάθιος Τμήμα Ηλεκτρονικών Μηχανικών Τ.Ε. Άδειες

Διαβάστε περισσότερα

Table15 Table of Motors Used and Corresponding Intermediate Flanges

Table15 Table of Motors Used and Corresponding Intermediate Flanges Intermediate Flange Motor Used and Applicable Intermediate Flanges for Model KR Several types of intermediate fl anges for mounting motors are available for model KR. Specify an intermediate flange that

Διαβάστε περισσότερα

PCB Footprint Library

PCB Footprint Library PCB Tantalum Capacitors EIA Standard Low Inductance MLCs Chip Film Capacitors SuperCaps Filters TVS Diodes Couplers Crossovers Inductors Timing Devices Resistive Products http://www.avx.com Tantalum Capacitors

Διαβάστε περισσότερα

Exercises in Electromagnetic Field

Exercises in Electromagnetic Field DR. GYURCSEK ISTVÁN Exercises in Electromagnetic Field Sources and additional materials (recommended) Gyurcsek I. Elmer Gy.: Theories in Electric Circuits, Globe Edit 206, ISBN:97833307343 Simonyi K.:

Διαβάστε περισσότερα

SMD Transient Voltage Suppressors

SMD Transient Voltage Suppressors SMD Transient Suppressors Feature Full range from 0 to 22 series. form 4 to 60V RMS ; 5.5 to 85Vdc High surge current ability Bidirectional clamping, high energy Fast response time

Διαβάστε περισσότερα

GigaDevice Semiconductor Inc. GD32103C-EVAL Evaluation Board. User Manual

GigaDevice Semiconductor Inc. GD32103C-EVAL Evaluation Board. User Manual GigaDevice Semiconductor Inc. GD0C-EVAL Evaluation Board User Manual GD0C-EVAL Table of Contents List of Figures... Introduction... Function pin assignment... Getting started... Hardware layout overview....

Διαβάστε περισσότερα

ΗΥ360 Αρχεία και Βάσεις εδοµένων ιδάσκων:. Πλεξουσάκης

ΗΥ360 Αρχεία και Βάσεις εδοµένων ιδάσκων:. Πλεξουσάκης ΗΥ360 Αρχεία και Βάσεις εδοµένων ιδάσκων:. Πλεξουσάκης ιαχείριση Συναλλαγών II Tree Protocols Τζικούλης Βασίλειος redits:γιάννης Μακρυδάκης 1 ιαχείριση Συναλλαγών Συναλλαγή = Αδιάσπαστη Λογική Οµάδα Ενεργειών

Διαβάστε περισσότερα

BLOCK DIAGRAM TRAVIS_L ANX3110 DP0/TXPN[0:1] DP0_AUXP/N DP0. Socket FS1-LIano APU ( CPU + GPU ) upga 722 pin DP2 DP2/PCI-E 0_3.

BLOCK DIAGRAM TRAVIS_L ANX3110 DP0/TXPN[0:1] DP0_AUXP/N DP0. Socket FS1-LIano APU ( CPU + GPU ) upga 722 pin DP2 DP2/PCI-E 0_3. X'TL MHz P STK UP LYER : TOP LYER : GN LYER : IN LYER : SGN LYER : SGN LYER : IN LYER : V LYER : OT theros /M R Transformer RJ PIEx GPP PIE Mini ard WWN/G R.V support ~ MHz R III SO-IMM SO-IMM Memory size

Διαβάστε περισσότερα

OST-7080HD Διασυνδέσεις Sleep ΠΛΗΚΤΡΟ ΜΑΘΗΣΗΣ: Το τηλεχειριστήριο του ψηφιακού δέκτη έχει 6 πλήκτρα μάθησης. Κάθε πλήκτρο μπορεί να είναι αντίγραφο κάθε πλήκτρου λειτουργίας του τηλεχειριστηρίου. Οδηγίες

Διαβάστε περισσότερα

WANDBOARD USER GUIDE Revision B1

WANDBOARD USER GUIDE Revision B1 WNOR USER GUIE Revision (000) WNOR ESIGN N ISLIMER These design materials referred to in this document are *NOT SUPPORTE* and O NOT constitute a reference design. Only "community" support is allowed via

Διαβάστε περισσότερα

Product Selection Tables. 2005 SMD Resistors. Yageo brand

Product Selection Tables. 2005 SMD Resistors. Yageo brand eo.com Product Selection Tables 2005 SMD Resistors Yageo brand Table of Contents www.yageo.com Table of contents Resistor chips, General purpose / Yageo brand 2 General purpose, 0201-0805 2 General purpose,

Διαβάστε περισσότερα

DAISY CHAIN PATTERN BUMP (PAD) VIEW SOLDER BUMP PAD DETAIL 1 WIRE BONDING PAD DETAIL 2 BUMP 95 UBM 115

DAISY CHAIN PATTERN BUMP (PAD) VIEW SOLDER BUMP PAD DETAIL 1 WIRE BONDING PAD DETAIL 2 BUMP 95 UBM 115 SOLDER PD DETIL 95 UBM 5 5 WIRE BONDING PD DETIL 2 00 2 5 2 5 55 B D E F G H J K L M N P R T U V W B D DIS HIN PTTERN (PD) VIEW 2 4 6 8 0 2 4 6 8 20 22 24 3 5 7 9 3 5 7 9 2 23 NOTES: ) DIMENSIONS IN MIRONS

Διαβάστε περισσότερα

[bar] 0,5 (7.3 PSI) maximum continuous pressure - maximum working pressure, at which the pump can be operated without time limitation.

[bar] 0,5 (7.3 PSI) maximum continuous pressure - maximum working pressure, at which the pump can be operated without time limitation. Gear Pump High Performance Version GP3 up to cm 3 (6. inch 3 ) p max 3 (46 PSI) Speed from 35 to 32 RPM Technical Features Nominal pressure 29 bar, peak pressure 3 High quality aluminum alloys pump with

Διαβάστε περισσότερα

Unshielded Power Inductors

Unshielded Power Inductors Unshielded Power Inductors /080/0804/0810/106/106 Series Inductance with current and temperature: Inductance is measured with P-484 LR Meter or equivalent. Inductance drops 10% typical at Isat level with

Διαβάστε περισσότερα

M3 System Block Diagram

M3 System Block Diagram M System lock iagram M/ M socket LE Panel L Panel (LVS) R-SOMM & R-SOMM & LOK GEN SLGSP.MHz R 0/ MT/s R 0/ MT/s PU M thlon HT-Link N M RS0M PE.0 X 0~ ~ MXM.0 Type MUX PPE - MUX PPE - UM_P UM_P UM_LVS MXM_LVS

Διαβάστε περισσότερα

SPEEDO AQUABEAT. Specially Designed for Aquatic Athletes and Active People

SPEEDO AQUABEAT. Specially Designed for Aquatic Athletes and Active People SPEEDO AQUABEAT TM Specially Designed for Aquatic Athletes and Active People 1 2 Decrease Volume Increase Volume Reset EarphonesUSBJack Power Off / Rewind Power On / Fast Forward Goggle clip LED Status

Διαβάστε περισσότερα

AIT Mars PRO. PCIE Gen 1 x 1 Lane. Power : 25 (Watt) Package : M2 Size : 29 x 29 (mm) PAGE DP Port2. RTD2132S DP to LVDS.

AIT Mars PRO. PCIE Gen 1 x 1 Lane. Power : 25 (Watt) Package : M2 Size : 29 x 29 (mm) PAGE DP Port2. RTD2132S DP to LVDS. Volks_M omal IS/UM (") Ultra/Slim R SOIMM Maxima Gs PGE R SO-IMM Maxima Gs PGE R ~ MT/s R ~ MT/s M PU Processor : TRINITY aul / Quad ore Power : (Watt) Package : FP -PIN G Size : x (mm) IME PI-E Gen x

Διαβάστε περισσότερα

Forêts aléatoires : aspects théoriques, sélection de variables et applications

Forêts aléatoires : aspects théoriques, sélection de variables et applications Forêts aléatoires : aspects théoriques, sélection de variables et applications Robin Genuer To cite this version: Robin Genuer. Forêts aléatoires : aspects théoriques, sélection de variables et applications.

Διαβάστε περισσότερα

No Item Code Description Series Reference (1) Meritek Series CRA Thick Film Chip Resistor AEC-Q200 Qualified Type

No Item Code Description Series Reference (1) Meritek Series CRA Thick Film Chip Resistor AEC-Q200 Qualified Type Qualified FEATURE Excellent Mechanical Strength and Electrical Stability Ideal for Pick and Place Machinery Stable High Frequency Characteristics Miniature, High Board Density Equivalent Specification

Διαβάστε περισσότερα

3607 Ν. 7.28/88. E.E., Παρ. I, Αρ. 2371,

3607 Ν. 7.28/88. E.E., Παρ. I, Αρ. 2371, E.E., Παρ. I, Αρ. 271, 16.12. 607 Ν. 7.2/ περί Συμπληρματικύ Πρϋπλγισμύ Νόμς (Αρ. 5) τυ 19 εκδίδεται με δημσίευση στην επίσημη εφημερίδα της Κυπριακής Δημκρατίας σύμφνα με τ Άρθρ 52 τυ Συντάγματς- - Αριθμός

Διαβάστε περισσότερα

RECIPROCATING COMPRESSOR CALCULATION SHEET ISOTHERMAL COMPRESSION Gas properties, flowrate and conditions. Compressor Calculation Sheet

RECIPROCATING COMPRESSOR CALCULATION SHEET ISOTHERMAL COMPRESSION Gas properties, flowrate and conditions. Compressor Calculation Sheet RECIPRCATING CMPRESSR CALCULATIN SHEET ISTHERMAL CMPRESSIN Gas properties, flowrate and conditions 1 Gas name Air Item or symbol Quantity Unit Item or symbol Quantity Unit Formula 2 Suction pressure, ps

Διαβάστε περισσότερα

P r s r r t. tr t. r P

P r s r r t. tr t. r P P r s r r t tr t r P r t s rés t t rs s r s r r t é ér s r q s t r r r r t str t q q s r s P rs t s r st r q r P P r s r r t t s rés t t r t s rés t t é ér s r q s t r r r r t r st r q rs s r s r r t str

Διαβάστε περισσότερα

w o = R 1 p. (1) R = p =. = 1

w o = R 1 p. (1) R = p =. = 1 Πανεπιστήµιο Κρήτης - Τµήµα Επιστήµης Υπολογιστών ΗΥ-570: Στατιστική Επεξεργασία Σήµατος 205 ιδάσκων : Α. Μουχτάρης Τριτη Σειρά Ασκήσεων Λύσεις Ασκηση 3. 5.2 (a) From the Wiener-Hopf equation we have:

Διαβάστε περισσότερα

Q1a. HeavisideTheta x. Plot f, x, Pi, Pi. Simplify, n Integers

Q1a. HeavisideTheta x. Plot f, x, Pi, Pi. Simplify, n Integers 2 M2 Fourier Series answers in Mathematica Note the function HeavisideTheta is for x>0 and 0 for x

Διαβάστε περισσότερα

SERVICE MANUAL RE-2 PROJECTION TV CHASSIS. KP-41S5K RM-862 OIRT SCC-N62D-A KP-41S5R RM-862 Russian SCC-N62C-A KP-41S5U RM-862 UK SCC-N61B-A

SERVICE MANUAL RE-2 PROJECTION TV CHASSIS. KP-41S5K RM-862 OIRT SCC-N62D-A KP-41S5R RM-862 Russian SCC-N62C-A KP-41S5U RM-862 UK SCC-N61B-A SV MNU - SSS M MMN ST. SSS N. M MMN ST. SSS N......................... P-S M- P S-N- P-S M- rench S-N- P-S M- reek S-N- P-S M- T S-N- P-S M- ussian S-N- P-SU M- U S-N- MM Please file according to model

Διαβάστε περισσότερα

K72JK Schematic R2.0

K72JK Schematic R2.0 PGE ontent lock iagram System Setting PU()_MI,PEG,FI,LK,MIS PU()_R PU()_FG,RSV, PU()_PWR PU()_XP R SOIMM_0 R SOIMM_ R _Q VOLTGE 9 VI controller 0 PH_IEX()ST,IH,RT,LP PH_IEX()_PIE,LK,SM,PEG PH_IEX()_FI,MI,SYS

Διαβάστε περισσότερα

Axial Film Capacitors Metallized Polyester and Polypropylene

Axial Film Capacitors Metallized Polyester and Polypropylene Axial Film Capacitors Metallized Polyester and Polypropylene... your source for the Ultimate in Reliability 1 Table of Contents Part Numbering System 2 Dielectric Characteristics 3 AREM 5 AFEO 6 AFPX 7

Διαβάστε περισσότερα