BLOCK DIAGRAM TRAVIS_L ANX3110 DP0/TXPN[0:1] DP0_AUXP/N DP0. Socket FS1-LIano APU ( CPU + GPU ) upga 722 pin DP2 DP2/PCI-E 0_3.

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1 X'TL MHz P STK UP LYER : TOP LYER : GN LYER : IN LYER : SGN LYER : SGN LYER : IN LYER : V LYER : OT theros /M R Transformer RJ PIEx GPP PIE Mini ard WWN/G R.V support ~ MHz R III SO-IMM SO-IMM Memory size MX is G per channel PIEx GPP PIE Mini ard WiFi ual hannel ~MHz.GT/s PI-Express Gen PI-Express Gen.GT/s PI-Express Gen PIEx GPP PIE.GT/s LOK IGRM R SYSTEM MEMORY GPP PIEX GPP PIEX GPP PIEX M Support W/W TP Socket FS-LIano PU ( PU + GPU ) upg pin UMI X UMI interface.gt/s UMI P/TXPN[:] P_UXP/N P/PI-E _ P_P/PI-E _ P/TXPN[:] P P P PIE X TRVIS_L NX PI-Express Gen GT/s HMI ONN TI GPU Seymour XT S Package X'TL.MHz LVS PNEL SIM ard US./. ombo X US. H (ST) O (ST) ST ST US. Gbit/s Gbit/s US./. US. ST Gen ST Gen ST Gen US./. M FH Hudson-M/M P to VG RT US. VG X'TL.KHz VG ONN US. ports US. zalia ( H bus ) H FG pin PI-E RT_LK ardreader RTS US. US. udio OE onexant X LP SPI SPI ROM LP E Nuvoton NPEL.KHz sharing HP Jack MI Jack SPK MI M SPI ROM Touch Pad Keyboard utton on mechanical key bios.ru Quanta omputer Inc. PROJET : LF_LF Size ocument Number Rev System lock iagram Tuesday, pril, ate: Sheet of

2 LF/LF Power On Sequence: S > S +V_RT +VIN +VPU/+VPU/+V IN NSWON# S+ NOT implemented S_ON/S_ORE_EN S+ implemented S_ORE_EN +V_S not present equal to LOW; present equal to High Power button from switch to E To turn on dual power rails S+ implemented to turn off dual power rails PU Power on sequence required: Llano PU:.Group ( +.V_SUS, +.V_V ) ramp before Group ( +V_ORE, +VN_ORE, +.V_VPR ) HUSON-M/M:.+V_S ramp before +.V_UL.+V ramp before +.V.+V_RT must ramp at least secs before the +V_S +.V_UL RSMRST_GTE# RTLK PWR_TN#_E SLP_S# SUS_ON ms Max ms delay at least ms Min Power button from E to FH Seymour XT S package Power-on sequence ll power rails reach nominal within ms => +V_GPU => +VGPU_ORE/+V_GPU => +VGPU_ORE PWRG to enable +.V_GPU.=> +V_GPU PWRG to enable +.V_GPU NOTE.+V to turn on +V_GPU PU GROUP power +.V_SUS +.V_R_VTT VRM_PWRG SLP_S# RUN_ON +V/+V +.V_R_VTT only will be shut down in S mode and for R SOIMM only.+v_gpu ready to enable +VGPU_ORE/+V_GPU ( +V_GPU will ramp up before +VGPU_ORE ).+VGPU_ORE PWRG to enable +.V_GPU.+V_GPU PWRG to enable +.V_GPU +.V_V TRVIS_L NX power on sequecne PU GROUP power +.V_RUN/+.V/+.V V_PWRG +VN_ORE +V_ORE efault controlled by +.V.+V must lead +.V_TRVIS.+.V_TRVIS must lead TRVIS_RST# NOTE: FH must output PIE_RST#_TRVIS or PU_PIE_RST# after +.V_TRVIS ready +.V_VPR VRM_PWRG +.V_VPR_PG ms < T <ms FH_PWRG ms Max PU_LKP/N PU_PWRG ms Max bios.ru _RST#(PLTRST#) PIRST# PU_RST# ms < T <ms ns < T <ns ms < T <.ms Quanta omputer Inc. PROJET : LF_LF Size ocument Number Rev POWER SEQUENE ate: Tuesday, pril, Sheet of

3 V_PWRG VIN PU core N core (ISLHRZ-T) +V_ORE T/ +VN_ORE T/ TP/W +VPU </ Insert> +VPU MIN O +V +V O_EN O +V_O V_PWRG +VPU TP-H +.V_VPR VIN VL SYSTEM V/V (PMTR) +VPU S_ON MIN +VPU </ Insert> ME O +V +V_S RUN_ON +VPU +.V_UL (GRU) G-JFU +.V_UL +.V_V +V +.V O VG_P +V NE FH_VN +V_GPU_PG +VPU UPU +.V_GPU PTER TTERY HRGER ISLHRTZ-T VIN VIN +V +.V_SUS MIN +.V_SUS SUS_ON R PWR.V (RTLGQW) NK ME +.V_R_VTT +.V_RUN +.V +VGPU_ORE_PG TP-H +VPU +VGPU_ORE_PG ON +.V_SUS +.V_GPU +.V_GPU Suport.V use W/O.V use +.V_SUS Voltage ivider +.V_VREF_ +.V_SUS Voltage ivider +.V_VREF_Q PX_EN +V_GPU +.V_GPU PX_MOE GPU ORE/IO (ISLHRUZ-T) GPU ORE/IO (G-JFU) +VGPU_ORE +V_GPU VG_P +.V NE +FH_VN ML +VGPU_ORE +PIE_V MNK- MNK- +IF_V PX_EN bios.ru Quanta omputer Inc. PROJET : LF_LF Size ocument Number Rev Power Tree ate: Tuesday, pril, Sheet of

4 _SOIMM _SOIMM MEM_M_LK_P/N MEM_M_LK_P/N MEM_M_LK_P/N MEM_M_LK_P/N M FS PU MHz (non-spread) INTERNL LOK MOE E MHz.KHZ LPLK RTLK LK_P_NSSP/N PU_LKP/N SLT_GFX_LKP/N GPP_LKP/N GPP_LKP/N GPP_LKP/N MHz MHz MHz MHz iscrete GPU WLN LN (R) WWN/G LP ebug port MHz LPLK M HUSON-M MHz TRVIS_L Integrated LOK GENERTOR SPI ROM H UIO R REER MHz MHz MHz SPI_LK Z_ITLK M_M_M_OS FOR MSTER FOR RT M HZ.K Hz bios.ru Quanta omputer Inc. PROJET : LF_LF Size ocument Number Rev lock istribution iagram ate: Tuesday, pril, Sheet of

5 UF LN WLN G PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PIE_RXP_LN PIE_RXN_LN PIE_RXP PIE_RXN PIE_RXP PIE_RXN UMI_RXP UMI_RXN UMI_RXP UMI_RXN UMI_RXP UMI_RXN UMI_RXP UMI_RXN +.V_VPR PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN R /F_ Y Y W W W W V V U U U U T T R R R R P P N N N N M M L L L L F F E E E E K PI EXPRESS P_GFX_RXP P_GFX_TXP P_GFX_RXN P_GFX_TXN P_GFX_RXP P_GFX_TXP P_GFX_RXN P_GFX_TXN P_GFX_RXP P_GFX_TXP P_GFX_RXN P_GFX_TXN P_GFX_RXP P_GFX_TXP P_GFX_RXN P_GFX_TXN P_GFX_RXP P_GFX_TXP P_GFX_RXN P_GFX_TXN P_GFX_RXP P_GFX_TXP P_GFX_RXN P_GFX_TXN P_GFX_RXP P_GFX_TXP P_GFX_RXN P_GFX_TXN P_GFX_RXP P_GFX_TXP P_GFX_RXN P_GFX_TXN P_GFX_RXP P_GFX_TXP P_GFX_RXN P_GFX_TXN P_GFX_RXP P_GFX_TXP P_GFX_RXN P_GFX_TXN P_GFX_RXP P_GFX_TXP P_GFX_RXN P_GFX_TXN P_GFX_RXP P_GFX_TXP P_GFX_RXN P_GFX_TXN P_GFX_RXP P_GFX_TXP P_GFX_RXN P_GFX_TXN P_GFX_RXP P_GFX_TXP P_GFX_RXN P_GFX_TXN P_GFX_RXP P_GFX_TXP P_GFX_RXN P_GFX_TXN P_GFX_RXP P_GFX_TXP P_GFX_RXN P_GFX_TXN P_GPP_RXP P_GPP_RXN P_GPP_RXP P_GPP_RXN P_GPP_RXP P_GPP_RXN P_GPP_RXP P_GPP_RXN P_UMI_RXP P_UMI_RXN P_UMI_RXP P_UMI_RXN P_UMI_RXP P_UMI_RXN P_UMI_RXP P_UMI_RXN P_ZVP GRPHIS GPP UMI-LINK P_GPP_TXP P_GPP_TXN P_GPP_TXP P_GPP_TXN P_GPP_TXP P_GPP_TXN P_GPP_TXP P_GPP_TXN P_UMI_TXP P_UMI_TXN P_UMI_TXP P_UMI_TXN P_UMI_TXP P_UMI_TXN P_UMI_TXP P_UMI_TXN P_ZVSS Y Y Y Y W W V V V V U U T T T T R R P P P P N N M M M M L L F F F F E E K PEG_HMI_TXP PEG_HMI_TXN PEG_HMI_TXP PEG_HMI_TXN PEG_HMI_TXP PEG_HMI_TXN PEG_HMI_TXP PEG_HMI_TXN PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PIE_TXP_LN_ PIE_TXN_LN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ PIE_TXN_ UMI_TXP_ UMI_TXN_ UMI_TXP_ UMI_TXN_ UMI_TXP_ UMI_TXN_ UMI_TXP_ UMI_TXN_ P_ZVSS R.U/V_X.U/V_X.U/V_X.U/V_X IS@.U/V_X IS@.U/V_X IS@.U/V_X IS@.U/V_X IS@.U/V_X IS@.U/V_X IS@.U/V_X IS@.U/V_X.U/V_X.U/V_X G@.U/V_X.U/V_X.U/V_X.U/V_X.U/V_X /F_.U/V_X.U/V_X.U/V_X.U/V_X INT_HMI_TXP INT_HMI_TXN INT_HMI_TXP INT_HMI_TXN INT_HMI_TXP INT_HMI_TXN INT_HMI_TXP INT_HMI_TXN PEG_TXP IS@.U/V_X PEG_TXN PEG_TXP IS@.U/V_X PEG_TXN PEG_TXP IS@.U/V_X PEG_TXN PEG_TXP IS@.U/V_X PEG_TXN PEG_TXP IS@.U/V_X PEG_TXN PEG_TXP IS@.U/V_X PEG_TXN PEG_TXP IS@.U/V_X PEG_TXN PEG_TXP IS@.U/V_X PEG_TXN PIE_TXP_LN.U/V_X PIE_TXN_LN PIE_TXP.U/V_X PIE_TXN PIE_TXP G@.U/V_X PIE_TXN.U/V_X.U/V_X.U/V_X.U/V_X UMI_TXP UMI_TXN UMI_TXP UMI_TXN UMI_TXP UMI_TXN UMI_TXP UMI_TXN INT_HMI_TXP INT_HMI_TXN INT_HMI_TXP INT_HMI_TXN INT_HMI_TXP INT_HMI_TXN INT_HMI_TXP INT_HMI_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PIE_TXP_LN PIE_TXN_LN PIE_TXP PIE_TXN PIE_TXP PIE_TXN UMI_TXP UMI_TXN UMI_TXP UMI_TXN UMI_TXP UMI_TXN UMI_TXP UMI_TXN HMI LN WLN G P_GFX_TXP/N[:] correspond to isplayport. Llano PU bios.ru Quanta omputer Inc. PROJET : LF_LF Size ocument Number Rev Llano PIE/UMI/GPP ate: Tuesday, pril, Sheet of

6 bios.ru Place close to PU within " Soldermask openings for all bottom side vias/tps under FS M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M S# M S# M S# M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M S# M S# M S# M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M EVENT# M EVENT# M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSN M QSN M QSN M QSN M QSN M QSN M QSN M QSN M KE M KE M OT M OT M S# M S# M RS# M RST# M S# M WE# M EVENT# M LKP M LKN M LKP M LKN M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSN M QSN M QSN M QSN M QSN M QSN M QSN M QSN M LKP M LKN M LKP M LKN M RS# M OT M OT M S# M RST# M WE# M EVENT# M KE M KE M S# M S# M Q[..] M Q[..] PU_MEMHOT# HUSON_MEMHOT# M M[..] M S#[..] M [:] M [:] M S#[..] M M[..] +M_VREF +.V_SUS +M_VREF +.V_SUS +.V_SUS +.V_SUS +.V_SUS +.V_SUS Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : Llano R MEM I/F Tuesday, pril, LF_LF Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : Llano R MEM I/F Tuesday, pril, LF_LF Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : Llano R MEM I/F Tuesday, pril, LF_LF Q *MMT--F_M Q *MMT--F_M.U/V_X.U/V_X MEMORY HNNEL Llano PU U MEMORY HNNEL Llano PU U M_ZVIO W M_VREF W M_EVENT_L T M_RESET_L H M_WE_L W M_S_L W M_RS_L V M_S_L M_S_L V M_OT M_OT Y M_KE H M_KE H M_LK_L R M_LK_H R M_LK_L T M_LK_H T M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H E M_QS_L E M_QS_H E M_QS_L H M_QS_H J M_QS_L H M_QS_H G M_QS_L H M_QS_H G M_M M_M M_M M_M M_M F M_M E M_M J M_M E M_NK L M_NK U M_NK U M_ L M_ L M_ M_ L M_ M M_ U M_ M M_ N M_ N M_ N M_ N M_ P M_ P M_ R M_ U M_T Y M_T M_T M_T Y M_T M_T M_T Y M_T M_T M_T M_T Y M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T Y M_T M_T Y M_T M_T M_T M_T E M_T M_T M_T M_T M_T F M_T E M_T H M_T F M_T G M_T G M_T E M_T G M_T H M_T G M_T E M_T G M_T H M_T J M_T F M_T H M_T F M_T H M_T H M_T G M_T J M_T E M_T F M_T H M_T E M_T F M_T F M_T H M_T J M_T H M_T J M_T E M_ R R K/F_ R K/F_ R K/F_ R K/F_ R./F_ R./F_ P/V_X P/V_X R *_ R *_ R K/F_ R K/F_ R *.K_ R *.K_ R *.K_ R *.K_ MEMORY HNNEL Llano PU U MEMORY HNNEL Llano PU U M_EVENT_L T M_RESET_L J M_WE_L V M_S_L V M_RS_L V M_S_L Y M_S_L V M_OT Y M_OT W M_KE J M_KE J M_LK_L P M_LK_H P M_LK_L R M_LK_H R M_QS_L G M_QS_H H M_QS_L G M_QS_H G M_QS_L F M_QS_H G M_QS_L G M_QS_H G M_QS_L M_QS_H M_QS_L M_QS_H E M_QS_L M_QS_H E M_QS_L M_QS_H M_M M_M H M_M G M_M F M_M M_M M_M M_M M_NK K M_NK T M_NK U M_ K M_ K M_ W M_ K M_ L M_ U M_ L M_ M M_ M M_ M M_ M M_ N M_ N M_ P M_ P M_ T M_T F M_T E M_T F M_T G M_T M_T G M_T M_T G M_T M_T F M_T G M_T G M_T H M_T E M_T E M_T F M_T M_T M_T M_T M_T H M_T E M_T H M_T E M_T E M_T H M_T F M_T G M_T G M_T F M_T H M_T G M_T M_T M_T M_T M_T M_T M_T M_T E M_T M_T E M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T E M_T M_T M_T M_T M_T M_T M_T M_T M_T E M_T M_T M_T R K/F_ R K/F_ Q *MMT--F_M Q *MMT--F_M

7 P to LVS P to Hudson-M VG output,, Note: LK_PU_HLKP/N is MHZ SS Note: LK_P_NSSP/N is MHZ non-ss PU_RST# PU_PWRG PU_THERMTRIP# +.V_SUS R _ PU_PROHOT# PU_PROHOT#_VIO PU_TI PU_TO PU_TK PU_TMS PU_TRST# R _ TP TP TP TP TP +.V_RUN R *_ Q R K_ Q MMT--F_M PU_PROHOT# R *_ PU_PROHOT#_VIO INT_LVS_TXP INT_LVS_TXN INT_LVS_TXP INT_LVS_TXN PU_P_TXP PU_P_TXN PU_P_TXP PU_P_TXN PU_P_TXP PU_P_TXN PU_P_TXP PU_P_TXN LK_PU_HLKP LK_PU_HLKN LK_P_NSSP LK_P_NSSN SV SV PU_RY PU_REQ# PU_VN_RUN_F_L PU_V_RUN_F_L PU_VP_F_H PU_VN_RUN_F_H PU_VIO_RUN_F_H PU_V_RUN_F_H PU_VR_F_H +.V_SUS *MMT--F_M *.U/V_X R K_ R +.V_SUS TP TP TP TP TP *SHORT_ R *K_ TP TP These TP near the PU +.V_SUS R R R R R PU_THERMTRIP#_VIO R K_ R R R R K/F_.U/V_X.U/V_X.U/V_X.U/V_X.U/V_X.U/V_X.U/V_X.U/V_X.U/V_X.U/V_X.U/V_X.U/V_X *SHORT_LK_PU_HLKP_R *SHORT_LK_PU_HLKN_R *SHORT_LK_P_NSSP_R *SHORT_LK_P_NSSN_R *SHORT_ *SHORT_ *SHORT_ SV_R SV_R PU_SI PU_SI PU_RST# PU_PWRG INT_LVS_TXP_ INT_LVS_TXN_ INT_LVS_TXP_ INT_LVS_TXN_ PU_P_TXP_ PU_P_TXN_ PU_P_TXP_ PU_P_TXN_ PU_P_TXP_ PU_P_TXN_ PU_P_TXP_ PU_P_TXN_ PU_PROHOT#_VIO PU_THERMTRIP#_VIO PU_LERT PU_TI PU_TO PU_TK PU_TMS PU_TRST# PU_RY PU_REQ# *SHORT_ VSS_SENSE PU_VP_F_H PU_VN_RUN_F_H PU_VIO_RUN_F_H PU_V_RUN_F_H PU_VR_F_H, FH_PWRG F F E E K K J J H H G G H H H H H G F E G H E K U P_TXP P_TXN P_TXP P_TXN P_TXP P_TXN P_TXP P_TXN P_TXP P_TXN P_TXP P_TXN P_TXP P_TXN P_TXP P_TXN LKIN_H LKIN_L ISP_LKIN_H ISP_LKIN_L SV SV SI SI RESET_L PWROK PROHOT_L THERMTRIP_L LERT_L TI TO TK TMS TRST_L RY REQ_L RSV_ RSV_ RSV_ VSS_SENSE VP_SENSE VN_SENSE VIO_SENSE V_SENSE VR_SENSE +.V_SUS NLOG/ISPLY/MIS ISPLY PORT ISPLY PORT RSV JTG TRL SER. LK SENSE Llano PU R *K_ Q *N_M R *K_ ISPLY PORT MIS. TEST Q *MMT--F_M P_UXP P_UXN P_UXP P_UXN P_UXP P_UXN P_UXP P_UXN P_UXP P_UXN P_UXP P_UXN P_HP P_HP P_HP P_HP P_HP P_HP P_LON P_IGON P_VRY_L P_UX_ZVSS TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST_H TEST_L TEST_H TEST_L TEST_H TEST_L TEST TEST_H TEST_L TEST FSR MTIVE_L TEST TEST SYS_SHN#, E E J J H H G G F F E J H G F G H H E G H H G F E F G H H K K K Y E N_MLK N_MT INT_LVS_UXP_ INT_LVS_UXN_ PU_P_UXP_ PU_P_UXN_ INT_HMI_UXP INT_HMI_UXN INT_LVS_HP_Q INT_VG_HP_Q INT_HMI_HP P_UX_ZVSS PU_TEST PU_TEST PU_TEST_SNSHIFTEN PU_TEST_P PU_TEST_P PU_TEST_P PU_TEST_P PU_TEST_PLLTEST PU_TEST_PLLTEST PU_TEST_SNLK PU_TEST_SNEN PU_TEST_SNSHIFTEN PU_TEST PU_TEST_SNLK PU_TEST_H PU_TEST_L PU_TEST_H PU_TEST_L NTSTIN_H NTSTIN_L M_TEST PU_TEST_H PU_TEST_L PU_TEST FSR MTIVE_L PU_TEST PU_TEST N_MLK R N_MT +VPU R.K_.U/V_X.U/V_X.U/V_X.U/V_X R.K_ /F_ TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP PU_P_UXP PU_P_UXN +.V_SUS SMK--F_M INT_HMI_HP R K/F_ PU_VRY_L INT_LVS_UXP INT_LVS_UXN PU_P_UXP PU_P_UXN INT_HMI_UXP INT_HMI_UXN PU_TEST_PLLTEST PU_TEST_PLLTEST +VPU Q R *K_ R K/F_ +.V_RUN R *K_ MMT--F_M Q MMT--F_M SMK--F_M +.V_SUS LVS +.V_RUN +.V_SUS +V R R VG *K_ K_ HMI +.V_SUS R K_ R K/F_ R R PU_SI PU_SI INT_LVS_HP_Q INT_VG_HP_Q FSR, MTIVE_L R K/F_ *_ *_ NK_M Q NK_M Q +.V_RUN R *K_ +.V_SUS R K_ NK_M Q SM_LV_LK SM_LV_T NK_M Q +V R K_ PU_TEST_L PU_TI PU_TK PU_TMS PU_TRST# R K_ PU_REQ# PU_P_UXN PU_P_UXP R K_ R K_ PU_TEST_SNSHIFTEN PU_TEST_PLLTEST PU_TEST_PLLTEST PU_TEST_SNLK PU_TEST_SNEN PU_TEST_SNSHIFTEN PU_TEST_SNLK LVS Hot-plug RT Hot-plug R R R R R R _ R R R R R R R R R INT_LVS_HP FH_VG_HP /F_ K_ K_ K_ K_ *K_ *K_ K_ K_ K_ K_ K_ K_ K_ +.V_VPR_VP +.V_SUS +V FH_PROHOT# R *_ +.V_RUN PU_TEST_H R /F_ ORE_PWM_PROHOT# R *_, H_PROHOT# ebug only R *EUG@_ R *EUG@_ PU_RST# U GN Y V +V PU_RST_L_UF PU_RST_L_UF +VPU PU_P_UXP_ PU_P_UXN_ PU_PWRG Y PU_PWROK_UF PU_PWROK_UF R.K_ R.K_.U/V_X *EUG@LVG R *.K_ R *.K_ NER PU VL +VPU R _ R bios.ru Rset(Kohm)=.T*T-.T+., Shut down on dgree (Follow thermal team report) Hysteresis is *_ +VPU_HW_S.U/V_Y U V HYST GTU +VPU +VPU dgree E R UM@.K/F_ R R IS@.K/F_ *K_ SET GN R *_ THER_SH# OT# Q *MMT--F_M R *SHORT_ *.U/V_X E +.V_SUS R SYS_SHN#, *./F_ M_TEST M_TEST ONNETION T R./F_ PU_TEST +.V_SUS R _ R *_ INT_LVS_UXP_ INT_LVS_UXN_ R.K_ R.K_ INT_HMI_UXP INT_HMI_UXN R R *.K_ *.K_ Quanta omputer Inc. PROJET : LF_LF Size ocument Number Rev Llano isplay/misc Tuesday, pril, ate: Sheet of

8 bios.ru PIN NME VOLTGE V ynamic PU POWER TLE +VN_ORE +.V VIO +.V VP VR +.V V +.V ynamic NET NME +V_ORE VN +.VSUS EMI reserve EMI reserve +.V_VP +.V_VR +.V_V cross VIO and VSS split EMI reserve EMI reserve EMI reserve OTTOM SIE EOUPLING EOUPLING between PROESSOR and IMMs If the VSS plane is cut to create a VIO plane, ceramic capacitors are connected across the VIO and VSS plane split as follows EMI Suggestion E +V_ORE +V_ORE +.V_VPR_VP +.V_VPR +VN_ORE +VN_ORE +.V_SUS +.V_SUS +.V_V +.V_SUS +V_ORE +VN_ORE +.V_SUS +.V_VPR_VR +.V_VPR +.V_VPR_VP +.V_VPR_VR +.V_SUS Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : Llano POWER/GN Tuesday, pril, LF_LF Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : Llano POWER/GN Tuesday, pril, LF_LF Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : Llano POWER/GN Tuesday, pril, LF_LF U/.V_X U/.V_X P/V_N P/V_N.U/.V_X.U/.V_X.U/.V_X.U/.V_X P/V_N P/V_N.U/V_X.U/V_X U/.V_X U/.V_X.U/.V_X.U/.V_X P/V_N P/V_N.U/.V_X.U/.V_X *P/V_N *P/V_N.U/.V_X.U/.V_X P/V_N P/V_N *P/V_N *P/V_N U/.V_X U/.V_X.U/.V_X.U/.V_X U/.V_X U/.V_X P/V_X P/V_X.U/.V_X.U/.V_X.U/.V_X.U/.V_X.U/.V_X.U/.V_X U/.V_X U/.V_X U/.V_X U/.V_X P/V_N P/V_N.U/.V_X.U/.V_X U/.V_X U/.V_X L HKF-T_ L HKF-T_ U/.V_X U/.V_X.U/.V_X.U/.V_X P/V_N P/V_N.U/V_X.U/V_X.U/.V_X.U/.V_X *P/V_N *P/V_N P/V_N P/V_N U/.V_X U/.V_X U/.V_X U/.V_X P/V_X P/V_X P/V_N P/V_N Llano PU UE Llano PU UE VSS_ T VSS_ R VSS_ R VSS_ R VSS_ R VSS_ P VSS_ P VSS_ P VSS_ N VSS_ N VSS_ N VSS_ N VSS_ M VSS_ M VSS_ M VSS_ L VSS_ L VSS_ L VSS_ K VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ F VSS_ F VSS_ F VSS_ F VSS_ F VSS_ F VSS_ F VSS_ F VSS_ F VSS_ F VSS_ E VSS_ E VSS_ E VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ H VSS_ H VSS_ H VSS_ H VSS_ H VSS_ H VSS_ H VSS_ H VSS_ H VSS_ G VSS_ F VSS_ F VSS_ F VSS_ F VSS_ F VSS_ F VSS_ F VSS_ F VSS_ F VSS_ F VSS_ F VSS_ F VSS_ E VSS_ E VSS_ E VSS_ E VSS_ E VSS_ E VSS_ E VSS_ E VSS_ E VSS_ E VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ Y VSS_ Y VSS_ W VSS_ W VSS_ W VSS_ W VSS_ W VSS_ W VSS_ W VSS_ V VSS_ V VSS_ V VSS_ U VSS_ U VSS_ U VSS_ U VSS_ T VSS_ T.U/.V_X.U/.V_X U/.V_X U/.V_X.U/.V_X.U/.V_X.U/.V_X.U/.V_X.U/.V_X.U/.V_X P/V_N P/V_N R *SHORT_ R *SHORT_.U/.V_X.U/.V_X P/V_N P/V_N.U/.V_X.U/.V_X.U/V_X.U/V_X P/V_X P/V_X.U/.V_X.U/.V_X P/V_X P/V_X P/V_N P/V_N.U/.V_X.U/.V_X.U/.V_X.U/.V_X.U/.V_X.U/.V_X.U/.V_X.U/.V_X U/.V_X U/.V_X U/.V_X U/.V_X U/.V_X U/.V_X.U/.V_X.U/.V_X P/V_N P/V_N R *SHORT_ R *SHORT_.U/.V_X.U/.V_X P/V_N P/V_N Llano PU U Llano PU U V_ F V_ E VR_ G VR_ G VR_ G VR_ G VP G VP G VP G VP G VIO_ P VIO_ P VIO_ P VIO_ N VIO_ N VIO_ N VIO_ M VIO_ M VIO_ M VIO_ L VIO_ L VIO_ L VIO_ K VIO_ K VIO_ K VIO_ J VIO_ H VIO_ G VN_ K VN_ K VN_ J VN_ J VN_ J VN_ J VN_ J VN_ J V_ T V_ R V_ R V_ R V_ P V_ P V_ P V_ P V_ N V_ N V_ N V_ M V_ M V_ M V_ M V_ L V_ L V_ L V_ K V_ K V_ J V_ H V_ H V_ H V_ G V_ F V_ F V_ F V_ E V_ V_ V_ VR_ VR_ VR_ VR_ VP VP VP VP VIO_ VIO_ Y VIO_ Y VIO_ W VIO_ W VIO_ W VIO_ V VIO_ V VIO_ V VIO_ U VIO_ U VIO_ U VIO_ T VIO_ T VIO_ T VIO_ R VIO_ R VIO_ R VN_ L VN_ K VN_ K VN_ K VN_ K VN_ K VN_ K VN_ K V_ E V_ V_ V_ V_ V_ V_ V_ Y V_ Y V_ Y V_ Y V_ Y V_ Y V_ Y V_ Y V_ W V_ W V_ W V_ W V_ W V_ W V_ V V_ V V_ V V_ V V_ U V_ U V_ U V_ T V_ T V_ T *P/V_N *P/V_N *P/V_N *P/V_N P/V_X P/V_X P/V_N P/V_N.U/.V_X.U/.V_X.U/.V_X.U/.V_X P/V_N P/V_N.U/.V_X.U/.V_X U/.V_X U/.V_X U/.V_X U/.V_X

9 VI Override ircuit +V +.V_RUN +.V_RUN +.V_SUS +.V_RUN R *_ R K_ R K_ R *K_ R *K_ R *K_ R *K_ R *.K_ SV SV, PU_PWRG SV SV PU_PWRG R R R *SHORT_ *SHORT_ *SHORT_ PU_SV PU_SV PU_PWRG_SVI_REG PU_SV PU_SV PU_PWRG_SVI_REG R *_ R *_ R *_ *.U/V_X HT+ onnector ebug only +.V_SUS J PU_TRST# PU_TRST# R R R R *EUG@_ *EUG@K_ *EUG@K_ *EUG@K_ PU_VIO GN GN GN PU_TRST_L PU_RY PU_RY PU_RY GN PU_VIO PU_TK PU_TK PU_TMS PU_TMS PU_TI PU_TI PU_TO PU_TO PU_PWROK_UF PU_PWROK_UF PU_RST_L_UF PU_RST_L_UF PU_RY PU_RY PU_REQ# PU_REQ_L R *EUG@_ PU_PLLTEST R *EUG@_ PU_PLLTEST PU_TEST_PLLTEST PU_TEST_PLLTEST PU_TK PU_TMS PU_TI PU_TO PU_PWROK_UF PU_RST_L_UF PU_RY PU_REQ# PU_TEST_PLLTEST PU_TEST_PLLTEST *EUG@HT+ HEER bios.ru Quanta omputer Inc. PROJET : LF_LF Size ocument Number Rev Llano EUG&OTHER ate: Tuesday, pril, Sheet of

10 R _ +V_S N,no install by default O_PRSNT# Note:LL#, WKE# and PWR_TN need pull up to +VPU only if S+ mode is supported,,, +V_S +V_S +VPU RSMRST_GTE# IN +V +V_S +V R R R R *_ R R R R R R R R R R R R *.K_ *.K_ *.K_.K_.K_.K_.K_ *.K_ *.K_ *K_.K_.K_ K_ K_ K_ R _ FH_TEST FH_TEST FH_TEST +V_S R SM_RUN_LK SM_RUN_T SM_LN_LK SM_LN_T VG_P PIE_WKE#_R PWR_TN# remove pull hi ( chip internal have pull hi ) PU_THERMTRIP# GEVENT# US_S_O# US_NORML_O# GEVENT# O_PRSNT# R R *K/F_ *_ +VPU K_ PQ *NK_M.U/.V_X,, +VPU PU_THERMTRIP# _PRESENT O_PRSNT# US_S_O# US_NORML_O# R *K/F_ PQ *NK_M R _PRES O_M# PU_THERMTRIP# VG_P for power control *SHORT PRES O_PRSNT# US_S_O# FH_JTG_TO US_NORML_O# RSMRST# T T T, SLP_S# SLP_S# NSWON#, FH_PWRG PEEP,, SM_RUN_LK,, SM_RUN_T SM_LN_LK SM_LN_T T FH_PIE_WLN_LKREQ# PU_MEMHOT# E_GTE E_KRST# E_EXT_SI# LPP# PIE_WKE# T FH_PIE_G_LKREQ# FH_PIE_LN_LKREQ# OR_I OR_I TRVIS_EN# T VG_P SPI_HOL# FH_PIE_PEG_LKREQ# R R R R R +V FH_LINK T *_ T H audio interface is +V_S voltage G *SHORT_P PQ G P/V_N +V_S +V_S *NE *_ +V *_ *SHORT_ *SHORT_ R R K_ *SHORT_ P *K_ +V SYS_RST# KSO_ R *K_ T T T R R T T R VG_P R R R R R R GEVENT# RSMRST# *SHORT_ SM_RUN_LK SM_RUN_T SM_LN_LK SM_LN_T FH_JTG_TK FH_JTG_TI FH_JTG_RST# SLP_S# SLP_S# PWR_TN# FH_PWRG FH_TEST T FH_TEST T FH_TEST V E_GTE R *SHORT_E E_KRST# R *SHORT_G E_EXT_SI# R T SYS_RST# U R *SHORT_ PIE_WKE#_R K V R *SHORT_ FH_THERMTRIP# R R K/F_ W_PWRG F OR_I OR_I *_ R R *SHORT_ GEVENT# GEVENT# *K/F_ *K/F_ *K/F_ *K/F_ *K/F_ *_ *SHORT_ R *SHORT_ R *SHORT_ T T T T T T T T T T T T T T T T T *_ GEVENT# GEVENT# GEVENT# Z_LK_R Z_SOUT_R Z_SIN Z_SIN Z_SIN_R Z_SIN_R Z_SYN_R Z_RST#_R T T KSO_ KSO_ KSO_ KSO_ KSO_ KSO_ KSO_ KSO_ KSO_ KSO_ KSO_ KSO_ KSO_ KSO_ KSO_ KSO_ KSO_ KSO_ Provided test points from checklist R W T W J N U G E E F H G F T R G G J G V W Y V F M R T P F P J T Y Y Y E K J J F E F E J H G K U PIE_RST#/GEVENT# RI#/GEVENT# SPI_S#/GE_STT/GEVENT# SLP_S# SLP_S# PWR_TN# PWR_GOO RSMRST# Z_ITLK Z_SOUT Z_SIN/GPIO Z_SIN/GPIO Z_SIN/GPIO Z_SIN/GPIO Z_SYN Z_RST# PSK_T/GPIO PSK_LK/GPIO PSM_T/GPIO PSM_LK/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/X/GPIO KSO_/X/GPIO KSO_/X/GPIO KSO_/X/GPIO Hudson-M HUSON-M Part of TEST TEST/TMS TEST GIN/GEVENT# KRST#/GEVENT# PME#/GEVENT# LP_SMI#/GEVENT# LP_P#/GEVENT# SYS_RESET#/GEVENT# WKE#/GEVENT# IR_RX/GEVENT# THRMTRIP#/SMLERT#/GEVENT# W_PWRG LK_REQ#/ST_IS#/GPIO LK_REQ#/ST_IS#/GPIO SMRTVOLT/ST_IS#/GPIO LK_REQ#/ST_IS#/GPIO ST_IS#/FNOUT/GPIO ST_IS#/FNIN/GPIO SPKR/GPIO SL/GPIO S/GPIO SL/GPIO S/GPIO LK_REQ#/FNIN/GPIO LK_REQ#/FNOUT/GPIO IR_LE#/LL#/GPIO SMRTVOLT/SHUTOWN#/GPIO R_RST#/GEVENT#/VG_P GE_LE/GPIO SPI_HOL#/GE_LE/GEVENT# GE_LE/GEVENT# GE_STT/GEVENT# LK_REQG#/GPIO/OSIN/ILEEXIT# H UIO PS_T/S/GPIO PS_LK/E/SL/GPIO SPI_S#/GE_STT/GPIO EMEE TRL PI / WKE UP EVENTS LINK/US_O#/GEVENT# US_O#/IR_TX/GEVENT# US_O#/IR_TX/GEVENT# US_O#/IR_RX/GEVENT# US_O#/_PRES/TO/GEVENT# US_O#/TK/GEVENT# US_O#/TI/GEVENT# US_O#/SPI_TPM_S#/TRST#/GEVENT# GPIO US O USLK/M_M_M_OS US MIS US. US. US. US_ROMP US_FSP/GPIO US_FSN US_FSP/GPIO US_FSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN USSS_LRP USSS_LRN US_SS_TXP US_SS_TXN US_SS_RXP US_SS_RXN US_SS_TXP US_SS_TXN US_SS_RXP US_SS_RXN US_SS_TXP US_SS_TXN US_SS_RXP US_SS_RXN US_SS_TXP US_SS_TXN US_SS_RXP US_SS_RXN SL/GPIO S/GPIO SL_LV/GPIO S_LV/GPIO E_PWM/E_TIMER/GPIO E_PWM/E_TIMER/GPIO E_PWM/E_TIMER/WOL_EN/GPIO E_PWM/E_TIMER/GPIO KSI_/GPIO KSI_/GPIO KSI_/GPIO KSI_/GPIO KSI_/GPIO KSI_/GPIO KSI_/GPIO KSI_/GPIO G H H H H H G K J G F K K E F H G F E E E E F F G H G J H J K H G G G E H J H K K F F E F US_ROMP_S USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USSS_LRP USSS_LRN US_TXP US_TXN US_RXP US_RXN SM_E_LK SM_E_T SM_LV_LK SM_LV_T E_PWM R R R R US_US_SW_FH US_US_SW_FH R U@_ U@_ U@_ U@_ R R R R T T T T T T.K/F_ T T T T USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- T T USP+ USP- T T USP+ USP- R R US_TXP US_TXN US_RXP US_RXN *_ *_ E_PWM Note: US P/N pairs with trace lengths up to " US_S& US_S&# Reserve US./. option G SIM ard WLN on LVS ard Reader US_S& US_S&# US. x U@K/F_ U@K/F_ SM_LV_LK SM_LV_T *_ *_ TO US daughter board TO US daughter board US. x MLK, MT, US_US_SW, US_US_SW, +FH_V SSUS_S HU HU HU SYS_RST# Z_SOUT_R Z_SYN_R Z_LK_R Z_RST#_R Z_SIN +V_S R *EUG@K_ To zalia R _ R _ R _ R _ SW *EUG@MSK:NTQ-G-T *EUG@VPORT K-V *P/V_N Z_SOUT Z_SYN Z_ITLK Z_RST# Z_SIN Quanta omputer Inc. PROJET : LF_LF Size ocument Number Rev Hudson-M GPIO/US/Z/RGMII Tuesday, pril, ate: Sheet of bios.ru

11 ,,, PU_PIE_RST# PU_PIE_RST# P/V_N UMI_RXP UMI_RXN UMI_RXP UMI_RXN UMI_RXP UMI_RXN UMI_RXP UMI_RXN UMI_TXP UMI_TXN UMI_TXP UMI_TXN UMI_TXP UMI_TXN UMI_TXP UMI_TXN Note: LK_FH_SRP/N is MHZ SS Note: LK_P_NSSP/N is MHZ non-ss Note: LK_PIE_TRVISP/N is MHZ non-ss Note: LK_PU_HLKP/N is MHZ SS Note: LK_PIE_VGP/N is MHZ SS UMI_RXP UMI_RXN UMI_RXP UMI_RXN UMI_RXP UMI_RXN UMI_RXP UMI_RXN Note: GPP_LK(:)P/N is MHZ SS capable, LK_P_NSSP LK_P_NSSN LK_PIE_TRVISP LK_PIE_TRVISN LK_PU_HLKP LK_PU_HLKN LK_PIE_VGP LK_PIE_VGN LK_PIE_WLNP LK_PIE_WLNN LK_PIE_LNP LK_PIE_LNN LK_PIE_G LK_PIE_G# R _ PLTRST# +.V_PIE_VR P/V_N +.V_KV RP RP RP RP RP RP RP PIE_RST#_R R _ R R TP TP TP TP.U/V_X.U/V_X.U/V_X.U/V_X.U/V_X.U/V_X.U/V_X.U/V_X R /F_ K/F_ *SHORT_X *SHORT_X *SHORT_X _RST# E UMI_RXP_ UMI_RXN_ UMI_RXP_ UMI_RXN_ UMI_RXP_ UMI_RXN_ UMI_RXP_ UMI_RXN_ INT_LK_FH_SRP INT_LK_FH_SRN INT_LK_P_NSSP INT_LK_P_NSSN INT_LK_PIE_TRVISP INT_LK_PIE_TRVISN INT_LK_PU_HLKP INT_LK_PU_HLKN *IS@SHORT_X INT_LK_PIE_VGP INT_LK_PIE_VGN *SHORT_X *SHORT_X K/F_ INT_LK_PIE_WLNP INT_LK_PIE_WLNN INT_LK_PIE_LNP INT_LK_PIE_LNN *G@SHORT_XINT_LK_PIE_G INT_LK_PIE_G# E E E Y Y Y Y F F V V W W W V V W W W F G G R T H H T T J K H H J K F F E E M M M M N N UE PIE_RST# _RST# UMI_TXP UMI_TXN UMI_TXP UMI_TXN UMI_TXP UMI_TXN UMI_TXP UMI_TXN UMI_RXP UMI_RXN UMI_RXP UMI_RXN UMI_RXP UMI_RXN UMI_RXP UMI_RXN PIE_LRP PIE_LRN GPP_TXP GPP_TXN GPP_TXP GPP_TXN GPP_TXP GPP_TXN GPP_TXP GPP_TXN GPP_RXP GPP_RXN GPP_RXP GPP_RXN GPP_RXP GPP_RXN GPP_RXP GPP_RXN LK_LRN PIE_RLKP PIE_RLKN ISP_LKP ISP_LKN ISP_LKP ISP_LKN PU_LKP PU_LKN SLT_GFX_LKP SLT_GFX_LKN GPP_LKP GPP_LKN GPP_LKP GPP_LKN GPP_LKP GPP_LKN GPP_LKP GPP_LKN GPP_LKP GPP_LKN GPP_LKP GPP_LKN GPP_LKP GPP_LKN HUSON-M PI EXPRESS INTERFES Part of LOK GENERTOR PI LKS PILK PILK/GPO PILK/GPO PILK/GPO PILK/M_OS/GPO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO E# E# E# E# FRME# EVSEL# IRY# TRY# PR STOP# PERR# SERR# REQ# REQ#/GPIO REQ#/LK_REQ#/GPIO REQ#/LK_REQ#/GPIO GNT# GNT#/GPO GNT#/S_LE/GPO GNT#/LK_REQ#/GPIO LKRUN# LOK# PI INTERFE LPLK LPLK L L L L LFRME# LRQ# LRQ#/LK_REQ#/GPIO SERIRQ/GPIO LP PIRST# INTE#/GPIO INTF#/GPIO INTG#/GPIO INTH#/GPIO F F F G F PI_LK PI_LK_R PI_LK PI_LK_R PI_LK_R *SHORT_ PI_LK PI_LK PI_LK J L T G T L T H T J T L T N T N T RT ircuitry(rt) J T L T L T +V_RT M T J T K T MIL R /F_ N T G T M T J T L T +V +V K T U/V_X N T R *SHORT_ PIE_RST#_TRVIS G T R R E T PI_ PI_ *.K_ *.K_ PI_ PI_ E PI_ PI_ F PI_ PI_ H PI_ PI_ Q H dgpu_pwrok R *IS@SHORT_ *MMT--F_M +VGPU_ORE_PG,,, HUSON_MEMHOT#_R R *_ HUSON_MEMHOT# E T R N T J T N T T G T K T R L T F T E T +V +V H T M T H T G T G T R F T R *IS@K_ M T *IS@K_ PX. fixed mode with O T T PE_GPIO PE_GPIO PE_GPIO PE_GPIO,, K T LKRUN# LKRUN# H T F E E E INTE# INTF# INTG# INTH# T T T T T LP_LK_R LP_LK_R L L L L LFRME# LRQ# LRQ# SERIRQ R R R *SHORT_ *SHORT_ R NMP@_ R _ R _ R _ LP_LK LP_LK T PI_LK T PI_LK PI_LK LP_LK LP_LK L, L, L, L, LFRME#, LRQ# T SERIRQ, PLK_EUG PLK_ PLK_EUG PLK_ *P/V_ *P/V_ +VRT MIL SMK--F_M R SMK--F_M PU_STOP# MIL R K/F_ MIL +T +VRT_ +.V_RUN *SHORT_ R *K_ N +VPU -T--K +.V_SUS FOR HIPSET UTOMTION R *K/F_ R E *K_ P/V_ LK_M_R ard Reader LK_M_R P/V_N Y MHZ_ P/V_N TP TP R M/F_ R LK_PIE_USP_R LK_PIE_USN_R R _ *SHORT_ LK_M_R_R M_X M_X R R N R J GPP_LKP GPP_LKN GPP_LKP GPP_LKN M_M_M_OS M_X M_X Hudson-M PU S PLUS M_TIVE# PROHOT# PU_PG LT_STP# PU_RST# K_X K_X S_ORE_EN RTLK INTRUER_LERT# VT_RT_G G E E G F G G H F F E MTIVE_L PU_PROHOT#_VIO PU_PWRG_R R PU_STOP# PU_RST# K_X K_X S_ORE_EN RT_LK INTRUER_LERT# +V_RT MIL *SHORT_ G *SHORT_ P PU_PWRG.U/V_X *.U/V_X +V_RT T MTIVE_L PU_PROHOT#_VIO, PU_PWRG, +V_RT PU_RST# S_ORE_EN RT_LK, R *M/F_ INTRUER_LERT# Left not connected (FH has -kohm internal pull-up to VT). S_ORE_EN is necessary to connect enable pin of +VPU/+VPU regulator for S+ mode implementation K_X R M_ K_X Y.KHZ_ USE GROUN GUR FOR K_X N K_X Quanta omputer Inc. PROJET : LF_LF Size ocument Number Rev Hudson-M PI/PI/LOK P/V_ P/V_ Tuesday, pril, ate: Sheet of bios.ru

12 ST H/SS ST O ST_TXP ST_TXN ST_RXN ST_RXP ST_TXP ST_TXN ST_RXN ST_RXP PLE ST OUPLING PS LOSE TO HUSON-M/M.U/V_X.U/V_X.U/V_X.U/V_X PLE ST_L RES VERY LOSE TO LL OF HUSON-M/M ST_TXP_ ST_TXN_ ST_TXP_ ST_TXN_ K M L N N L H J J H M K H J N L L N J H N L K M L N L L H H U ST_TXP ST_TXN ST_RXN ST_RXP ST_TXP ST_TXN ST_RXN ST_RXP ST_TXP ST_TXN ST_RXN ST_RXP ST_TXP ST_TXN ST_RXN ST_RXP ST_TXP ST_TXN ST_RXN ST_RXP ST_TXP ST_TXN ST_RXN ST_RXP N N N N N N HUSON-M SERIL T S R SPI ROM GE LN Part of S_LK/SLK_/GPIO S_M/SLO_/GPIO S_#/GPIO S_WP/GPIO S_T/STI_/GPIO S_T/STO_/GPIO S_T/GPIO S_T/GPIO GE_OL GE_RS GE_MK GE_MIO GE_RXLK GE_RX GE_RX GE_RX GE_RX GE_RXTL/RXV GE_RXERR GE_TXLK GE_TX GE_TX GE_TX GE_TX GE_TXTL/TXEN GE_PHY_P GE_PHY_RST# GE_PHY_INTR SPI_I/GPIO SPI_O/GPIO SPI_LK/GPIO SPI_S#/GPIO ROM_RST#/SPI_WP#/GPIO VG_RE VG_GREEN VG_LUE L N J H K M H J W H F E G F G E W V V V T V L L M GE_OL GE_RS GE_MIO GE_RXERR GE_PHY_INTR FH_SPI_SI FH_SPI_SO FH_SPI_LK FH_SPI_S# FH_SPI_WP FH_RT_RE FH_RT_GRE FH_RT_LU R R R R R K_ K_ K_ K_ K_ T +V_S +V_S FH_SPI_S# FH_SPI_LK FH_SPI_SO FH_SPI_SI +V_S FH_RT_RE FH_RT_GRE FH_RT_LU R R R R *_ *_ *_ *.K_ WQVSSIG: KEFPN +V_S Socket: G FH_SPI_LK_R FH_SPI_SO_R FH_SPI_SI_R *P/V_N FH_SPI_WP R place close to PH FH_RT_RE FH_RT_GRE FH_RT_LU R R R U E# SK SI SO WP# /F_ V HOL# *WQVSSIG /F_ /F_ VSS R *K_ *.U/V_X FH_T FH_LK FH_O_EN SPI_HOL# R R R *.K_ *.K_ *.K_ +V +V +.V_V_ST R /F_ ST_LE# R K/F_ ST_LE# ST_LRP ST_LRN J J F F N N ST_LRP ST_LRN ST_T#/GPIO VG VG_HSYN/GPO VG_VSYN/GPO VG S/GPO VG SL/GPO VG RSET UX_VG_H_P UX_VG_H_N M N M N K V V R /F_ FH_RT_HSYN FH_RT_VSYN FH_T FH_LK PU_P_UXP PU_P_UXN +.V_SUS R *K/F_ +.V_VPR R *K/F_ FH_PROHOT# Q *MMT--F_M FH_PROHOT# +V R *K/F_ +V R *K/F_ FH_O_EN Integrated lock Mode: Leave unconnected. Remove Zero Power O funciton OR_I FH_O_EN FH_PROHOT#_ OR_I OR_I OR_I OR_I OR_I OR_I TEMPIN R K_ F G H M J K N L K K K M ST_X ST_X FNOUT/GPIO FNOUT/GPIO FNOUT/GPIO FNIN/GPIO FNIN/GPIO FNIN/GPIO TEMPIN/GPIO TEMPIN/GPIO TEMPIN/GPIO TEMPIN/TLERT#/GPIO Hudson-M HW MONITOR VG MINLINK UXL ML_VG_LP ML_VG_LN ML_VG_LP ML_VG_LN ML_VG_LP ML_VG_LN ML_VG_LP ML_VG_LN ML_VG_HP/GPIO VIN/GPIO VIN/GPIO VIN/STI_/GPIO VIN/STO_/GPIO VIN/SLO_/GPIO VIN/SLK_/GPIO VIN/GE_STT/GPIO VIN/GE_LE/GPIO N N N N N U T T T T R R P P N M L N P P M M G H G L FH_VG_HP VIN VIN VIN MEM_PV MEM_PV VIN_VIO VIN_VR VIN R R R R R OR I SETTING oard I I UM SKU H VG SKU L W/ M W/O M FH-M FH-M W/O G W/ G " " W/O T W/ T Reserve Reserve Reserve /F_ K_ K_ K_ K_ MEM_PV MEM_PV I H L +FH_VN ML I H L I L H PU_P_TXP PU_P_TXN PU_P_TXP PU_P_TXN PU_P_TXP PU_P_TXN PU_P_TXP PU_P_TXN I H L I L H +V I X R *K/F_ I X +V_S I X R *K/F_ FH_VG_HP +V_S +V OR_I OR_I R R R R R R R R R VIN_VIO R *K/F_ UM@K_ K_ M@K_ *K_ *K_ *K_ K_ K_ *K_ OR_I OR_I OR_I OR_I OR_I OR_I OR_I OR_I OR_I OR_I OR_I *.U/V_X VIN_VR R R R R R R R R R R *K/F_ IS@K_ *K_ M@_ K_ *K_ *K_ *K_ *K_ *K_ *.U/V_X Quanta omputer Inc. PROJET : LF_LF Size ocument Number Rev Hudson-M ST/HWM/SPI Tuesday, pril, ate: Sheet of bios.ru

13 bios.ru m m m m KV_.V-- Internal clock Generator I/O power m m V-- S/ ORE power m PIE_VR--PIE I/O power V_ST--ST phy power m m S_.--.v standby power m S_.V--.V standby power m m PLE LL THE EOUPLING PS ON THIS SHEET LOSE TO S S POSSILE. Trace width >= mil TRE WITH >=mil m m TRE WITH >=mil TRE WITH >=mil TRE WITH >=mil TRE WITH >=mil m TRE WITH >=mil TRE WITH >=mil TRE WITH >=mil TRE WITH >=mil TRE WITH >=mil TRE WITH >=mil m m VQ--.V I/O power m m m m m m m m Max m Max m m EMI S plus mode +VXL_.V +VR_.V +FH_VPL PIE +FH_VPL ST +FH_VN US_S +FH_VR US_S +FH_VN SSUS_S_R +FH_VR SSUS_S +FH_VN VG_P +FH_VN ML VG_P +VPL_.V +FH_VPL ML +FH_VN R +FH_VPL SSUS_S +FH_VPL SUS_S +V +V +.V_V_FH_R +.V +.V +.V_KV +.V_PIE_VR +.V +.V +.V_V_ST +VIO_Z +VN_.V_HWM +VPL_.V +.V_UL +V_S +.V_SUS +FH_VN ML +V_S +V_V_US +.V_UL +.V_UL +.V_UL +FH_V SSUS_S +VPL_.V +.V_UL +VIO_Z +VIN +FH_VN R +V +.V +FH_VN ML +FH_VPL ML +V +FH_VN R +V_S +FH_VPL SSUS_S +V_V_US +FH_VPL SUS_S +VN_.V_HWM +V_S +FH_VN +V_S +VPL_.V +V +.V_FH_R +V +VPU +V_S +.V Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : Hudson-M POWER/GN Tuesday, pril, LF_LF Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : Hudson-M POWER/GN Tuesday, pril, LF_LF Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : Hudson-M POWER/GN Tuesday, pril, LF_LF.U/V_X.U/V_X R *M_ R *M_ U/V_X U/V_X.U/.V_X.U/.V_X U/V_X U/V_X L *PYT-Y-N_ L *PYT-Y-N_.U/V_X.U/V_X *.U/.V_X *.U/.V_X L PYT-Y-N_ L PYT-Y-N_.U/V_X.U/V_X R *SHORT_ R *SHORT_ Part of GROUN HUSON-M Hudson-M U Part of GROUN HUSON-M Hudson-M U VSSPL_SYS H VSSXL K VSSN_HWM N VSS_ T VSS_ T VSS_ T VSS_ R VSS_ R VSS_ R VSS_ R VSS_ P VSS_ P VSS_ P VSS_ P VSS_ P VSS_ P VSS_ N VSS_ N VSS_ N VSS_ N VSS_ N VSS_ M VSS_ M VSS_ M VSS_ M VSS_ L VSS_ L VSS_ L VSS_ L VSS_ L VSS_ L VSS_ K VSS_ K VSS_ K VSS_ K VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ H VSS_ H VSS_ H VSS_ G VSS_ G VSS_ G VSS_ F VSS_ F VSS_ F VSS_ F VSS_ F VSS_ F VSS_ F VSS_ F VSS_ F VSS_ F VSS_ E VSS_ E VSS_ E VSS_ E VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ EFUSE R VSSIO_ N VSSNQ_ K VSSN_ L VSSPL_ T VSS_ N VSS_ N VSS_ N VSS_ N VSS_ M VSS_ M VSS_ L VSS_ K VSS_ K VSS_ J VSS_ J VSS_ J VSS_ H VSS_ H VSS_ H VSS_ H VSS_ H VSS_ H VSS_ H VSS_ H VSS_ G VSS_ G VSS_ F VSS_ F VSS_ F VSS_ F VSS_ E VSS_ E VSS_ E VSS_ E VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ Y VSS_ Y VSS_ Y VSS_ W VSS_ W VSS_ W VSS_ W VSS_ V VSS_ V VSS_ V VSS_ U VSS_ U VSS_ U VSS_ U VSS_ U VSS_ U VSS_ U VSS_ T VSS_ T US MIN LINK GE LN LKGEN I/O US SS SERIL T PI EXPRESS.V_S I/O ORE S PI/GPIO I/O POWER HUSON-M Part of Hudson-M U US MIN LINK GE LN LKGEN I/O US SS SERIL T PI EXPRESS.V_S I/O ORE S PI/GPIO I/O POWER HUSON-M Part of Hudson-M U VR SSUS_S_ M VR SSUS_S_ P VR SSUS_S_ N VR SSUS_S_ N VN SSUS_S_ P VN SSUS_S_ P VN SSUS_S_ N VN SSUS_S_ M VN SSUS_S_ P VR US_S_ T VR US_S_ T VN US_S_ U VN US_S_ U VN US_S_ M VN US_S_ N VN US_S_ M VN US_S_ N VN US_S_ N VN US_S_ M VN US_S_ M VN US_S_ K VN US_S_ K VN US_S_ J VN US_S_ H VN US_S_ G VIO_GE_S_ VIO_GE_S_ VR GE_S_ VR GE_S_ VIO GE_S VN ML_ V VN ML_ V VN ML_ V VN ML_ Y VPL V LO_P M VPL ST G VPL PIE H VPL US_S VPL SSUS_S L VN T VPL ML U VPL V VPL SYS H VIO PIGP_ VIO PIGP_ VIO PIGP_ VIO PIGP_ VIO PIGP_ VIO PIGP_ G VIO PIGP_ VIO PIGP_ E VIO PIGP_ VIO PIGP_ VIO_Z_S VN HWM_S M VPL SYS_S J VR S_ M VR S_ N VXL S G VIO S_ W VIO S_ Y VIO S_ Y VIO S_ V VIO S_ V VIO S_ M VIO S_ L VIO S_ N VN ST_ VN ST_ VN ST_ VN ST_ VN ST_ VN ST_ VN ST_ VN ST_ VN ST_ Y VN ST_ VN PIE_ G VN PIE_ F VN PIE_ VN PIE_ VN PIE_ VN PIE_ E VN PIE_ Y VN PIE_ VN LK_ P VN LK_ N VN LK_ N VN LK_ M VN LK_ L VN LK_ K VN LK_ J VN LK_ H VR Y VR V VR V VR V VR U VR U VR T VR T VR T L U@PYT-Y-N_ L U@PYT-Y-N_ U/V_X U/V_X.U/V_X.U/V_X.U/.V_X.U/.V_X L *PYT-Y-N_ L *PYT-Y-N_ U/V_X U/V_X L PYT-Y-N_ L PYT-Y-N_.U/.V_X.U/.V_X R *SHORT_ R *SHORT_.U/.V_X.U/.V_X U@U/V_X U@U/V_X PQ *N_M PQ *N_M.U/V_X.U/V_X U/V_X U/V_X U@.U/V_X U@.U/V_X *.U/V_X *.U/V_X U/V_X U/V_X U/.V_X U/.V_X U@.U/V_X U@.U/V_X U/V_X U/V_X R *SHORT_ R *SHORT_ L HKF-T_. L HKF-T_..U/.V_X.U/.V_X PR *K/F_ PR *K/F_ U@.U/V_X U@.U/V_X U/V_X U/V_X.U/V_X.U/V_X.U/.V_X.U/.V_X U/.V_X U/.V_X L PYT-Y-N_ L PYT-Y-N_ *.U/V_X *.U/V_X U/V_X U/V_X.U/V_X.U/V_X U/V_X U/V_X PQ *N_M PQ *N_M L PYT-Y-N_ L PYT-Y-N_.U/V_X.U/V_X *U/V_X *U/V_X.U/.V_X.U/.V_X L HKF-T_. L HKF-T_. R *SHORT_ R *SHORT_.U/V_X.U/V_X *.U/V_X *.U/V_X R *_ R *_.U/.V_X.U/.V_X U/.V_X U/.V_X R *SHORT_ R *SHORT_.U/V_X.U/V_X U/V_X U/V_X U/.V_X U/.V_X.U/V_X.U/V_X *.U/V_X *.U/V_X U/V_X U/V_X.U/.V_X.U/.V_X U/V_X U/V_X U/V_X U/V_X PQ *N_M PQ *N_M U/V_X U/V_X U@U/V_X U@U/V_X R *SHORT_ R *SHORT_ U/.V_X U/.V_X.U/V_X.U/V_X.U/V_X.U/V_X L PYT-Y-N_ L PYT-Y-N_ R *SHORT_ R *SHORT_ U/V_X U/V_X U/V_X U/V_X.U/.V_X.U/.V_X U/V_X U/V_X.U/.V_X.U/.V_X U/.V_X U/.V_X R *SHORT_ R *SHORT_ R U@_ R U@_.U/.V_X.U/.V_X L HKF-T_. L HKF-T_. L *PYT-Y-N_ L *PYT-Y-N_.U/V_X.U/V_X U/V_X U/V_X L PYT-Y-N_ L PYT-Y-N_ U/V_X U/V_X.U/.V_X.U/.V_X *.U/V_X *.U/V_X L PYT-Y-N_ L PYT-Y-N_ R U@_ R U@_ U/.V_X U/.V_X.U/V_X.U/V_X.U/V_X.U/V_X.U/V_X.U/V_X R *_ R *_.U/.V_X.U/.V_X U@.U/V_X U@.U/V_X U@U/V_X U@U/V_X U/V_X U/V_X.U/V_X.U/V_X U/V_X U/V_X L PYT-Y-N_ L PYT-Y-N_ U/V_X U/V_X U/V_X U/V_X L U@PYT-Y-N_ L U@PYT-Y-N_ U@.U/.V_X U@.U/.V_X U/V_X U/V_X R U@_ R U@_ R *SHORT_ R *SHORT_ *.U/V_X *.U/V_X.U/.V_X.U/.V_X R *SHORT_ R *SHORT_ U/.V_X U/.V_X.U/V_X.U/V_X.U/.V_X.U/.V_X L PYT-Y-N_ L PYT-Y-N_.U/V_X.U/V_X R *SHORT_ R *SHORT_ L PYT-Y-N_ L PYT-Y-N_ *U/V_X *U/V_X U@.U/V_X U@.U/V_X U/V_X U/V_X.U/.V_X.U/.V_X L PYT-Y-N_ L PYT-Y-N_.U/.V_X.U/.V_X L PYT-Y-N_ L PYT-Y-N_ L PYT-Y-N_ L PYT-Y-N_ U/.V_X U/.V_X U/V_X U/V_X R.K_ R.K_ U@U/.V_X U@U/.V_X R *SHORT_ R *SHORT_

14 STRPS PINS OVERLP OMMON PS WHERE POSSILE FOR UL-OP RESISTORS. +V +V +V +V_S +V_S +V_S +V_S R K_ R *K_ R *K_ R *K_ R K_ R *K_ R K_ PI_LK PI_LK PI_LK PI_LK LP_LK LP_LK E_PWM, RT_LK PI_LK PI_LK LP_LK LP_LK E_PWM RT_LK R R R *K_ K_ K_ Remove PI_LK function R K_ R *K_ R *.K_ R *.K_ E_PWM--> SPI ROM:.-KΩ % pull-down LP ROM: Pull-up to.v_s. External pull-up resistor is not required as FH has integrated -KΩ pull-up to.v_s. +V_S +V_S REQUIRE STRPS PULL HIGH PULL LOW EUG STRPS PI_LK LLOW PIE Gen EFULT FORE PIE Gen PI_LK PI_LK USE EUG STRP IGNORE EUG STRP EFULT PI_LK non_fusion LOK MOE FUSION LOK MOE EFULT LP_LK E ENLE E ISLE EFULT LP_LK LKGEN ENLE EFULT LKGEN ISLE E_PWM LP ROM EFULT SPI ROM RT_LK S PLUS MOE ISLE EFULT S PLUS MOE ENLE, VRM_PWRG, +.V_UL_PG, SLP_S# +.V_VPR_PG R K_ SWPT_M R *_ *UPGGW *.U/.V_X *.U/V_X U *T R *SHORT_ *SWPT_M FH_PWRG, FH HS K INTERNL PU FOR PI_[:] MPWROK SWPT_M PI_ PI_ PI_ PI_ FH PWRG KT PI_ PI_ PI_ PI_ PI_ PI_ R *.K_ R *.K_ R *.K_ R *.K_ R *.K_ PI_ PI_ PI_ PI_ PI_ PULL HIGH USE PI PLL ISLE IL UTORUN USE F PLL USE EFULT PIE STRPS ISLE PI MEM OOT EFULT EFULT EFULT EFULT EFULT PULL LOW YPSS PI PLL ENLE IL UTORUN YPSS F PLL USE EEPROM PIE STRPS ENLE PI MEM OOT Quanta omputer Inc. PROJET : LF_LF Size ocument Number Rev Hudson-M STRP/PWRG Tuesday, pril, ate: Sheet of bios.ru

15 bios.ru. R_ST(R) Place these aps near So-imm. EMI Suggestion E E M M M M M M M M M M M M M M M M SM_RUN_LK SM_RUN_T M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSN M QSN M QSN M QSN M QSN M QSN M QSN M QSN M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q IMM_S IMM_S M [:] M S# M S# M LKP M LKN M LKP M LKN M KE M KE M S# M RS# M WE# M QSP[:] M QSN[:] M OT M OT M Q[..] SM_RUN_LK,, SM_RUN_T,, M RST# M EVENT# M M M M M M M M M M M M M M M M M S# M S# M S# +.V_SUS +V +.V_R_VTT +V +.V_SUS +.V_R_VTT +.V_VREF_Q +.V_VREF_ +.V_SUS +.V_VREF_ +.V_VREF_ +.V_VREF_Q +.V_SUS +.V_VREF_Q +.V_SUS +.V_SUS +.V_SUS Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : RIII SO-IMM- Tuesday, pril, LF_LF Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : RIII SO-IMM- Tuesday, pril, LF_LF Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : RIII SO-IMM- Tuesday, pril, LF_LF U/.V_X U/.V_X R *SHORT_ R *SHORT_ U/.V_X U/.V_X *U/.V_X *U/.V_X E P/V_X E P/V_X U/.V_X U/.V_X R *SHORT_ R *SHORT_ R *_ R *_ P/V_X P/V_X R K/F_ R K/F_ *P/V_N *P/V_N P R SRM SO-IMM (P) JIM RRK--TP P R SRM SO-IMM (P) JIM RRK--TP /P /# S# S# K K# K K# KE KE S# RS# WE# S S SL S OT OT M M M M M M M M QS QS QS QS QS QS QS QS QS# QS# QS# QS# QS# QS# QS# QS# Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q P/V_X P/V_X U/V_X U/V_X *P/V_N *P/V_N R *_ R *_ *P/V_N *P/V_N.U/.V_X.U/.V_X + *U/V_P_Eb + *U/V_P_Eb U/.V_X U/.V_X *U/.V_X *U/.V_X.U/V_X.U/V_X U/V_X U/V_X U/.V_X U/.V_X R K_ R K_.U/V_X.U/V_X U/.V_X U/.V_X R K/F_ R K/F_ U/.V_X U/.V_X U/.V_X U/.V_X U/V_X U/V_X U/.V_X U/.V_X P/V_X P/V_X *P/V_N *P/V_N U/.V_X U/.V_X *P/V_N *P/V_N E P/V_X E P/V_X *P/V_N *P/V_N P/V_X P/V_X *P/V_N *P/V_N R K_ R K_ U/.V_X U/.V_X U/V_X U/V_X R K/F_ R K/F_ U/.V_X U/.V_X P R SRM SO-IMM (P) JIM RRK--TP P R SRM SO-IMM (P) JIM RRK--TP V V V V V V V V V V V V V V V V V V VSP N N NTEST EVENT# RESET# VREF_Q VREF_ VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VTT VTT GN GN R K/F_ R K/F_ U/.V_X U/.V_X.U/V_X.U/V_X

16 bios.ru Place these aps near So-imm.. R_RVS(R) EMI Suggestion E M M M M M M M M M M M M M M M M M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSN M QSN M QSN M QSN M QSN M QSN M QSN M QSN M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q IMM_S IMM_S M [:] M S# M S# M S# M S# M S# M LKP M LKN M LKP M LKN M KE M KE M S# M RS# M WE# M QSP[:] M QSN[:] M OT M OT M Q[..] M RST# M EVENT# SM_RUN_LK,, SM_RUN_T,, M M M M M M M M M M M M M M M M +.V_SUS +V +.V_R_VTT +.V_VREF_ +V +.V_SUS +.V_R_VTT +.V_VREF_Q +V +.V_VREF_ +.V_VREF_Q +.V_SUS +.V_SUS +.V_SUS Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : RIII SO-IMM- Tuesday, pril, LF_LF Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : RIII SO-IMM- Tuesday, pril, LF_LF Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : RIII SO-IMM- Tuesday, pril, LF_LF U/.V_X U/.V_X U/V_X U/V_X U/.V_X U/.V_X P R SRM SO-IMM (P) JIM RRK--TP P R SRM SO-IMM (P) JIM RRK--TP /P /# S# S# K K# K K# KE KE S# RS# WE# S S SL S OT OT M M M M M M M M QS QS QS QS QS QS QS QS QS# QS# QS# QS# QS# QS# QS# QS# Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q *P/V_N *P/V_N U/.V_X U/.V_X U/.V_X U/.V_X R K_ R K_ P R SRM SO-IMM (P) JIM RRK--TP P R SRM SO-IMM (P) JIM RRK--TP V V V V V V V V V V V V V V V V V V VSP N N NTEST EVENT# RESET# VREF_Q VREF_ VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VTT VTT GN GN *P/V_N *P/V_N U/V_X U/V_X P/V_X P/V_X U/.V_X U/.V_X U/.V_X U/.V_X U/V_X U/V_X P/V_X P/V_X U/.V_X U/.V_X *P/V_N *P/V_N U/V_X U/V_X U/.V_X U/.V_X *U/.V_X *U/.V_X.U/V_X.U/V_X *P/V_N *P/V_N U/.V_X U/.V_X.U/V_X.U/V_X *U/.V_X *U/.V_X U/.V_X U/.V_X.U/V_X.U/V_X *P/V_N *P/V_N U/.V_X U/.V_X U/.V_X U/.V_X R K_ R K_ R *_ R *_ U/.V_X U/.V_X.U/.V_X.U/.V_X R *_ R *_ *P/V_N *P/V_N

17 U +.V_PE_V UG P E/F POWER G G PEF_V# PEF_V# P / POWER P_V# P_V# E F R *IS@SHORT_ +.V_P_V F E PIE_RXP PIE_RXN PIE_TXP PIE_TXN H G +.V_PE_V G G PEF_V# PEF_V# P_V# P_V# F F +.V_P_V PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN E Y Y W W V V U U T T R R P P N PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PI EXPRESS INTERFE PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN G F F F Y Y Y Y W W V U U U T T T T _PEG_RXP _PEG_RXN _PEG_RXP _PEG_RXN _PEG_RXP _PEG_RXN _PEG_RXP _PEG_RXN _PEG_RXP _PEG_RXN IS@.U/V_X IS@.U/V_X IS@.U/V_X IS@.U/V_X IS@.U/V_X IS@.U/V_X IS@.U/V_X IS@.U/V_X IS@.U/V_X IS@.U/V_X PEG_RXP PEG_RXN PEG_RXP PEG_RXN +.V_PE_V +.V_PE_V F G PEF_V# PEF_V# Reserve to support Future GPU Multi Level SEYMOUR/FutureSI R *IS@SHORT_ F G P_VSSR#/PS_ M P_VSSR# M P_VSSR# M P_VSSR# P_VSSR# +.V_PF_PV PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN +.V_PE_PV R IS@/F_ +.V_PE_PVG F G H P_VSSR# M P_VSSR# M P_VSSR# M P_VSSR# P_VSSR# F G PEF_V# PEF_V# F PEF_LR R *IS@SHORT_ G R *IS@SHORT_ F PEF_V# P_VSSR# P PLL POWER PEF_V# P_V# P_VSSR# P_VSSR# IS@ROSON/SEYMOUR-S P_VSSR# P_VSSR# P_VSSR# P_VSSR# P_VSSR# P_V# P_V# P_V# P_V# P_VSSR# P_VSSR# P_VSSR# P_VSSR# P_VSSR# P_LR P_V# P_VSSR# E E G G H E F F F F G H M M E G G G G R R +.V_P_PV +.V_P_PV +V_GPU *IS@SHORT_ (V@m P_V) IS@HKF-T_. +.V_P_V L +.V_P_PV +.V_P_PV +.V_P_V IS@.U/V_X IS@U/V_X IS@U/.V_X IS@/F_ PEG_TXP PEG_TXN N M PIE_RXP PIE_RXN PIE_TXP PIE_TXN P P _PEG_RXP _PEG_RXN IS@.U/V_X IS@.U/V_X PEG_RXP PEG_RXN +.V_PE_V (V@m PE_V) +.V_P_V (.V@m P_V) PEG_TXP PEG_TXN PEG_TXP PEG_TXN M L L K PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN P P M N _PEG_RXP _PEG_RXN _PEG_RXP _PEG_RXN IS@.U/V_X IS@.U/V_X IS@.U/V_X IS@.U/V_X PEG_RXP PEG_RXN PEG_RXP PEG_RXN +.V_PE_V L IS@HKF-T_. IS@U/V_X IS@.U/V_X IS@U/.V_X +V_GPU +.V_P_V L +.V_GPU IS@HKF-T_. IS@.U/V_X IS@U/V_X IS@U/.V_X LK_PIE_VGP LK_PIE_VGN LK_PIE_VGP LK_PIE_VGN IS@K/F_ R K K N LOK PIE_REFLKP PIE_REFLKN PWRGOO LIRTION PIE_LRP PIE_LRN Y M_PIE_LRP M_PIE_LRN R R IS@.K/F_ IS@K/F_ +V_GPU +.V_PE_V IS@.U/V_X IS@U/V_X +.V_P_PV (.V@m P_PV) (.V@m PE_V) +.V_P_PV L +.V_GPU L +.V_GPU IS@HKF-T_. IS@HKF-T_. IS@.U/V_X IS@U/V_X IS@U/.V_X IS@U/.V_X +V GPU_RST# L PERST IS@ROSON/SEYMOUR-S +.V_PF_PV (.V@m PF_PV) +.V_PF_PV L +.V_GPU IS@HKF-T_. IS@.U/V_X IS@U/V_X IS@U/.V_X +.V_PE_PV (.V@m PE_PV) +.V_PE_PV L +.V_GPU IS@HKF-T_. IS@U/V_X IS@.U/V_X IS@U/.V_X PX. fixed mode with O IS@.U/V_X PE_GPIO,,, PU_PIE_RST# bios.ru R U IS@TSHFU(F) *IS@_ GPU_RST# Quanta omputer Inc. PROJET : LF_LF Size ocument Number Rev ROSON_XT PIE_Interface ate: Tuesday, pril, Sheet of

18 +.V_GPU +.V_GPU +V_GPU T T T T T T T T T Memory I T T RM_STRP RM_STRP RM_STRP RM_STRP RM_STRP IS@HKF-T_ (.V@m P_PV) +.V_P_PV L IS@U/.V_X IS@.U/V_X IS@U/V_X IS@HKF-T_ (.V@m P_V) +.V_P_V L IS@U/.V_X IS@.U/V_X IS@U/V_X IS@HKF-T_ (V@m P_V) +.V_P_V L IS@U/.V_X IS@.U/V_X IS@U/V_X U Y E VLK L VNTL_ N VNTL_ VNTL_ E VT_ VT_ VT_ VT_ VT_ VT_ VT_ VT_ VT_ VT_ Y VT_ Y VT_ VT_ W V P_V# P_VSSR# P_V# P_V# P_V# P_V# U W P_VSSR# U P_VSSR# Y P_VSSR# P_VSSR# P_VSSR# VO P P P TXP_PP F TXM_PN F TXP_PP G TXM_PN G TXP_PP H TXM_PN H TXP_PP K TXM_PN K TXP_PP K TXM_PN M TXP_PP K TXM_PN M TXP_PP J TXM_PN H TXP_PP K TXM_PN L TXP_PP V TXM_PN U TXP_PP W TXM_PN V TXP_PP Y TXM_PN W TXP_PP TXM_PN Y P_LR J HMILK+_ *IS@.U/V_X HMILK-_ *IS@.U/V_X HMITXP_ *IS@.U/V_X HMITXN_ *IS@.U/V_X HMITXP_ *IS@.U/V_X HMITXN_ *IS@.U/V_X HMITXP_ *IS@.U/V_X HMITXN_ *IS@.U/V_X R IS@/F_ EXT_HMILK+ EXT_HMILK- EXT_HMITXP EXT_HMITXN EXT_HMITXP EXT_HMITXN EXT_HMITXP EXT_HMITXN HMI +.V_V_Q (.V@m V) +.V_V_Q L +.V_GPU IS@HKF-T_ IS@.U/V_X IS@U/V_X IS@U/.V_X +.V_V_Q (.V@.m VQ) +.V_V_Q L +.V_GPU *IS@HKF-T_ IS@.U/V_X IS@U/V_X IS@U/.V_X +V (.V@m VI) +V L +.V_GPU IS@HKF-T_ IS@.U/V_X IS@U/V_X IS@U/.V_X +V +V IS@.U/V_X IS@U/V_X (.V@m V) L +V_GPU IS@HKF-T_. IS@U/.V_X +V_GPU R IS@K/F_ R IS@K/F_ I TEMP_FIL +V_GPU +V_GPU EXT_LVS_LON R R R R,,, SYS_SHN# Q IS@K/F_ IN *IS@N_M GPIO SYS_SHN#, GPIO(ROMS#) P without external VIOS ROM *IS@K/F_ *IS@K/F_ IS@K/F_ GPU_LON R FH_PIE_PEG_LKREQ# If no contact this pin to LVS need pull low *IS@_ *P/V_X GPIO_ROMSK TEMP_FIL +V_GPU R *IS@K/F_ T R IS@K/F_ GPIO GPIO GPIO GPIO_SMT GPIO_SMLK GPU_LON SOUT_GPIO SIN_GPIO GFX_ORE_NTRL TESTEN SL S RM_FG RM_FG RM_FG T LT#_GPIO T GFX_ORE_NTRL T GPIO FH_PIE_PEG_LKREQ# PX_EN R GENERI +.V_GPU T T T T T T *IS@SHORT_ EXT_HMI_HP SL S R *IS@SHORT_EXT_LVS_LON SOUT_GPIO SIN_GPIO GPIO_ROMSK RM_FG RM_FG RM_FG HMI_HP GFX_ORE_NTRL OS_SPRE LT#_GPIO HP GENERI.V+R(R)=.V/=.V R IS@/F_ R T T *IS@K/F_ IS@/F_ GPIO GPIO GPIO GPIO_SMT GPIO_SMLK IN_GPU_R GFX_ORE_NTRL _EN GPIO FH_PIE_PEG_LKREQ# R OHM GPIO_TRST GPIO_TI GPIO_TK GPIO_TMS GPIO_TO TESTEN_RSV GENERI R R U U T U U T T T P P P N N N Y N M R W M P P N N L L L L K K F W W W SL S GENERL PURPOSE I/O GPIO_ GPIO_ GPIO_ GPIO SMT GPIO SMLK GPIO TT GPIO_ GPIO LON GPIO ROMSO GPIO ROMSI GPIO ROMSK GPIO_ GPIO_ GPIO_ GPIO HP GPIO PWRNTL_ GPIO_ GPIO THERML_INT GPIO HP GPIO TF GPIO PWRNTL_ GPIO EN GPIO ROMS GPIO LKREQ JTG_TRST JTG_TI JTG_TK JTG_TMS JTG_TO TESTEN RSV GENERI GENERI GENERI GENERI GENERIE_HP HP PX_EN R R G G HSYN VSYN RSET V VSSQ VI VSSI FutureSI/SEYMOUR/PRK E_/N/R N/R TS_/N/G PS_/N/G LK_UXP/N/ T_UXN/N/ SWPLOK/ N/Y GENERIF_HP/N/OMP GENLK_LK GENLK_VSYN PS_/N/VI N/VSSI N/V PS_/N/VQ TSVSSQ/VSSQ M K L J H G H J G E E M K L J K L H M J L J E E E R +V _VSY _HSY R R R +.V_V_Q IS@/F_ GPU_RT_HSYN GPU_RT_VSYN +.V_V_Q *IS@_ *IS@_ *IS@_ +V _VSY _HSY +V +V +.V_V_Q +.V_V_Q R *IS@/F_ +V R *IS@/F_ R *IS@/F_ GPU_RT_RE GPU_RT_GRE GPU_RT_LU E Need pull high near chip side Pure IS FF need install Pure IS F should EL MUXLESS should EL GPU_RT_HSYN GPU_RT_VSYN R R Y IS@MHZ_ +V_GPU *IS@K/F_ *IS@K/F_ IS@P/V_N IS@P/V_N E EVG-XTLI R IS@M_ EVG-XTLO For Int lk Mhz +V_GPU +V_GPU R *IS@K/F_ TESTEN R IS@K/F_ +V_GPU +.V_GPU L +.V_GPU IS@HKF-T_. L IS@HKF-T_. (.V@m PLL_V) IS@HKF-T_ L (.V@m PLL_PV) IS@U/.V_X IS@U/V_X (.V@m TSV) IS@U/.V_X IS@.U/V_X IS@U/V_X IS@.U/V_X IS@.U/V_X VG_THERMP VG_THERMN +.V_M_VREFG +.V_PLL_PV +.V_PLL_V EVG-XTLI IS@U/.V_X IS@.U/V_X EVG-XTLO IS@U/V_X R *IS@_/S R *IS@_/S +.V_TSV F E M K T T R VREFG PLL_PV PLL_PVSS PLL_V XTLIN XTLOUT XO_IN XO_IN PLL/LOK SEYMOUR/FutureSI PLUS MINUS THERML TS_FO/GPIO FO TSV TSVSS /UX SWPLOK/RSET LK T UXP UXN LK T UXP UXN LK_UXP T_UXN LK_UXP T_UXN LK T G E E E R IS@/F_ GPU_LK GPU_T T T T T EV_L_EILK EV_L_EIT GPU_LK GPU_T LVS RT +V_GPU R R R R R JTG EUG PORT TESTEN=V : efault TESTEN=.V : JTG signals enabled *IS@K/F_ *IS@K/F_ *IS@K/F_ *IS@K/F_ GPIO_TK GPIO_TMS GPIO_TI GPIO_TO *IS@K/F_ GPIO_TO J TESTEN GPIO_TRST *EUG@JTG_SOKET_ GPIO_TRST R R R +V_GPU *IS@K/F_ *EUG@_ *IS@K/F_ R R *IS@K/F_ GPIO_SMT *IS@K/F_ GPIO_SMLK IS@ROSON/SEYMOUR-S Quanta omputer Inc. PROJET : LF_LF Size ocument Number Rev ROSON_XT Main ate: Tuesday, pril, Sheet of bios.ru

19 E F G H K K L M N N P P R T T U U V W W W Y Y M N N N N N N P P R R R R T T T T T U U U U V V V Y Y Y Y R T UE PIE_VSS# PIE_VSS# PIE_VSS# PIE_VSS# PIE_VSS# PIE_VSS# PIE_VSS# PIE_VSS# PIE_VSS# PIE_VSS# PIE_VSS# PIE_VSS# PIE_VSS# PIE_VSS# PIE_VSS# PIE_VSS# PIE_VSS# PIE_VSS# PIE_VSS# PIE_VSS# PIE_VSS# PIE_VSS# PIE_VSS# PIE_VSS# PIE_VSS# PIE_VSS# PIE_VSS# PIE_VSS# PIE_VSS# PIE_VSS# PIE_VSS# GN# N# N# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# GN# VSS_MEH# VSS_MEH# VSS_MEH# E G H H E F F F F F F F F F F F F G G G G H H H H H J J K K K K M M UF LVS ONTROL LVTMP IS@ROSON/SEYMOUR-S SIN_GPIO RM_FG RM_FG RM_FG VRY_L IGON H TXLK_UP_PFP TXLK_UN_PFN J L TXOUT_UP_PFP TXOUT_UN_PFN K H TXOUT_UP_PFP TXOUT_UN_PFN J L TXOUT_UP_PFP TXOUT_UN_PFN K K TXOUT_UP TXOUT_UN J L TXLK_LP_PEP TXLK_LN_PEN K H TXOUT_LP_PEP TXOUT_LN_PEN J L TXOUT_LP_PEP TXOUT_LN_PEN K H TXOUT_LP_PEP TXOUT_LN_PEN J L TXOUT_LP TXOUT_LN K SIN_GPIO RM_FG RM_FG RM_FG Reserve only for MUXLESS R *IS@K/F_ R R R R GPU_VRY_L GPU_IGON EV_L_TXLLKOUT+ EV_L_TXLLKOUT- EV_L_TXLOUT+ EV_L_TXLOUT- EV_L_TXLOUT+ EV_L_TXLOUT- EV_L_TXLOUT+ EV_L_TXLOUT- +V_GPU *IS@K/F_ *IS@K/F_ *IS@K/F_ IS@K/F_ RSV IF_VG_IS RSV LLOW FOR PULLUP PS FOR THESE STRPS N IF THESE GPIOS RE USE, THEY MUST NOT ONFLIT URING RESET TX_PWRS_EN TX_EEMPH_EN IF_GEN_EN_ VIP_EVIE_STRP_EN RSV U[] U[] STRPS IOS_ROM_EN ROMIFG(:) HSYN ONFIGURTION STRPS PIN GPIO GPIO GPIO GPIO GPIO GPIO GPIO ROMS GPIO[:] VSYN GENERI HSYN VSYN GENERI GPIO EN ESRIPTION OF EFULT SETTINGS Transmitter Power Savings Enable : % Tx output swing for mobile mode : full Tx output swing (efault setting for esktop) PI Express Transmitter e-emphasis Enable : Tx de-emphasis disabled for mobile mode : Tx de-emphasis enabled (efault setting for esktop) Enable LKREQ# Power Management - LKREQ# power management capability is disabled - LKREQ# power management capability is enabled VG ENLE ENLE EXTERNL IOS ROM SERIL ROM TYPE OR MEMORY PERTURE SIZE SELET IGNORE VIP EVIE STRPS U[] U[] No audio function udio for isplayport and HMI if dongle is detected udio for isplayport only udio for both isplayport and HMI M RESERVE ONFIGURTION STRPS LLOW FOR PULLUP PS FOR THESE STRPS N IF THESE GPIOS RE USE, THEY MUST NOT ONFLIT URING RESET PULLUP PS RE NOT REQUIRE FOR THESE STRPS UT IF THESE GPIOS RE USE, THEY MUST NOT ONFLIT URING RESET REOMMENE SETTINGS = O NOT INSTLL RESISTOR = INSTLL K RESISTOR X = ESIGN EPENNT N = NOT PPLILE IS@ROSON/SEYMOUR-S Memory perture size +V_GPU bios.ru GPIO GPIO GPIO GPIO IOSROM M M M M M G G G ROMIFG ROMIFG ROMIFG It is a shared pin strap with ONFIG[:] if IOS_ROM_EN is set to. GENERI GPIO GPIO GPIO SOUT_GPIO _VSY _HSY GPIO GPIO_ROMSK GPIO GPIO GPIO SOUT_GPIO R R R R IS@K/F_ *IS@K/F_ IS@K/F_ *IS@K/F_ R *IS@K/F_ R *IS@K/F_ R *IS@K/F_ GPIO R *IS@K/F_ R *IS@K/F_ Quanta omputer Inc. PROJET : LF_LF Size ocument Number Rev ROSON_XT GN / LVS/ Straps ate: Tuesday, pril, Sheet of