AIT Mars PRO. PCIE Gen 1 x 1 Lane. Power : 25 (Watt) Package : M2 Size : 29 x 29 (mm) PAGE DP Port2. RTD2132S DP to LVDS.

Transcript

1 Volks_M omal IS/UM (") Ultra/Slim R SOIMM Maxima Gs PGE R SO-IMM Maxima Gs PGE R ~ MT/s R ~ MT/s M PU Processor : TRINITY aul / Quad ore Power : (Watt) Package : FP -PIN G Size : x (mm) IME PI-E Gen x Lane P Port IT Mars PRO Power : (Watt) Package : M Size : 9 x 9 (mm) PGE - VRM R x (9 MHz) x x, bit Max Gs/Gs PGE - MHz PGE HMI onn PGE P L STK UP LYER : TOP LYER : SGN LYER : IN(High) LYER : IN(Low) LYER : SV LYER : OT Power Source ST - st H Package : 9. (mm) Power : PGE mst Package :. (mm) Power : PGE System IOS SPI ROM PGE ST G/s ST G/s SPI Interface LP Interface M FH UMI x LKM Hudson M Power :. Watt Package : pin FG Size :. x. (mm) zalia PGE - Green LK.KHz PGE PGE - P Port US. Interface PORT, US. Interface RTS P to LVS Translator PGE PIE Gen x Lane US./. ombo x PGE L onn (.") US. x amera External US T US. x, PGE PGE PGE PGE PGE Q System harge Power (THG) G9RZU System ischarge Power (.V/V/V) (VSUSV/VLNV/.V) Ricktek RTPZ System Power (VPU/VPU/ VS/VS) ISL/RTZ/P/ISLRZ Processor Power (V_ORE/.V/.V/VN_ORE) Richtek RTL System Memory Power (.VSUS/.V_R_VTT) Port (ebug) PGE E SPI ROM PGE 9 Keyboard PGE Touch Pad PGE ite ITE/HX Embedded ontroller Power : Package : LQPF Size : x (mm) PGE 9 IT 9H99 udio odec Power : Package : QFN- Size : x (mm) PGE Realtek RTLE LN ontroller Power : Package : OFN Size : x (mm) PGE Realtek RTS9 ard Reader Power : Package : LQPF Size : x (mm) PGE Intel Rambo Peak Halt Mini ard WLN / T ombo Power : Package : Size : PGE Richtek RTZ PH Power (.VS) RTE/G9/G9RU/N GPU Power (VG_ORE/.V_VG/V_VG/.V_VG/.V_VG/VI) SLGN GreenLK PGE MHz FN ontroller PGE aughterl/ ONN ombo Jack PGE MHz NS RJ onn TRNSFORMER PGE PGE PROJET : VOLKS_omal " Quanta omputer Inc. Size ocument Number Rev lock iagram N ate: Thursday, September, Sheet of

2 TO WLN [] PEG_RXP [] PEG_RXN [] PEG_RXP [] PEG_RXN [] PEG_RXP [] PEG_RXN [] PEG_RXP [] PEG_RXN [] PEG_RXP [] PEG_RXN [] PEG_RXP [] PEG_RXN [] PEG_RXP [] PEG_RXN [] PEG_RXP [] PEG_RXN [] PIE_RXP_WLN [] PIE_RXN_WLN [] UMI_RXP [] UMI_RXN [] UMI_RXP [] UMI_RXN [] UMI_RXP [] UMI_RXN [] UMI_RXP [] UMI_RXN.V_VP /9 For omal. R PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PIE_RXP_WLN PIE_RXN_WLN P P M M K K J J H H F F Y Y V V T T P P N N M M K K H H G G E E M N N M P R R P 9/F_ P_ZVP R U P_GFX_RXP[] P_GFX_RXN[] P_GFX_RXP[] P_GFX_RXN[] P_GFX_RXP[] P_GFX_RXN[] P_GFX_RXP[] P_GFX_RXN[] P_GFX_RXP[] P_GFX_RXN[] P_GFX_RXP[] P_GFX_RXN[] P_GFX_RXP[] P_GFX_RXN[] P_GFX_RXP[] P_GFX_RXN[] P_GFX_RXP[] P_GFX_RXN[] P_GFX_RXP[9] P_GFX_RXN[9] P_GFX_RXP[] P_GFX_RXN[] P_GFX_RXP[] P_GFX_RXN[] P_GFX_RXP[] P_GFX_RXN[] P_GFX_RXP[] P_GFX_RXN[] P_GFX_RXP[] P_GFX_RXN[] P_GFX_RXP[] P_GFX_RXN[] P_GPP_RXP[] P_GPP_RXN[] P_GPP_RXP[] P_GPP_RXN[] P_GPP_RXP[] P_GPP_RXN[] P_GPP_RXP[] P_GPP_RXN[] P_UMI_RXP[] P_UMI_RXN[] P_UMI_RXP[] P_UMI_RXN[] P_UMI_RXP[] P_UMI_RXN[] P_UMI_RXP[] P_UMI_RXN[] P_ZVP UMI GPP GRPHIS TRINITY--SERIES_G P_GFX_TXP[] P_GFX_TXN[] P_GFX_TXP[] P_GFX_TXN[] P_GFX_TXP[] P_GFX_TXN[] P_GFX_TXP[] P_GFX_TXN[] P_GFX_TXP[] P_GFX_TXN[] P_GFX_TXP[] P_GFX_TXN[] P_GFX_TXP[] P_GFX_TXN[] P_GFX_TXP[] P_GFX_TXN[] P_GFX_TXP[] P_GFX_TXN[] P_GFX_TXP[9] P_GFX_TXN[9] P_GFX_TXP[] P_GFX_TXN[] P_GFX_TXP[] P_GFX_TXN[] P_GFX_TXP[] P_GFX_TXN[] P_GFX_TXP[] P_GFX_TXN[] P_GFX_TXP[] P_GFX_TXN[] P_GFX_TXP[] P_GFX_TXN[] P_GPP_TXP[] P_GPP_TXN[] P_GPP_TXP[] P_GPP_TXN[] P_GPP_TXP[] P_GPP_TXN[] P_GPP_TXP[] P_GPP_TXN[] P_UMI_TXP[] P_UMI_TXN[] P_UMI_TXP[] P_UMI_TXN[] P_UMI_TXP[] P_UMI_TXN[] P_UMI_TXP[] P_UMI_TXN[] P_Z N N M M K K H H F F E E Y Y V V U U T T P P M M K K J J G G E E N UMI_TXP_ M UMI_TXN_ P UMI_TXP_ R UMI_TXN_ P UMI_TXP_ R UMI_TXN_ P UMI_TXP_ R UMI_TXN_ P P_Z PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PIE_TXP_ PIE_TXN_ R *.U/V_ *.U/V_ *.U/V_ *.U/V_ *.U/V_ 9 *.U/V_ *.U/V_ *.U/V_ 9/F_.U/V_.U/V_.U/V_ 9 UM can remove.u/v_.u/v_ 9 9 *.U/V_ *.U/V_ *.U/V_ *.U/V_ *.U/V_ *.U/V_ *.U/V_ *.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_ PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN UMI_TXP UMI_TXN UMI_TXP UMI_TXN UMI_TXP UMI_TXN UMI_TXP UMI_TXN PEG_TXP [] PEG_TXN [] PEG_TXP [] PEG_TXN [] PEG_TXP [] PEG_TXN [] PEG_TXP [] PEG_TXN [] PEG_TXP [] PEG_TXN [] PEG_TXP [] PEG_TXN [] PEG_TXP [] PEG_TXN [] PEG_TXP [] PEG_TXN [] PIE_TXP_WLN [] PIE_TXN_WLN [] UMI_TXP [] UMI_TXN [] UMI_TXP [] UMI_TXN [] UMI_TXP [] UMI_TXN [] UMI_TXP [] UMI_TXN [] PEG X TO WLN HT onnector for ebug only V R *_/S.V /9 For omal. VI Override ircuit SV SV OOT VOLTGE VFIX_V =V/GN VFIX_V =OPEN R K/F_ R K/F_.. [,] PU_RST# PU_RST# PU_PWRG U GN Y V Y PU_RST_L_UF PU_PWROK_UF Note: To override VI,Remove Rd, Re, Rf, install Rc set VI via SV & SV option RES LVGGW J PU_TI PU_TK PU_TMS PU_TRST# PU_REQ# close to HT debug HEER R R R R R9 K/F_ K/F_ K/F_ K/F_ K/F_ /9 For omal..vsus.vsus [] PU_TEST [] PU_TEST9 TP [] PU_REQ# [] PU_RY [] PU_TK [] PU_TMS [] PU_TI [] PU_TRST# [] PU_TO PU_TEST PU_TEST9 PU_RST_L_UF PU_LT_RST_HTP# PU_REQ# PU_RY PU_TK PU_TMS PU_TI PU_TRST# PU_TO PU_PWROK_UF 9 9 *HT ONN --p-l [] SV [] SV Rd SV R *_/S PU_SV Re SV R *_/S PU_SV Rf PU_SV [9] PU_SV [9] [,] PU_PWRG PU_PWRG R *_/S PU_PWRG_SVI_REG PU_PWRG_SVI_REG [9] PU_PWRG have pull up ohm to.v on page PV hange to short pad PROJET : VOLKS_omal " Quanta omputer Inc. Size ocument Number Rev ustom N Llano PIE/UMI/GPP ate: Thursday, September, Sheet of

3 Place close to PU within " Soldermask openings for all bottom side vias/tps under FS Reserved for M suggest M Q M Q M Q9 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q M Q M Q M Q9 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q M Q M Q M Q M Q M Q M Q M Q9 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q M Q M Q M Q9 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q M Q M Q M Q M Q M Q M Q9 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q M Q M Q M Q M Q M Q M Q M Q M S# M S# M S# M M M M M M M M M M M M M M M M M 9 M M M M M M M M M M M M M M M MEMVREF_PU MEMVREF_PU M_ZVIO M M M M M M M M M M M M M M M 9 M M M M M S# M M M M M M M M S# M S# M M M M M M M Q[..] [] M Q[..] [] M M[..] [] M S#[..] [] M [:] [] M [:] [] M S#[..] [] M M[..] [] M QSP [] M QSP [] M QSP [] M QSP [] M QSP [] M QSP [] M QSP [] M QSP [] M QSN [] M QSN [] M QSN [] M QSN [] M QSN [] M QSN [] M QSN [] M QSN [] M LKP [] M LKN [] M LKP [] M LKN [] M KE [] M KE [] M OT [] M OT [] M S# [] M S# [] M RS# [] M S# [] M WE# [] M RST# [] M EVENT# [] M QSP [] M QSP [] M QSP [] M QSP [] M QSP [] M QSP [] M QSP [] M QSP [] M QSN [] M QSN [] M QSN [] M QSN [] M QSN [] M QSN [] M QSN [] M QSN [] M LKP [] M LKN [] M LKP [] M LKN [] M OT [] M OT [] M KE [] M KE [] M S# [] M S# [] M RS# [] M S# [] M WE# [] M RST# [] M EVENT# [,].VSUS.VSUS.VSUS.VSUS Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : VOLKS_omal " N Llano R MEM I/F Thursday, September, ustom Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : VOLKS_omal " N Llano R MEM I/F Thursday, September, ustom Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : VOLKS_omal " N Llano R MEM I/F Thursday, September, ustom U TRINITY--SERIES_G M_[] Y M_[] R M_[] T M_[] P M_[] P M_[] P M_[] N M_[] M M_[] M M_[9] L M_[] M_[] M M_[] K M_[] F M_[] K M_[] J M_NK[] M_NK[] M_NK[] K M_M[] M_M[] M_M[] M_M[] M_M[] M M_M[] N M_M[] R M_M[] N M_QS_H[] M_QS_L[] M_QS_H[] M_QS_L[] M_QS_H[] M_QS_L[] 9 M_QS_H[] M_QS_L[] M_QS_H[] M M_QS_L[] M M_QS_H[] N M_QS_L[] P9 M_QS_H[] P M_QS_L[] P M_QS_H[] R M_QS_L[] P M_LK_H[] W M_LK_L[] Y M_LK_H[] V M_LK_L[] V M_LK_H[] U M_LK_L[] V M_LK_H[] T M_LK_L[] T M_KE[] H M_KE[] H M_OT[] F M_OT[] H M_OT[] E M_OT[] H M_S_L[] M_S_L[] F M_S_L[] M_S_L[] G M_RS_L M_S_L M_WE_L M_RESET_L H M_EVENT_L Y M_T[] M_T[] M_T[] M_T[] M_T[] M_T[] M_T[] 9 M_T[] M_T[] M_T[9] M_T[] M_T[] M_T[] M_T[] M_T[] M_T[] M_T[] M_T[] M_T[] M_T[9] M_T[] M_T[] M_T[] M_T[] M_T[] M_T[] M_T[] F M_T[] F M_T[] M_T[9] M_T[] E M_T[] F M_T[] K M_T[] L M_T[] P M_T[] N M_T[] K M_T[] K M_T[] N M_T[9] P M_T[] P M_T[] R M_T[] P M_T[] N M_T[] R M_T[] P M_T[] R M_T[] P M_T[] P M_T[9] N M_T[] R M_T[] P M_T[] P M_T[] R M_T[] N M_T[] P M_T[] R M_T[] P9 M_T[] P M_T[9] R M_T[] N M_T[] P M_T[] P M_T[] N U TRINITY--SERIES_G M_[] M_[] R9 M_[] T M_[] R M_[] R M_[] P M_[] P M_[] P M_[] P9 M_[9] M M_[] M_[] M M_[] M9 M_[] E M_[] L M_[] L M_NK[] M_NK[] 9 M_NK[] M M_M[] M_M[] M_M[] E M_M[] F M_M[] K9 M_M[] L M_M[] M M_M[] M M_QS_H[] G M_QS_L[] H M_QS_H[] F M_QS_L[] G M_QS_H[] E M_QS_L[] F M_QS_H[] H M_QS_L[] G M_QS_H[] L9 M_QS_L[] L M_QS_H[] H M_QS_L[] J M_QS_H[] K M_QS_L[] L M_QS_H[] K M_QS_L[] L M_LK_H[] W9 M_LK_L[] Y M_LK_H[] W M_LK_L[] W M_LK_H[] U9 M_LK_L[] V M_LK_H[] U M_LK_L[] U M_KE[] L9 M_KE[] K M_OT[] M_OT[] G M_OT[] E M_OT[] G9 M_S_L[] M_S_L[] E9 M_S_L[] M_S_L[] F M_RS_L 9 M_S_L 9 M_WE_L M_RESET_L J M_EVENT_L M_VREF G M_ZVIO J M_T[] F M_T[] E M_T[] H9 M_T[] F9 M_T[] E M_T[] H M_T[] E M_T[] M_T[] G M_T[9] E M_T[] H M_T[] G M_T[] E9 M_T[] H M_T[] E M_T[] M_T[] H M_T[] F M_T[] M_T[9] 9 M_T[] E M_T[] M_T[] M_T[] M_T[] G M_T[] G9 M_T[] H M_T[] J9 M_T[] E M_T[9] F M_T[] H9 M_T[] H M_T[] H9 M_T[] J M_T[] M M_T[] M M_T[] H M_T[] H M_T[] J9 M_T[9] K M_T[] K M_T[] J M_T[] K M_T[] J M_T[] M M_T[] L M_T[] M M_T[] L M_T[] K M_T[9] H M_T[] K9 M_T[] H9 M_T[] M M_T[] L M_T[] J M_T[] L9 M_T[] K M_T[] J M_T[] K M_T[9] H M_T[] M M_T[] L M_T[] H M_T[] L 9 P/V_ R K/F_ R K/F_ R K/F_ R 9./F_ P/V_ P/V_.U/V_ R *_/S R K/F_

4 /9 HMI change to P for omal. note --HMI P&N can not swap Thermal FH_THERMTRIP# P output to ep to LVS converter isplay port power.v min.v max :.v P output to HMI connector Note: LK_PU_HLKP/N is MHZ SS Note: LK_P_NSSP/N is MHZ non-ss PV add for HW thermal protect Q9 MMT9--F R K/F_.VSUS PU_THERMTRIP# THERMTRIP# shutdown temperature 度 9_RST# Q9 MMT9--F S/G EPWROK R R K/F_ K/F_ IN_ IN_# IN_ IN_# IN_ IN_# IN_LK IN_LK# INT_eP_TXP INT_eP_TXN LK_PU_P LK_PU_N LK_P_P LK_P_N SV SV PU_SVT PU_RST# PU_PWRG PU_V_RUN_F_L VP_F_H PU_VN_RUN_F_H VIO_F_H PU_V_RUN_F_H 9_RST# TP TP TP TP9 IN_ IN_# IN_ IN_# IN_ IN_# PU_TI PU_TO PU_TK PU_TMS PU_TRST# PU_RY PU_REQ# /9 For omal, close to PU. _TX_HMI _TX_HMI-.V.V.V.VSUS EPWROK PV change GPU thermal protect V Place caps with PU < inch route PIE as ohm /- % 9 R R R R R.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_ /F_ K/F_ INT_eP_TXP_ INT_eP_TXN_ PEG_HMI_TXP PEG_HMI_TXN PEG_HMI_TXP PEG_HMI_TXN PEG_HMI_TXP PEG_HMI_TXN PEG_HMI_TXP PEG_HMI_TXN LK_PU_P LK_PU_N LK_P_P LK_P_N SV SV PU_SVT_R PU_SI PU_SI PU_RST# PU_PWRG PU_PROHOT# PU_THERMTRIP# PU_LERT PU_TI PU_TO PU_TK PU_TMS PV change to short-pad PU_TRST# PU_RY PU_REQ# R *_/S *K/F_ /F_ *_/S _SENSE VP_F_H PU_VN_RUN_F_H VIO_F_H PU_V_RUN_F_H VP_F_H FH_PROHOT# H_PROHOT# R9 R U H H P_TXP[] P_TXN[] H H P_TXP[] P_TXN[] F F P_TXP[] P_TXN[] F F P_TXP[] P_TXN[] E E P_TXP[] P_TXN[] P_TXP[] P_TXN[] P_TXP[] P_TXN[] P_TXP[] P_TXN[] P_TXP[] P_TXN[] P_TXP[] P_TXN[] P_TXP[] P_TXN[] P_TXP[] P_TXN[] L9 K9 LKIN_H LKIN_L L K ISP_LKIN_H ISP_LKIN_L E E SV SV SVT J H SI SI K H9 RESET_L PWROK L K PROHOT_L R THERMTRIP_L LERT_L E G TI H TO F TK H TMS E TRST_L E RY REQ_L G H _SENSE H VP_SENSE G VN_SENSE G VIO_SENSE H V_SENSE VR_SENSE *_/S to E reserve only P/V_ ISPLY PORT ISPLY PORT ISPLY PORT LK SER. TRL JTG SENSE ISPLY PORT MIS. RSV TEST TRINITY--SERIES_G *_/S PU_PROHOT# M P_UXP P_UXN M L P_UXP P_UXN L J P_UXP P_UXN J P P_UXP P_UXN P R P_UXP P_UXN R U P_UXP P_UXN U P_HP M P_HP L P_HP J P_HP P P_HP R P_HP U P_LON P_IGON P_VRY_L P_UX_Z L TEST Y TEST9 V TEST G9 TEST F9 TEST E9 TEST G TEST F TEST E TEST9 F TEST G TEST TEST_H J H TEST_L TEST_H G H TEST_L TEST_H V Y TEST_L H TEST TEST_H R T TEST_L L TEST P MTIVE_L T TEST R TEST RSV L RSV P RSV H RSV J RSV K.V R9 *K/F_.VSUS INT_eP_UXP_ INT_eP_UXN_ FH_LVS_HP HMI_HP_Q PU_LEN PU_IGON P_UX_Z PU_TEST9 PU_TEST PU_TEST_P PU_TEST_P PU_TEST_P PU_TEST_P PU_TEST PU_TEST9 PU_TEST_SNLK PU_TEST_SNLK PU_TEST_H PU_TEST_L PU_TEST_H PU_TEST_L M_TEST PU_TEST MTIVE_L PU_THERM PU_THERM R9 K/F_ VRHOT R.U/V_.U/V_ /F_ TP TP9 TP TP TP TP TP TP TP TP TP TP R R TP TP R99 *_/S INT_eP_UXP INT_eP_UXN INT_HMI_UXP INT_HMI_UXN FH_LVS_HP HMI_HP_Q TP TP PU_LPWM PU_TEST PU_TEST9 PU_PROHOT# To M HT INT_eP_UXP R *K/F_ LVS INT_eP_UXN R *K/F_ V HMI MTIVE_L controls entry and exit from the sleep and power states MTIVE_L *K/F_.V K/F_.VSUS SI MLK M_TEST M_TEST ONNETION T MLK INT_eP_UXP_ INT_eP_UXN_.VSUS PU_TEST_L PU_TEST9 PU_TEST PU_TEST9 PU_TEST_SNLK PU_TEST_SNLK PU_TEST_H Q MMT9--F.VSUS RV- R R9 R *9./F_ R 9./F_ R9 K/F_ PU_TEST / For omal. TEST PU FOR INTERNL TEST P FOR USTOMER R9 K/F_.K_.K_ R R9 R9 R9 R9 R R R K/F_ /F_ *_ PU_SI K/F_ K/F_ K/F_ K/F_ /F_.VSUS.VSUS R9 */_.V R K/F_ R9 /_ Q *MENE SYS_SHN-# *NE Q9 GPU_OVT# GPU_PWROK THERMTRIP# R *_/S FH_THERMTRIP# R *_ HW_LERT# HW_LERT# 9 *RV- PV add for HW thermal protect HWPG VG TEMP_ FIL function is active Hi over degree = Low R *K/F_ HW_LERT# VPU VPU *U/.V_ R U9 *G V GN *_/S OT OT TMSNS RHYST TMSNS RHYST When K-NT =.K Thermal Trip = R R *.K/F_ R *.K/F_ R *.K/F_ *K_ NT R *.K/F_ R MT *K_ NT MT Q MMT9--F RV- PU_SI PROJET : VOLKS_omal " Quanta omputer Inc. Size ocument Number Rev N Llano isplay/misc ate: Thursday, September, Sheet of

5 PIN NME V VN VIO VP VR V PU POWER TLE.V.V NET NME V_ORE VN_ORE.VSUS.V_VP.V_VR.V_V U/.VS_ 9.U/V_ U/.VS_ VOLTGE.V??.V.V.V.V VN_P VP_P. Up to VIO.U/V_ P/V_ R U/.VS_ 9.U/V_ 9 U/.VS_.U/V_ 9 P/V_.U/V_.V_VP VP = *_/S U/.VS_ 9 P/V_ 9 U/.VS_ U/.VS_ U/.VS_ 9 P/V_ *U/.VS_ P/V_ U/.VS_ P/V_ L PYT-Y-N(,) P/V_ VN_ORE.U/V_ P/V_ 9 P/V_ 99 9 U/.VS_ P/V_.U/V_ 9.U/V_.V_VP.U/V_ *U/.VS_ V=..V_V VN_ORE.VSUS P/V_.U/.V_.U/V_ 9 U/.VS_ VP_P TP.U/V_ V_ORE J J J J J9 J J M M M M M M9 M M R R9 R R R R R R9 R R U V9 V V V V 9 9 J K K L L L M N N N N P R R R U U U W W M N P P R R M M P/V_ UE V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V VN VN VN VN VN VN VN VN VN VN VN VN VN VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VP VP VP VP VP VP V V V V9 V V V V V W V V 9 V V V V V V 9 V V V 9 V V V V V V 9 V V V G V G V G V G V G9 V G V G VN VN VN VN VN VN VN VN VN VN VN VN VN M9 VN_P N9 VN_P VIO W VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO E VIO E VIO E VIO G VIO G VIO G VIO G VIO G VR N VR P VR P VR R VR R VP_P VP_P V V TRINITY--SERIES_G V_ORE U/.VS_ U/.VS_.U/V_ VN_ORE VN_P.VSUS U/.VS_ Maximum Ispike Maximum INspike.VSUS If the plane is cut to create a VIO plane, ceramic capacitors are connected across the VIO and plane split as follows VR =. ( Up to ).V_VR_.U/V_ 9 U/.VS_ U/.VS_.U/V_ EMI suggestion EOUPLING between PROESSOR and IMMs cross VIO and split.u/.v_ U/.VS_.U/V_ U/.VS_ U/.VS_ P/V_.U/.V_.U/.V_ P/V_ U/.VS_ *U/.VS_ P/V_.U/.V_.U/.V_ 9 P/V_ U/.VS_ *U/.VS_ P/V_.U/.V_.U/.V_ P/V_ P/V_ 9 U/.VS_ *U/.VS_.U/V_.U/V_ 9.U/.V_ R9 *P/V_ U/.VS_ *U/.VS_ 9.U/V_.U/V_ *_/S V_ORE.V *P/V_ 9 U/.VS_.U/V_.U/V_.U/V_ E E E9 E E F F F F F F F F F9 G G G G G9 G G G G H H9 H H J J J9 J J J J J J K9 K K K K K K9 K K L L L M M M N N N N N N N9 N N R R R T9 T T T T T T9 T T U W W W W W W Y9 UF TRINITY--SERIES_G Y Y Y Y Y Y9 Y Y 9 9 E F9 F F F F F F9 F F F F G G G G9 G G H H H H H H J J J J J9 J J J9 J J J J K K K K K L L L L L L L L M M M9 M M M M9 M M M M9 M N N N P P9 R R R9 R R9 R R R R R9 R PROJET : VOLKS_omal " Quanta omputer Inc. Size ocument Number Rev ustom N Llano POWER/GN ate: Thursday, September, Sheet of

6 ,,] VS V VS R R R VS N,no install by default R R R R R R R R R R R Z_SOUT_R Z_SYN_R Z_LK_R Z_RST#_R Z_SIN [] VG_REQ GPU_PWROK *.K_ *.K_ *.K_ FH_TEST FH_TEST FH_TEST.K_ SM_RUN_LK to R SMUS.K_ SM_RUN_T *K/F_ SYS_RST# SYS_RST# internal K pull up K/F_ K/F_ K/F_ K/F_.K_.K_ *.K_ *.U/V_ K/F_ SL S SL S SL S Pure UM can remove FH_THERMTRIP# NSWON# To zalia R _ R _ R _ R _ *P/V_ R K/F_ *RV- P/V_ LK_REQ# already internal pull up.k LKREQ# GEVENT# internal pull Hi.K to V GEVENT# internal pull Hi.K to V GEVENT# internal pull Hi.K to V GEVENT# internal pull Hi.K to VS PIE_WKE# no need to pull Hi resistor from check list [] PIE_LKREQ_R# LK_REQ# internal pull Hi.K to V [] PIE_LKREQ_LN# LK_REQ# internal pull Hi.K to V LK_REQ# internal pull Hi.K to V This pin is used to power down VG regulators when RT no connected GEVENT# internal pull Hi.K to VS GEVENT# internal pull Hi.K to VS Z_SOUT_UIO [] Z_SYN_UIO [] IT_LK_UIO [] Z_RST#_UIO [] Z_SIN [] Q *MMT9--F [9] SUS# [9] SUS# [9] NSWON# [] FH_PWRG [9] E_GTE [9] E_RIN# [9] SIO_EXT_SMI# [9] SIO_EXT_SI# [,] PIE_WKE# [] FH_THERMTRIP# V [9] RSMRST# [] SPKR [,] SM_RUN_LK [,] SM_RUN_T [,] SL [,] S [] PIE_LKREQ_WLN# [] RF_OFF# TP For Zero O H audio interface is V_S voltage /9 For omal. PIE_RST# RI# SUS# SUS# NSWON# FH_PWRG FH_TEST T9 FH_TEST T TP FH_TEST V9 E TP R *_/S GEVENT# SYS_RST# U PIE_WKE# K *P/V_ V FH_THERMTRIP# R R K/F_ W_PWRG F9 E_GTE E_RIN# G9 FH_PME# R9 SIO_EXT_SMI# T R RF_OFF# R R R R9 R TP TP9 TP TP TP TP TP9 TP TP9 TP TP9 TP TP [] T_OMO_OFF# [] VG_RST [9] VG_ON_S RSMRST# PIE_LKREQ_R# G PIE_LKREQ_LN# E E F H G *_/S FH_GPIO F SM_RUN_LK SM_RUN_T SL S T R PIE_LKREQ_WLN# G LKREQ# G J SMRTVOLT G VG_P V GE_LE W Y V F O_PLUGIN# FH_JTG_TK FH_JTG_TI FH_JTG_RST# *K/F_ Z_LK_R Z_SOUT_R *K/F_ Z_SIN *K/F_ Z_SIN *K/F_ Z_SIN_R *K/F_ Z_SIN_R Z_SYN_R Z_RST#_R T_OMO_OFF# VG_RST VG_ON_S R W T W J N U M R T P F P J T Y Y Y E K9 J9 J F E F E J H G K 9 9 U PIE_RST#/GEVENT# RI#/GEVENT# SPI_S#/GE_STT/GEVENT# SLP_S# SLP_S# PWR_TN# PWR_GOO RSMRST# Z_ITLK Z_SOUT Z_SIN/GPIO Z_SIN/GPIO Z_SIN/GPIO9 Z_SIN/GPIO Z_SYN Z_RST# PSK_T/GPIO9 PSK_LK/GPIO9 PSM_T/GPIO9 PSM_LK/GPIO9 KSO_/GPIO9 KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_9/GPIO KSO_/GPIO9 KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/X/GPIO KSO_/X/GPIO KSO_/X/GPIO KSO_/X/GPIO HUSON-M Part of TEST TEST/TMS TEST GIN/GEVENT# KRST#/GEVENT# PME#/GEVENT# LP_SMI#/GEVENT# LP_P#/GEVENT# SYS_RESET#/GEVENT9# WKE#/GEVENT# IR_RX/GEVENT# THRMTRIP#/SMLERT#/GEVENT# W_PWRG LK_REQ#/ST_IS#/GPIO LK_REQ#/ST_IS#/GPIO SMRTVOLT/ST_IS#/GPIO LK_REQ#/ST_IS#/GPIO ST_IS#/FNOUT/GPIO ST_IS#/FNIN/GPIO9 SPKR/GPIO SL/GPIO S/GPIO SL/GPIO S/GPIO LK_REQ#/FNIN/GPIO LK_REQ#/FNOUT/GPIO IR_LE#/LL#/GPIO SMRTVOLT/SHUTOWN#/GPIO R_RST#/GEVENT#/VG_P GE_LE/GPIO SPI_HOL#/GE_LE/GEVENT9# GE_LE/GEVENT# GE_STT/GEVENT# LK_REQG#/GPIO/OSIN/ILEEXIT# H UIO PS_T/S/GPIO PS_LK/E/SL/GPIO SPI_S#/GE_STT/GPIO EMEE TRL PI / WKE UP EVENTS LINK/US_O#/GEVENT# US_O#/IR_TX/GEVENT# US_O#/IR_TX/GEVENT# US_O#/IR_RX/GEVENT# US_O#/_PRES/TO/GEVENT# US_O#/TK/GEVENT# US_O#/TI/GEVENT# US_O#/SPI_TPM_S#/TRST#/GEVENT# GPIO US O USLK/M_M_M_OS US MIS US. US. US. SL/GPIO9 S/GPIO9 SL_LV/GPIO9 S_LV/GPIO9 E_PWM/E_TIMER/GPIO9 E_PWM/E_TIMER/GPIO9 E_PWM/E_TIMER/WOL_EN/GPIO99 E_PWM/E_TIMER/GPIO US_ROMP US_FSP/GPIO US_FSN US_FSP/GPIO US_FSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HS9P US_HS9N US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN USSS_LRP USSS_LRN US_SS_TXP US_SS_TXN US_SS_RXP US_SS_RXN US_SS_TXP US_SS_TXN US_SS_RXP US_SS_RXN US_SS_TXP US_SS_TXN US_SS_RXP US_SS_RXN US_SS_TXP US_SS_TXN US_SS_RXP US_SS_RXN KSI_/GPIO KSI_/GPIO KSI_/GPIO KSI_/GPIO KSI_/GPIO KSI_/GPIO KSI_/GPIO KSI_/GPIO G 9 H H H H H G K J G F K K E F H9 G9 F E E E E F F G H G J H J K H9 G9 G G E H J H K K F F E F US_ROMP_S USP USP- USP USP- USP USP- USSS_LRP USSS_LRN US. Not Implemented: left unconnected. SL S SL S E_PWM R R R No need for GPIO.K/F_ USP [] USP- [] USP [] USP- [] USP [] USP- [] USP [] USP- [] USP [] USP- [] K/F_ K/F_ US_TX [] US_TX- [] US_RX [] US_RX- [] US_TX [] US_TX- [] US_RX [] US_RX- [] E_PWM [] US ombo./.. US ombo./.. MER WLN Min-ard EXternal MI SL of a TSI-capable PU's thermal bus,pulled up to PU_VIO. Resistor value verified in the relevant PU design guide. LEFT side US. onnector FH_V SSUS_S Hudson-M- PROJET : VOLKS_omal " Quanta omputer Inc. Size ocument Number Rev ustom N Hudson-M GPIO/US/Z/RGMII ate: Thursday, September, Sheet of

7 [] R_PIE_RST# [,] MINI_PIE_RST# [] LN_PIE_RST# [] GPU_RST# Place these PIE coupling cap close to FH [] PIE_TXP_R [] PIE_TXN_R [] PIE_TXP_LN [] PIE_TXN_LN [] PIE_RXP_R [] PIE_RXN_R [] PIE_RXP_LN [] PIE_RXN_LN [] PH_XTL_IN PV change to non-stuff for Green lock solution 9 P/V_ P/V_ [] UMI_RXP [] UMI_RXN [] UMI_RXP [] UMI_RXN [] UMI_RXP [] UMI_RXN [] UMI_RXP [] UMI_RXN [] UMI_TXP [] UMI_TXN [] UMI_TXP [] UMI_TXN [] UMI_TXP [] UMI_TXN [] UMI_TXP [] UMI_TXN.V_PIE_VR PIE_RXP_R PIE_RXN_R PIE_RXP_LN PIE_RXN_LN.V_KV *P/V_ 9 R _ R _ R _ R _ R R R Y *MHZ.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_ R9 *M/F_ 9/F_ K/F_ K/F_ TP PIE_RST# E _RST# PIE_RST# _RST# UMI_RXP_ E UMI_RXN_ E UMI_TXP UMI_RXP_ UMI_TXN UMI_RXN_ UMI_TXP UMI_RXP_ UMI_TXN UMI_RXN_ 9 UMI_TXP UMI_RXP_ UMI_TXN UMI_RXN_ UMI_TXP UMI_TXN UMI_RXP UMI_RXN 9 UMI_RXP Y UMI_RXN Y UMI_RXP Y UMI_RXN Y9 UMI_RXP UMI_RXN PIE_LRP_FH F9 PIE_LRN_FH F PIE_LRP PIE_LRN PIE_TXP_R_ V PIE_TXN_R_ V GPP_TXP PIE_TXP_ W GPP_TXN PIE_TXN_ W GPP_TXP GPP_TXN GPP_TXP GPP_TXN GPP_TXP GPP_TXN GPP_RXP W GPP_RXN V GPP_RXP V GPP_RXN W GPP_RXP W GPP_RXN W GPP_RXP GPP_RXN LK_LRN_FH SI, change to Ω & Ω G TP for Rise/Fall time issue G PIE_RLKP PIE_RLKN LK_P_P_FH R [] LK_P_P LK_P_N_FH T ISP_LKP [] LK_P_N RP _PR_ ISP_LKN H 9/ add RP/RP for LK Slew Rate TP9 H ISP_LKP ISP_LKN LK_PU_P_FH T [] LK_PU_P LK_PU_N_FH T PU_LKP [] LK_PU_N RP _PR_ PU_LKN LK_VG_P_FH J [] LK_VG_P [] LK_VG_N LK_VG_N_FH K9 SLT_GFX_LKP RP _PR_ SLT_GFX_LKN [] LK_WLN_P LK_WLN_P_FH H [] LK_WLN_N LK_WLN_N_FH H GPP_LKP RP _PR_ GPP_LKN [] LK_PIE_R_P LK_PIE_R_P_FH J LK_PIE_R_N_FH K GPP_LKP [] LK_PIE_R_N RP _PR_ GPP_LKN F TP9 F GPP_LKP GPP_LKN Note: LK_FH_SRP/N is MHZ SS E TP E GPP_LKP GPP_LKN Note: LK_PIE_TRVISP/N is MHZ non-ss M Note: LK_P_NSSP/N is MHZ non-ss M GPP_LKP GPP_LKN Note: LK_PU_HLKP/N is MHZ SS M TP9 Note: LK_PIE_VGP/N is MHZ SS M GPP_LKP GPP_LKN Note: GPP_LK(:)P/N is MHZ SS capable N TP9 N GPP_LKP GPP_LKN R TP9 R GPP_LKP GPP_LKN [] LK_PIE_LNP LK_PIE_LNP_FH N LK_PIE_LNN_FH R GPP_LKP [] LK_PIE_LNN RP _PR_ GPP_LKN P/V_ P/V_.U/V_.U/V_ *P/V_ R9 _.U/V_ TP M_X M_X F J UE LK_LRN M_M_M_OS M_X M_X Hudson-M- HUSON-M Part of PI EXPRESS INTERFES LOK GENERTOR PI LKS /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO 9/GPIO9 /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO 9/GPIO9 /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO 9/GPIO9 /GPIO /GPIO E# E# E# E# FRME# EVSEL# IRY# TRY# PR STOP# PERR# SERR# REQ# REQ#/GPIO REQ#/LK_REQ#/GPIO REQ#/LK_REQ#/GPIO GNT# GNT#/GPO GNT#/S_LE/GPO GNT#/LK_REQ#/GPIO LKRUN# LOK# PU S PLUS PILK PILK/GPO PILK/GPO PILK/GPO PILK/M_OS/GPO9 PI INTERFE LPLK LPLK L L L L LFRME# LRQ# LRQ#/LK_REQ#/GPIO9 SERIRQ/GPIO LP S_ORE_EN RTLK INTRUER_LERT# VT_RT_G PIRST# INTE#/GPIO INTF#/GPIO INTG#/GPIO INTH#/GPIO M_TIVE# PROHOT# PU_PG LT_STP# PU_RST# K_X K_X F F F G F J L G L H J L N N J L L M J K N G9 M J L K N G E E F H H E N J N G K9 L F E H M9 H G G F M K 9 H9 F E 9 E E9 G E E G F G G H F F E PI_LK PI_LK PI_LK PIRST#_L PI_ PI_ PI_ PI_ PI_ HUSON_MEMHOT#_R 9 LKRUN# TRVIS_EN# EL_INTH# LP_LK LP_LK L L L L LFRME# LRQ# LRQ# SERIRQ MTIVE_L FH_PROHOT# PU_PWRG_R PU_STOP# PU_RST# K_X K_X S_ORE_EN LK_RT INTRUER_LERT# VT_RT_G MIL G *SHORT_ P R R9 _ P/V_ TP TP9 TP TP TP TP TP L [,9] L [,9] L [,9] L [,9] LFRME# [,9] TP TP SERIRQ [9] *_ LK_M_EUG LP_LK [] LP_LK [] R _ R _ *P/V_ TP PI_LK [] PI_LK [] PI_LK [] K_RST# PI_SERR# [9] LKRUN# [9] EL_INTH# [] K_RST# [9] INTRUER_LERT# Left not connected (FH has -kohm internal pull-up to VT). MIL dd G-sensor signal FH PROHOT#--- (input.v threshold ) When it isasserted, it can generate SI or SMI to OS/IOS MIL *99/F_ VRT_ S_ORE_EN is necessary to connect enable pin of VPU/VPU regulator for S mode implementation MIL PV change to non-stuff for Green lock solution LK_M_K [9] LK_M_EUG [] MIL MIL PV change to short-pad K_X MTIVE_L [] *P/V_ FH_PROHOT# [] R *_/S USE GROUN GUR FOR K_X N K_X PU_PWRG [,] TP PU_RST# [,] LT_STP# let is N from schematic recommend PV change to non-stuff for Green lock solution.u/v_.u/v_ TP LK_RT [] TP R9 _ PI_ [] PI_ [] PI_ [] PI_ [] PI_ [] GPU_PWROK [,,9,,,] TP V_RT U/.V_ V_RT *P/V_ R P/V_ P/V_ K_X R R *M_ */F_ VRT Y *.KHZ X'tal Stuff'R9 change to hm. Green LK Stuff'R9 change to ohm. R _ *RV- *RV- *P/V_ R N T_ONN ate: Thursday, September, Sheet of VRT_ */F_ T VPU T LKGEN_RT_X [] PROJET : VOLKS_omal " Quanta omputer Inc. Size ocument Number Rev ustom N Hudson-M PI/PI/LOK

8 Hudson-M- UM ST H MINIST I I I I I ONFIG - Level OM Item U _ 9 E _ E _ E _ E9 _9 F _ F9 _ F _ F _ F _ F _ F9 _ F _ F _ F9 _9 G _ G _ G _ H _ H _ H9 _ J _ J9 _ J _ J _9 J _ J _ K _ K _ K _ K _ L _ L _ L _ L _9 L _ L _ M _ M _ M _ M _ N _ N _ N _ N _9 N _ P _ P _ P _ P _ P _ P _ R _ R _ R _9 R _ T _ T _ T N N_HWM K XL H PL_SYS HUSON-M Part of GROUN T _ T _ U _ U _ U _9 U _ U _ U _ U _ V _ V _ V _ W _ W _ W _9 W _ Y _ Y _ Y _9 _9 _9 _9 _9 _9 _9 _9 _9 _9 E _99 E _ E _ E _ F _ F _ F _ F _ G _ G _ H _9 H _ H _ H9 _ H _ H _ H _ H _ J _ J _ J9 _9 K _ K _ L _ M _ M _ N _ N _ N _ N _ PL_ T N_ L NQ_ K IO_ N R EFUSE [] ST_LE# GPIO internal pull Hi.K to V GPIO internal pull Hi.K to V GPIO internal pull Hi.K to V GPIO internal pull Hi.K to V GPIO internal pull Hi.K to V GPIO internal pull Hi.K to V R.V_V_ST /9 For omal. V PLE ST OUPLING PS LOSE TO HUSON-M/M [] ST_TXP [] ST_TXN [] ST_RXN [] ST_RXP [] ST_TXP [] ST_TXN [] ST_RXN [] ST_RXP *_/S [] RF_OFF# TP99 TP9 [] _LE# [] L_K S_ST_LE# PV, change to short pad ST_TXP ST_TXN ST_TXP ST_TXN PLE ST_L RES VERY LOSE TO LL OF HUSON-M/M R R9 R K/F_ 9/F_ ST_LRP ST_LRN */F_ S_ST_LE# Integrated lock Mode: Leave unconnected. RF_OFF# T_OFF# T_OMO_EN# L_K K9 M9 L N N L H J J H M K H J N L L N J H N9 L K M L9 N L L H H J J F F F G H M J K N L TEMPIN K TEMPIN K TEMPIN K TEMPIN M U N N N N9 ST_TXP ST_TXN ST_RXN ST_RXP ST_TXP ST_TXN ST_RXN ST_RXP ST_TXP ST_TXN ST_RXN ST_RXP ST_TXP ST_TXN ST_RXN ST_RXP ST_TXP ST_TXN ST_RXN ST_RXP ST_TXP ST_TXN ST_RXN ST_RXP N N N N ST_LRP ST_LRN ST_T#/GPIO ST_X ST_X FNOUT/GPIO FNOUT/GPIO FNOUT/GPIO FNIN/GPIO FNIN/GPIO FNIN/GPIO HUSON-M SERIL T TEMPIN/GPIO TEMPIN/GPIO TEMPIN/GPIO TEMPIN/TLERT#/GPIO S R SPI ROM VG VG MINLINK HW MONITOR GE LN Part of S_LK/SLK_/GPIO S_M/SLO_/GPIO S_#/GPIO S_WP/GPIO S_T/STI_/GPIO S_T/STO_/GPIO S_T/GPIO9 S_T/GPIO GE_OL GE_RS GE_MK GE_MIO GE_RXLK GE_RX GE_RX GE_RX GE_RX GE_RXTL/RXV GE_RXERR GE_TXLK GE_TX GE_TX GE_TX GE_TX GE_TXTL/TXEN GE_PHY_P GE_PHY_RST# GE_PHY_INTR SPI_I/GPIO SPI_O/GPIO SPI_LK/GPIO SPI_S#/GPIO ROM_RST#/SPI_WP#/GPIO VG_RE VG_GREEN VG_LUE VG_HSYN/GPO VG_VSYN/GPO9 VG S/GPO VG SL/GPO VG RSET UX_VG_H_P UX_VG_H_N UXL ML_VG_LP ML_VG_LN ML_VG_LP ML_VG_LN ML_VG_LP ML_VG_LN ML_VG_LP ML_VG_LN ML_VG_HP/GPIO9 VIN/GPIO VIN/GPIO VIN/STI_/GPIO VIN/STO_/GPIO VIN/SLO_/GPIO9 VIN/SLK_/GPIO VIN/GE_STT/GPIO VIN/GE_LE/GPIO N N N N N L N J H K M H J 9 W H F E G F9 G E 9 W9 V V V T V L L M9 M N M N K V V9 U T T T9 T R R P9 P 9 N M L N P P M M G H G L GE_PHY_INTR SPI_SI SPI_SO SPI_LK SPI_S# FH_SPI_WP TP TP9 TP SIE_PORT_I SIE_PORT_I SIE_PORT_I OR_I OR_I OR_I OR_I OR_I R TP TP TP TP TP9 K/F_ VIN ( - ) Voltage Monitor Not Implemented -KΩ % pull-up to VS or -KΩ % pull-down VS R K/F_ VS Vender MI WINON Socket SPI_S# *_/S SPI_LK *_/S SPI_SO *_/S SPI_SI *_/S Size M M R R R R P/N KEZN KEFPN FHSFS E_IOS_S# [9] E_IOS_SPI_LK_I [9] E_IOS_WR# [9] E_IOS_R# [9] R K/F_ R K/F_ R K/F_ R K/F_ Hudson-M- TEMP( - ) Temp Monitor Not Implemented -KΩ % pull-up to VS or -KΩ % pull-down VS R9 R9 *K/F_ *K/F_ OR_I OR_I R9 R99 K/F_ K/F_ R *K/F_ OR_I R K/F_ SIE_PORT_I SIE_PORT_I SIE_PORT_I R *K/F_ OR_I R K/F_ Samsung R9 *K/F_ OR_I R9 K/F_ SG / Muxless 9 Hynix N no supprot side port R9 R R9 K/F_ K/F_ *K/F_ SIE_PORT_I R9 SIE_PORT_I R SIE_PORT_I R *K/F_ *K/F_ K/F_ PROJET : VOLKS_omal " Quanta omputer Inc. Size ocument Number Rev ustom N Hudson-M ST/HWM/SPI ate: Thursday, September, Sheet of

9 PLE LL THE EOUPLING PS ON THIS SHEET LOSE TO S S POSSILE..V_VIO 9 VQ--.V I/O power m m for M V R *_/S U 9m for M VR-- S/ ORE power PV hange to short pad HUSON-M Part of T TRE WITH >=mil.v 9 VIO PIGP_ VR T.U/V_ U/.VS_.U/V_.U/V_.U/V_ E9 VIO PIGP_ VR T VIO PIGP_ VR U G VIO PIGP_ VR U.U/V_.U/V_ U/.V_ U/.V_ U/.V_ VIO PIGP_ VR V V L TRE WITH >=mil VIO PIGP_ VR V VIO PIGP_ VR V PYT-Y-N(,) VIO PIGP_ VR Y.V_KV VPL_.V VIO PIGP_9 VR 9.U/.V_ *.U/V_ VIO PIGP_ m m VN LK-- Internal clock PV hange to short pad H H Generator I/O power V VPL SYS VN LK_ J TRE WITH >=mil L.V *_/S R U VPL VN LK_ K LMPGSN(,.)_ V L TRE WITH >=mil T VPL ML VN LK_ L FH_VPL SSUS_S m L VN VN LK_ M 9 9 PYT-Y-N(,) FH_VPL SUS_S m VPL SSUS_S VN LK_ N U/.V_ U/.V_.U/V_.U/V_ U/.VS_ FH_VPL PIE m H9 VPL US_S VN LK_ N.U/.V_ *.U/V_ FH_VPL ST m G VPL PIE VN LK_ P VPL ST VN LK_.V_PIE_VR VPL SYS_S : System lock Gen VN ML -- UMI.V analog power m VN PIE --PIE/UMI analog power TRE WITH >=mil PLLs analog power LO_P M L9 LO_P VN PIE_.V Y LMPGSN(,.)_ *.U/.V_ V VN PIE_ E VPL_.V VPL VN PIE_ 9 Y VN PIE_.U/V_.U/V_ U/.V_ U/.V_ U/.VS_.VS L V VN ML_ VN PIE_ PYT-Y-N(,) V VN ML_ VN PIE_ F *_/S R V VN ML_ VN PIE_ G.V_V_ST VN ML_ VN PIE_ PV hange to short pad.u/.v_.u/v_ m VN ST--ST PHY analog/io power TRE WITH >=mil V VPL_.V L VIO GE_S VN ST_.V Y LMPGSN(,.)_ VN ST_ L VN ST_ VPL US_S : US PHY PLL analog power if support US PYT-Y-N(,) VN ST_ U/.V_ U/.V_.U/V_.U/V_ U/.VS_. wake up V_V_US FH_VPL SUS_S VR GE_S_ VN ST_ should be 9 VR GE_S_ VN ST_ change pull hi.u/.v_.u/v_ L VN ST_ PYT-Y-N(,) 9 VN ST_ to S power VIO_GE_S_ VN ST_9 9 VIO_GE_S_ VN ST_.U/.V_ U/.V_ MIN LINK PI/GPIO I/O GE LN LKGEN I/O PI EXPRESS SERIL T ORE S.VS VN US_S : US PHY I/O analog power VS L VN US_S : US PHY PLL analog power VR US_S : US PHY core power.vs M chipset need to stuff for support US. L PYT-Y-N(,) PYT-Y-N(,).VS L PYT-Y-N(,) PYT-Y-N(,) SI, M SR tool review FH_V SSUS_S.U/V_ L U/.V_ V_V_US TRE WITH >=mil m FH_VN US_S.U/V_ U/.V_ U/.V_.U/V_ m.u/.v_ TRE WITH >=mil.u/v_ m FH_VR US_S TRE WITH >=mil.u/v_ U/.V_ m FH_VN SSUS_S_R VN SSUS_S : US. PHY PLL analog power FH_VR SSUS_S U/.V_ m G H J K K9 M9 M N9 N M N M U U T T P M N P P N N P M VN US_S_ VN US_S_ VN US_S_ VN US_S_ VN US_S_ VN US_S_ VN US_S_ VN US_S_ VN US_S_9 VN US_S_ VN US_S_ VN US_S_ VN US_S_ VN US_S_ VR US_S_ VR US_S_ VN SSUS_S_ VN SSUS_S_ VN SSUS_S_ VN SSUS_S_ VN SSUS_S_ VR SSUS_S_ VR SSUS_S_ VR SSUS_S_ VR SSUS_S_ US.V_S I/O US SS 9m N VIO S_ L9 VIO S_ M VIO S_ V VIO S_ V VIO S_ Y VIO S_ Y VIO S_ W VIO S_ VXL S VR S_ VR S_ VPL SYS_S VN HWM_S m m VIO_Z_S Trace width >= mil TRE WITH >=mil V.U/V_ VIO S--.v S I/O power.u/.v_ m VXL S-- MHZ XTL IO power G VXL_.V VR_._S--.V S ore power m N VR_.V.VS M TRE WITH >=mil m J VPL_.V 9 U/.V_.U/.V_ M.U/.V_ *.U/V_ VS.U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ *.U/V_ VS L PYT-Y-N(,).U/.V_ if support US. wake up should be change pull hi to S power VS 9 U/.V_.U/V_.U/V_ U/.V_ U/.V_ U/.V_.U/V_.U/V_ POWER VR SSUS_S : US. PHY core power Hudson-M- if support Modem wake up should be change pull hi to S power VS L PYT-Y-N(,).U/.V_ FH_VPL SSUS_S M chipset need to stuff for support US..U/V_ PROJET : VOLKS_omal " Quanta omputer Inc. Size ocument Number Rev ustom N Hudson-M POWER/GN ate: Thursday, September, Sheet 9 of

10 STRPS PINS OVERLP OMMON PS WHERE POSSILE FOR UL-OP RESISTORS. EUG STRPS V VS VS VS [] PI_LK [] PI_LK [] PI_LK [] LP_LK PI_LK PI_LK PI_LK LP_LK R K/F_ R K/F_ R *K/F_ R K/F_ [] PI_ [] PI_ [] PI_ [] PI_ [] PI_ FH has K Internal Pull Up for PI_[:] PI_ PI_ PI_ PI_ PI_ TP TP TP TP TP remove reserve pull low resistor reserve test point only. [] LP_LK LP_LK [] E_PWM E_PWM [] LK_RT LK_RT PI_ PI_ PI_ PI_ PI_ R9 *K/F_ R K/F_ R K/F_ R K/F_ R9.K_ R *.K_ PULL HIGH USE PI PLL ISLE IL UTORUN USE F PLL USE EFULT PIE STRPS ISLE PI MEM OOT EFULT EFULT EFULT EFULT EFULT REQUIRE STRPS PULL LOW YPSS PI PLL ENLE IL UTORUN YPSS F PLL USE EEPROM PIE STRPS ENLE PI MEM OOT PI_LK PI_LK PI_LK LP_LK LP_LK E_PWM LK_RT PULL HIGH LLOW PIE Gen EFULT USE EUG STRP non_fusion LOK MOE M internal E ENLE LKGEN ENLE EFULT LP ROM EFULT S PLUS MOE ENLE PULL LOW FORE PIE Gen IGNORE EUG STRP EFULT FUSION LOK MOE EFULT E ISLE EFULT LKGEN ISLE SPI ROM S PLUS MOE ISLE EFULT FH PWRG VS R K/F_ [9] PU_VRM_PG [,9] EPWROK 9 RV- RV- *.U/.V_ R *_/S FH_PWRG [] PROJET : VOLKS_omal " Quanta omputer Inc. Size ocument Number Rev ustom N Hudson-M STRP/PWRG ate: Thursday, September, Sheet of

11 V R *_/S TRVIS.V_ U/.V_.U/V_.U/V_ V R *_/S TRVIS.V U/.V_.U/V_.U/V_.V R9 *_ TRVIS.V [] PH_EIT [] PH_EILK S_S TRVIS.V [] FH_LVS_HP FH_LVS_HP R9 *_/S PRX_HP S_SL.U/V_ R9 K/F_ R9 K/F_ PH_L_TN [] PH_L_TP [] [] INT_eP_UXN [] INT_eP_UXP [] INT_eP_TXP [] INT_eP_TXN V R R INT_eP_TXP INT_eP_TXN TRVIS.V *M/F_ *M/F_.U/V_ TRVIS.V_ 9.U/V_ NX_eP_UXN.U/V_ NX_eP_UXP.U/V_.U/V_ R9 K/F_ LNEP LNEN U UX-H_N UX-H_P P_V P_GN LNEP LNEN P_V GN P_REXT RTS-G 9 HP IISL SPI_E/IRQ/MIISL IIS SPI_SO/SS/MIIS SWR_VK 9 RTS SPI_SI/SLK/MIISL SWR_LX SPI_K/SIO/MIIS SWR_V VK PWMOUT TXO- TXO- Panel_V TXO PWMIN TXO TXO TXO- TXO- TXO 9 PV L_EN PH_L_TN [] PH_L_TP [] PH_L_TN [] PH_L_TP [] PH_L_LK# [] PH_L_LK [].U/V_ PH_LVS_LON [] TRVIS.V S_SL pull high => EEPROM mode S_S pull low = > EEPROM Free mode TRVIS.V TRVIS.V R9.K_ R9 *.K/F_ R9.K/F_ S_S S_SL ddress=x U V WP S SL GN SGT-M-WMNTP TRVIS.V.U/V_ lose to Pin TRVIS.V K/F_ K/F_ R9 R99 SL S NX_PWM PV change to stuff TRVIS.V TRVIS.V.U/V_ U/.V_ L.UH/m/TLP-RM U/.V_.U/V_ TRVIS.V PH_ISP_ON [] PH_PST_PWM [] NX_PWM R9 *_ R K/F_ V.V R.k_ Q MMT9--F PU_LPWM [] SL Q NKW SL_R R *_/S SL [,] PWM_VJ [9] V ual *_ R PV change to stuff R/R MLK [,,,9] S S_R R *_/S S [,] Q NKW *_ R MT [,,,9] EE PROM R,R E OPTION R,R N PROJET : VOLKS_omal " Quanta omputer Inc. Size ocument Number Rev ustom RTS ate: Thursday, September, Sheet of

12 [] M M[..] [] M [:] [] M S# [] M S# [] M S# [] M S# [] M S# [] M LKP [] M LKN [] M LKP [] M LKN [] M KE [] M KE [] M S# [] M RS# [] M WE# [,] SM_RUN_LK [,] SM_RUN_T [] M OT [] M OT M M M M M M M M M M M M M M M M [] M QSP[:] [] M QSN[:] M M M M M M M M M M 9 M M M M M M IMM_S IMM_S SM_RUN_LK SM_RUN_T M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSN M QSN M QSN M QSN M QSN M QSN M QSN M QSN JIM /P 9 /# 9 9 S# S# K K# K K# KE KE S# RS# 9 WE# S S SL S OT OT M M M M M M M M 9 QS QS QS QS QS QS QS QS QS# QS# QS# QS# QS# 9 QS# QS# QS# P R SRM SO-IMM (P) Q Q Q Q Q Q Q Q Q Q9 Q Q Q Q Q Q Q Q Q Q9 Q Q Q Q Q Q Q Q Q Q9 Q Q Q Q Q Q Q Q Q Q9 Q Q Q Q Q Q Q Q Q Q9 Q Q Q Q Q Q Q Q Q Q9 Q Q Q Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q M Q M Q M Q M Q M Q[:] [] VREF_Q [] M EVENT# [] M RST# R VREF_ *_/S. V VREF_Q VREF_.VSUS JIM V V V V V 9 V 9 V 99 V V9 V V V V V V V V V 99 VSP N N NTEST 9 EVENT# RESET# VREF_Q VREF_ P R SRM SO-IMM (P) VTT VTT GN GN GN GN R-IMM_H=._RVS ddr-ddrrk--tpb-p-ruv GMK SOKET R SOIMM(P,H.,RVS)QON.V_R_VTT R-IMM_H=._RVS ddr-ddrrk--tpb-p-ruv GMK SOKET R SOIMM(P,H.,RVS)QON [,,,,9,,,,,,,,,,,9,,,,,] V [,,,,,,,].VSUS [,].V_R_VTT Place these aps near So-imm..U/V_ For EMI RESERVE VREF_.VSUS.V_R_VTT.VSUS U/.V_ U/.V_ P/V_ R *_/S.VSUS R_VTTREF [,] U/.V_ U/.V_ P/V_ U/.V_ U/.V_ 9 P/V_ R 9 U/.V_ 9 U/.V_ P/V_ K/F_ U/.VS_ 9 U/.VS_ 9 P/V_ U/.VS_ *U/.V_ R9 *_/S P/V_ U/.VS_ VREF_Q P/V_ R U/.VS_.U/V_ K/F_ U/.VS_ P/V_.V_R_VTT U/.VS_ 9 *P/V_ *U/.V_ SI, change to P 9 *P/V_ U/.V_ VREF_ to meet ref design U/.V_ P/V_ *.U/V_ Reserved for M suggest N VREF_Q VREF_Q PROJET : VOLKS_omal " Quanta omputer Inc. Size ocument Number Rev ustom System Memory / (.H) ate: Thursday, September, Sheet of

13 R V [] M M[..].K/F_ [] M [:] [] M S# [] M S# [] M S# [] M S# [] M S# [] M LKP [] M LKN [] M LKP [] M LKN [] M KE [] M KE [] M S# [] M RS# [] M WE# [,] SM_RUN_LK [,] SM_RUN_T [] M OT [] M OT M M M M M M M M M M M M M M M M [] M QSP[:] [] M QSN[:] M M M M M M M M M M 9 M M M M M M IMM_S IMM_S M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSN M QSN M QSN M QSN M QSN M QSN M QSN M QSN JIM /P 9 /# 9 9 S# S# K K# K K# KE KE S# RS# 9 WE# S S SL S OT OT M M M M M M M M 9 QS QS QS QS QS QS QS QS QS# QS# QS# QS# QS# 9 QS# QS# QS# P R SRM SO-IMM (P) Q Q Q Q Q Q Q Q Q Q9 Q Q Q Q Q Q Q Q Q Q9 Q Q Q Q Q Q Q Q Q Q9 Q Q Q Q Q Q Q Q Q Q9 Q Q Q Q Q Q Q Q Q Q9 Q Q Q Q Q Q Q Q Q Q9 Q Q Q Q M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q M Q M Q9 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q[:] [] VREF_Q [,] M EVENT# [] M RST# R *_/S VREF_. V M EVENT# VREF_Q VREF_.VSUS JIM V V V V V 9 V 9 V 99 V V9 V V V V V V V V V 99 VSP N N NTEST 9 EVENT# RESET# VREF_Q VREF_ P R SRM SO-IMM (P) VTT VTT GN GN GN GN R-IMM_H=._ST ddr-ddrsk--tpb-p-ldv GMK SOKET R SOIMM(P,H.,ST)QON.V_R_VTT R-IMM_H=._ST ddr-ddrsk--tpb-p-ldv GMK SOKET R SOIMM(P,H.,ST)QON [,,,,9,,,,,,,,,,,9,,,,,] V [,,,,,,,].VSUS [,].V_R_VTT Place these aps near So-imm. For EMI VREF_.VSUS.V_R_VTT.VSUS U/.V_ U/.V_ P/V_ R *_/S R_VTTREF [,] 9 U/.V_ U/.V_ 9 P/V_ 9 U/.V_ U/.V_ P/V_ U/.V_ U/.V_ P/V_ U/.VS_ U/.VS_ P/V_ U/.VS_ *U/.V_ P/V_ 9 U/.VS_ VREF_Q 9 P/V_ U/.VS_.U/V_ 9 P/V_ U/.VS_ U/.VS_ P/V_ 9 *U/.V_ U/.V_ U/.V_ VREF_ 99 9.U/V_ P/V_ *.U/V_ V.U/V_.U/.V_ PROJET : VOLKS_omal " Quanta omputer Inc. N Size ocument Number Rev ustom System Memory / (9.H) ate: Thursday, September, Sheet of

14 PRT F 9 U FOR Mars support Gne: cap nees use.u FOR Thems: cap need use.u for Gen [] PEG_TXP [] PEG_TXN Y PIE_RXP PIE_RXN PIE_TXP PIE_TXN Y Y _PEG_RXP _PEG_RXN *.U/V_ *.U/V_ PEG_RXP [] PEG_RXN [] [] PEG_TXP [] PEG_TXN Y W PIE_RXP PIE_RXN PIE_TXP PIE_TXN W W _PEG_RXP _PEG_RXN 9 9 *.U/V_ *.U/V_ PEG_RXP [] PEG_RXN [] [] PEG_TXP [] PEG_TXN W V PIE_RXP PIE_RXN PIE_TXP PIE_TXN U U _PEG_RXP _PEG_RXN *.U/V_ *.U/V_ PEG_RXP [] PEG_RXN [] [] PEG_TXP [] PEG_TXN V U PIE_RXP PIE_RXN PIE_TXP PIE_TXN U U9 _PEG_RXP _PEG_RXN *.U/V_ *.U/V_ PEG_RXP [] PEG_RXN [] [] PEG_TXP [] PEG_TXN U T PIE_RXP PIE_RXN PIE_TXP PIE_TXN T T _PEG_RXP _PEG_RXN 9 *.U/V_ *.U/V_ PEG_RXP [] PEG_RXN [] [] PEG_TXP [] PEG_TXN T R PIE_RXP PIE_RXN PIE_TXP PIE_TXN T T9 _PEG_RXP _PEG_RXN 9 *.U/V_ *.U/V_ PEG_RXP [] PEG_RXN [] [] PEG_TXP [] PEG_TXN R P PIE_RXP PIE_RXN PIE_TXP PIE_TXN P P _PEG_RXP _PEG_RXN 99 9 *.U/V_ *.U/V_ PEG_RXP [] PEG_RXN [] [] PEG_TXP [] PEG_TXN P N PIE_RXP PIE_RXN PIE_TXP PIE_TXN P P9 _PEG_RXP _PEG_RXN 9 9 *.U/V_ *.U/V_ PEG_RXP [] PEG_RXN [] N M PIE_RXP PIE_RXN PIE_TXP PIE_TXN N N For Mars N pin : N,M,M,L,L,K,K,J,J H,H,G,G,F,F,E M L L K K J PIE_RX9P PIE_RX9N PIE_RXP PIE_RXN PIE_RXP PIE_RXN PI EXPRESS INTERFE PIE_TX9P PIE_TX9N PIE_TXP PIE_TXN PIE_TXP PIE_TXN N N9 L L L L9 FOR Mars N pin : N,N,N,N9,L,L,L,L9,K,K J,J,K,K9,H,H J H PIE_RXP PIE_RXN PIE_TXP PIE_TXN K K H G PIE_RXP PIE_RXN PIE_TXP PIE_TXN J J G F PIE_RXP PIE_RXN PIE_TXP PIE_TXN K K9 Mars/ helsea Only : Stuff Ra o not install For Thames F E PIE_RXP PIE_RXN PIE_TXP PIE_TXN H H R Ra *.9K/F_.V_VG [] LK_VG_P [] LK_VG_N LK_VG_P LK_VG_N LOK PIE_REFLKP PIE_REFLKN Install for Thames ONLY: Stuff Rb o not install for helsea Install for Mars/ helsea Ra R9 *K/F_ H PEGX_RST# TEST_PG PERST LIRTION PIE_LR_TX PIE_LR_RX Y Y9 PIE_LRP PIE_LRN R R Rb Rc *.K/F_ *K/F_ Install k for Thames Install k for Mars.V_VG *MRS_M_PRO V helsea/mrs Thames Ra.9K n/a [] GPU_RST# [] VG_RST R *_ GPU_HIN_RST# *TSHFU U *.U/V_ R PEGX_RST# *K_ Rb Rc n/a.k K K.V_VG [,,9,].V_VG PROJET : VOLKS_omal " Quanta omputer Inc. N Size ocument Number Rev ustom Mars_PIE_Interface ate: Thursday, September, Sheet of

15 MEM_I[:] Vendor Type Vendor P/N GPIO GPIO PWRNTL PWRNTL Hynix- (VEG) Mx *, 9Mhz HTQGFR- Micron- G die Mx *, 9Mhz MTJMJT-G:G Samsung- G die Mx *, 9Mhz KWGG- Hynix- (VEG) Mx *, 9Mhz HTQGFR- Micron- die Mx *, 9Mhz MTJMH-G: Samsung- die Mx *, 9Mhz KWG-H Reserve Reserve Reserve Hynix- (VEG) Mx *, 9Mhz HTQGFR- GPIO GPIO GPIO Thames XT PWRNTL PWRNTL PWRNTL V-ORE.V.9V.V.V.V.V V_ELY [9] [9] R9 GPUT_LK GPUT_T R *.K/F_ *.K/F_ For Mars only : R/W/R/R/U: all N pin.v_vg R9 R R R Memory I R R *K/F_ *K/F_ *K/F_ *K/F_ *_ *_ MEM_I MEM_I MEM_I MEM_I 9 9 J K R U P W R R U U W P W U R W U T V N V9 T9 R W U P V T R W U P MUTI GFX GENLK_LK GENLK_VSYN SWPLOK SWPLOK VPNTL_MVP_ VPNTL_MVP_ VPNTL_ VPNTL_ VPNTL_ VPLK VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_9 VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_9 VPT_ VPT_ VPT_ VPT_ U PRT F 9 P P P TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN U V T R U V T R R T9 V U R T T U U V T R U V T R U T9 T R For Mars only : P to Port: all N pin V_ELY R *K/F_ GPIO LKREQb ccess to SMus ans S/SL is mandatory on all designs dd test points on SMus and S/SL for debug R *.K/F_ V_ELY R *.K/F_ TP TP9 GPUT_LK GPUT_T J H K J SMLK SMT SL S I SMus P TXP_PP TXM_PN TXP_PP TXM_PN U V T R Mars / helsea : N must be short to gnd [,,,9] [,,,9] MT MLK R9 R R R R R R9 MT MLK *K/F_ *K/F_ *K/F_ *K/F_ *K/F_ *K/F_ *K/F_ GPIO GPU_TRST GPU_TI GPU_TMS GPU_TK TEMP_FIL Q *NW--F ual SM_GPU_T ual GPU_PROHOT# R R R9 Q *NW--F V_ELY *.K/F_ SM_GPU_LK */F_ *.K/F_ [] [,] [] [] [] [9] [] GPIO GPIO GPIO GPIO9, are N on Thems/ whistler/ Seymour.V_VG [] [] [] GPU TT VI_GPIO GFX_ORE_NTRL [] GPIO GFX_ORE_NTRL [] GPIO GFX_ORE_NTRL GFX_ORE_NTRL GFX_ORE_NTRL R R [] TP R GPU_PROHOT# TP *99/F_ *9/F_ TP TP *_ R.V_VREFG GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO HMI_HP GFX_ORE_NTRL GFX_ORE_NTRL VG_LERT HP TEMP_FIL GFX_ORE_NTRL GPIO LKREQb *_ H H N H J K J H J K L M M M K G N M L J K N G G J9 K9 J K J H H K H GENERL PURPOSE I/O GPIO_ GPIO_ GPIO_ GPIO TT GPIO_ GPIO LON GPIO ROMSO GPIO_9_ROMSI GPIO ROMSK GPIO_ GPIO_ GPIO_ GPIO HP GPIO PWRNTL_ GPIO_ GPIO THERML_INT GPIO HP GPIO_9_TF GPIO PWRNTL_ GPIO_ GPIO ROMS LKREQ GPIO_9 GPIO_ GENERI GENERI GENERI GENERI GENERIE_HP GENERIF_HP GENERIG_HP E_ HP VREFG MLPS R N# G N# N# HSYN VSYN RSET V Q VI I N# N# N# N# N# N# N# N# N#9 N_TSQ PS_ PS_ PS_ 9 E F E E V U F 9 G F M G R V Thames INSTLL Ra,Rb. o not install for Mars/ helsea PS_ should be tied to GN on Thames R R Ra Rb PS_ PS_ PS_ *99/F_.V_V_Q *_ *_ V TP TP TP TP TP TP.V_V_Q PS_,PS_, PS_ are N on Thames o not install for Thames IT => IT PS => PS => PS => PS_.V_VG R *.K_ PS_.V_VG R *.K_ Thermal Solution(lose to GPU) 9 *.U/V_ TP L PX_EN O PS_ PS_ TP PS => R *K_ *.U/V_ R *K_ *.U/V_ 9 *.U/V_ U SM_GPU_LK SLK V V_ELY SM_GPU_T GPU_THERM S XP LERT# XN V_ELY R *K/F_ GN *P/V_ OVERT# GPU_THERM [] GPU_OVT# *G-P Main:L9 G-P(9h) nd:l EM--ZL-TR(9h) Reserve for Power Play GFX_ORE_NTRL R *.K/F_.V_TSV GFX_ORE_NTRL R *.K/F_ *HKF-T(,M).V(m TSV).V_VG GFX_ORE_NTRL R *.K/F_ L GFX_ORE_NTRL R *.K/F_ GFX_ORE_NTRL R *.K/F_ *U/.V_ *U/V_ *.U/V_ Ra GFX_ORE_NTRL R9 *K/F_ V_ELY Rb GFX_ORE_NTRL R *K/F_ For Mars: Stuff Ra only=> V.V VI_GPIO R *.K/F_ For Thems: Stuff Ra, Rb=> V.V V_ELY R *.K/F_ TESTEN TP R *K/F_ GPU_TRST M TP GPU_TI N TP GPU_TK K TP GPU_TMS L TP GPU_TO M TP GPU_THERM F9 GPU_THERM G9 GPIO K [] GPIO L TP.V_TSV J J EUG TESTEN JTG_TRST JTG_TI JTG_TK JTG_TMS JTG_TO THERML PLUS MINUS GPIO FO TS_ TSV TS *MRS_M_PRO /UX LK T UXP UXN LK T UXP UXN LK_UXP T_UXN LK_UXP T_UXN LK_UXP T_UXN LK_UXP T_UXN VGLK VGT For Mars:N pin L, M, L9, M9, N, M, K, K9 M N M L M9 L9 N M L M L9 M9 N M K K9 J J PV, change to ohm.v_vg L9 L PV, change to ohm nalog Power V m *_ *U/.VS_ igital Power. VI m *_ *U/.VS_ PV, change to NI *U/.V_ *U/.V_.V_V_Q 9 *.U/V_ *.U/V_ V [,,,9,].V_VG [,,9,].V_VG [,] V_ELY PS_.V_VG.V_VG V_ELY.V_VG.V_VG R9 R *_ *_ PS_ R9 R *.K/F_ *.U/V_ *.K/F_ *.U/V_ N PROJET : VOLKS_omal " Quanta omputer Inc. Size ocument Number Rev ustom Mars_Main & GN Thursday, September, ate: Sheet of

16 For Mars only : G N UF Fo Mars/ helsea hange La, Lb ead to ohm For Thems: La,Lb: XPG/LMPGSN/_ La.V_PLL_PV.V_VG.V_VG.V_VG.V_VG.V_VG Lb L.V(m PLL_V) L L9 L *_.V(m PLL_V) *_ *LMPGSN/_ L *U/.V_ *U/.V_ *U/.V_ *U/.V_ *U/.V_ isplay Phase Lock Loop Power PLL_PV m.v_pll_pv.v_pll_v PLL_V m *U/.V_ *HKF-T(,M) *LMPGSN/_ *U/.V_ *U/.V_.V_PLL_V PLL_P.V_MPLL_PV MPLL_PV m.v_mpll_pv.v_spll_pv SPLL_PV m.v_spll_pv.v_spll_v SPLL_V m *U/.V_ *U/.V_ *.U/V_ *.U/V_ *.U/V_ *.U/V_ *.U/V_.V_PLL_PV.V_SPLL_V SPLL_P R R Ra *_ Rb *_ Memory Type R GR M N N reserve Ra, Rb for future SI H H M N9 N F F PLL_PV PLL_V PLL_P MPLL_PV MPLL_PV SPLL_PV SPLL_V SPLL_P N_XTL_PV N_XTL_P *MRS_M_PRO -MHz (± ppm) crystal connected to XTLIN/XTLOUT, or -MHz (. V) oscillator connected to XTLIN. -MHz (. V) oscillator connected to XO_IN, and -MHz (. V) oscillator connected to XO_IN. (y default, this clock should not be spread since internal spreading is used.) PRT 9 F 9 PLLS/XTL UI XTLIN XTLOUT XO_IN XO_IN LKTEST LKTEST V U W W K L EVG-XTLI EVG-XTLO R9 LKTEST LKTEST R *M_ Ra *_ EVG-XTLI *.U/V_ ebug only, for clock observation, if not needed, NI R9 *./F_ *P/V_ Y *MHZ *P/V_ route ohms single-ended/ ohms diff and keep short For Mars: Stuff Ra only 9 *.U/V_ R *./F_ 9 PIE_ E9 PIE_ F PIE_ F9 PIE_ G PIE_ G PIE_ H PIE_ H PIE_ H9 PIE_ J PIE_ J PIE_ K PIE_ K PIE_ K9 PIE_ L PIE_ L PIE_ M PIE_ M9 PIE_ N PIE_ N PIE_ P PIE_ P PIE_ P9 PIE_ R PIE_ T PIE_ T PIE_ T9 PIE_ U PIE_ U PIE_ V PIE_ V9 PIE_ W PIE_ W PIE_ Y PIE_ Y9 PIE_ F GN F GN F9 GN F GN F GN F GN F GN F9 GN F GN F GN F GN F9 GN G GN G GN H9 GN J GN J GN J GN J GN K GN K GN L GN L GN L GN L GN L GN L GN M GN M GN M GN N GN N GN N GN N GN N GN N GN N GN R GN R GN R GN R GN R GN R GN R GN R GN T GN T GN T GN T GN T GN T GN T GN U GN U GN U GN U GN U GN U GN U GN U GN V GN V GN V GN V GN V GN V GN W GN W GN Y GN Y GN Y GN Y GN Y GN Y GN PRT F 9 GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN 9 GN E GN E GN F GN F GN F GN F GN G GN G GN G GN G GN G GN G9 GN H GN J GN J GN J GN J GN J GN K GN K GN K GN L GN L GN L GN L GN L GN L GN L GN L GN L GN L GN M GN M GN M9 GN N GN N GN N GN N GN N GN P GN P GN P9 GN R GN GN GN GN GN 9 GN GN GN GN GN 9 GN GN GN GN 9 GN GN 9 GN E GN E GN F GN F _MEH 9 _MEH W _MEH W9 *MRS_M_PRO [,,9,].V_VG [,,9,].V_VG.V_VG.V_VG PROJET : VOLKS_omal " Quanta omputer Inc. N Size ocument Number Rev ustom Mars_XTL & GN Thursday, September, ate: Sheet of

17 PRT F 9 LVS ONTROL UG VRY_L IGON K J Fo Mars only: F, G: N pin Fo Mars only: N, P: N pin TXLK_UP_PFP TXLK_UN_PFN TXOUT_UP_PFP TXOUT_UN_PFN K L J K ONFIGURTION STRPS -- SEE EH TOOK FOR STRP ETILS LLOW FOR PULLUP PS FOR THESE STRPS N IF THESE GPIOS RE USE, THEY MUST NOT ONFLIT URING RESET STRPS MLPS GPIO PIN ESRIPTION OF EFULT SETTINGS efault Setting LVTMP TXOUT_UP_PFP TXOUT_UN_PFN TXOUT_UP_PFP TXOUT_UN_PFN TXOUT_UP TXOUT_UN TXLK_LP_PEP TXLK_LN_PEN TXOUT_LP_PEP TXOUT_LN_PEN TXOUT_LP_PEP TXOUT_LN_PEN H J G H F G P R W U R U9 MLPS_ISLE TX_PWRS_EN TX_EEMPH_EN IF_GEN_EN_ IF_VG IS N PS_[] PS_[] PS_[] PS_[] GPIO FO GPIO GPIO GPIO GPIO9 Enable MLPS, N for Thames/Whistler/Seymour : Enable MLPS, disable GPIO PINSTRP : isable MLPS, enable GPIO PINSTRP Transmitter Power Savings Enable : % Tx output swing : Full Tx output swing PIE Transmitter e-emphasis Enable : Tx de-emphasis disabled : Tx de-emphasis enabled PIE Gen Enable (NOTE: RESERVE for Thames/Whistler/Seymour) : GEN not supported at power-on : GEN supported at power-on VG ontrol : VG controller capacity enabled : VG controller capacity disabled (for multi-gpu) X X X *MRS_M_PRO TXOUT_LP_PEP TXOUT_LN_PEN TXOUT_LP TXOUT_LN P R N P V_ELY ROMIFG[:] IOS_ROM_EN PS_[..] PS_[] GPIO[:] GPIO Serial ROM type or Memory perture Size Select If GPIO =, defines memory aperture size If GPIO, defines ROM type Kbit MP (ST) Mbit MP (ST) - Mbit MP (ST) Mbit MP (ST) Mbit MP (ST) Kbit PmLV (hingis) - Mbit PmLV (hingis) Enable external IOS ROM device : isabled : Enabled XXX X [] GPIO [] GPIO [] GPIO GPIO GPIO GPIO R9 R9 R *K/F_ *K/F_ *K/F_ U[] U[] N N HSYN VSYN - No audio function udio for P only - udio for P and HMI if dongle is detected udio for both P and HMI HMI must only be enabled on systems that are legally entitled. It is the responsibility of the system designer to ensure that the system is entitled to support this feature. XX [] GPIO GPIO R *K/F_ E_IS PS_[] GENLK_VSYN Enable E function. Reserved for Thames/Whistler/Seymour : isabled : Enabled X [,] GFX_ORE_NTRL GPIO R *K/F_ [] GPIO GPIO R *K/F_ NOTE: LLOW FOR PULLUP PS FOR THE RESERVE STRPS UT O NOT INSTLL RESISTOR IF THESE GPIOS RE USEE, THEY MUST KEEP LOW N NOT ONFLIT URING RESET RESERVE RESERVE RESERVE RESERVE PS_[] PS_[] N N GENLK_LK GPIO GPIO GENERI Reserved Reserved Reserved Reserved (for Thames/Whistler/Seymour only) [] Memory perture size GPIO9 IOSROM GPIO M M M M M G G G GPIO Ra R *K/F_ Rb R *K/F_ Mars : stuff Ra=> disable MLPS helsea : stuff Rb=> enable MLPS GPIO GPIO GPIO ROMIFG ROMIFG ROMIFG It is a shared pin strap with ONFIG[:] if IOS_ROM_EN is set to. U_PORT_ONN_PINSTRP[] U_PORT_ONN_PINSTRP[] U_PORT_ONN_PINSTRP[] VG_ORE VG_ORE.V_VG.V_elay.V_VG.V_VG V VI VR VR VR PS_[] PS_[] PS_[] V_T N N STRPS TO INITE THE NUMER OF UIO PLE ISPLY OUTPUTS = usable endpoints XXX N = usable endpoints = usable endpoints = usable endpoints = usable endpoints = usable endpoints = usable endpoints = all endpoints are usable Power Up/own Sequence ms ms PROJET : VOLKS_omal " Quanta omputer Inc.

18 .V_VG I/O power for the memory interface..v_vg V_VG Support O Mode GR 9MHz *U/.V_ *U/.VS_ 9 *U/.VS_ L9 L *U/.V_ L *_ *U/.V_ *U/.VS_ *U/.VS_ *_ *_ *U/.V_ *U/.VS_ *U/.VS_ *U/.VS_ *U/.V_ PV, change to NI *U/.V_ *U/.VS_ *U/.VS_ *U/.V_ VR m VR m *U/.VS_ *U/.V_ *U/.V_ *U/.V_ *U/.V_ Route as differential pair and connect to the VSEN and RTN pins of the VR through a decoupling and termination circuit. [] VGPU_ORE_SENSE [] 9 *U/.V_ *U/.VS_.V_V_T *U/.V_ *U/.V_ VR *U/.V_ *.U/V GPU_SENSE *U/.V_ *U/.VS_ *U/.V_ *U/.V_ *.U/V_ TP V_ELY *.U/V_ F G J K L9 G G G G G G G9 H J J9 K K K L L L L L L M N P R U U Y Y F F G G F F G G F F F F G G G F G H9 VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR MEM I/O LEVEL TRNSLTION V_T V_T V_T V_T VR VR VR VR VR VR VR VR VR VR VR VR I/O VP VOLTGE SENESE F_V F_VI F_GN *MRS_M_PRO PRT F 9 UE PIE O ORE ISOLTE ORE I/O N_PIE_VR N_PIE_VR N_PIE_VR N_PIE_VR N_PIE_VR N_PIE_VR N_IF_V N_IF_V PIE_PV PIE_V PIE_V PIE_V PIE_V PIE_V PIE_V PIE_V PIE_V PIE_V PIE_V PIE_V PIE_V IF_V IF_V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V VI VI VI VI VI VI VI VI VI VI VI VI VI VI VI VI VI VI VI VI VI VI W Y V W9 G G H9 H J9 J L M N R T U N T F F F G G H H H M N R R R R T T T T U U U U U V V V V V Y Y Y Y Y Y M M M M N N N N N R R R T T V Y IF_V Mars N *.U/V_ *.U/V_ *.U/V_ Must always be connected to PIE_V for Mars *U/.V_ *U/.V_ *U/.V_ R *U/.VS_ *U/.VS_ 9 *U/.V_ *U/.VS_ VG_ORE *U/.V_ *U/.V_ *U/.V_ *_ *U/.V_ 9 *U/.VS_.V_VG *U/.V_ *U/.V_ *U/.VS_ VI *U/.V_ *U/.V_ *U/.V_ 99 *U/.VS_ *U/.VS_ 9 *U/.V_ *U/.V_ *U/.V_ *U/.VS_ 9 *U/.V_ PIe igital Power Supply PIE_V (GEN.) PIE_V (GEN.) 9 *U/.V_ *U/.V_ *U/.V_ *U/.V_ *U/.VS_ *U/.V_ *U/.V_ *U/.V_ *U/.V_ *U/.V_ *U/.VS_ 9 *U/.VS_ *U/.V_ 9 *U/.V_ 9 *U/.V_ *U/.V_ 9 *U/.V_ 9 *U/.VS_ [,,,] [,,9,] [,,9,] [] [] 9 *U/.V_ *U/.V_ *U/.V_ *U/.V_ *U/.V_ Reserve for rop *U/.V_ 9 *U/.V_ *U/.V_ *U/.V_ *u_.v_.v_vg.v_vg.v_vg V_VG VG_ORE *U/.V_ *U/.V_ *U/.V_ *U/.V_ *U/.V_.V_VG *U/.V_ *U/.V_ *U/.VS_ *U/.V_ *U/.V_ *U/.V_.V_VG.V_VG.V_VG V_VG VG_ORE.V_VG *U/.VS_ IF_V *U/.VS_ *U/.V_ *U/.V_ *U/.VS_ Note.. No O Support :IF_V shorts with V (Install Ra) PX_EN =, for Normal Operation PX_EN =, for O MOE. O Support: Refer to the O reference schematics/pplication note for detail about IF_V Rail if O is Supported (Uninstall Ra) PROJET : VOLKS_omal " Quanta omputer Inc. N Size ocument Number Rev ustom Mars_Power & O Thursday, September, ate: Sheet of