AMD Champlain S1G4 Processor 35mm X 35mm 638P (PGA) 35W PAGE 2,3,4 NORTH BRIDGE RS880M A11

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1 P STK UP LYER : TOP LYER : GN LYER : IN LYER : IN LYER : V LYER : OT IV@ -----> igpu EV@ -----> dgpu SPE@ -----> Option Notice MHz LN ROOM PIE-LN M RJ P (//) R- SOIMM R- SOIMM PGE PGE PGE PGE Mini PI-E ard (Wireless LN) R channel R channel PU Sideand TemperatureSense I PI-Expresss P PGE M hamplain SG Processor mm X mm P (PG) W PGE,, HT NORTH RIGE RSM TP: W. ~.V -LINK GFX Engine: MHz PGE,,, PU THERML SENSOR (Reserve Only) PGE PU_LK NGFX_LK NGPP_LK SLINK_LK PWM FN SH. mm X mm PGE,,,,, PGE PGE PU (PROHOT) E.. (PUFN#) HMI RT LVS MHz From S LK GEN SM PGE PGE PGE.KHz PGE LK_PI_ PLK_EUG HRGER (ISL) PGE M PU ORE (ISL) PGE N_ORE (UPQ) PGE.V/R.V(RT) PGE SYSTEM V/V (RT) PGE PU N ST - H ST M PGE ST - O ST M PGE LK_PI_ PU Sideand TemperatureSense I Winbond K NPEL No PI I/F SOUTH RIGE SM P P P US. Port lue Tooth Web-amera on board x PGE PGE PGE P P Mini ard ardreader PLK_EUG WLN & ebug U TP:.W PGE PGE PGE,,,, LP zalia udio OE RTL LX PGE PGE MHz FF US OR US. Ports x PGE.V(UPQ) PGE ischarge /Thermal protec PGE Keyboard TouchPad PGE PGE SPI ROM igital MI PGE UIO ONN Speaker N (H.P./ MI) PGE PGE ocument Number lock iagram ate: Monday, May, Sheet of

2 SG (PU).V.V W/S= mil/mil PUV PU_LT_RST# /F_ R.V L LMPGSN(_)_ PUV PU_LT_REQ#_PU */F_ R.V@..V_VLT.V@m LS-M-N PU LK PU_LT_STOP# /F_ R.U/.V_.U/.V_.u/.V_ p/v_ *u/.v_ R *SHORT_P [] HT_INP [] HT_INN [] HT_INP [] HT_INN [] HT_INP [] HT_INN [] HT_INP [] HT_INN [] HT_INP [] HT_INN [] HT_INP [] HT_INN [] HT_INP [] HT_INN [] HT_INP [] HT_INN [] HT_INP [] HT_INN [] HT_INP [] HT_INN [] HT_INP [] HT_INN [] HT_INP [] HT_INN [] HT_INP [] HT_INN [] HT_INP [] HT_INN [] HT_INP [] HT_INN [] HT_INP [] HT_INN [] HT_LKINP [] HT_LKINN [] HT_LKINP [] HT_LKINN [] HT_TLINP [] HT_TLINN [] HT_TLINP [] HT_TLINN FOX PZ-R-F G^ I SOKET SM P S(P.,H.) MLX - G^ I SOKET SM P S(P.,H.) TY -- G^ I SOKET SM P S(P.,H.) u/.v_ u/.v_.u/.v_ p/v_ HT_INP HT_INN HT_INP HT_INN HT_INP HT_INN HT_INP HT_INN HT_INP HT_INN HT_INP HT_INN HT_INP HT_INN HT_INP HT_INN HT_INP HT_INN HT_INP HT_INN HT_INP HT_INN HT_INP HT_INN HT_INP HT_INN HT_INP HT_INN HT_INP HT_INN HT_INP HT_INN HT_LKINP HT_LKINN HT_LKINP HT_LKINN HT_TLINP HT_TLINN HT_TLINP HT_TLINN U.V_VLT.V_VLT VLT_.V_VLT VLT_.V_VLT VLT_ VLT_ E L_IN_H E L_IN_L E L_IN_H F L_IN_L G L_IN_H G L_IN_L G L_IN_H H L_IN_L J L_IN_H K L_IN_L L L_IN_H L L_IN_L L L_IN_H M L_IN_L N L_IN_H N L_IN_L E L_IN_H F L_IN_L F L_IN_H F L_IN_L G L_IN_H H L_IN_L H L_IN_H H L_IN_L K L_IN_H K L_IN_L L L_IN_H M L_IN_L M L_IN_H M L_IN_L N L_IN_H P L_IN_L J L_LKIN_H J L_LKIN_L J L_LKIN_H K L_LKIN_L N L_TLIN_H P L_TLIN_L P L_TLIN_H P L_TLIN_L HT LINK SOKET PIN VLT_ E VLT_ E E VLT_ E VLT_ L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_OUT_H W W L_OUT_L L_OUT_H V L_OUT_L U U L_OUT_H L_OUT_L U T L_OUT_H L_OUT_L R L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_OUT_H L_OUT_L Y L_OUT_H W L_OUT_L L_OUT_H V V L_OUT_L L_OUT_H V U L_OUT_L L_OUT_H T L_OUT_L T L_LKOUT_H Y W L_LKOUT_L Y L_LKOUT_H Y L_LKOUT_L R L_TLOUT_H R L_TLOUT_L T L_TLOUT_H R L_TLOUT_L.V_VLT u/.v_.v_vlt.u/.v_.v_vlt p/v_.v_vlt HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_LKOUTP HT_LKOUTN HT_LKOUTP HT_LKOUTN HT_TLOUTP HT_TLOUTN HT_TLOUTP HT_TLOUTN HT_OUTP [] HT_OUTN [] HT_OUTP [] HT_OUTN [] HT_OUTP [] HT_OUTN [] HT_OUTP [] HT_OUTN [] HT_OUTP [] HT_OUTN [] HT_OUTP [] HT_OUTN [] HT_OUTP [] HT_OUTN [] HT_OUTP [] HT_OUTN [] HT_OUTP [] HT_OUTN [] HT_OUTP [] HT_OUTN [] HT_OUTP [] HT_OUTN [] HT_OUTP [] HT_OUTN [] HT_OUTP [] HT_OUTN [] HT_OUTP [] HT_OUTN [] HT_OUTP [] HT_OUTN [] HT_OUTP [] HT_OUTN [] HT_LKOUTP [] HT_LKOUTN [] HT_LKOUTP [] HT_LKOUTN [] HT_TLOUTP [] HT_TLOUTN [] HT_TLOUTP [] HT_TLOUTN [] Keep trace from resisor to PU within." keep trace from caps to PU within." LK_PU_LKP_ R [] LK_PU_LKP_PR [] LK_PU_LKN_PR.VSUS /F_ LK_PU_LKN_ [] PU_LT_RST# [,] PU_PWRG [,] PU_LT_STOP#.V_VLT [] [] PU_SI PU_SI T [] PU_V_F_H [] PU_V_F_L W/S= mil/mil PUV PUV PUTEST PUTEST PUTEST PU_LERT#./F_ PU_HTREF./F_ PU_HTREF place them to PU within." PU_RY PU_TMS PU_TK PU_TRST# PU_TI PU_SV PU_SV PU_THERMTRIP_L# PU_PROHOT_L# H_THRM H_THRM VIO_F_H VIO_F_L [] PU_V_F_H Y V_F_H VN_F_H H PU_VN_F_H [] T V_F_L VN_F_L G PU_VN_F_L [].VSUS R R K_ */F_ R R R R p/v_ p/v_ T T T T T PUV m LK_PU_LKP_ LK_PU_LKN_ U F V F V LKIN_H LKIN_L PU_LT_RST# PU_PWRG RESET_L PU_LT_STOP# PWROK F PU_LT_REQ#_PU LTSTOP_L LTREQ_L F SI F SI E LERT_L R HT_REF P HT_REF F V_F_H E V_F_L G RY TMS TK TRST_L F TI TEST H TEST G TEST /F_ PUTESTH E /F_ PUTESTL TEST_H E place them to PU within." TEST_L PUTEST PUTEST TEST F PUTEST TEST E PUTEST TEST E PUTEST TEST PUTEST TEST F TEST TEST TEST RSV RSV RSV RSV RSV SOKET PIN VSS M RSV W SV SV F THERMTRIP_L PROHOT_L MEMHOT_L THERM W THERM W VIO_F_H W VIO_F_L Y E PU_REQ# R REQ_L PU_TO TO E TEST_H J H TEST_L TEST TEST E F TEST TEST TEST TEST K TEST TEST_H TEST_L H RSV H RSV RSV RSV RSV PUTEST PUTEST PUTEST PUTEST PUTESTH PUTESTL T T T T T /F_ T T T T R./F_.VSUS V R K/F_ NTR_VREF.u/V_ R.K/F_.VSUS NTR_VREF [] R K_ Serial VI.V.VSUS.VSUS PU_SV PU_SV PU_PWRG R R R /F_ K_ K_ PU_SV [] PU_SV [] VFIX MOE VI Override ircuit SV SV Voltage Output.V.V.V.V.VSUS.VSUS R /F_ PU_PROHOT_L# Q MMT PM_THERM# [] R R R *_ *_ *_ [] HWPG R Q SS_NL/SOT K_ PU_PROHOT# [] HT onnector PUTEST PUTEST PUTEST PUTEST PUTEST PUTEST PUTEST PUTEST PUTEST PUTEST R R R R R R R R R R K_ K_ K_ K_ K_ */F_ */F_ K_ K_ K_.VSUS R K_ PU_THERMTRIP_L# Q MMT SYS_SHN# [,] ocument Number SG HT,TL I/F / ate: Monday, May, Sheet of

3 E W PU support.v W PU support.v VR=>. VR=>.V support / R VR= >.V support / / R PU_VR PU_VR PU_VR U [] M Q[..].VSUS PLE THEM LOSE TO VR MEM:M/TRL/LK VR W U PU WITHIN " VR VR M Q[..] [] VR VR MEM:T M Q M Q.VSUS VR VR R M Q M_T M_T G M Q M_ZP VR F K/F_ M Q M_T M_T F R./F_ M Q M_ZN MEMZP R./F_ E PU_VTT_SENSE M Q M Q MEMZN VR_SENSE Y R *_ M_T M_T H M Q M_T M_T G G M Q MEMVREF_PU M Q M_T M_T H M Q [] M RST# H M_RESET_L MEMVREF W E u/.v_ M Q M_T M_T H M Q M Q M_T M_T M Q [] M OT T M_OT M_RESET_L M RST# [] M Q M Q [] M OT V R M_T M_T E M_OT M Q M_T M_T H U M Q M_OT M_OT W M OT [] V M Q M Q M_OT M_OT W K/F_ M_T M_T E M OT [] P/V_ M Q M Q M_OT Y.u/V_ M_T M_T E M Q M_T M_T H M Q [] M S# T M_S_L M Q M_T M_T E M Q [] M S# U M_S_L M_S_L V M S# [] M Q M_T M_T F U M Q M_S_L M_S_L W M S# [] M Q M_T M_T V M Q M_S_L M_S_L U M Q M_T M_T G M Q M Q M_T M_T G M Q [] M KE J M_KE M_KE J M KE [] M Q M_T M_T M Q [] M KE J M_KE M_KE H M KE [] M Q M_T M_T M Q M Q M_T M_T E M Q [] M LKP N M_LK_H M_LK_H P M LKP [] M Q M_T M_T E M Q [] M LKN N M_LK_L M_LK_L R M LKN [] M Q M_T M_T F E M Q M_LK_H M_LK_H M Q M_T M_T F M Q M_LK_L M_LK_L M Q M_T M_T Y M Q M_LK_H M_LK_H F E M Q M_T M_T F M Q M_LK_L M_LK_L F E M Q M_T M_T F M Q [] M LKP P M_LK_H M_LK_H R M LKP [] G M Q M_T M_T H M Q [] M LKN P M_LK_L M_LK_L R M LKN [] G M Q M_T M_T J M Q M N M M Q M_T M_T E M Q M M_ M_ P M M M Q M_T M_T E M Q M M_ M_ N G N M M Q M_T M_T H M Q M M_ M_ P G M M M Q M_T M_T H M Q M M_ M_ N M M M Q M_T M_T Y M Q M M_ M_ N L M M Q M_T M_T M Q M M_ M_ L M M M Q M_T M_T M Q M M_ M_ N E L M M Q M_T M_T M Q M M_ M_ L L M M Q M_T M_T W M Q M M_ M_ M K M M Q M_T M_T W M Q M M_ M_ K R M M Q M_T M_T Y M Q M M_ M_ T E L M M Q M_T M_T M Q M M_ M_ L K M M Q M_T M_T Y M Q M M_ M_ L V M M Q M_T M_T M Q M M_ M_ W E K M M Q M_T M_T M Q M M_ M_ J F M M Q M_T M_T M Q [] M [..] K M_ M_ J M [..] [] F M Q M_T M_T F M Q M Q M_T M_T M Q [] M NK R M_NK M_NK R M NK [] M Q M_T M_T M Q [] M NK R M_NK M_NK U M NK [] M Q M_T M_T Y M Q [] M NK J M_NK M_NK J M NK [] M Q M_T M_T E M Q M Q M_T M_T W M Q [] M RS# R M_RS_L M_RS_L U M RS# [] M Q M_T M_T W M Q [] M S# T M_S_L M_S_L U M S# [] M Q M_T M_T Y M Q [] M WE# T M_WE_L M_WE_L U M WE# [] F M Q M_T M_T Y M Q M Q M_T M_T F M Q SOKET PIN M Q M_T M_T F M Q M Q M_T M_T F M Q PU_VR M Q M_T M_T M Q Place close to socket M Q M_T M_T M Q M Q M_T M_T Y Y M Q M Q M_T M_T W E M Q M Q M_T M_T F M Q M Q M_T M_T F M Q *.U/.V_.U/.V_.U/.V_.U/.V_.u/.V_.u/.V_.u/.V_.u/.V_ M Q M_T M_T M Q [] M M[..] M_T M_T M M[..] [] PU_VR M M M M M M M_M M_M E M M M M M_M M_M M M M M M_M M_M E E M M M M M_M M_M F M M M M M_M M_M E M M P/V_ P/V_ P/V_ P/V_ p/v_ p/v_ p/v_ p/v_ M M M_M M_M Y M M M M M_M M_M M M M_M M_M Y SOKET PIN [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] M QSP M QSN M QSP M QSN M QSP M QSN M QSP M QSN M QSP M QSN M QSP M QSN M QSP M QSN M QSP M QSN Processor Memory Interface M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L F M_QS_H E M_QS_L M_QS_H M_QS_L F M_QS_H F M_QS_L E M_QS_H M_QS_L F M_QS_H E M_QS_L M_QS_H G M_QS_L H M_QS_H G M_QS_L G M_QS_H M_QS_L M_QS_H G M_QS_L G M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H Y M_QS_L W M_QS_H W M_QS_L W M QSP [] M QSN [] M QSP [] M QSN [] M QSP [] M QSN [] M QSP [] M QSN [] M QSP [] M QSN [] M QSP [] M QSN [] M QSP [] M QSN [] M QSP [] M QSN [] ocument Number SG RIII MEMORY I/F / ate: Monday, May, Sheet of E

4 PU_SMT PU_SMLK PU_SI [] PU_SI [] NTR_VREF [] PU_SMLK [] PU_SMT [].VSUS.VSUS.VSUS.VSUS.VSUS PU_VN_ORE VORE VORE VORE VORE PU_VN_ORE.VSUS ocument Number ate: Sheet of SG PWR & GN / Monday, May, ocument Number ate: Sheet of SG PWR & GN / Monday, May, ocument Number ate: Sheet of SG PWR & GN / Monday, May, OTTOM SIE EOUPLING PROESSOR POWER N GROUN EOUPLING ETWEEN PROESSOR N IMMs PLE LOSE TO PROESSOR S POSSILE.V@ u/.v_ u/.v_ p/v_ p/v_ p/v_ p/v_ P *u/v_ P *u/v_.u/.v_.u/.v_.u/.v_.u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ u/.v_.u/.v_.u/.v_.u/.v_.u/.v_ u/.v_ u/.v_.u/.v_.u/.v_ R K_ R K_ Q SS_NL/SOT Q SS_NL/SOT.u/.V_.u/.V_ u/.v_ u/.v_ UF SOKET PIN UF SOKET PIN VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS E VSS E VSS E VSS E VSS E VSS E VSS E VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS E VSS F VSS F VSS F VSS F VSS F VSS F VSS F VSS F VSS F VSS H VSS H VSS H VSS H VSS J VSS J VSS J VSS J VSS J VSS J VSS J VSS J VSS K VSS K VSS K VSS K VSS K VSS K VSS K VSS L VSS L VSS L VSS L VSS L VSS L VSS L VSS M VSS M VSS VSS M VSS N VSS N VSS N VSS N VSS N VSS P VSS P VSS P VSS P VSS P VSS R VSS R VSS R VSS R VSS T VSS T VSS T VSS T VSS T VSS T VSS U VSS U VSS U VSS U VSS U VSS U VSS U VSS U VSS V VSS V VSS V VSS V VSS V VSS V VSS V VSS W VSS Y VSS Y VSS N Q SS_NL/SOT Q SS_NL/SOT.U/.V_.U/.V_ R K_ R K_.u/.V_.u/.V_.u/V_.u/V_ p/v_ p/v_.u/.v_.u/.v_ p/v_ p/v_.u/v_.u/v_ u/.v_ u/.v_.u/v_.u/v_.u/.v_.u/.v_ u/.v_ u/.v_.u/.v_.u/.v_.u/.v_.u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ p/v_ p/v_.u/v_.u/v_ u/.v_ u/.v_ UE SOKET PIN UE SOKET PIN V_ V_ V_ G V_ H V_ J V_ J V_ J V_ K V_ K V_ K V_ K V_ L V_ L V_ L V_ L V_ L V_ M V_ M V_ M V_ M V_ N V_ N V_ N V_ P V_ P V_ R V_ R V_ R V_ R V_ T V_ T V_ T V_ T V_ T V_ T V_ U V_ U V_ U V_ U V_ V V_ V V_ V V_ V V_ V V_ W V_ Y V_ J VN_ K V_ L VN_ M VN_ P VN_ T V_ U VN_ V VIO H VIO J VIO K VIO K VIO K VIO K VIO L VIO M VIO M VIO M VIO M VIO N VIO P VIO P VIO P VIO P VIO R VIO T VIO T VIO T VIO T VIO U VIO V VIO V VIO V VIO V VIO Y.u/V_.u/V_

5 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q MEM_M_TEST MEM_M_TEST IM_S IM_S IM_S M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M NK M NK M NK IM_S IM_S IM_S M NK M NK M NK M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M IM_S IM_S M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q PT_SM PLK_SM M M[..] [] M Q[..] [] M Q[..] [] PT_SM [,] PLK_SM [,] M QSP [] M QSP [] M QSP [] M QSP [] M QSP [] M QSP [] M QSP [] M QSP [] M QSN [] M QSN [] M QSN [] M QSN [] M QSN [] M QSN [] M QSN [] M QSN [] M QSN [] M QSN [] M QSN [] M QSN [] M QSP [] M QSP [] M QSP [] M QSP [] M QSP [] M QSP [] M QSN [] M QSP [] M QSN [] M QSP [] M QSN [] M QSN [] M M[..] [] M [..] [] M NK[..] [] M LKP [] M LKN [] M LKP [] M LKN [] M KE [] M KE [] M RS# [] M S# [] M WE# [] M S# [] M S# [] M OT [] M OT [] M RST# [] M [..] [] M NK[..] [] M LKP [] M LKN [] M LKP [] M LKN [] M KE [] M KE [] M RS# [] M S# [] M WE# [] M S# [] M S# [] M OT [] M OT [] M RST# [].VSUS V V V.VSMVREF_SUS.VSUS.VSMVREF_SUS.VSMVREF_SUS.VSUS.VSUS.VSMVREF_SUS SMR_VREF.VSUS VREF VREF SMR_VREF.VSUS VREF VREF.V_R_VTT.V_R_VTT.VSUS.VSUS.VSUS.VSUS ocument Number ate: Sheet of R SOIMMS: / HNNEL Monday, May, ocument Number ate: Sheet of R SOIMMS: / HNNEL Monday, May, ocument Number ate: Sheet of R SOIMMS: / HNNEL Monday, May, SMbus address SMbus address onnector ON_SOIMM_ST_V Standard onnector ON_SOIMM_ST_V Standard H= H= o Place these aps near So-imm H=. Place these aps near So-imm H=. Place on each IMM onnector R K_ R K_.U/.V_.U/.V_.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_ u/.v_ u/.v_.u/v_.u/v_.u/v_.u/v_.u/v_.u/v_.u/.v_.u/.v_ R *Short_ R *Short_ *u/.v_ *u/.v_.u/v_.u/v_ *u/v_ *u/v_.u/.v_.u/.v_.u/v_.u/v_ R K_ R K_.u/V_.u/V_.U/.V_.U/.V_.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_ *u/v_ *u/v_.u/v_.u/v_.u/v_.u/v_.u/v_.u/v_.u/v_.u/v_ R K/F_ R K/F_ R K_ R K_.u/V_.u/V_ R *K/F_ R *K/F_ R *Short_ R *Short_.u/V_.u/V_ R K_ R K_ R SO-IMM (Standard ) N R_SO-IMM_H=_.V_Standard R SO-IMM (Standard ) N R_SO-IMM_H=_.V_Standard Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q N N TEST / / / / / / /P _# / / M M M M M M M M QS QS QS QS QS QS QS QS K K# K K# KE KE RS# S# WE# S# S# S S S SL Vspd V V V V V V V V V V V V VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS / QS# QS# QS# QS# QS# QS# QS# QS# OT OT VSS VSS VSS VSS RST# V V V V V V EVENT# VREF Vref VTT VTT R K/F_ R K/F_.u/V_.u/V_ T T P/V_ P/V_.u/V_.u/V_.u/V_.u/V_ R *K/F_ R *K/F_ P/V_ P/V_.u/V_.u/V_ R *K/F_ R *K/F_.u/V_.u/V_.u/V_.u/V_ *u/.v_ *u/.v_.u/v_.u/v_ R *K/F_ R *K/F_ R K/F_ R K/F_ R K/F_ R K/F_.u/V_.u/V_ u/.v_ u/.v_ R SO-IMM (Standard ) N R_SO-IMM_H=_.V_Standard R SO-IMM (Standard ) N R_SO-IMM_H=_.V_Standard Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q N N TEST / / / / / / /P _# / / M M M M M M M M QS QS QS QS QS QS QS QS K K# K K# KE KE RS# S# WE# S# S# S S S SL Vspd V V V V V V V V V V V V VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS / QS# QS# QS# QS# QS# QS# QS# QS# OT OT VSS VSS VSS VSS RST# V V V V V V EVENT# VREF Vref VTT VTT T T

6 [] HT_OUTP [] HT_OUTN [] HT_OUTP [] HT_OUTN [] HT_OUTP [] HT_OUTN [] HT_OUTP [] HT_OUTN [] HT_OUTP [] HT_OUTN [] HT_OUTP [] HT_OUTN [] HT_OUTP [] HT_OUTN [] HT_OUTP [] HT_OUTN [] HT_OUTP [] HT_OUTN [] HT_OUTP [] HT_OUTN [] HT_OUTP [] HT_OUTN [] HT_OUTP [] HT_OUTN [] HT_OUTP [] HT_OUTN [] HT_OUTP [] HT_OUTN [] HT_OUTP [] HT_OUTN [] HT_OUTP [] HT_OUTN [] HT_LKOUTP [] HT_LKOUTN [] HT_LKOUTP [] HT_LKOUTN [] HT_TLOUTP [] HT_TLOUTN [] HT_TLOUTP [] HT_TLOUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_LKOUTP HT_LKOUTN HT_LKOUTP HT_LKOUTN HT_TLOUTP HT_TLOUTN HT_TLOUTP HT_TLOUTN R /F_ HT_RXLP HT_TXLP HT_RXLN HT_RXLP HT_TXLP R /F_ HT_TXLN HT_RXLN HT_TXLN Ra U Y HT_RXP HT_TXP Y HT_RXN PRT OF HT_TXN V HT_RXP HT_TXP E V HT_RXN HT_TXN E V HT_RXP HT_TXP F V HT_RXN HT_TXN F U HT_RXP HT_TXP F U HT_RXN HT_TXN F T HT_RXP HT_TXP H T HT_RXN HT_TXN H P HT_RXP HT_TXP J P HT_RXN HT_TXN J P HT_RXP HT_TXP K P HT_RXN HT_TXN K N HT_RXP HT_TXP K N HT_RXN HT_TXN K HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN Y HT_RXP Y HT_RXN W HT_RXP W HT_RXN V HT_RXP V HT_RXN U HT_RXP U HT_RXN U HT_RXP U HT_RXN T HT_RXLKP T HT_RXLKN HT_RXLKP HT_RXLKN M HT_RXTLP M HT_RXTLN R HT_RXTLP R HT_RXTLN RS/RX HYPER TRNSPORT PU I/F HT_TXP F HT_TXN G HT_TXP G HT_TXN H HT_TXP J HT_TXN J HT_TXP J HT_TXN K HT_TXP L HT_TXN J HT_TXP M HT_TXN L HT_TXP M HT_TXN P HT_TXP P HT_TXN M HT_TXLKP H HT_TXLKN H HT_TXLKP L HT_TXLKN L HT_TXTLP M HT_TXTLN M HT_TXTLP P HT_TXTLN R HT_INP HT_INN HT_INP HT_INN HT_INP HT_INN HT_INP HT_INN HT_INP HT_INN HT_INP HT_INN HT_INP HT_INN HT_INP HT_INN HT_INP HT_INN HT_INP HT_INN HT_INP HT_INN HT_INP HT_INN HT_INP HT_INN HT_INP HT_INN HT_INP HT_INN HT_INP HT_INN HT_LKINP HT_LKINN HT_LKINP HT_LKINN HT_TLINP HT_TLINN HT_TLINP HT_TLINN HT_INP [] HT_INN [] HT_INP [] HT_INN [] HT_INP [] HT_INN [] HT_INP [] HT_INN [] HT_INP [] HT_INN [] HT_INP [] HT_INN [] HT_INP [] HT_INN [] HT_INP [] HT_INN [] HT_INP [] HT_INN [] HT_INP [] HT_INN [] HT_INP [] HT_INN [] HT_INP [] HT_INN [] HT_INP [] HT_INN [] HT_INP [] HT_INN [] HT_INP [] HT_INN [] HT_INP [] HT_INN [] HT_LKINP [] HT_LKINN [] HT_LKINP [] HT_LKINN [] HT_TLINP [] HT_TLINN [] HT_TLINP [] HT_TLINN [] Rb Signals RS RX HT_TXLP HT_TXLN HT_RXLP HT_RXLN Ra ohm % Rb ohm % Ra.k ohm % Rb.k ohm % RES HIP.K /W -%() P/N : SF This block is for Side-Port only U PR OF MEM_(N) MEM_Q/VO_VSYN(N) E MEM_(N) MEM_Q/VO_HSYN(N) V MEM_(N) MEM_Q/VO_E(N) E MEM_(N) MEM_Q/VO_(N) MEM_(N) MEM_Q(N) MEM_(N) MEM_Q/VO_(N) MEM_(N) MEM_Q/VO_(N) MEM_(N) MEM_Q/VO_(N) MEM_(N) MEM_Q/VO_(N) MEM_(N) MEM_Q/VO_(N) MEM_(N) MEM_Q/VO_(N) E MEM_(N) MEM_Q/VO_(N) MEM_(N) MEM_Q(N) Y MEM_(N) MEM_Q/VO_(N) MEM_Q/VO_(N) MEM_(N) MEM_Q/VO_(N) E MEM_(N) MEM_(N) MEM_QSP/VO_IKP(N) MEM_QSN/VO_IKN(N) W MEM_RSb(N) MEM_QSP(N) Y MEM_Sb(N) MEM_QSN(N) MEM_WEb(N) MEM_Sb(N) MEM_M(N) MEM_KE(N) MEM_M/VO_(N) V MEM_OT(N) IOPLLV(N) V MEM_KP(N) IOPLLV(N) W MEM_KN(N) IOPLLVSS(N) E MEM_OMPP(N) MEM_OMPN(N) MEM_VREF(N) S_MEM/VO_I/F Y V Y E Y W E W E E E E.V.V m m RS/RX ocument Number RSM-HT LINK I/F / ate: Monday, May, Sheet of

7 [] [] [] [] [] [] [] [] [] [] [] [] [] PEG_RXP[..] [] PEG_RXN[..] PIE_RX PIE_RX- PIE_RXP PIE_RXN _RXP _RXN _RXP _RXN _RXP _RXN _RXP _RXN PEG_RXP[..] PEG_RXN[..] PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN T T E E V W U U U U Y Y W Y INT HMI U GFX_RXP GFX_RXN GFX_RXP GFX_RXN GFX_RXP GFX_RXN E GFX_RXP F GFX_RXN G GFX_RXP G GFX_RXN H GFX_RXP H GFX_RXN J GFX_RXP J GFX_RXN J GFX_RXP J GFX_RXN L GFX_RXP L GFX_RXN M GFX_RXP L GFX_RXN P GFX_RXP M GFX_RXN P GFX_RXP M GFX_RXN R GFX_RXP P GFX_RXN R GFX_RXP R GFX_RXN P GFX_RXP P GFX_RXN T GFX_RXP T GFX_RXN GPP_RXP GPP_RXN GPP_RXP GPP_RXN GPP_RXP GPP_RXN GPP_RXP GPP_RXN GPP_RXP GPP_RXN GPP_RXP GPP_RXN S_RXP S_RXN S_RXP S_RXN S_RXP S_RXN S_RXP S_RXN RS/RX PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PRT OF PIE I/F GFX PIE I/F GPP PIE I/F S GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GPP_TXP GPP_TXN GPP_TXP GPP_TXN GPP_TXP GPP_TXN GPP_TXP GPP_TXN GPP_TXP GPP_TXN GPP_TXP GPP_TXN S_TXP S_TXN S_TXP S_TXN S_TXP S_TXN S_TXP S_TXN PE_LRP(PE_LRP) PE_LRN(PE_LRN) IV@.u/V_ IV@.u/V_ IV@.u/V_ IV@.u/V_ IV@.u/V_ IV@.u/V_ IV@.u/V_ IV@.u/V_ E E F F F F H H H H J J K K K K M M M M N N P P Y Y Y Y V V E E E [] [] PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ PIE_TXN TXP TXN TXP TXN TXP TXN TXP TXN_ N_PIELRP N_PIELRN IV_TX_HMI [] IV_TX_HMI- [] IV_TX_HMI [] IV_TX_HMI- [] IV_TX_HMI [] IV_TX_HMI- [] IV_TX_HMI [] IV_TX_HMI- [] PEG_TXP[..] PEG_TXN[..] T T EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ R R PEG_TXP[..] PEG_TXN[..].u/V_.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_.K/F_ K/F_ PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PIE_TX [] PIE_TX- [] PIE_TXP [] PIE_TXN [] _TXP [] _TXN [] _TXP [] _TXN [] _TXP [] _TXN [] _TXP [] _TXN [].V RS isplay Port Support (muxed on GFX) P P ocument Number LN WLN S RSM-PIE I/F / GFX_TX,TX,TX and TX UX and HP GFX_TX,TX,TX and TX UX and HP ate: Monday, May, Sheet of

8 For heck list JTG R *.K_ N_PWRG_IN V R *.K_ INT_EIT R *.K_ INT_EILK V R *.K_ IV_HMI T [] INT_RT_RE [] INT_RT_GRE [] INT_RT_LU R R R m V_V_N L_TP [] L_TN [] m.v_vi_n L_TP [] L_TN [] m U F V(N) TXOUT_LP(N) E V(N) PRT OF TXOUT_LN(N) F VI(N) TXOUT_LP(N) G.V_VQ_N VSSI(N) TXOUT_LN(N) H VQ(N) TXOUT_LP(N) L_TP [] H VSSQ(N) TXOUT_LN(G_GPIO) L_TN [] TXOUT_LP(N) E _Pr(FT_GPIO) TXOUT_LN(G_GPIO) F Y(FT_GPIO) F OMP_Pb(FT_GPIO) TXOUT_UP(N) TXOUT_UN(N) G RE(FT_GPIO) TXOUT_UP(PIE_RESET_GPIO) IV@/F_ G REb(N) TXOUT_UN(PIE_RESET_GPIO) E GREEN(FT_GPIO) TXOUT_UP(N) IV@/F_ F GREENb(N) TXOUT_UN(N) E LUE(FT_GPIO) TXOUT_UP(PIE_RESET_GPIO) IV@/F_ F LUEb(N) TXOUT_UN(N) RT/TVOUT For version (/) on t need. ohm P. R *./F_ R *./F_ LK_SLINKP LK_SLINKN VG [,] N_PWRG_IN.V R /F_ [] [] [] INT_RT_HSYN [] INT_RT_VSYN [] INT_T [] INT_LK R /F_ [,] [] [] _RST#_S LK_N_HTREFP_PR LK_N_HTREFN_PR [] LK_N_REF_LKP [] LK_N_REF_LKN R.K_ R.K_ LK_SLINKP LK_SLINKN m m T T INT_RT_HSYN INT_RT_VSYN _RSET_N.V_PLLV.V_PLLV.V_VHTPLL.V_VPIEPLL N_LT_STOP# N_LLOW_LTSTOP LK_N_REF_LKP LK_N_REF_LKN NGFX_LKP NGFX_LKN GPP_REFLKP GPP_REFLKN E F G H E E F T T U U V V _HSYN(PWM_GPIO) _VSYN(PWM_GPIO) _S(PE_TLRN) _SL(PE_RLRN) _RSET(PWM_GPIO) PLLV(N) PLLV(N) PLLVSS(N) VHTPLL VPIEPLL VPIEPLL SYSRESETb POWERGOO LTSTOPb LLOW_LTSTOP HT_REFLKP HT_REFLKN REFLK_P/OSIN(OSIN) REFLK_N(PWM_GPIO) GFX_REFLKP GFX_REFLKN GPP_REFLKP GPP_REFLKN GPPS_REFLKP(S_REFLKP) GPPS_REFLKN(S_REFLKN) LOKs PM PLL PWR LVTM TXLK_LP(G_GPIO) TXLK_LN(G_GPIO) TXLK_UP(PIE_RESET_GPIO) TXLK_UN(PIE_RESET_GPIO) VLTP(N) VSSLTP(N) VLT_(N) VLT_(N) VLT_(N) VLT_(N) VSSLT(VSS) VSSLT(VSS) VSSLT(VSS) VSSLT(VSS) VSSLT(VSS) VSSLT(VSS) VSSLT(VSS) LVS_IGON(PE_TLRP) LVS_LON(PE_RLRP) LVS_EN_L(PWM_GPIO) E E F G.V_VLTP_N.V_VLT N L_LK [] L_LK# [] m m INT_LVS_IGON [] INT_PST_PWM [] INT_LVS_LON [] [] INT_EIT [] INT_EILK IV_HMI T [] IV_HMI T [] IV_HMI LK _T & _LK Not applicable to RX [] N_ORE_ON T N_ORE_ON RS_UX_L I_T I_LK _T/UXN(N) _LK/UXP(N) UXP(N) UXN(N) STRP_T G RSV UX_L(N) RS/RX MIS. TMS_HP(N) HP(N) TVLKIN(PWM_GPIO) THERMLIOE_P THERMLIOE_N TESTMOE E SUS_STT#_N TEST_EN R.K/F_ R R *K_ *Short_ INT_HMI_HP [] SUS_STT# [] Made provision for external pull-down which is not installed by default. Pulled up externally for bypassing EEPROM strapping and using default values. RSM --- V.V.V STRP_EUG_US_GPIO_ENLEb Enables the Test ebug us using GPIO. RSM isable V INT_RT_VSYN Enable RSM: Enables Side port memory RSM:INT_RT_HSYN R K_ V.V L LMPGSN(_.)_ solve RTflicker u/.v_.u/v_.v_vi_n V_V_N V- nalog not applicable to RX.U/.V_ VI- igital not applicable to RX.V L LMPGSN(_.)_ L LMPGSN(_.)_ u/.v_.v_pllv PLLV - Graphics PLL not applicable to RX.U/.V_.V_PLLV PLLV - Graphics PLL not applicable to RX.U/.V_ L LMPGSN(_.)_ L LMPGSN(_)_.U/.V_.V_VLTP_N VLTP - LVS or VI/HMI PLL.U/.V_ not applicable to RX.u/V_.V_VLT N VLT - LVS or VI/HMI digital not applicable to RX Selects if Memory SIE PORT is available or not = Memory Side port Not available L LMPGSN(_.)_.V_VQ_N.U/.V_ VQ- andgap Reference not applicable to RX = Memory Side port available Register Readback of strap: N_LKFG:LK_TOP_SPRE_[] INT_RT_HSYN R K_ V.V VPIEPLL -PIE PLL L.V_VPIEPLL LMPGSN(_.)_.U/.V_ mils width [,] PU_LT_STOP#.V U Open rain - LV.V / need modify PN R.K_ N_LT_STOP# R based PU : Level shifted to. V on the Northbridge side using an open-drain buffer and pulled up to.v_s through a.k Ohm % resistor on the Northbridge side. For extrnal EEPROM ebug only N_ORE_ON R RS/RX/RS K/F_ VHTPLL -HT LINK PLL L.V_VHTPLL LMPGSN(_.)_ mils width [] LLOW_LTSTOP R *Short_ R K_.V N_LLOW_LTSTOP isplay Port interface from PIeGraphics (RS/rsM only) RS_UX_L R */F_.U/.V_ The RS family does not support LM architecture The LTREQ# connection from the PU to LLOW_LTSTOP of the Northbridge is no longer required. ocument Number RSM-SYSTEM I/F / Monday, May, ate: Sheet of

9 E G G G H J R L L L L M N P R R R V U V V W W W W W Y E E E G E E J J K M L UF VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS PRT / GROUN E G G G H J L L L L M N P R R R R H U V W W W Y L M N P P R R T U U U V W W Y E K VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS.V.V L.V *Short_ L LMPGSN(_)_....V L L.U/.V_ *Short_ V-RS I/O Transform.V for RSM.U/.V_.U/.V_.U/.V_.U/.V_.u/V_ R *Short_.u/V_ *Short_.u/V_.V_VG_N.V_VHT.V_VHTRX.V_VHTTX.V for RSMS m V_MEM For UM RS only Not applicable to RX memory I/O transform.u/v_.u/v_.u/v_ U/.V_.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_.V_VPIE.u/V_ J K L M P R T H G F E E Y W V U T R P M J P K M L W H T R Y E U F G E UE VHT_ VPIE_ VHT_ PRT / VPIE_ VHT_ VPIE_ VHT_ VPIE_ VHT_ VPIE_ VHT_ VPIE_ VHT_ VPIE_ VPIE_ VHTRX_ VPIE_ VHTRX_ VPIE_ VHTRX_ VPIE_ VHTRX_ VPIE_ VHTRX_ VPIE_ VHTRX_ VPIE_ VHTRX_ VPIE_ VPIE_ VHTTX_ VPIE_ VHTTX_ VHTTX_ V_ VHTTX_ V_ VHTTX_ V_ VHTTX_ V_ VHTTX_ V_ VHTTX_ V_ VHTTX_ V_ VHTTX_ V_ VHTTX_ V_ VHTTX_ V_ VHTTX_ V_ V_ VPIE_ V_ VPIE_ V_ VPIE_ V_ VPIE_ V_ VPIE_ V_ VPIE_ V_ VPIE_ V_ VPIE_ V_ VPIE_ V_ VPIE_ V_ VPIE_ VPIE_ V_MEM(N) VPIE_ V_MEM(N) VPIE_ V_MEM(N) VPIE_ V_MEM(N) V_MEM(N) VG_(V_) V_MEM(N) VG_(V_) V_MEM(N) VG_(N) V_MEM(N) VG_(N) RS/RX POWER E F G H J K M L P R T V U K J U J K M L L M M N N P P P R R T T U T J E Y H H.V_V_PIE.u/V_.u/V_.u/V_ W/I SP (Ra).U V_VG.u/V_.u/V_.u/V_..~.V@.u/V_ W/O SP ohm U/.V_ W/O sideport contect to GN R.u/V_ U/.V_.u/V_ *Short_.u/V_.u/V_ m R V -.V I/O Not applicable to RX.U/.V_ u/.v_ *Short_ u/.v_ V.V(.).V VPIE - PIE-E Main power N_ORE V - ore Logic power No need side port V_MEM For UM RS only Not applicable to RX memory I/O transform W/O side port -->stuff Ohm SJ ocument Number RSM-POWER/ ate: Monday, May, Sheet of

10 [,] PIE_RST# [,] _RST#_S [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] N & E _RXP _RXN _RXP _RXN _RXP _RXN _RXP _RXN _TXP _TXN _TXP _TXN _TXP _TXN _TXP _TXN.V_PIE_VR p/v_ R R [] LK_SLINKP [] LK_SLINKN [] LK_N_REF_LKP [] LK_N_REF_LKN [] LK_N_HTREFP_PR [] LK_N_HTREFN_PR [] LK_PU_LKP_PR [] LK_PU_LKN_PR [] LK_PIE_VGP [] LK_PIE_VGN RP [] LK_PIE_LOM [] LK_PIE_LOM# [] LK_PIE_WLNP_ [] LK_PIE_WLNN_ p/v_ T p/v_ PLE PS VERY LOSE TO LL OF SM R _.u/v_.u/v_.u/v_.u/v_.u/v_.u/v_.u/v_.u/v_ /F_ K/F_ MHz R Y M_ PIE_RST#_S _RST#_S _TXP _TXN _TXP _TXN _TXP _TXN _TXP _TXN PIE_LRP_S PIE_LRN_S LK_SLINKP LK_SLINKN LK_N_REF_LKP LK_N_REF_LKN LK_N_HTREFP_PR LK_N_HTREFN_PR LK_PU_LKP_PR LK_PU_LKN_PR SLT_GFX_LKP SLT_GFX_LKN EV@_PR_ LK_PIE_LOM LK_PIE_LOM# LK_PIE_WLNP_ LK_PIE_WLNN_ LK_M_VG _RXP RXN RXP RXN RXP RXN RXP RXN_ M_X M_X U P PIE_RST# L _RST# _TXP _TXN _TXP _TXN _TXP _TXN _TXP _TXN E _RXP E _RXN _RXP _RXN _RXP _RXN _RXP _RXN PIE_LRP PIE_LRN GPP_TXP GPP_TXN Y GPP_TXP Y GPP_TXN Y GPP_TXP Y GPP_TXN W GPP_TXP W GPP_TXN GPP_RXP Y GPP_RXN GPP_RXP GPP_RXN W GPP_RXP V GPP_RXN W GPP_RXP W GPP_RXN S I TRL(P) S (-) P/N : JT S PI EXPRESS INTERFES LOK GENERTOR PI LKS M PIE_RLKP/N_LNK_LKP P PIE_RLKN/N_LNK_LKN U N_ISP_LKP U N_ISP_LKN T N_HT_LKP T N_HT_LKN V PU_HT_LKP T PU_HT_LKN V SLT_GFX_LKP T SLT_GFX_LKN L GPP_LKP L GPP_LKN N GPP_LKP N GPP_LKN M GPP_LKP M GPP_LKN T GPP_LKP V GPP_LKN L GPP_LKP L GPP_LKN P GPP_LKP M GPP_LKN P GPP_LKP P GPP_LKN N GPP_LKP N GPP_LKN T GPP_LKP T GPP_LKN L L L M_M_M_OS M_X M_X Part of PILK PILK/GPO PILK/GPO PILK/GPO PILK/M_OS/GPO PU RT PI INTERFE LP PIRST# /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO E# E# E# E# FRME# EVSEL# IRY# TRY# PR STOP# PERR# SERR# REQ# REQ#/GPIO REQ#/LK_REQ#/GPIO REQ#/LK_REQ#/GPIO GNT# GNT#/GPO GNT#/GPO GNT#/LK_REQ#/GPIO LKRUN# LOK# INTE#/GPIO INTF#/GPIO INTG#/GPIO INTH#/GPIO LPLK LPLK L L L L LFRME# LRQ# LRQ#/LK_REQ#/GPIO SERIRQ/GPIO LLOW_LTSTP/M_TIVE# PROHOT# LT_PG LT_STP# LT_RST# K_X K_X RTLK INTRUER_LERT# VT_RT_G W W W W Y V E E F E F G F E F F F H G H E J E F E E E H H J H J G G J H H J J H H G J G H K G J PI_LK PI_LK PI_LK PI_LK PI_LK OR_I OR_I OR_I OR_I OR_I LRQ#_S LRQ#_S RT_X RT_X INTRUER_LERT# T T T T T T T T PI_LK [] PI_LK [] PI_LK [] PI_LK [] OR_I [] OR_I [] OR_I [] OR_I [] OR_I [] [] [] [] [] R _ R _ T T G *SHORT_ P dgpu_pwrok [] dgpu_rst_gpio [] LP_L [,] LP_L [,] LP_L [,] LP_L [,] LP_LFRME# [,] IRQ_SERIRQ [] LLOW_LTSTOP [] PU_PWRG [,] PU_LT_STOP# [,] PU_LT_RST# [] RT_LK [] VT.u/V_ R For M RST [,,] _RST# GPU MINI-PIE ard reader *Short_ *.p/v_ R R mil [] VR_._EN [] for EMI suggestion V_S dgpu_vron [] LKRUN# [] For STRPS *P/V_ *K/F_ *M_ R _ LP_LK [] LP_LK [] _RST#_N VPU VRT_ T PLK_EUG [] LK_PI_ [] PU_PROHOT# [] INTRUER_LERT# Left not connected (Southbridge has -kohm internal pull-up to VT). VT MIL MIL R K_ MIL.u/V_ *P/V_ T N RT_ONN V_S VRT MIL R (Non-hargeable) HL HL HLM U TSHFU R RT_X RT_X /F_ Y.KHZ R p/v_ ocument Number _RST#_S VRT_ M_ S_GPIO_PIE_RST# [] R p/v_ S-PIE/PI/PU/LP / ate: Monday, May, Sheet of mil /F_ U/.V_ R *M_ VT

11 N only,an't be install V_S V V_S V_S V V R R R To zalia Z_SOUT Z_SYN Z_LK Z_RST# Z_SIN S_TEST S_TEST S_TEST SL/ST is V tolerance. M datasheet define it lk Gen/ Robson/ TV tuner/ R/ Thermal/ ccelerometer R R.K_ PLK_SM PT_SM SL/ST is V/S tolerance M datasheet define it R R SL/ST is V/S tolerance. M datasheet define it R R R R R *.K_ *.K_ *.K_.K_.K_.K_ K_ K_ K_ K_.K_ R _ R _ R _ R _ S_SMLK S_SMT S_SLK S_ST SUS_STT# LK_PIE_LN_REQ# LK_PIE REQ# Z_SOUT_UIO [] *P/V_ Z_SYN_UIO [] *P/V_ *P/V_ Z_ITLK_UIO [] Z_RST#_UIO [] Z_SIN [] [] SUS# [] SUS# [] NSWON# [] S_PWRG_IN [] SUS_STT# [] SIO_GTE [] SIO_RIN# [] SIO_EXT_SMI# [] SIO_EXT_SI# [] PIE_WKE# [,] N_PWRG_IN T S_PI_PME# SUS# S_TEST S_TEST S_TEST SIO_RIN# LNLINK_STTE# SYS_RST# IR_RX S_THERMTRIP# Z_LK Z_SOUT Z_SIN Z_SYN Z_RST# US_ROMP_S US_FSP US_FSN [] IH_RSMRST# G RSMRST# US_HSP J USP [] US_HSN J USP- [] LK_REQ#/ST_IS#/GPIO S_GPIO_PIE_RST# LK_REQ#/ST_IS#/GPIO US_HSP USP [] [] S_GPIO_PIE_RST# USP- [] LK_PIE_LN_REQ# SMRTVOLT/ST_IS#/GPIO US_HSN [] LK_PIE_LN_REQ# LK_REQ#/ST_IS#/GPIO [] dgpu_pwr_en F USP [] S_GPIO ST_IS#/FNOUT/GPIO US_HSP T E ST_IS#/FNIN/GPIO US_HSN USP- [] [] SPKR F PLK_SM SPKR/GPIO [,] PLK_SM PT_SM SL/GPIO US_HSP G [,] PT_SM E S_SMLK S/GPIO US_HSN G F S_SMT SL/GPIO F S/GPIO US_HSP G [] LK_PIE REQ# H LK_REQ#/FNIN/GPIO US_HSN G LK_REQ#/FNOUT/GPIO E IR_LE#/LL#/GPIO US_HSP J SMRTVOLT/SHUTOWN#/GPIO US_HSN T H R_RST#/GEVENT# GE_LE/GPIO US_HSP USP [] GE_LE/GEVENT# US_HSN USP- [] G GE_LE/GEVENT# K E_S_OS GE_STT/GEVENT# US_HSP E T LK_REQG#/GPIO/OSIN US_HSN E [] [] Eliot (/) urrent gesa bios doesn t program LERT_L and S won t process alert. [] O_# O_# S_PM_THERM# O_# T S_JTG_TO T S_JTG_TK T S_JTG_TI T S_JTG_RST# T H audio interface is VS voltage Z_SOUT V_S T T T T T T R R R R R K_ K_ K_ K_ K_ GE_OL GE_RS GE_MIO GE_RXERR GE_PHY_INTR P_PRES [/] M FE and checklist request PL. U J PI_PME#/GEVENT# K RI#/GEVENT# SPI_S#/GE_STT/GEVENT# F SLP_S# H SLP_S# F PWR_TN# H PWR_GOO S G SUS_STT# TEST Part of TEST/TMS F TEST GIN/GEVENT# E KRST#/GEVENT# K LP_PME#/GEVENT# J LP_SMI#/GEVENT# H GEVENT# J SYS_RESET#/GEVENT# H WKE#/GEVENT# F IR_RX/GEVENT# J THRMTRIP#/SMLERT#/GEVENT# N_PWRG H LINK/US_O#/GEVENT# US_O#/IR_TX/GEVENT# E US_O#/IR_TX/GEVENT# US_O#/IR_RX/GEVENT# E US_O#/_PRES/TO/GEVENT# F US_O#/TK/GEVENT# E US_O#/TI/GEVENT# F US_O#/TRST#/GEVENT# M Z_ITLK N Z_SOUT L Z_SIN/GPIO M Z_SIN/GPIO M Z_SIN/GPIO M Z_SIN/GPIO N Z_SYN P Z_RST# T GE_OL T GE_RS L GE_MK L GE_MIO T GE_RXLK U GE_RX U GE_RX T GE_RX U GE_RX T GE_RXTL/RXV V GE_RXERR P GE_TXLK M GE_TX P GE_TX T GE_TX P GE_TX M GE_TXTL/TXEN P GE_PHY_P M GE_PHY_RST# V GE_PHY_INTR S GE LN H UIO E PS_T/S/GPIO E PS_LK/SL/GPIO F SPI_S#/GE_STT/GPIO G F_RST#/GPO PSK_T/GPIO F PSK_LK/GPIO F PSM_T/GPIO E PSM_LK/GPIO EMEE TRL USLK/M_M_M_OS pin is LK input pin when EXT LKGEN mode. It is output LK source when INT LKGEN mode. PI / WKE UP EVENTS GPIO US O USLK/M_M_M_OS US. US MIS EMEE TRL US. US_ROMP G US_FSP/GPIO J US_FSN H US_FSP/GPIO H US_FSN J US_HSP US_HSN US_HSP F US_HSN E US_HSP E US_HSN E US_HSP J US_HSN J US_HSP US_HSN US_HSP US_HSN SL/GPIO S/GPIO F SL_LV/GPIO S_LV/GPIO E E_PWM/E_TIMER/GPIO F E_PWM/E_TIMER/GPIO E E_PWM/E_TIMER/GPIO F E_PWM/E_TIMER/GPIO E KSI_/GPIO G KSI_/GPIO G KSI_/GPIO E KSI_/GPIO E KSI_/GPIO KSI_/GPIO KSI_/GPIO KSI_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO US M USP USP- S_SLK S_ST S_GPIO S_GPIO USP [] USP- [] USP [] USP- [] USP [] USP- [] T T T R.K/F_ T T USP [] USP- [] T GPIO [] GPIO [] heck list S_GPIO S_GPIO MER USX board USX board ard reader LUETOOTH - LUETOOTH - WLN Min-ard On oard US onnector Only US Port can be configured as debug port. R R ocument Number S-PI/GPIO/US / ate: Monday, May, Sheet of K_ K_ EHI/ OHI EHI/ OHI EHI/ OHI

12 E-ST Max trace length: " U ST H ST O [] ST_RX- [] ST_RX [] ST_TX [] ST_TX- [] ST_TX [] ST_TX- [] ST_RX- [] ST_RX ST PORT,,, can support HI mode Signal Name ST_LRP ST_LRN S : ohm % resistor to GN. S : K ohm % resistor to GN. S : ohm % resistor to VN ST. S : ohm % resistor to VN ST. PLE ST_L RES VERY LOSE TO LL OF S.V_V_ST [] Explanation R R ST_T#.u/V_.u/V_.u/V_.u/V_ V T T T T T K/F_ /F_ R *p/v_ *p/v_ ST_TX_ ST_TX-_ ST_TX_ ST_TX-_ ST_LRP ST_LRN K_ ST_X *MHz R Y *M_ ST_X S_GPIO S_GPIO S_GPIO S_GPIO S_GPIO H ST_TXP J ST_TXN J ST_RXN H ST_RXP H ST_TXP J ST_TXN G ST_RXN F ST_RXP G ST_TXP F ST_TXN J ST_RXN H ST_RXP H ST_TXP J ST_TXN G ST_RXN F ST_RXP G ST_TXP F ST_TXN J ST_RXN H ST_RXP J ST_TXP H ST_TXN H ST_RXN J ST_RXP ST_LRP ST_LRN ST_T#/GPIO ST_X ST_X J SPI_I/GPIO E SPI_O/GPIO K SPI_LK/GPIO K SPI_S#/GPIO G ROM_RST#/GPIO SERIL T S Part of SPI ROM HW MONITOR FLSH F_LK H F_FLKOUT G F_FLKIN F F_OE#/GPIO F F_V#/GPIO G F_WE#/GPIO G F_E#/GPIO F F_E#/GPIO E F_INT/GPIO F F_INT/GPIO H F_Q/GPIO J F_Q/GPIO J F_Q/GPIO H F_Q/GPIO H F_Q/GPIO G F_Q/GPIO H F_Q/GPIO J F_Q/GPIO G F_Q/GPIO F F_Q/GPIO H F_Q/GPIO J F_Q/GPIO F F_Q/GPIO J F_Q/GPIO J F_Q/GPIO G F_Q/GPIO H FNOUT/GPIO W FNOUT/GPIO W FNOUT/GPIO Y FNIN/GPIO W FNIN/GPIO V FNIN/GPIO W TEMPIN/GPIO TEMPIN/GPIO TEMPIN/GPIO TEMPIN/TLERT#/GPIO TEMP_OMM /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GE_STT/GPIO /GE_LE/GPIO N G N Y T_OFF# WWN_ET# PPE_N# R_REQ# TEMPIN TEMPIN M_THRM_S S_GPIO TEMP_OMM S_GPIO S_GPIO SIE_PORT_I SIE_PORT_I MEM_V S_GPIO S_GPIO T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T IF THERE IS NO IE, TEST POINTS FOR EUG US IS MNTORY R *Short_ V R R R R TEMPIN TEMPIN M_THRM_S S_GPIO S_GPIO S_GPIO OM check *SP@K_ EV@K_ *SP@K_ *SP@K_ OR_I OR_I OR_I OR_I heck list R R R R R R R R R R SP@K_ IV@K_ SP@K_ SP@K_ K_ K_ K_ K_ K_ K_ I I I I IS UM S R *SP@K_ OR_I R SP@K_ I [] OR_I [] OR_I [] OR_I [] OR_I [] OR_I OR_I OR_I OR_I OR_I OR_I V_S R *K_ SIE_PORT_I R *K_ V R *K_ SIE_PORT_I R *K_ P.u/V_ [] VR_._EN MEM_V U TSHFU VR_OPT [] VR_._EN: : VR =.V : VR =.V (efault) ocument Number S-ST/IE/SPI / ate: Monday, May, Sheet of

13 V.V.V V_S VQ--.V I/O power R If the VIO_Z_S power rail is configured for.v_s then Z_SIN[:] can not be connected to.-v devices. *Short_ V L T _ L T _ u/.v_ L LMPGSN(_.)_ V_VIO_PIGP u/.v_ u/.v_ U/.V_.u/V_ S_VIO F V L V_VPL_ST LMPGSN(_.)_.U/.V_ *.u/v_.v_v_st For support US wakeup-->v_s.v_s u/.v_.v_vn_us.u/v_ L.V_VN_US LMPGSN(_.)_ m m R *Short_ m L V_VPLL PIE LMPGSN(_.)_.V_PIE_VR.U/.V_ *.u/v_ *u/.v_ u/.v_.u/v_.u/v_ m m m xx m.v_s PLE LL THE EOUPLING PS ON THIS SHEET LOSE TO S S POSSILE. U Part of m m m m m VIO_Z.V_US_PHY_R V_VPL.V_VPL VPL_.V_US V_HWM_VN VXL_.V V-- S/ ORE power S without GE/ onnected to GN plane..u/v_ m m m m.u/.v_ U/.V_ U/.V_ u/.v_ u/.v_.v_vr_ V_S.V_S V_S VIO_Z.V_S L _.V_US_PHY_R V V_VPL V_S V_HWM_VN.V_S.V_VPL V_S VPL_.V_US L LMPGSN(_.)_.u/V_ *.u/v_.u/.v_.u/.v_ L *_.u/v_ L LMPGSN(_.)_.u/V_ *.u/v_ V_VIO R *Short_.u/V_ U/.V_ U/.V_ u/.v_ u/.v_ U/.V_ U/.V_.u/V_ POWER S S H VIO PIGP_ V VIO PIGP_ Y VIO PIGP_ E VIO PIGP_ VIO PIGP_ VIO PIGP_ VIO PIGP_ VIO PIGP_ VIO PIGP_ VIO PIGP_ F VIO PIGP_ VIO PIGP_ F VIO F_ E VIO F_ F VIO F_ VIO F_ E VPL PIE U VN PIE_ V VN PIE_ V VN PIE_ V VN PIE_ V VN PIE_ V VN PIE_ W VN PIE_ W VN PIE_ VPL ST J VN ST_ F VN ST_ H VN ST_ G VN ST_ E VN ST_ VN ST_ E VN ST_ PI/GPIO I/O VN US_S_ VN US_S_ VN US_S_ VN US_S_ VN US_S_ VN US_S_ VN US_S_ VN US_S_ VN US_S_ VN US_S_ VN US_S_ E VN US_S_ VN US_S_ VN US_S_ ORE S FLSH I/O SERIL T PI EXPRESS US I/O PLL GE LN LKGEN I/O ORE S.V_S I/O VR VR VR VR VR VR VR VR VR VN LK_ VN LK_ VN LK_ VN LK_ VN LK_ VN LK_ VN LK_ VN LK_ VRF_GE_S VIO GE_S VR GE_S_ VR GE_S_ VIO_GE_S_ VIO_GE_S_ VIO S_ VIO S_ VIO S_ VIO S_ VIO S_ VIO S_ VIO S_ VIO S_ VR S_ VR S_ VIO_Z_S VR US_S_ VR US_S_ VPL SYS VPL SYS_S VPL US_S VN HWM_S VXL S N R N U U V V W W K K J K J J K J V M L L M P K L J T T F G M M L F L.V_VR R *Short_.V.u/V_.u/V_ U/.V_ U/.V_ u/.v_.v_vn_lk L T _.V L V_S LMPGSN(_.)_.u/V_.u/V_.U/.V_ UE S Y VSSIO_ST_ Y VSSIO_ST_ VSSIO_ST_ VSSIO_ST_ E VSSIO_ST_ E VSSIO_ST_ F VSSIO_ST_ F VSSIO_ST_ F VSSIO_ST_ F VSSIO_ST_ G VSSIO_ST_ H VSSIO_ST_ H VSSIO_ST_ H VSSIO_ST_ H VSSIO_ST_ J VSSIO_ST_ J VSSIO_ST_ J VSSIO_ST_ J VSSIO_ST_ VSSIO_US_ VSSIO_US_ K VSSIO_US_ VSSIO_US_ VSSIO_US_ VSSIO_US_ VSSIO_US_ VSSIO_US_ E VSSIO_US_ F VSSIO_US_ F VSSIO_US_ F VSSIO_US_ F VSSIO_US_ VSSIO_US_ G VSSIO_US_ F VSSIO_US_ VSSIO_US_ H VSSIO_US_ H VSSIO_US_ H VSSIO_US_ H VSSIO_US_ J VSSIO_US_ J VSSIO_US_ K VSSIO_US_ K VSSIO_US_ K VSSIO_US_ K VSSIO_US_ H VSSIO_US_ Y EFUSE VSSN_HWM M VSSXL R *Short_ u/.v_.u/v_ GROUN VSS_ J VSS_ VSS_ VSS_ E VSS_ VSS_ E VSS_ E VSS_ F VSS_ N VSS_ R VSS_ R VSS_ T VSS_ P VSS_ V VSS_ U VSS_ M VSS_ V VSS_ M VSS_ L VSS_ L VSS_ J VSS_ P VSS_ V VSS_ VSS_ VSS_ VSS_ VSS_ V VSS_ W VSS_ W VSS_ J VSS_ VSS_ U VSS_ Y VSS_ Y VSS_ Y VSS_ Y VSS_ VSS_ VSS_ G VSS_ J VSS_ G VSS_ G VSS_ M VSS_ F VSS_ H VSS_ H VSS_ V VSS_ P VSS_ N VSS_ L VSS_ L VSSPL_SYS M P VSSIO_PIELK_ VSSIO_PIELK_ H P VSSIO_PIELK_ VSSIO_PIELK_ H M VSSIO_PIELK_ VSSIO_PIELK_ M VSSIO_PIELK_ VSSIO_PIELK_ M VSSIO_PIELK_ VSSIO_PIELK_ P VSSIO_PIELK_ VSSIO_PIELK_ P VSSIO_PIELK_ VSSIO_PIELK_ P VSSIO_PIELK_ VSSIO_PIELK_ T VSSIO_PIELK_ VSSIO_PIELK_ Y T VSSIO_PIELK_ VSSIO_PIELK_ W T VSSIO_PIELK_ VSSIO_PIELK_ W V VSSIO_PIELK_ VSSIO_PIELK_ E J VSSIO_PIELK_ VSSIO_PIELK_ L VSSIO_PIELK_ K Part of S U/.V_.U/.V_ R *Short_ U/.V_ L LMPGSN(_.)_ *.u/v_.u/.v_ L *Short_ *.u/v_.u/.v_ () M FE confirmed *.u/v_.u/.v_.u/.v_.u/v_ ocument Number S-PWR/EOUPLING / ate: Monday, May, Sheet of

14 REQUIRE STRPS SM is supported Gen. mode only. For internal clock GEN. V_S V V V V V_S V_S V_S OVERLP OMMON PS WHERE POSSILE FOR UL-OP RESISTORS. R *K_ R *K_ R *K_ R *K_ R K_ R K_ R *K_ R *K_ [] GPIO [] GPIO [] LP_LK [] LP_LK [] PI_LK [] PI_LK [] PI_LK [] PI_LK [] Z_SOUT R K_ R K_ R K_ R K_ R *K_ R K_ R.K_ R *.K_ Z_SOUT PI_LK PI_LK PI_LK PI_LK LP_LK LP_LK GPIO GPIO PULL HIGH LOW POWER MOE LLOW PIE Gen Watchdog Timer Enable USE EUG STRPS non_fusion LOK MOE EFULT E ENLE LKGEN ENLE EFULT H, H=Reserved H, L=SPI ROM PULL LOW PERFORMNE MOE EFULT FORE PIE Gen Watchdog Timer isable IGNORE EUG STRPS EFULT EFULT EFULT Fusion LOK MOE E ISLE EFULT LKGEN ISLE L, H=LP ROM EFULT L, L=FWH ROM internal have pull Hi K EUG STRPS S HS K INTERNL PU FOR PI_[:] [] [] [] [] [] R *.K_ R *.K_ R *.K_ R *.K_ R *.K_ V_S R K_ *.u/.v_ N_PWRG_IN: RS/RX =.V; o NOT share it with S_PWRG when use Internal lk Gen (Need S PLL initialize firstly) R.V *Short_ S_PWRG_IN S_PWRG_IN [] N/S POWER GOO IRUIT PULL HIGH PI_ USE PI PLL EFULT PI_ ISLE IL UTORUN EFULT PI_ USE F PLL EFULT PI_ USE EFULT PIE STRPS EFULT PI_ ISLE PI MEM OOT EFULT [,,] PU_OREPG [] PWROK_E *S S U N V GN Y *NLSZFTG SOT- R *.u/v_ *_ N_PWRG_IN [,] PULL LOW YPSS PI PLL ENLE IL UTORUN YPSS F PLL USE EEPROM PIE STRPS ENLE PI MEM OOT LSZ LUG I(P) NLSZFTG(SOT-) I OTHER(P) SNUGVR(SOT-) SOT- SOT- ocument Number S-STRPS ate: Monday, May, Sheet of

15 PIE_RST_VG# PIE_RST_VG# PEG_TXN PEG_TXP PEG_TXN PEG_TXN PEG_TXP PEG_TXP PEG_TXP PEG_TXN PEG_TXN PEG_TXN PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXN PEG_TXN PEG_RXP_ PEG_RXN_ PEG_RXN_ PEG_RXN_ PEG_RXP_ PEG_RXN_ PEG_RXP_ PEG_RXP_ PEG_RXP_ PEG_RXN_ PEG_RXN_ PEG_RXN_ PEG_RXP_ PEG_RXP_ PEG_RXN_ PEG_RXP_ PEG_RXP_ PEG_RXN_ PEG_RXP_ PEG_RXN_ PEG_RXP_ PEG_RXN_ PEG_RXN_ PEG_RXP_ PEG_RXN_ PEG_RXP_ PEG_RXP_ PEG_RXN_ PEG_RXP_ PEG_RXN_ PEG_RXN_ PEG_RXP_ PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXP[..] PEG_RXN PEG_RXP PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP[..] PEG_TXN[..] PEG_RXN[..] PEG_TXP PEG_TXN LK_PIE_VGP [] LK_PIE_VGN [] _RST# [,,] dgpu_rst_gpio [] PEG_TXP[..] [] PEG_RXP[..] [] PEG_TXN[..] [] PEG_RXN[..] [] V V_ ocument Number ate: Sheet of Madison/Park-PIE / Monday, May, ocument Number ate: Sheet of Madison/Park-PIE / Monday, May, ocument Number ate: Sheet of Madison/Park-PIE / Monday, May, For Madison and Park PIE_V is.v For Madison and Park the PWRGOO ball must be conneccted to ground.v EV@.u/V_ EV@.u/V_ EV@S EV@S EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@S EV@S EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ PI EXPRESS INTERFE LOK LIRTION EV@Park_M U PI EXPRESS INTERFE LOK LIRTION EV@Park_M U N# J N# K PWRGOO H PIE_LRN Y PIE_LRP Y PIE_REFLKN PIE_REFLKP PIE_RXN Y PIE_RXP PIE_RXN K PIE_RXP L PIE_RXN J PIE_RXP K PIE_RXN H PIE_RXP J PIE_RXN G PIE_RXP H PIE_RXN F PIE_RXP G PIE_RXN E PIE_RXP F PIE_RXN W PIE_RXP Y PIE_RXN V PIE_RXP W PIE_RXN U PIE_RXP V PIE_RXN T PIE_RXP U PIE_RXN R PIE_RXP T PIE_RXN P PIE_RXP R PIE_RXN N PIE_RXP P PIE_RXN M PIE_RXP N PIE_RXN L PIE_RXP M PERST PIE_TXN Y PIE_TXP Y PIE_TXN L PIE_TXP L PIE_TXN L PIE_TXP L PIE_TXN K PIE_TXP K PIE_TXN J PIE_TXP J PIE_TXN K PIE_TXP K PIE_TXN H PIE_TXP H PIE_TXN W PIE_TXP W PIE_TXN U PIE_TXP U PIE_TXN U PIE_TXP U PIE_TXN T PIE_TXP T PIE_TXN T PIE_TXP T PIE_TXN P PIE_TXP P PIE_TXN P PIE_TXP P PIE_TXN N PIE_TXP N PIE_TXN N PIE_TXP N R EV@K_ R EV@K_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ R EV@.K/F_ R EV@.K/F_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ R EV@K/F_ R EV@K/F_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ R EV@K/F_ R EV@K/F_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_ EV@.u/V_

16 U TXP_PP TXM_PN U V EV_TX_HMI [] EV_TX_HMI- [] UG R EV@K_ GPU Power-on sequence => V_ => VGPU_ORE => V =>.V_GPU =>.V_GPU => dgpu_pwrok.v GPIO [] [] [] RM_STRP RM_STRP RM_STRP For Park-M N pin VPT_ - VPT_ V_ For Park-M N pin R U P W R R U U W P T W U R W U T V N V T R W U P V T R W U P MUTI GFX VPNTL_MVP_ VPNTL_MVP_ VPNTL_ VPNTL_ VPNTL_ VPLK VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ P P P TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN T R U V T R R T V U R T T U U V T R U V T R U T T R EV_TX_HMI [] EV_TX_HMI- [] EV_TX_HMI [] EV_TX_HMI- [] EV_TX_HMI [] EV_TX_HMI- [] LVS ONTROL VRY_L IGON TXLK_UP_PFP TXLK_UN_PFN TXOUT_UP_PFP TXOUT_UN_PFN TXOUT_UP_PFP TXOUT_UN_PFN TXOUT_UP_PFP TXOUT_UN_PFN TXOUT_UP TXOUT_UN LVTMP TXLK_LP_PEP TXLK_LN_PEN TXOUT_LP_PEP TXOUT_LN_PEN TXOUT_LP_PEP TXOUT_LN_PEN TXOUT_LP_PEP TXOUT_LN_PEN TXOUT_LP TXOUT_LN K J K L J K H J G H F G P R W U R U P R N P EV_LVS_RIGHT [] EV_LVS_VEN [] EV_TXLLKOUT [] EV_TXLLKOUT- [] EV_TXLOUT [] EV_TXLOUT- [] EV_TXLOUT [] EV_TXLOUT- [] EV_TXLOUT [] EV_TXLOUT- [] R EV@K/F_ R EV@K/F_ K J I SL S P TXP_PP TXM_PN TXP_PP TXM_PN U V T R EV@Park_M.V GPIO R [] GPU_GPIO [] GPU_GPIO [] GPU_GPIO [] GPIO_SMT [] GPIO_SMLK T T [] EV_LVS_LON T [] SIN_GPIO T [] GPU_GPIO [] GPU_GPIO [] GPU_GPIO [] [] [] EV@K/F_ [] GPU_VI LT#_GPIO GPU_VI T SS#_GPIO T T T T T IO_VI IO_VI EV_LVS_LON SOUT_GPIO SIN_GPIO SLK_GPIO T T T SS#_GPIO GPIO_TRST GPIO_TI GPIO_TK GPIO_TMS GPIO_TO GPU_VI H H N H J H J K J H J K L M M M K G N M L J K N M N K L M J K J K J H H GENERL PURPOSE I/O GPIO_ GPIO_ GPIO_ GPIO SMT GPIO SMLK GPIO TT GPIO_ GPIO LON GPIO ROMSO GPIO ROMSI GPIO ROMSK GPIO_ GPIO_ GPIO_ GPIO HP GPIO PWRNTL_ GPIO SSIN GPIO THERML_INT GPIO HP GPIO TF GPIO PWRNTL_ GPIO EN GPIO ROMS GPIO LKREQ JTG_TRST JTG_TI JTG_TK JTG_TMS JTG_TO GENERI GENERI GENERI GENERI GENERIE_HP GENERIF GENERIG R R G G HSYN VSYN RSET V VSSQ VI VSSI R R G G Y OMP HSYN VSYN E F E E F F F R V VI T EV@/F_ EXT_RT_RE EXT_RT_GRN EXT_RT_LU EXT_HSYN [,] EXT_VSYN [,] VSYN [] EV@/F_ R EV@/F_ R EV@/F_ R EXT_RT_RE [] EXT_RT_GRN [] EXT_RT_LU [].V_GPU (.V@m V) ohm/m V L EV@SYT-Y-N/./ohm_ EV@.u/V_ EV@U/.V_ EV@U/.V_ (.V@m VI) ohm/m VI L EV@SYT-Y-N/./ohm_ EV@.u/V_ EV@U/.V_ EV@U/.V_ [] EXT_HMI_HP EXT_HMI_HP K HP VI VSSI G G VI V G V_ (.V@m V).V_GPU R EV@/F_ VREFG H VREFG VQ VSSQ F VQ EV@.u/V_.V_GPU V.V_GPU.V(m) ohm/m L EV@SYT-Y-N/./ohm_ PLL_PV EV@U/.V_ EV@U/.V_ EV@.u/V_.V(m) ohm/m L EV@SYT-Y-N/./ohm_ PLL_V EV@U/.V_ EV@U/.V_ EV@.u/V_.V(m) ohm/m L EV@SYT-Y-N/./ohm_ TS_V EV@U/.V_ EV@.u/V_ EV@p/V_ EV@p/V_ Y R EV@MHZ EV@M_ [] [] R EV@/F_ EV@.u/V_ GPU_ GPU_- T PLL_PV PLL_V XTLI_M XTLO_M TS_V M N N V U F G K J J PLL_PV PLL_PVSS PLL_V XTLIN XTLOUT PLUS MINUS TS_FO TSV TSVSS EV@Park_M PLL/LOK THERML /UX RSET LK T UXP UXN LK T UXP UXN LK_UXP T_UXN LK_UXP T_UXN LK_UXP T_UXN LK T N_LK_UXP N_T_UXN M N M L M L N M L M L M N M J J K K R EV@/F_ T T T T T T T T T T T T EV_HMI_K [] EV_HMI_T [] EV_LVS_LK [] EV_LVS_T [] EV_RTLK [] EV_RTT [] HMI LVS RT.V_GPU (.V@m VQ) ohm/m VQ L EV@SYT-Y-N/./ohm_ EV@U/.V_ EV@.u/V_ ocument Number Madison/Park-HOST / Monday, May, ate: Sheet of

17 MVREFS MVREF VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q MVREF MVREFS TESTEN VM_LKN VM_LKN VM_S# VM_RS# VM_WE# VM_LKP VM_RS# VM_KE VM_WE# VM_S# VM_S# VM_S# VM_KE VM_WQS VM_RQS VM_M VM_WQS VM_RQS VM_M VM_RQS VM_WQS VM_M VM_M VM_RQS VM_M VM_RQS VM_RQS VM_WQS VM_M VM_WQS VM_M VM_M VM_WQS VM_WQS VM_RQS VM_RQS VM_WQS VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_ VM_ VM_ VM_M VM_LKP VM_M[..] VM_Q[..] VM_M[..] VM_WQS[..] VM_RQS[..] VM_M VM_LKN [] VM_OT [] VM_OT [] VM_LKN [] VM_RS# [] VM_WE# [] VM_LKP [] VM_KE [] VM_S# [] VM_RS# [] VM_WE# [] VM_S# [] VM_S# [] VM_S# [] VM_KE [] VM_LKP [] VM_M[..] [] VM_RQS[..] [] VM_WQS[..] [] VM_Q[..] [] VM_M[..] [] VM_ [] VM_ [] VM_ [] MEM_RST# [].V_GPU.V_GPU.V_GPU.V_GPU.V_GPU.V_GPU V_ ocument Number ate: Sheet of Madison/Park-MEM / Monday, May, ocument Number ate: Sheet of Madison/Park-MEM / Monday, May, ocument Number ate: Sheet of Madison/Park-MEM / Monday, May, QS[..] QS#[..] For PRK MEM_LRNP MEM_LRNP MEM_LRNP stuff R/GR Memory Stuff Option GR.V/.V Rb Ra.R.V_VG GR R.V R.R R.V R.R K R NI pf For Mannhatton NI R/Short esignator For M-M K.nF Ra Rb Rc a R *EV@K_ R *EV@K_ R EV@/F_ R EV@/F_ R *EV@.K_ R *EV@.K_ R EV@./F_ R EV@./F_ TP TP R *EV@/F_ R *EV@/F_ R *EV@/F_ R *EV@/F_ R EV@./F_ R EV@./F_ R EV@./F_ R EV@./F_ R *EV@_ R *EV@_ R EV@./F_ R EV@./F_ R EV@/F_ R EV@/F_ EV@.u/V_ EV@.u/V_ R EV@_ R EV@_ R *EV@/F_ R *EV@/F_ MEMORY INTERFE R GR/GR R R GR/GR R GR GR/R/GR EV@Park_M U MEMORY INTERFE R GR/GR R R GR/GR R GR GR/R/GR EV@Park_M U Q_/Q_ Q_/Q_ Q_/Q_ J Q_/Q_ K Q_/Q_ K Q_/Q_ L Q_/Q_ M Q_/Q_ M Q_/Q_ M Q_/Q_ M Q_/Q_ N Q_/Q_ P Q_/Q_ E Q_/Q_ P Q_/Q_ R Q_/Q_ T Q_/Q_ T Q_/Q_ U Q_/Q_ V Q_/Q_ V Q_/Q_ V Q_/Q_ Y Q_/Q_ Y Q_/Q_ E Q_/Q_ Y Q_/Q_ Y Q_/Q_ Q_/Q_ Q_/Q_ Q_/Q_ Q_/Q_ Q_/Q_ Q_/Q_ Q_/Q_ Q_/Q_ F Q_/Q_ F Q_/Q_ F Q_/Q_ F Q_/Q_ G Q_/Q_ H Q_/Q_ H Q_/Q_ J Q_/Q_ K Q_/Q_ F Q_/Q_ F Q_/Q_ F Q_/Q_ G Q_/Q_ G Q_/Q_ K Q_/Q_ L Q_/Q_ M Q_/Q_ M Q_/Q_ K Q_/Q_ L Q_/Q_ M Q_/Q_ M Q_/Q_ F Q_/Q_ N Q_/Q_ P Q_/Q_ P Q_/Q_ P Q_/Q_ G Q_/Q_ H Q_/Q_ H MVREF Y MVREFS TESTEN S W S KE U KE LK L LK L LK LK LKTEST K LKTEST L S_ P S_ L S_ S_ WK_/QM_ H WK_/QM_ H WK_/QM_ T WK_/QM_ T WK_/QM_ E WK_/QM_ F WK_/QM_ K WK_/QM_ K RM_RST H M_/M_ P M_/M_ T M_/M_ M_/M_ M_/M_ M_/ M_/ Y M_/ M_/M_ P M_/M_ N M_/M_ N M_/M_ N M_/M_ U M_/M_ U M_/M_ Y M_/M_ W I/OT T I/OT W RS T RS Y E_/QS_/RQS_ F E_/QS_/RQS_ K E_/QS_/RQS_ P E_/QS_/RQS_ V E_/QS_/RQS_ E_/QS_/RQS_ H E_/QS_/RQS_ J E_/QS_/RQS_ M I_/QS_/WQS_ G I_/QS_/WQS_ K I_/QS_/WQS_ P I_/QS_/WQS_ W I_/QS_/WQS_ I_/QS_/WQS_ H I_/QS_/WQS_ J I_/QS_/WQS_ M WE N WE M_ T M_ W R *EV@/F_ R *EV@/F_ R *EV@_ R *EV@_ MEMORY INTERFE R GR/GR R GR/R/GR R GR/GR R GR EV@Park_M U MEMORY INTERFE R GR/GR R GR/R/GR R GR/GR R GR EV@Park_M U Q_/Q_ Q_/Q_ Q_/Q_ Q_/Q_ Q_/Q_ F Q_/Q_ Q_/Q_ Q_/Q_ E Q_/Q_ Q_/Q_ F Q_/Q_ Q_/Q_ Q_/Q_ Q_/Q_ F Q_/Q_ Q_/Q_ Q_/Q_ E Q_/Q_ Q_/Q_ Q_/Q_ F Q_/Q_ Q_/Q_ Q_/Q_ F Q_/Q_ E Q_/Q_ Q_/Q_ E Q_/Q_ Q_/Q_ Q_/Q_ F Q_/Q_ Q_/Q_ Q_/Q_ F Q_/Q_ Q_/Q_ E Q_/Q_ G Q_/Q_ F Q_/Q_ Q_/Q_ F Q_/Q_ Q_/Q_ Q_/Q_ F Q_/Q_ Q_/Q_ Q_/Q_ G Q_/Q_ H Q_/Q_ Q_/Q_ J Q_/Q_ H Q_/Q_ G Q_/Q_ G Q_/Q_ K Q_/Q_ K Q_/Q_ G Q_/Q_ Q_/Q_ Q_/Q_ E Q_/Q_ F Q_/Q_ Q_/Q_ Q_/Q_ E Q_/Q_ Q_/Q_ E Q_/Q_ Q_/Q_ F MEM_LRP M MVREF L MVREFS L MEM_LRN L MEM_LRN N MEM_LRN G MEM_LRP M MEM_LRP H S K S K KE K KE J LK H LK G LK J LK H S_ K S_ K S_ M S_ K WK_/QM_ WK_/QM_ WK_/QM_ WK_/QM_ E WK_/QM_ WK_/QM_ WK_/QM_ E WK_/QM_ M_/M_ G M_/M_ J M_/M_ L M_/M_ G M_/M_ J M_/M H M_/M J M_/M H M_/M_ H M_/M_ J M_/M_ H M_/M_ J M_/M_ H M_/M_ G M_/M_ H M_/M_ H I/OT J I/OT G RS K RS K E_/QS_/RQS_ E_/QS_/RQS_ E_/QS_/RQS_ E_/QS_/RQS_ E E_/QS_/RQS_ E E_/QS_/RQS_ E E_/QS_/RQS_ J E_/QS_/RQS_ RSV L M_ H M_ J I_/QS_/WQS_ I_/QS_/WQS_ E I_/QS_/WQS_ E I_/QS_/WQS_ I_/QS_/WQS_ I_/QS_/WQS_ I_/QS_/WQS_ J I_/QS_/WQS_ F WE K WE L R EV@/F_ R EV@/F_ EV@.u/V_ EV@.u/V_ R EV@K_ R EV@K_ R EV@K_ R EV@K_ R EV@/F_ R EV@/F_ EV@.u/V_ EV@.u/V_ R EV@/F_ R EV@/F_ EV@p/V_ EV@p/V_ EV@.u/V_ EV@.u/V_ R EV@/F_ R EV@/F_