SERVICE MANUAL COMMUNICATIONS RECEIVER

Transcript

1 SERVICE MANUAL COMMUNICATIONS RECEIVER

2 This service manual describes the latest service information for the IC-R at the time of publication. VERSION U.S.A. Europe U.K. S.E.Asia Other INTRODUCTION SYMBOL USA EUR UK SEA OTH To upgrade quality, all electrical or mechanical parts and internal circuits are subject to change without notice or obligation. DANGER NEVER connect the receiver to an AC outlet or to a DC power supply that uses more than V. Such a connection could cause a fire hazard and/or electric. DO NOT expose the receiver to rain, snow or any liquids. DO NOT reverse the polarities of the power supply when connecting the receiver. DO NOT apply an RF signal of more than 0 dbm (00mW) to the antenna connector. This could damage the receiver's front end. ORDERING PARTS Be sure to include the following four points when ordering replacement parts:. 0-digit order numbers. Component part number and name. Equipment model name and unit name. Quantity required <SLE ORDER> 000 PCB B-C IC-R PLL UNIT pieces 0000 Screw Bih Mx ZK IC-R Chassis 0 pieces Addresses are provided on the inside back cover for your convenience. REPAIR NOTES. Make sure a problem is internal before disassembling the receiver.. DO NOT open the receiver until the receiver is disconnected from its power source.. DO NOT force any of the variable components. Turn them slowly and smoothly.. DO NOT short any circuits or electronic parts. An insulated turning tool MUST be used for all adjustments.. DO NOT keep power ON for a long time when the receiver is defective.. READ the instructions of test equipment thoroughly before connecting equipment to the receiver.

3 TABLE OF CONTENTS SECTION SPECIFICATIONS SECTION INSIDE VIEWS SECTION CIRCUIT - RECEIVER CIRCUITS PLL CIRCUITS LOGIC CIRCUITS POWER SUPPLY CIRCUITS PORT ALLOCATIONS SECTION ADJUSTMENT PROCEDURES - PREPARATION PLL ADJUSTMENT RECEIVER ADJUSTMENT SET MODE ADJUSTMENT SECTION PARTS LIST SECTION MECHANICAL PARTS AND DISASSEMBLY SECTION SEMI-CONDUCTOR INFORMATION SECTION BOARD LAYOUTS - PHONE AND VR BOARDS DISPLAY BOARD LOGIC BOARD PLL UNIT MAIN UNIT SECTION BLOCK DIAGRAM SECTION OLTAGE DIAGRAM 0- FRONT UNIT PLL UNIT MAIN UNIT

4 SECTION SPECIFICATIONS M GENERAL Frequency range : Sensitivity * Specifications guaranteed for. MHz and 0 MHz * Specifications guaranteed for. MHz May differ according to selected IF filter. : MHz. MHz (Preamplifiers are OFF) SSB, CW, RTTY less than.0 µv for 0 db S/N AM, S-AM less than.0 µv for 0 db S/N. MHz. MHz (The preamplifier is ON) SSB, CW, RTTY less than µv for 0 db S/N (typical) AM, S-AM less than.0 µv for 0 db S/N MHz. MHz (The preamplifier is ON) SSB, CW, RTTY less than µv for 0 db S/N (typical) AM, S-AM less than.0 µv for 0 db S/N FM less than 0. µv for db SINAD 0 MHz MHz (The preamplifier is ON) SSB, CW, RTTY less than µv for 0 db S/N (typical) AM, S-AM less than.0 µv for 0 db S/N FM less than 0. µv for db SINAD selectivity : SSB, CW, RTTY More than. khz/ db Less than.0 khz/ 0 db AM, S-AM More than.0 khz/ db less than 0.0 khz/ 0 db FM More than.0 khz/ db less than 0.0 khz/ 0 db Audio output power Antenna impedance Squelch sensitivity (threshold) : Version USA, EUR, UK, OTH SEA Mode : SSB (LSB, USB), AM, FM, CW, RTTY, S-AM Receive system : Triple-conversion superheterodyne Intermediate frequencies : SSB CW RTTY AM, S-AM st (MHz) nd (MHz) rd (MHz) : More than.0 W at 0 % distortion with an Ω load : 0 Ω or 0 Ω Frequency (MHz) Frequency coverage 0 khz 0 MHz* 0 khz 0 MHz* SSB less than µv* less than. µv* less than. µv* *Preamplifiers are OFF; * Preamplifier is ON; * Preamplifier is ON Current drain (. V DC) : Less than. A (Standby), Less than. A (Max. audio out) Spurious and image rejection : More than 0 db (. MHz SSB, AM, S-AM are more than 0 db) Dimensions : (W) (H) (D) mm; (W) (H) (D) inch (projection not included) Weight (approximate) :.0 kg; lb 0 oz (AC adaptor AD /A/V is not included) Antenna connector : SO- (0 Ω), push connection terminal (0 Ω) CI-V connector : -connector. (d) mm ( ")/ Ω PHONES connector : -conductor. (d) mm ( ") External speaker connector : -conductor. (d) mm ( ")/ Ω All stated specifications are subject to change without notice or obligation. - FM FM less than 0. µv* less than 0. µv*

5 SECTION INSIDE VIEWS MAIN UNIT PLL UNIT st mixer circuit nd mixer circuit st IF filter (FI0) Fuse (A) VCO circuit Bandpass filter PLL IC (IC) nd IF circuit Noise blaker circuit Back up battery (BT ) rd IF filter (FI) BFO mixer circuit (IC0) nd IF filter (FI: FL-) rd LO circuit rd mixer circuit (IC) BFO circuit -

6 SECTION CIRCUIT - RECEIVER CIRCUITS -- RF SWITCHING CIRCUIT (MAIN UNIT) The IC-R has two antenna connectors. RF signals enter either the [0 Ω ANT.] or [0 Ω ANT.] connector. RF signals from the [0 Ω ANT.] connector are applied to the antenna switching circuit (RL), and then pass through the low-pass filter (L, L, C C). RF signals from the [0 Ω ANT.] connector are passed through the L0 to exchange the impeadance value, and are then applied to the antenna switching circuit (RL). The signals are applied to the low-pass filter (L, L, C C). Each RF signals from the [0 Ω ANT.] connector or [0 Ω ANT.] connector are chosen by the antenna switching circuit (RL). -- RF FILTER CIRCUIT (MAIN UNIT) The filtered signals are applied to the RX attenuator switching circuit (RL). Either the signals bypass or pass through the attenuator circuit. The signals are attenuated at 0 db when passing through the attenuators. The attenuator system excludes non-linear components between an antenna connector and an attenuator to prevent strong signals from causing distortion. The signals are then applied to the RF filters. The MAIN UNIT has RF bandpass fileters for signals above.0 MHz and low-pass filters for signals below.0 MHz. () Below. MHz The signals are applied to the low-pass filter consisting of C0 C, L L via the limitter circuit (D, D). A diode is removed at the entrance of the low-pass filter. This device prevents the diode from causing distortion when receiving very strong signals. A switching diode (D) is turned on when the B0 line is HIGH. () Above. MHz The signals are applied to the high-pass filter consisting of C C, L L. This filter suppresses strong signals below. MHz such as broadcasting stations. The filtered signal between. MHz and.0 MHz are applied to the low-pass filter (C C, L, L) via the switching diode (D). The switching diodes (D, D) are turned ON when the B line is HIGH. The filtered signals above.0 MHz are applied to one of bandpass filters depending on the receive frequencies. After passing through a bandpass or low-pass filter, the signals are applied to the pre-amplifier circuit (Q, Q, IC). () FILTER SWITCHING CIRCUIT The RF bandpass filter corresponds to the BPF switching voltage (B0 B) based on the CPU via the shifit registor (IC, IC) and driver (IC, IC). The switching voltage of the BPF exit ot improve multi-signal and strong signal characteristics. RF bandpass and preamplifier circuit ANT (0 Ω) 0.. MHz LPF ATT (0 db) 0 MHz LPF to st mixer (Q, Q) ANT (0 Ω) ATT (0 db) HPF. MHz B0..0 MHz LPF PRE Q, Q B.0.0 MHz BPF PRE IC B preamplifier circuit 0 0 MHz BPF B -

7 -- PRE-LIFIER CIRCUIT (MAIN UNIT) The pre-amplifier circuit uses low noise junction FETs (Q, Q) or wideband amplifier (IC) to provide gain over a wide frequency range. When the [P.] switch is turned PRE, the signals from the RF filter are amplified by the junction FETs preamplifier circuit (Q, Q). When the [P.] switch is turned PRE, the signals from the RF filter are amplified by the wideband pre-amplifier circuit (IC). When the [P.] switch is turned PRE OFF, the signals from the RF filter bypass the pre-amplifiers through D and D. The amplified or bypassed signals are applied to the st mixer circuit (Q, Q) via the low-pass filter (L, L and C CC). The low-pass filter attenuates at 0 MHz to suppress image frequency. -- ST MIXER AND IF CIRCUITS (MAIN UNIT) The filtered signals are mixed with a.0.0 MHz st LO signal to produce a.0 MHz st IF signal at the st mixer circuit (Q, Q). The.0.0 MHz st LO signal is applied to an LO amplifier (Q) from the PLL unit via J, and then passes through the low-pass filter (L, L, C C). The filtered signal is applied to the st mixer circuit. The st IF signal is applied to the crystal bandpass filter(fi- ) to suppress out-of-band signals. The filtered signal is amplified at a st IF amplifier (Q), and then applied to a nd mixer circuit (D) -- ND MIXER AND IF CIRCUITS (MAIN UNIT) The st IF signal is mixed with a 0.0 MHz nd LO signal to produce MHz nd IF signal at the nd mixer (D, C, L, L). The 0.0 MHz nd LO signal is applied to the nd mixer from the PLL unit via J. ND IF FREQUEY MODE LSB, USB, FM CW RTTY AM, S-AM FREQUEY.0 MHz.00 MHz.00 MHz.000 MHz The MHz nd IF signal is applied to the crystal bandpass filter (FI0) to suppress unwanted signals. ST IF FREQUEY MODE LSB, USB, FM CW RTTY AM, S-AM FREQUEY.0 MHz.00 MHz.00 MHz.000 MHz The filtered signal enters the noise blanker gate (D D). The signal is applied to L to obtain clear reception and is then amplified at the nd IF amplifier (Q). The signal passes through a loose resonator circuit (C, L) and then is applied to one of the two crystal bandpass filters. The st mixer circuit employs a balanced mixer using lownoise junction FETs (Q, Q) to expand the dynamic range. IF circuit Option Received signals st LO signal.0.0 MHz st mixer Q, Q BPF Q IF nd LO signal 0 MHz nd mixer D Noise Blanker NB GATE Q IF BPF khz BPF rd LO signal. MHz Buffer rd mixer Q0 IC "" signal Q0 D0 detector BPF Option AF signal PWR LPF AF selector IC0 AM detector IC00, Q0, X0 Q0 Buffer BFO circuit IC0 BFO signal khz IF Q, Q IF Q BPF khz BPF khz BPF khz deemphasis ICD FM detector IC00, X00 IF Q00 -

8 When the [FIL] switch is turned FK, the filter is selected FI which covering the. khz bandwith. When the [FIL] switch is turned FOP, the filter is selected an optional filter. When the [FIL] switch is turned FTH, the signal from the nd IF amplifier bypass the crystal bandpass filters through D and D. The filtered or bypassed signal is amplified at the buffer amplifier (Q0) and applied to the rd mixer circuit (IC). -- NOISE BLANKER CIRCUITS (MAIN UNIT) The IC-R uses a trigger noise blanker circuit which removes pulse-type noise signals at the noise blanker gate (D D). The nd IF signal passes through the crystal bandpass filter (FI0) to suppress unwanted signals. A portion of the output signal is applied to a noise amplifier circuit (IC, Q, Q) and detected at a noise detector circuit (D). The detected voltage is applied to a noise blanker gate control circuit (Q Q, D). The threshold level of the noise blanker gate control circuit (Q Q, D) is set at. on SSB mode (In case of AM mode, is set at. V). When the detected voltage exceeds the threshold level, Q outputs a blanking signal to activate the noise blanker gate (D D). A portion of the detected voltage is applied to the noise blanker circuit (Q, Q). The noise components are fed back to the noise amplifier (IC). The time constant of the noise blanker circuit is determined by R, R and C. This circuit does not operate to detect pulse-type noise. When the operating frequency or mode is changed, the UNLC signal is applied to the noise blanker gate control circuit (D). The noise blanker gate prevents PLL click noise. -- RD MIXER AND IF CIRCUITS (MAIN UNIT) The nd IF signal is mixed with a. MHz rd LO signal to produce a 0 khz rd IF signal at the rd mixer (IC). RD IF FREQUEY MODE LSB, USB CW RTTY AM, S-AM FREQUEY.0 khz. khz.0 khz 0.0 khz The. MHz rd LO signal is applied to the rd mixer IC (IC, pin 0) from the PLL unit via J. The 0 khz rd IF signal is applied either to one of the ceramic bandpass filters (FI, FI, FI) or to an optional crystal bandpass filter to suppress unwanted signals. When the [FIL] switch is turned FK, the filter is selected FI which covering the. khz bandwith. When the [FIL] switch is turned FK, the filter is selected FI which covering the khz bandwith. When the [FIL] switch is turned F, the filter is selected FI which covering the khz bandwith. When the [FIL] switch is turned FOP, the filter is selected an optional crystal bandpass filter. When the mode is selected SSB mode, the filtered rd IF signal is amplified at the rd IF amplifier (Q), and is then applied to the rd IF amplifier (Q) via the receiver total gain control circuit (R). The amplified signal is applied to the SSB demodulator circuit. When the mode is selected FM mode, the filtered rd IF signal is amplified at the rd IF amplifier (Q), and is then applied to the FM demodulator circuit. When the mode is selected AM mode, the filtered rd IF signal is amplified at the rd IF amplifier (Q), and is then applied to the rd IF amplifier (Q) via the receiver total gain control circuit (R). The amplified signal is applied to the AM demodulator circuit. st, nd and rd IF amplifiers (Q, Q, Q) are controlled by bias voltage. -- BFO CIRCUIT (PLL UNIT) The BFO (Beat Frequency Oscillator) circuit consists of Q, X, Q0 and IC 0 on PLL unit. The oscillator provides a beat frequency signal to the SSB demodulator circuit (MAIN UNIT; IC0) for demodulating the rd IF signal into an AF signal. The 0 MHz signal is oscillated at Q and X for the system clock signal of the DDS IC (IC0). The oscillated signal is amplified at Q0 and is applied to the DDC IC (IC0, pin ) to produce the khz BFO signal. The khz signal passes through the low-pass filter (L0, L0, C0 C0) via the D/A converter, and is then mixed with the rd IF signal at the SSB demodulator circuit (MAIN unit; IC0). -- DEMODULATOR CIRCUIT (MAIN UNIT) The demodulator circuit consists of detector circuits. () SSB DEMODULATOR CIRCUIT A product detector (IC0) demodulates SSB, RTTY and CW signals into an AF signal. The rd IF signal from the IF amplifier (Q) is mixed with the BFO signal at the product detector (IC0) to be demodulated into an AF signal. The AF signal passes through the AF input mode selector switch (IC0). () FM DEMODULATOR CIRCUIT A FM detector (IC00, X00) demodulates the FM signal into an AF signal. The rd IF signal from the IF amplifier (Q) is amplified at the rd IF amplifier (Q00), and is then applied to the FM detector (IC00, X00) to demodulate the rd IF signal. The demodulated signal is applied to the de-emphasis circuit (ICD) to produce the FM AF signal. The AF signal passes through the AF input mode selector switch (IC0). -

9 The FM detector outputs FMNL signal from IC00, pin is applied to the CPU (LOGIC unit; IC0, pin ) to control the noise squelch level. () AM DEMODULATOR CIRCUIT The AM demodulater circuit (IC00) has the envelope detect function and the synchronous detect function. An AM detector (IC00) demodulates the AM signal into an AF signal. The rd IF signal from the IF amplifier (Q) is amplified at the buffer amplifier (Q0), and is then applied to the AM demodulater circuit (IC00)to demodulate the rd IF signal into the AM AF signal. The AF signal which is the AM envelope detect the AF signal or the AM synchronous detect AF signal passes through the AF input mode selector switch (IC0). --0 AF INPUT MODE SELECTOR SWITCH (MAIN AND LOGIC UNITS) The AF input mode selector switch (MAIN unit; IC0) consists of analog switches. The switches are selected mode signals of AFS and AFS from the CPU (LOGIC unit; IC0) via the shift registor (MAIN unit; IC0), and are selected by the squelch control signal from the CPU (LOGIC unit; IC0). The AF signal is output from IC0 (MAIN unit; pin ). -- AF LIFIER CIRCUIT (MAIN AND FRONT UNITS) The AF signal output is passed though the low-pass filter (IC) to suppress unwanted signals. The filtered signal is mixed with BEEP signal at the AF level variable circuit (MAIN unit; IC), and is then applied to the AF amplifier circuit and the AF level variable circuit (IC). The AF level variable circuit controls the AF level by the AF GAIN (R) on the VR BOARD. The AF signal is applied to the AF mute circuit to suppress the noise when AF GAIN (R) level is minimum, and is then power-amplified at IC on the MAIN unit to drive the speaker. The one of the AF amplified signal is output A signal to record the AF signal to the AF recording jack (PLL unit; J). The mode is selected by the receiver mode or swtich on the front panel using the delay control circuit (Q0 Q0). The signal from the CPU (LOGIC board; IC0, pin ) is applied to the shift resistor (IC0, pin ) to produce the AGSS and the AGFS signals. The AGSS signal is applied to the Q0, the AGFS signal is applied to the Q0, the AGRS signal from the CPU (LOGIC unit; IC0, pin 0) is applied to the Q0 to control the delay control circuit. The AGRS signal resets the circuit when IC-R is working the memory scaning. When the switch is selected OFF, the Q0 do not supply the voltage to the amplifier (Q0) via the AGOS line, determining the time constant to deactivate the circuit. A portion of the bias voltage is amplified at the S-Meter amplifier circuit (ICC, D), and then applied to the CPU (LOGIC unit; IC0, pin ) via the SML line. Thus, the CPU controls S-Meter display. -- SQUELCH CIRCUIT (MAIN AND LOGIC UNIT) The SML signal is applied to the CPU (LOGIC unit; IC0, pin ) from the meter amplifier circuit (ICC, D). The CPU compares SML signal with the level of SQL volume on the VR BOARD to control the SQL signal. The CPU is output the SQLS signal from pin, and then applied to the AF selector circuit (MAIN unit; IC0, pin ) which has also the squelch gate circuit. - PLL CIRCUITS -- GENERAL The PLL unit generates a st LO signal (.0.0 MHz variable), nd LO signal (0 MHz), rd LO signal (. MHz) and BFO signal ( khz) used in the MAIN unit. The IC-R uses a DDS (Direct Digital synthesizer) system. The DDS system provides rapid lockup time and high quality frequency oscillation. -- AND S-METER CIRCUITS (MAIN UNIT) The (Automatic Gain Control) circuit reduces signal fading and keep the audio output level constant. The receiver gain is determined by voltage on the line (Q0, collector). When strong signals are received, the circuit decreases the voltage on this line. The rd IF signal is amplified at the IF amplifier (Q). A portion of the rd IF signal is applied to the buffer amplifier (Q0) to convert the impedance. The amplified IF signal is detected at the detector (D0) via the C0, and enters the base of the amplifier (Q0) to control the voltage on the line. -- REFEREE OSCILLATOR CIRCUIT (PLL CIRCUIT) The 0 MHz reference oscillator circuit consists of X and Q. The 0 MHz reference frequency is oscillated to produce all of the LO signals. -- ST LO CIRCUIT (PLL AND MAIN UNIT) The 0 MHz reference frequency is applied to the DDS-IC (PLL unit; IC, pin 0) to oscillate the st LO signal. The reference frequency is compared to the DDS output signal (PLL unit; IC, pin ) to oscillate the PLL lock voltage. The PLL lock voltage controlls the oscillate frequency of the VCO and VCO circuit. -

10 The oscillated signal at the VCO and VCO circuit is amplified at the LO-amplifier (PLL unit; Q), and passes through the low-pass filter (PLL unit; Q, D, D, L, L, C C00, C0, C0) to supperss high harmonic components. The low-pass filter controlls the cut-off frequency of less than. MHz and more than MHz by switching C0 and C0 ON and OFF respectively. The filtered signal is applied to the LO-amplifier (MAIN unit; Q), and is then applied to the st mixer circuit (MAIN unit; Q, Q) via the low-pass filter (MAIN unit; L, L, C C). The reference frequency from the LO-amplifier (PLL unit; Q) is also divided by at IC, and is amplified at the IC. The signal is applied to the DDS-IC (PLL unit; IC, pin ) for the clock signal. -- ND LO CIRCUIT (PLL AND MAIN UNIT) The 0 MHz reference frequency from the Q and X on the PLL unit is multiplied by at Q on the PLL unit. The 0 MHz nd LO signal is obtained at the L and L on the MAIN unit, and is then applied to the nd mixer circuit (MAIN unit; D) via the db attenuator (MAIN UNIT; R R). -- RD LO CIRCUIT (PLL AND MAIN UNIT) The 0 MHz reference frequency is oscillated at the Q and X on the PLL unit, and is then amplified at the Q on the PLL unit. The amplified signal is applied to the 0 bits DDS- IC (PLL unit; IC, pin ) for the clock signal to produce the. MHz rd LO signal. The rd LO signal is applied to the D/A converter circuit, and passes through the low-pass filter (PLL unit; L, L, C C) to suppress spurious components. The filtered. MHz rd LO signal is applied to the rd mixer circuit (MAIN unit; IC, pin 0) -- BFO CIRCUIT (PLL AND MAIN UNIT) The 0 MHz reference frequency is amplified at the Q0 on the PLL unit, and is applied to the 0 bits DDS-IC (PLL unit; IC0, pin ) for the clock signal to produce the khz BFO signal. The BFO signal is applied to the D/A converter circuit, and passes through the low-pass filter (PLL unit, L0, L0, C0 C0) to suppress spurious components. The filtered khz BFO signal is applied to the BFO mixer circuit (MAIN unit; IC0, pin 0). -- VCO CIRCUIT The VCO circuit consists of the VCO circuit (PLL unit; Q, Q, D) and VCO circuit (PLL unit; Q, Q, D). The VCO controls less than displayed frequency of. MHz to use the PLL lock voltage from the DDS-IC. The VCO controls more than displayed frequency of MHz to use the PLL lock voltage from the DDS-IC. - LOGIC CIRCUITS The LOGIC circuit consists of the CPU, the reset circuit, backup battery circuit, and so on. -- CPU (LOGIC UNIT) The CPU (IC0) contains -bit one chip CPU. The CPU controls the operating frequency, mode, function, display, panel switches, panel volumes. The panel switches are connected the CPU input port to the function of the panel switch or are connected some functions of panel switches to the A/D converter input port in the CPU. The CI-V signal which is used for communicate to the personal computer is controlled by the level control circuit (IC0A, IC0B, Q0 and so on). PLL circuit "PCK" signal from the CPU "PDAT" signal from the CPU "PST" signal from the CPU "" signal from the CPU rd LO signal (. MHz) LPF D/A DDS Q, Q, D Q, Q, D VCO switch Q Q LO P/D st LO signal (.0.0 MHz) DDS LPF LPF D/A / "PCK" signal from the CPU "PDAT" signal from the CPU "PST" signal from the CPU "" signal from the CPU BFO signal ( khz) LPF D/A DDS Loop filter nd LO signal (0 MHz) Q IC X DIV "VCOS" signal "LOF" signal "" signal from the CPU "PST" signal from the CPU "PCO" signal from the CPU "PCK" signal from the CPU "PDAT" signal from the CPU -

11 The CPU has the clock function. Thus, the CPU and the clock function have the crystal separately. The CPU has the.0 MHz crystal (X) for the CPU clock, and then the oscillated.0 MHz signal is applied to the IC0, pin and. The clock function has the. khz crystal (X). The oscillated. khz signal is applied to the CPU (IC0, pin and ). When the power is OFF, the EEPROM (IC) is used for keep on saving the data of memory channels, and so on. -- RESET CIRCUIT (LOGIC UNIT) The reset circuit consists of Q, D, D, D, IC and IC. When IC-R is supplied. V to connect the AC adapter, the HV signal is applied to the IC, pin. The signal which is output from the IC, pin is applied to the IC, pin. The signal is applied to the Q, and is then output to the CPU (IC0, pin ) as CRES reset signal. A portion of the output signal from the IC is input to the CPU (IC0, pin ) as BKUP signal to backup the clock data. -- BACKUP SWITCH CIRCUIT (LOGIC UNIT) IC-R has a backup switch circuit (Q and Q). When IC-R is supplied to. V to connect the AC adapter, the HV signal is applied to Q, pin, and then Q is OFF. When the AC adapter is disconnected, the BATT signal from the battery (MAIN unit; BT) is applied to the Q, and then Q is OFF. The output signal is applied to the CPU (IC0, pin ) as BV signal to keep on working the clock function. The backup battery is not used while the AC adapter is connected. - POWER SUPPLY CIRCUITS -- VOLTAGE LINES (MAIN UNIT) Line HVR HV V RV V V V Description The voltage from the connected DC power supply. Common V converted from the HVR line by the + regulator circuit (IC). Common V converted from the HVR line by the regulator circuit (IC and D). The output voltage is applied to the pre-amplifier (Q and Q) via the PRE regulator circuit (Q) and the IF-amplifier (Q) via the RV regulator circuit (Q). Receive V converted from the V line by the R regulator circuit (Q, Q and D). The output voltage is applied to the IF-amplifier (Q, Q), the switch control circuit (Q), and the driver circuit (IC and IC, pin ). Common V converted from the V line by the + regulator circuit (IC). The output signal is applied to the low-pass filter (ICA, pin ), buffer amplifiers (Q0 and Q0), the preamplifier (IC) via the REG regulator circuit (Q) and the AM detector circuit (IC00, pin ). Common V converted from the V line by the + regulator circuit (IC0). Common V converted from the V line by the V DC-DC convertor circuit (IC, D and D). -

12 - PORT ALLOCATIONS -- CPU (LOGIC UNIT; IC0) Pin number Port name Description Pin number Port name Description KEY CRES Input port for [0] and [ENT] switch from the 0-key. Input port for the reset signal. Low : While the reset switch is pushed. 0 MWK CLRK SELK SCAK Input port for the [MW] switch. Input port for the [CLR] switch. Input port for the [SEL] switch. Input port for the [SCAN] switch. PWRK DUD Input for the [POWER] switch. Low : While [POWER] switch is pushed. Input port for the UP signal from the [MAIN DIAL]. UPK DNK LOCK SETK Input port for the [UP] switch. Input port for the [DN] switch. Input port for the [LOCK] switch. Input port for the [SET] switch. DAST RSTB Outputs strobe signals for the D/A converter (LOGIC unit; IC). Outputs strobe signals for the shift registor (MAIN unit; IC, IC). CLKK Input port for the [CLOCK] switch. Outputs reset signal to the PLL IC and DDS IC. Low: PLL IC and DDS IC is reset. ISTB ASTB Outputs strobe signals for the shift registor (MAIN unit; IC0). Outputs strobe signals for the shift registor (MAIN unit; IC0). PWRS BEEP Outputs control signal for the regulator circuit (MAIN unit; IC and D). Outputs beep audio signals. 0 ECS PCK PST PDAT PST PST SSBK CWK AMK FMK FILK TSK PREK Outputs ECS signals for the EEPROM (LOGIC unit; IC). Outputs clock signal to the EEPROM and shift registors. Outputs data signals to the EEPROM, shift registors, etc. Outputs clock signals to the PLL IC (PLL unit; IC) and the DDS IC (PLL unit; IC, IC0). Outputs strobe signals for the PLL IC. Outputs data signals to the PLL IC and the DDS IC. Outputs strobe signals for the DDS IC (IC). Outputs strobe signals for the DDS IC (IC0). Input port for the [SSB] switch. Input port for the [CW] switch. Input port for the [AM] switch. Input port for the [FM] switch. Input port for the [FIL] switch. Input port for the [TS] switch. Input port for the [P.] switch. 0 0 RXS AGRS SQLS BKUP DCK RECS AFGL RFGL PBL Outputs control signal for the R regulator circuit (MAIN unit; Q, Q, D). Outputs reset signal to the delay control circuit (MAIN unit; Q0). Outputs control signal for the delay control circuit (MAIN unit; Q0, Q0 Q0). Outputs squelch control signal to the AF selector circuit (MAIN unit; IC0). Input port for the BKUP signal from the reset circuit (LOGIC unit; IC). Input port for the UP signal from the [MAIN DIAL]. Outputs control signal for the remote recording driver. Input port for the AF gain signal from the [AF] volume on the front panel. Input port for the SQL/RF gain signal from the [SQL/RF] volume on the front panel. Input port for the PBT signal from the [TWIN PBT] volume on the front panel. ATTK NRK ANFK NBK K Input port for the [ATT] switch. Input port for the [NR] switch. Input port for the [ANF] switch. Input port for the [NB] switch. Input port for the [] switch. PBL FMNL Input port for the PBT signal from the [TWIN PBT] volume on the front panel. Input port for the FM noise squelch signal from the FM detector circuit (MAIN unit; IC00 and X00). VMK Input port for the [V/M] switch. -

13 SECTION ADJUSTMENT PROCEDURES - PREPARATION REQUIRED TEST EQUIPMENT EQUIPMENT DC power supply Frequency counter Audio generator DC Voltmeter GRADE AND RANGE Output voltage :. V DC Current capacity : A or more Frequency range : 0 MHz Frequency accuracy : ± ppm or better Sensitivity : 00 mv or better Frequency range : 0 Hz Measuring range : mv Input impedance : 0 kω/v DC or better EQUIPMENT Oscilloscope AC millivoltmeter External speaker Standard signal generator (SSG) GRADE AND RANGE Frequency range : DC 0 MHz Measuring range : 0.0 Measuring range : 0 mv Input impedance : Ω Capacity : W or more Frequency range : 00 MHz Output level : µv mv ( to dbm) CONNECTION NOTE: The [0 Ω] ANT jack is not used for adjustment AC milli-voltmeter Standard Signal Generator Terminator for the entering adjustment mode DC power supply. V / 0A /" (. mm) Speaker -conductor plug Shorten inner and outer plugs DC IN 0 Ω ANT 0 Ω ANT EXT SP REMOTE connector -

14 - PLL ADJUSTMENT ADJUSTMENT REFEREE FREQUEY VCO VOLTAGE ST LO VOLTAGE RD LO VOLTAGE RD LO FREQUEY BFO VOLTAGE ADJUSTMENT CONDITION Displayed frequency :. MHz Mode : USB Displayed frequency :. MHz Mode : USB Displayed frequency : MHz Mode : USB Displayed frequency : MHz Mode : USB Displayed frequency : MHz Mode: USB Displayed frequency : MHz Mode : USB Displayed frequency : MHz Mode : USB Displayed frequency :. MHz Mode : FM Displayed frequency : MHz Mode : USB Displayed frequency : MHz Mode : AM ADJUSTMENT MEASUREMENT VALUE POINT UNIT LOCATION UNIT ADJUST PLL Connect the frequency counter to MHz PLL L P. Connect the RF Maximum voltage L, L voltmater to P. PLL Connect the DC. PLL C voltmeter to HCP. PLL PLL PLL PLL Connect the RF voltmeter to P. Connect the RF voltmeter to P. Connect the frequency counter to P. Connect the RF voltmeter to P0. More than 0. V. More than 0. V More than V More than 0... MHz More than 0. Less than 0 µv PLL Verify C Verify Verify Verify Verify Verity *This output level of the standard signal generator (SSG) is indicated as SSG s open circuit. -

15 PLL UNIT P st and rd LO voltage check point C C VCO voltage adjustment HCP VCO voltage check point P Reference frequency check point L L Reference frequency adjustment (for output voltage is maximum) P rd LO frequency check point L Reference frequency adjustment (for output frequency is MHz) P0 BFO voltage check point -

16 - RECEIVER ADJUSTMENTS ADJUSTMENT RECEIVER SENSITIVITY ST MIXER BALAE ADJUSTMENT CONDITION Displayed frequency :.0000 MHz Mode : USB PRE : ON ANT select : ANT : FAST NOISE BLANKER : OFF RF/SQL : CENTER PBT/PBT : CENTER IF FILTER :. khz IF FILTER :. khz Connect an SSG to the antenna connector and set as: Frequency :.00 MHz Level : µv* ( dbµ) Modulation : OFF Receiving Displayed frequency : 0000 MHz PRE : OFF set an SSG level as : OFF Receiving MEASUREMENT ADJUSTMENT VALUE POINT UNIT LOCATION UNIT ADJUST Rear Connect the AC Pre-set to center MAIN R Panel milli-volt meter to R the [EXT SP] jack with an Ω load. Rear panel Connect an oscilloscope to the [EXT SP] jack with Ω load. *This output level of the standard signal generator (SSG) is indicated as SSG s open circuit. MAIN UNIT Maximum output level Minimum noise level MAIN MAIN L, L, L, L, L0, L, L, L, L, L L, R EXT SP JACK Receiver sensitivity and st mixer balance check point R L st mixer balance adjustment L0 L L L L L L L L L R R Receiver sensitivity adjustment Pre-set to center before receiver sensitivity adjustment -

17 RECEIVER ADJUSTMENTS (continued) ADJUSTMENT ST IF FILTER RECEIVER TOTAL GAIN ADJUSTMENT CONDITION Displayed frequency :.0000 MHz Mode : FM PRE : ON IF FILTER : khz IF FILTER : khz set an SSG as Frequency :.0000 MHz Level : 0. µv* ( 0 dbµ) Deviation : ±. khz Modulation : khz Receiving Displayed frequency :.0000 MHz Mode : USB PRE : OFF IF FILTER :. khz IF FILTER :. khz Set an SSG as Frequency :.00 MHz Level : 00 µv* ( dbµ) Modulation : OFF Set an SSG level as : OFF Receiving MEASUREMENT ADJUSTMENT VALUE POINT UNIT LOCATION UNIT ADJUST Rear Connect the AC Maximum output level MAIN L, panel milli-volt meter to L the [EXT SP] jack with an Ω load. Rear panel Connect the AC milli-volt meter to the [EXT SP] jack with an Ω load. 0 db (.) 0 db (0 mv) Front panel MAIN [AF GAIN] control R *This output level of the standard signal generator (SSG) is indicated as SSG s open circuit. MAIN UNIT EXT SP JACK st IF filter and receiver total gain check point L L st IF filter adjustment R Receiver total gain adjustment -

18 RECEIVER ADJUSTMENTS (CONTINUED) ADJUSTMENT NOISE BLANKER ADJUSTMENT CONDITION Displayed frequency :.0000 MHz Mode : USB Noise Blanker : OFF PRE. : ON Set an SSG as Frequency :.0000 MHz Level : µv* ( dbµ) Modulation : OFF Apply the following signal to the [ANT] connector 00 msec. MEASUREMENT ADJUSTMENT VALUE POINT UNIT LOCATION UNIT ADJUST MAIN Connect the oscilloscope Pre-set to center MAIN R to the check Minimun voltage L, point CP. L Rear Panel Connect the oscilloscope to the [EXT SP] jack with an Ω load. Noise is blanked when the [NB] switch is ON. MAIN R msec. *This output level of the standard signal generator (SSG) is indicated as SSG s open circuit. MAIN UNIT EXT SP JACK Noise blanker check point after apply the noise signal R Pre-set to center before apply the noise signal Noise blanker adjustment after apply the noise signal L L Noise blanker adjustment before apply the noise signal CP Noise blanker check point before apply the noise signal -

19 - SET MODE ADJUSTMENT ADJUSTMENT ADJUSTMENT CONDITION DISPLAY OPERATION ENTERING ADJUSTMENT SET MODE PBT VOLUME S-METER Turn power OFF Connect a terminator to the [REMOTE] connector on the rear panel. While pushing SET[ANT] and CLOCK keys, and turn power ON. Connect an SSG to the antenna connector and set as: Frequency :.0 MHz Level : 0 mv* ( dbm) Modulation : OFF Preset both the inner and outer TWIN PBT controls to o clock position. Receiving Set an SSG level as : OFF When success entering adjustment set mode, shown PBT SET on the display. Then advance to the following setting, or push UP key to scroll the display. Push SET[ANT] key.to set the PBT level. When the PBT level is true, shown GOOD on the display. When S0 level of S-meter adjustment mode entering, displayed S0 LV. Push the SET[ANT] key to set the S0 level. Set an SSG level as : µv* ( dbµ) When S level of S-meter adjustment mode entering, displayed S LV. Push the SET[ANT] key to set the S level. Set an SSG level as : mv* ( dbµ) When +0 db level of S-meter adjustment mode entering, displayed +0 LV. Push the SET[ANT] key to set the 0 db level. When the S-meter adjustment is end, displayed END. FILTER CALIBRATION Set an SSG level as : 0 µv* (0 dbµ) When filter calibration adjustment mode entering, displayed FIL CAL. Push the SET[ANT] key to set the filter calibration. Emit to the beep audio. Turn power OFF to exit the adjustment set mode. *This output level of the standard signal generator (SSG) is indicated as SSG s open circuit. -

20 SECTION PARTS LIST [VR BOARD] REF R 0000ARIABLE TPD-F-0KBX-0 R 0000ARIABLE TPD00-F-0KBX-0 R S.RESISTOR ERJGEYJ V (. kω) J S.CONNECTOR -00 EP 000 PCB B B L S.COIL HF0ACC -T R S.RESISTOR ERJYJ0H (00 Ω) R S.RESISTOR ERJYJ0H (00 Ω) C S.CERAMIC C0 JB H K-T-A C S.CERAMIC C0 JB H K-T-A C S.CERAMIC C0 JB H K-T-A J S.CONNECTOR -00 J 000 CONNECTOR HLJ EP 000 PCB B B IC S.IC HDSCH IC 0000 S.IC X0SI-.T IC 0000 S.IC MGP EC IC 0000 S.IC S-0ANMP-DD-T IC 0000 S.IC TCS0F (TER) IC0 000 S.IC TCHC0AF (TP) Q Q Q0 Q Q Q ORDER [PHONE BOARD] REF ORDER [LOGIC BOARD] REF ORDER S.TRANSISTOR DTCEUA T S.TRANSISTOR SC-BL (TER) 0000 S.TRANSISTOR XP0 (TX) S.TRANSISTOR DTAEUA T S.TRANSISTOR SAA T0R 0000 S.TRANSISTOR XP0 (TX) D 0000 S.ZENER MA0-M (TX) D S.DIODE MA (TX) D S.DIODE SS TE- D S.DIODE SS TE- D 0000 S.ZENER ND.G-T X S.XTAL CM00S SMD (.KHZ) X S.XTAL CR- (.0 MHz) L S.COIL HF0ACC -T L S.COIL HF0ACC -T L S.COIL NL T-J L S.COIL NL T-J [LOGIC BOARD] REF ORDER L S.COIL HF0ACC -T R S.RESISTOR ERJGEYJ ( MΩ) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ V (0 Ω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ V ( kω) R S.RESISTOR ERJGEYJ V ( kω) R S.RESISTOR ERJGEYJ V ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ (00 kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ V (0 Ω) R S.RESISTOR ERJGEYJ (0 kω) R S.RESISTOR ERJGEYJ (0 kω) R S.RESISTOR ERJGEYJ (0 kω) R S.RESISTOR ERJGEYJ (00 kω) R S.RESISTOR ERJGEYJ V (. kω) R S.RESISTOR ERJGEYJ V (. kω) R S.RESISTOR ERJGEYJ V (. kω) R S.RESISTOR ERJGEYJ V (. kω) R S.RESISTOR ERJGEYJ V (. kω) R S.RESISTOR ERJGEYJ V (. kω) R S.RESISTOR ERJGEYJ V (. kω) R S.RESISTOR ERJGEYJ V (. kω) R S.RESISTOR ERJGEYJ V (. kω) R S.RESISTOR ERJGEYJ V (. kω) R S.RESISTOR ERJGEYJ V (. kω) S.=Surface mount -

21 [LOGIC BOARD] REF ORDER R S.RESISTOR ERJGEYJ V (. kω) R S.RESISTOR ERJGEYJ V ( kω) R S.RESISTOR ERJGEYJ V ( kω) R S.RESISTOR ERJGEYJ V ( kω) R S.RESISTOR ERJGEYJ V ( kω) R S.RESISTOR ERJGEYJ V ( kω) R S.RESISTOR ERJGEYJ V ( kω) R S.RESISTOR ERJGEYJ V ( kω) R S.RESISTOR ERJGEYJ V ( kω) R S.RESISTOR ERJGEYJ V ( kω) R S.RESISTOR ERJGEYJ V ( kω) R S.RESISTOR ERJGEYJ V ( kω) R S.RESISTOR ERJGEYJ V ( kω) R S.RESISTOR ERJGEYJ V ( kω) R S.RESISTOR ERJGEYJ V ( kω) R S.RESISTOR ERJGEYJ V ( kω) R S.RESISTOR ERJGEYJ V ( kω) R S.RESISTOR ERJGEYJ V ( kω) R S.RESISTOR ERJGEYJ V ( kω) R S.RESISTOR ERJGEYJ V ( kω) R S.RESISTOR ERJGEYJ V ( kω) R S.RESISTOR ERJGEYJ V ( kω) R S.RESISTOR ERJGEYJ V ( kω) R S.RESISTOR ERJGEYJ V ( kω) R S.RESISTOR ERJGEYJ V (. kω) R S.RESISTOR ERJGEYJ V (. kω) R S.RESISTOR ERJGEYJ V (0 kω) R S.RESISTOR ERJGEYJ V (0 kω) R S.RESISTOR ERJYJ0H ( kω) R S.RESISTOR ERJGEYJ V ( kω) R S.RESISTOR ERJGEYJ V ( kω) R S.RESISTOR ERJGEYJ V ( kω) R S.RESISTOR ERJGEYJ V ( kω) R S.RESISTOR ERJGEYJ ( kω) R S.RESISTOR ERJGEYJ V (0 kω) R S.RESISTOR ERJGEYJ V (0 kω) R S.RESISTOR ERJGEYJ V (0 kω) R S.RESISTOR ERJGEYJ (00 kω) R S.RESISTOR ERJGEYJ (0 kω) R S.RESISTOR ERJGEYJ V ( kω) R S.RESISTOR ERJGEYJ V (. kω) R S.RESISTOR ERJGEYJ (00 kω) R S.RESISTOR ERJGEYJ V ( kω) R S.RESISTOR ERJGEYJ (00 kω) R S.RESISTOR ERJGEYJ V (0 Ω) R S.RESISTOR ERJGEYJ (00 kω) R S.RESISTOR ERJGEYJ (0 kω) R S.RESISTOR ERJGEYJ V (. MΩ) R S.RESISTOR ERJGEYJ (0 kω) R S.RESISTOR ERJGEYJ V ( kω) R S.RESISTOR ERJGEYJ V (. kω) [LOGIC BOARD] REF ORDER C S.CERAMIC C0 JF C 0Z-T-A C S.CERAMIC C0 JF C 0Z-T-A C S.CERAMIC C0 JF C 0Z-T-A C S.CERAMIC C0 JF C 0Z-T-A C S.CERAMIC C0 JF C 0Z-T-A C S.CERAMIC C0 JF C 0Z-T-A C S.CERAMIC C0 JF C 0Z-T-A C S.CERAMIC C0 JF C 0Z-T-A C S.CERAMIC C0 JF C 0Z-T-A J 000 S.CONNECTOR 0-0 J 000 S.CONNECTOR 0-00 J 000 S.CONNECTOR BB-PH-SM-TB J 000 S.CONNECTOR 0-00 J 000 S.CONNECTOR BB-PH-SM-TB J0 000 S.CONNECTOR 0-0 J 000 S.CONNECTOR 0-0 J 000 S.CONNECTOR 0-0 W S.JUMPER ERJGE JPW V [SEA] only W S.JUMPER ERJGE JPW V [SEA] only W S.JUMPER ERJGE JPW V [SEA] only W S.JUMPER ERJGE JPW V WS 000 CABLE RX0 J lead set () /LO EP 000 PCB B 0C EP0 000 S.BEAD MMZ0Y 0BT EP0 000 S.BEAD MMZ0Y 0BT EP 000 S.BEAD MMZ0Y 0BT EP 000 S.BEAD MMZ0Y 0BT EP 000 S.BEAD MMZ0Y 0BT EP 000 S.BEAD MMZ0Y 0BT EP 000 S.BEAD MMZ0Y 0BT EP 000 S.BEAD MMZ0Y 0BT EP 000 S.BEAD MMZ0Y 0BT [FRONT UNIT] REF ORDER SP SPEAKER VS-0-0 C S.CERAMIC C0 JF C 0Z-T-A C S.CERAMIC C0 JF C 0Z-T-A C S.TANTALUM TEMSVA A 0M-L C S.CERAMIC C0 JF C 0Z-T-A C S.CERAMIC C0 JF C 0Z-T-A C S.CERAMIC C0 CH H 00J-T-A C S.CERAMIC C0 CH H 0J-T-A C S.CERAMIC C0 CH H 00J-T-A C S.CERAMIC C0 CH H 00J-T-A C S.CERAMIC C0 JF C 0Z-T-A C S.CERAMIC C0 JF C 0Z-T-A C S.CERAMIC C0 JF C 0Z-T-A C S.CERAMIC C0 JF C 0Z-T-A C S.CERAMIC C0 JF C 0Z-T-A C S.CERAMIC C0 JF C 0Z-T-A C S.CERAMIC C0 JF C 0Z-T-A C S.CERAMIC C0 JF C 0Z-T-A C S.CERAMIC C0 JF C 0Z-T-A C S.CERAMIC C0 JF C 0Z-T-A C S.CERAMIC C0 JF C 0Z-T-A C S.CERAMIC C0 JF C 0Z-T-A C S.CERAMIC C0 JF C 0Z-T-A C S.CERAMIC C0 JF C 0Z-T-A C S.CERAMIC C0 JF C 0Z-T-A C 0000 S.ELECTROLYTIC ECEV0JA0SR C 0000 S.CERAMIC GRM B K 0PT C 0000 S.CERAMIC GRM B K 0PT C S.CERAMIC C0 CH H 0J-T-A C S.CERAMIC C0 JF C 0Z-T-A W CABLE OPC- W CABLE OPC- W CABLE OPC- WS 0000 CABLE RX0 P0FR EP 000 E.OTHER RMS0-0-0-R EP 0000 E.OTHER HLJ0-0-0 [DISPLAY BOARD] REF IC S.IC HD00F Q Q Q Q Q Q ORDER 0000 S.TRANSISTOR SC-BL (TER) 0000 S.TRANSISTOR SC-BL (TER) 0000 S.TRANSISTOR SC-BL (TER) 0000 S.TRANSISTOR SC-BL (TER) 0000 S.TRANSISTOR SC-BL (TER) 0000 S.TRANSISTOR SC-BL (TER) S.=Surface mount -

22 [DISPLAY BOARD] REF ORDER Q Q 0000 S.TRANSISTOR SC-BL (TER) 0000 S.TRANSISTOR SC-BL (TER) R S.RESISTOR MCR0EZHJ 0 Ω () R S.RESISTOR ERJGEYJ V (0 Ω) R S.RESISTOR MCR0EZHJ 0 Ω () R S.RESISTOR ERJGEYJ V (0 Ω) R S.RESISTOR MCR0EZHJ 0 Ω () R S.RESISTOR ERJGEYJ V (0 Ω) R S.RESISTOR MCR0EZHJ 0 Ω () R S.RESISTOR ERJGEYJ V (0 Ω) R S.RESISTOR MCR0EZHJ 0 Ω () R S.RESISTOR ERJGEYJ V (0 Ω) R S.RESISTOR MCR0EZHJ 0 Ω () R S.RESISTOR ERJGEYJ V (0 Ω) R S.RESISTOR MCR0EZHJ 0 Ω () R S.RESISTOR ERJGEYJ V (0 Ω) R S.RESISTOR MCR0EZHJ 0 Ω () R S.RESISTOR ERJGEYJ V (0 Ω) C S.CERAMIC C0 JF C 0Z-T-A J0 000 S.CONNECTOR 0-0 DS S.LED TLYE00 DS S.LED TLYE00 DS S.LED TLYE00 DS S.LED TLYE00 DS S.LED TLYE00 DS S.LED TLYE00 DS S.LED TLYE00 DS S.LED TLYE00 DS S.LED TLYE00 DS S.LED TLYE00 DS S.LED TLYE00 DS S.LED TLYE00 DS S.LED TLYE00 DS S.LED TLYE00 DS S.LED TLYE00 DS S.LED TLYE00 DS S.LED TLYE00 DS S.LED TLYE00 DS S.LED TLYE00 DS S.LED TLYE00 DS S.LED TLYE00 DS S.LED TLYE00 DS S.LED TLYE00 DS S.LED TLYE00 DS LCD HLC-000 EP 000 PCB B 0B EP 000 LCD CONTACT SRCN-0-SP-N-W [MAIN UNIT] REF ORDER IC 0000 S.IC µpcg-e IC 0000 S.IC BU0BCFV-E IC 0000 S.IC BU0BCFV-E IC S.IC TDAF (TP) IC S.IC TDAF (TP) IC 0000 IC LA0N IC S.IC MC D IC S.IC TAFN (EL) IC S.IC MC D IC S.IC BU0BCFV-E IC 0000 S.IC NJM0M-T IC S.IC MFP 0CD IC S.IC BU0BCFV-E IC IC LAA IC S.IC ANL0M-(E) [MAIN UNIT] REF ORDER IC 0000 IC PQ0RV IC 0000 S.IC TA0F (TEL) IC S.IC TA0F (TEL) IC S.IC µpcg-t IC S.IC BU0BCFV-E IC S.IC BU0BCFV-E IC S.IC TDAF (TP) IC 0000 S.IC DSCTM IC 0000 S.IC TCW0F (TEL) IC S.IC MC0ADWR Q S.TRANSISTOR DTCEUA T0 Q S.FET SK--TD Q S.FET SK--TD Q 0000 S.TRANSISTOR XP (TX) Q 0000 S.TRANSISTOR XP (TX) Q 0000 S.TRANSISTOR SCD-TD Q S.FET SK0-TA Q S.FET SK0-TA Q S.FET SK-T MAS Q 0000 S.TRANSISTOR XP (TX) Q S.FET SK-T MAS Q S.FET SK-GR (TEL) Q S.TRANSISTOR SAA T0R Q S.TRANSISTOR SC0 T0 R Q S.TRANSISTOR SC0 T0 R Q S.TRANSISTOR SC0 T0 R Q S.TRANSISTOR DTCEUA T0 Q 0000 S.TRANSISTOR XP (TX) Q S.TRANSISTOR SC0 T0 R Q S.FET SK-T MAS Q S.FET SK-GR (TEL) Q S.TRANSISTOR SC0 T0 R Q S.FET SK-GR (TEL) Q S.TRANSISTOR SC0 T0 R Q S.TRANSISTOR SC0 T0 R Q S.TRANSISTOR XP (TX) Q S.TRANSISTOR SC0 T0 R Q S.TRANSISTOR XP (TX) Q S.TRANSISTOR XP (TX) Q S.TRANSISTOR XP (TX) Q S.TRANSISTOR SC0 T0 R Q S.TRANSISTOR SD T00Q Q S.TRANSISTOR DTCEUA T0 Q S.TRANSISTOR SAA T0R Q S.TRANSISTOR SC0 T0 R Q S.TRANSISTOR DTCEUA T0 D S.DIODE SS0 (TER) D S.DIODE SS0 (TER) D S.DIODE SV-TL D S.DIODE (TX) D S.DIODE SV-TL D S.DIODE (TX) D S.DIODE (TX) D S.DIODE SV-TL D S.DIODE (TX) D S.DIODE (TX) D S.DIODE SV-TL D S.DIODE (TX) D S.DIODE (TX) D S.DIODE SV-TL D S.DIODE (TX) D S.DIODE (TX) D S.DIODE SV-TL D S.DIODE (TX) D S.DIODE (TX) D S.DIODE (TX) D S.DIODE (TX) D S.DIODE (TX) D S.DIODE (TX) D S.DIODE (TX) D S.DIODE HSBWSTR D S.DIODE (TX) D S.DIODE (TX) D S.DIODE (TX) D S.DIODE (TX) D 0000 S.DIODE SS-TL D S.DIODE SS TE- D S.DIODE (TX) S.=Surface mount -

23 [MAIN UNIT] REF ORDER D S.DIODE (TX) D S.DIODE (TX) D S.DIODE (TX) D S.DIODE (TX) D S.DIODE (TX) D S.DIODE (TX) D S.DIODE (TX) D S.DIODE (TX) D S.DIODE (TX) D S.DIODE (TX) D S.DIODE (TX) D S.DIODE SS0 (TER) D S.DIODE (TX) D S.DIODE (TX) D S.DIODE (TX) D S.DIODE (TX) D S.DIODE (TX) D S.DIODE (TX) D S.DIODE (TX) D S.DIODE (TX) D S.DIODE SS-TL D S.DIODE SS-TL D S.DIODE SS TE- D DIODE DSAA D S.DIODE SS TE- D S.DIODE SS0 (TER) D S.DIODE SS0 (TER) D 0000 S.ZENER MA0-M (TX) D S.DIODE SS TE- FI FILTER FL- (.0 MHz) FI FILTER MA (FL-) FI D.FILTER FL- (.0 MHz) FI CERAMIC CFJK (FL-) FI CERAMIC CFWS0HT FI CERAMIC CFWS0E X DISCRIMINATOR CDB0C X CERAMIC CSA.0MGF0 L COIL LR- L S.COIL NL T-R0J L S.COIL NL T-RJ- L S.COIL NL T-J L S.COIL NL T-J L S.COIL ACLS-RK L S.COIL ACLS-RK L S.COIL NL T-J L S.COIL NL T-RJ- L S.COIL NL T-RJ L S.COIL NL T-J L S.COIL NL T-RJ- L S.COIL NL T-RJ- L S.COIL NL T-J L S.COIL NL T-J L S.COIL NL T-RJ- L S.COIL NL T-RJ- L S.COIL NL T-RJ- L S.COIL NL T-RJ- L S.COIL NL T-J L S.COIL NL T-RJ- L S.COIL NL T-RJ- L S.COIL NL T-RJ- L S.COIL NL T-RJ- L S.COIL NL T-J L S.COIL NL T-RJ- L S.COIL NL T-R0J- L S.COIL NL T-R0J- L S.COIL NL T-RJ- L S.COIL NL T-J L S.COIL NL T-RJ- L S.COIL NL T-RJ- L S.COIL NL T-RJ- L S.COIL NL T-R0J- L S.COIL NL T-00J L S.COIL NL T-RJ- L S.COIL NL T-RJ- L S.COIL NL T-RJ- L S.COIL NL T-RJ- [MAIN UNIT] REF ORDER L S.COIL NL T-00J L S.COIL NL T-RJ- L S.COIL NL T-RJ- L S.COIL NL T-RJ- L S.COIL NL T-RJ- L S.COIL NL T-00J L S.COIL NL T-RJ- L S.COIL NL T-RJ- L 0000 S.COIL NL T-RJ- L S.COIL NL T-RJ- L S.COIL NL T-RJ- L S.COIL NL T-00J L S.COIL NL T-RJ- L S.COIL NL T-RJ- L S.COIL NL T-RJ- L S.COIL NL T-RJ- L S.COIL NL T-J L S.COIL NL T-J L S.COIL NL T-J L COIL LR- L S.COIL NL T-RJ- L COIL LR- L S.COIL NL T-J L COIL LW-0 L S.COIL NL T-J L S.COIL NL T-J L S.COIL NL T-J L S.COIL NL T-RJ- L S.COIL NL T-RJ- L S.COIL NL T-00J L S.COIL NL T-R0J L S.COIL NL T-RJ- L S.COIL NL T-R0J L S.COIL NL T-RJ- L COIL LR- L S.COIL NL T-R0J L 0000 COIL LS-A (C-) L S.COIL NL T-00J L 0000 COIL LS-A (C-) L 0000 COIL LS-A (C-) L 0000 COIL LS-B (C-) L 0000 S.COIL LR- L 0000 S.COIL LR- L COIL LS- L 0000 COIL LS- L 0000 COIL LS- L S.COIL NL T-00J L COIL LS- L COIL LS- L S.COIL NL T-J L 000 COIL LS-0 L 000 COIL LS-0 L 000 COIL LS-0 L S.COIL NL T-J L COIL LW- L S.COIL NL T-J L S.COIL HF0ACC -T L S.COIL NL T-J L S.COIL NL T-J L S.COIL NL T-J L S.COIL NL T-J L S.COIL NL T-J R S.RESISTOR ERJGEYJ V ( kω) R ABSORBER DSP-0M-S00B R S.RESISTOR ERJGEYJ V ( kω) R ABSORBER DSP-0M-S00B R S.RESISTOR ERJGEYJ V (. kω) R S.RESISTOR ERJGEYJ V (0 Ω) R S.RESISTOR ERJGEYJ V (0 Ω) R S.RESISTOR ERJGEYJ ( Ω) R S.RESISTOR ERJYJH (0 Ω) R S.RESISTOR ERJGEYJ (0 kω) R S.RESISTOR ERJGEYJ V (0 Ω) R S.RESISTOR ERJGEYJ ( Ω) R S.RESISTOR ERJGEYJ V (0 Ω) R S.RESISTOR ERJGEYJ 0 (0 Ω) R S.RESISTOR ERJGEYJ (00 Ω) R S.RESISTOR ERJGEYJ (00 Ω) R S.RESISTOR ERJGEYJ (00 Ω) R S.RESISTOR ERJGEYJ (00 Ω) S.=Surface mount -