SERVICE MANUAL. HF MARINE TRANSCEIVER im710

Transcript

1 SERVIE MANUAL HF MARINE TRANSEIVER im0

2 INTRODUTION DANGER This service manual describes the latest service information for the I-M0 HF MARINE TRANSEIVER. NEVER connect the transceiver to an A outlet or to a D power supply that uses more than V. This will ruin the transceiver. Version MODEL SYMBOL Others GEN- GEN I-M0 EUR GEN- Others GEN- GMDSS EUR- Others EUR- GMDSS DO NOT expose the transceiver to rain, snow or any liquids. DO NOT reverse the polarities of the power supply when connecting the transceiver. DO NOT apply an RF signal of more than 0 dbm (00 mw) to the antenna connector. This could damage the transceiver s front end. To upgrade quality, any electrical or mechanical parts and internal circuits are subject to change without notice or obligation. ING PARTS REPAIR NOTES Be sure to include the following four points when ordering replacement parts:. Make sure a problem is internal before disassembling the transceiver.. DO NOT open the transceiver until the transceiver is disconnected from its power source.. DO NOT force any of the variable components. Turn them slowly and smoothly.. DO NOT short any circuits or electronic parts. An insulated tuning tool MUST be used for all adjustments.. DO NOT keep power ON for a long time when the transceiver is defective.. DO NOT transmit power into a signal generator or a sweep generator.. ALWAYS connect a 0 db to 0 db attenuator between the transceiver and a deviation meter or spectrum analyzer when using such test equipment.. READ the instructions of test equipment thoroughly before connecting equipment to the transceiver.. 0-digit order numbers. omponent part number and name. Equipment model name and unit name. Quantity required <SAMPLE > TDAF I-M Screw PH M SUS ZK I-M0 MAIN UNIT pieces Top cover 0 pieces Addresses are provided on the inside back cover for your convenience.

3 TABLE OF ONTENTS SETION SPEIFIATIONS SETION INSIDE VIEWS SETION IRUIT - REEIVER IRUITS TRANSMITTER IRUITS PLL IRUITS D-D ONVERTER IRUIT PU PORT ALLOATIONS SETION ADJUSTMENT PROEDURES - PREPARATION BEFORE SERVIING PLL ADJUSTMENT POWER VOLTAGE ADJUSTMENT TRANSMITTER ADJUSTMENT REEIVER ADJUSTMENT SETION PARTS LIST SETION MEHANIAL PARTS AND DISASSEMBLY SETION SEMI-ONDUTOR INFORMATION SETION BOARD LAYOUTS - LOGI UNIT SENSOR/ BOARD MI BOARD VR BOARD VR BOARD MAIN UNIT PLL UNIT PLL-A UNIT PA0W BOARD FILTER BOARD TERMINAL BOARD REG BOARD ALARM BOARD SETION BLOK DIAGRAM SETION 0 VOLTAGE DIAGRAMS 0 - FRONT UNIT MAIN UNIT PLL UNIT PLL-A UNIT PA0W, TERMINAL, FILTER AND REG BOARDS

4 SETION SPEIFIATIONS GENERAL Frequency coverage : Receive Transmit Mode : JE (USB), HE (AM), JB (AFSK), FB (FSK), RE, AA (W) (Available modes differ according to versions) Number of channels : channels (max.) [0 (user programmable), (ITU SSB duplex), (ITU simplex), (ITU FSK duplex)] Antenna impedance : 0 Ω(nominal) : 0 to +0 ; F to +0 F (Specifications are guaranteed with 0 to +0 ; F to +0 F) Usable temperature range khz. MHz.000. MHz MHz MHz MHz MHz MHz MHz MHz MHz Frequency stability : ±0 Hz ( 0 to +0 ; F to +0 F) (±0 Hz above MHz for [GEN-], [GEN-], [EUR-].) Power supply requirement :. V D ±% Negative ground. V D ±% Floating ground urrent drain (at. V D) : Transmit (max. output power) Receive (max. audio output) Dimensions (projections not included) :.(W) (D).(H) mm /(H) /(W) /(D) in Weight :. kg; lb :. kg; lb 0 A. A A [GEN] [GEN] TRANSMITTER Output power (at. V D) : 0, 0, 0 W PEP (0, 0 W PEP only above MHz) [GEN] 0, 0 W PEP (0 W PEP only above MHz) W PEP ( W PEP MF and MHz bands) Spurious emissions : db 0 db arrier suppressions : 0 db unwanted sideband suppression : db Microphone impedance : 00 Ω [GEN] REEIVER Sensitivity JE, RE, JB, AA, FB (for db SINAD) HE (for 0dB S/N) : 0. µv (.000. MHz).0 µv (.000. MHz). µv ( MHz). µv (.000. MHz). µv (.000. MHz) µv ( MHz) Spurious response rejection : 0 db (.000. MHz) Audio output power Audio impedance :. W (at 0% distortion with a Ω load) : to Ω larity variable range : ±0 Hz All stated specifications are subject to change without notice or obligation. -

5 SETION INSIDE VIEWS PA0W, FILTER AND TERMINAL BOARDS TERMINAL board REG board [EUR-], [EUR-] only Fuse (F00) Drive amplifiers (Q00, Q00: S) FILTER board Thermal switches S00: OHD- 0M S00: OHD- 0M Power detector circuit Power amplifiers (Q00, Q00: S0) PA0W board MAIN, PLL AND LOGI UNITS MAIN unit RF filter circuit ALARM board except [GEN-] Noise blanker circuit nd mixer circuit Squelch circuit st IF amplifier (Q: SK) Demodulator circuit (I0: NJMV) st IF filter (FI: FL-0) PLL I (I00: LM) BFO DDS I (I00: S-) PLL/-A unit DDS I (I00: S-A) Reference oscillator (X00: R-) [GEN-], [GEN-], [EUR-] only LOGI unit -

6 SETION IRUIT - REEIVER IRUITS -- ND MIXER AND IF IRUITS (MAIN UNIT) -- RF FILTER IRUIT (MAIN UNIT) The st IF signal from the crystal filter (FIb) is converted again into a.0 MHz nd IF signal at the nd mixer circuit (D, L, L). The 0 MHz nd local signal (LO) from the PLL unit enters the MAIN unit via J to be applied to the nd mixer. Received signals from the antenna connector pass through the transmit/receive switching relay (FILTER board RL) and are then applied to the MAIN unit via J. The signals pass through the protection relay (RL),. MHz cut off high-pass filter (L L,, ) and are then applied to one of nine bandpass filters (including one low-pass filter for below.0 MHz). These filters are selected by the filter control signals (B0 B) as described in the table below. The nd IF signal is passed through the noise blanker gate (D, D) and amplified at the nd IF amplifier (Q) and then applied to one of the MHz IF filters as described below. The passed signal is amplified at the two stage nd IF amplifiers (Q, Q) and is applied to a demodulator circuit (D for HE or I0 for JE and others). The filtered signals pass through the 0 MHz cut-off lowpass filter (L, L, 0, ), and are then applied to the st mixer circuit (Q, Q). ND IF FILTERS USED RF FILTERS USED MODE Used filter ontrol signal JE, RE, FSK FI SEL: low, HE: low HE FI/FI SEL: low, HE: high FSK narrow, AA narrow Optional narrow filter* SEL: high, HE: low Frequency ontrol Entrance Frequency ontrol Entrance (MHz) signal signal coil coil (MHz) 0.. B0 L 0. B L. B L. B L. B L. B L. B L. B L. B L *Built-in to the GMDSS versions -- NOISE BLANKER IRUIT (MAIN UNIT) The noise blanker circuit cuts off the IF circuit line at the moment of receiving a pulse-type noise. A portion of the nd IF signal between resonator circuits (L, L after stage of the nd mixer, D) is amplified at the noise amplifiers (Q, I, Q). The signal is then detected at the noise detector (D) to convert the noise components to D voltages. -- ST MIXER AND IF IRUITS (MAIN UNIT) The st mixer circuit converts the received signals into a fixed frequency,.0 MHz st IF signal using the PLL output frequency. By changing the PLL frequency, only the desired frequency is picked up at the pair of crystal filters (FIa, FIb) at the next stage. The signals are then applied to the noise blanker switch (Q, Q). At the moment the detected voltage exceeds the Q s threshold level, Q outputs a blanking signal to close the noise blanker gate (D, D) by applying reverse-biased voltage. Q turns the noise blanker circuit ON and OFF. The IF amplifier (Q) and resonator circuits are designed between the filter pair. The PLL output signal (LO) enters the MAIN unit via J and is amplified at the st LO amplifier (Q) and then applied to the st mixer (Q, Q) REEIVE FREQUENY ONSTRUTION HE st mixer Q, Q LPF or BPF 0.. MHz Fla/Flb rystal filter.0 MHz st LO:..0 MHz nd mixer D Fl or Fl/Fl rystal filter.0 MHz nd LO: 0.0 MHz - Detector D Other modes Demodulator I0 Audio output BFO JE, JB, RE, FSK:.0 MHz FSK narrow, JB narrow:.0 MHz.0 MHz AA:

7 The detected voltage is also applied to the noise blanker AG circuit (Q, Q0) and is then fed back to the noise amplifier (I) as a bias voltage. The noise AG circuit prevents closure of the noise blanker gate for long periods by non-pulse-type noise. The time constant of the noise blanker AG circuit is determined by R and. -- S-METER IRUIT (MAIN UNIT) The S-meter indicates the AG level on the display, since the AG level varies with the received signal strength. The AG bias voltage (AG time constant line) from the AG amplifier (Q) is inverted and amplified at the meter amplifier (Ib). The amplified signal is applied to the PU via the RSM line. -- DEMODULATOR IRUIT (MAN UNIT) This circuit mixes the nd IF and BFO signals to pick up the AF components (except HE mode). The nd IF signal from the nd IF amplifier (Q) is applied to the balanced mixer (I0, pin ). The.0.00 MHz BFO signal from the PLL unit is also applied to I0 (pin 0). AF signals are output from pin and are then applied to the AF circuits. -- AF AMPLIFIER IRUITS (MAIN UNIT AND LOGI BOARD) AF signals from the demodulator or HE detector circuits pass through the active low-pass filter (I0b) and squelch gate (Ia), and are then applied to the electronic volume control (I). The PU (I, pin ) outputs the volume control signal ( to V) according to the [VOLUME] control setting. -- HE DETETOR IRUIT (MAIN UNIT) The nd IF signal from the nd IF amplifier (Q) is applied to the AM detector circuit (D) to be demodulated into AF signals. The detected signals are amplified at the buffer amplifier (Q), and are then applied to the AF circuits. The AF output signal from I ( pin) are supplied to the LOGI unit via J. The signals are amplified at the AF power amplifier (I00) and are then applied to the internal speaker via microphone connector (pins, ) and external [SP] jack via the MAIN unit. -- AG IRUIT (MAIN UNIT) The speaker switch relay (RL00) is connected to the ( ) terminal of internal speaker for the [SPEAKER] switch function. The AG (Automatic Gain ontrol) circuit reduces IF amplifier gain to prevent the receiver circuit from distorting and to keep the audio output at a constant level. A portion of the IF signals from the nd IF amplifier (Q) is detected at the AG detector circuit (D) and is then applied to the AG amplifier (Q) to control the AG time constant line. The reference voltage of the AG line is controlled by the RFG line which comes from the PU for the RF gain setting. --0 SQUELH IRUIT (MAIN UNIT) The transceiver has two squelch circuits, voice activated squelch for JE/HE and S-meter squelch for AA/FB/ JB. () AF ATIVATED SQUELH A portion of the AF signal from the active low-pass filter (I0b) is amplified at the limiter amplifier (I0a) and is then applied to the one-shot multi-vibrator (Ic, Id). The one shot multi-vibrator functions as an F-V converter which generates a signal only when audio signals are received. When receiving a strong signal, the detected voltage increases and the voltage of the AG line is decreased by the AG amplifier (Q) via the V voltage line. The AG line is used for the bias voltage of the IF amplifiers (Q, Q, Q, Q), so that these amplifiers reduce gain. When the strong signal disappears, the AG line voltage is released by /R and 0/R. The output signals pass through the NOR gate (Ib) and then the Hz low-pass filter (Ia) to remove the remaining noise components. The filtered signal is applied to the window comparator (Ib). The NOR gate (Ib) deactivates the audio activated squelch during AA/FB/JB mode operation. The AG switch (Q, D) turns the AG circuit OFF when the AG OFF function activates. The AG-fast switch (Q) sets the AG line as fast-release during scanning, AA mode selection and DS operation. nd IF filters AG IRUIT HE derector st IF signal Q D Q AG-fast control V AG time constant line Q Q W, DS, SAN Demodulator Q 0 R AG amplifier RFG (RF gain control) 0 to V D AG detector V Q - AG OFF control Q

8 The comparator outputs High when the integrated signals exceed the reference voltage., R0 and R0 are used as a time constant circuit. The resulting signal output from Ia is inverted at Q and is then applied to the PU as the SQLS signal. The PU controls the squelch gate (Ia) when the SQLS signal is received. The SSB signal from FI is amplified at the MHz amplifiers (Q Q) and is then applied to the mixer circuit (D). The switching diode (D) is turned ON when R voltage disappears. () HE AND RE MODES An SSB signal is applied to the IF amplifier (Q) in the same manner as with JE/JB mode. The BFO signal from the PLL unit is amplified at the buffer amplifier (Q0) and is then applied to the IF amplifier (Q) as a carrier signal to be added to an SSB signal. R and R adjust the carrier levels in HE and RE modes, respectively. () S-METER SQUELH The S-meter signal from Ib is applied to the squelch comparator (Ia) to close or open the squelch circuit. The reference voltage is adjusted by R and then applied to the ( ) terminal of the comparator (Ia). When the S-meter signal exceeds the reference voltage, the comparator outputs High to the PU via Ia and Q in the same manner as the voice activated squelch circuit. () AA AND FB MODES The W or FSK voltage are applied to the balanced modulator (I, pin ) to upset the balance and create a carrier signal. In AA mode, the W keying circuit (Ia) controls the bias voltage of the IF amplifiers (Q, Q) and T/R switching diode (D) to switch the carrier transmission. - TRANSMITTER IRUITS -- MIROPHONE AMPLIFIER IRUIT (LOGI BOARD) The AF signals from the [MIROPHONE] connector are pass through the AF amplifier (I00a), and are applied to the balanced modulator (MAIN unit; I, pin ) via the AF switch (Ib). The microphone AG circuit (D00, D00, Q00) controls the amplifier gain to prevent signal distortion. In FB mode, BFO frequency is shifted in the PLL unit to create the mark and space frequencies. -- ST MIXER IRUIT (MAIN UNIT) The amplified signal from the IF amplifier (Q) is mixed with a 0 MHz LO signal at the st mixer circuit (D) to produce a.0 MHz IF signal. The mixer is commonly used with the receiver nd mixer. External modulation inputs from the A, NBDP, DS sockets or a -tone emergency signal from the PU are applied to the balanced modulator directly via AF switches (I I). The.0 MHz IF signal passes through the filter (FIb) and is then applied to the nd mixer circuit. -- MODULATION IRUIT (MAIN UNIT) () JE AND JB MODES The balanced modulator is used for JE and JB modes to add the audio signal to the BFO frequency, and outputs the IF signal while suppressing the BFO signal. -- ND MIXER IRUIT (MAIN UNIT) The filtered signal is mixed with a PLL output frequency (LO:..0 MHz) at the nd mixer circuit (Q, Q) to produce an RF signal which is the same frequency as the displayed one. The AF signals from the microphone amplifier or external audio from the modulation terminals are applied to the balanced modulator (I, pin ). The BFO signal from the PLL unit is applied to (I, pin 0) as a carrier signal. A double sideband signal is output from I (pin ), and is then applied to the MHz filter (FI) to create an SSB signal. -- RF FILTER IRUIT (MAIN UNIT) The RF signal passes through the low-pass filter (L, L,, 0, ) and is then amplified at the RF amplifier (Q). R adjusts the balanced level of I for maximum carrier suppression. In JB mode, the BFO frequency is shifted. khz to set the transmit frequency the same as the displayed frequency. The amplified signal is applied to one of nine RF filters. These RF filters are commonly used with the receiver circuit which consists of eight high-pass filters and one lowpass filter. The filtered signal is amplified at the RF amplifier (Q) and is then applied to the PA0W board via J. MODULATOR IRUIT Microphone I00a -tone alarm A() socket NBDP socket DS socket (GMDSS version only) Ib Ia Ia Ib Ib Balance upset duing W, FSK, Modulator I 0 FI rystal filter D Q BFO from the PLL/PLLA unit (MHz) JE, RE, HE, JB:.0.0 AA:.0 (center) FSK:.00 (center) FSK narrow.0 JB narrow.0 During tuning - W keying control (AA only) Q Q.0 MHz carrier (RE, HE only)

9 -- POWER AMPLIFIER IRUIT (PA0W BOARD) -- AL IRUIT The transceiver has two AL (Auto Level ontrol) loops for constant output power over all marine bands and for high power setting. This circuit provides a stable 0 W (at. V) of output power. The RF signal from the MAIN unit is amplified at the pre-driver (Q00), drivers (Q00, Q00), and power amplifiers (Q00, Q00). () IF AL IRUIT (MAIN UNIT) A portion of the IF signals from the IF amplifier (Q) is applied to the IF AL circuit. The signal is amplified at Q and then detected at the AL detector (D). The detected signal is amplified at the AL amplifier (Ib) and is then applied to the comparator (Ia). The driver and power amplifiers form class AB push-pull circuits. Bias voltage to these transistors is produced by diodes (D00 D00) which have temperature junctions with the transistors. The reference voltage for the comparator is set by R. The antenna tuning control voltage (TUN) and low power set signal (PO) are also affected by the reference voltage to decrease the IF signal level. The amplified signal is then applied to one of eight lowpass filters to suppress high harmonic components. The filtered signal passes through the power detector circuit (FILTER board; L) and transmit/receive switching relay (FILTER board; RL) and is then applied to the antenna connector. The comparator output controls the gate bias of the IF amplifier (Q), so that the IF signal level is determined by the reference voltage of the comparator (Ia). LOW-PASS FILTERS USED (FILTER BOARD) Frequency ontrol Entrance Frequency ontrol Entrance signal signal Relay Relay (MHz) (MHz) 0.. L0 RL0 0. L RL. L RL0. L RL0.. L RL. L RL0 RL L RL. L () RF AL IRUIT (FILTER BOARD) The RF output power level is detected at D0 of the power detector circuit (FILTER board; L, D0, D0). The detected signal ( FOR signal) is applied to the RF AL amplifier (MAIN unit; Ia). The amplified signal enters the transmit gain controller (Ib) which functions as an inversion amplifier. The gain controller decrease the gain of the IF amplifier (MAIN unit; Q) to constant output power from differential amplifier gains which are occurred by their frequency characteristics. The bias voltage of the RF AL amplifier (Ia) is controlled by the low power control signal (PO for 0 W, PO for 0 W) and AP signal. AL IRUIT Q D Q, Q Q Q Q00 Q00 Q00 Q00 Q00 L V FOR IF AL IRUIT Ia D0 Q FILTER UNIT Ib Q High power set (R) Low power during tune (Q) 0 W low power set (Q) Ib Ia urrent AP control (Q) Low power during tune (Q, Q) urrent AP Q 0 W power set (Q) 0 W power set (Q) RF AL IRUIT V - Q PA UNIT D0 MAIN UNIT

10 -- AP IRUIT - PLL IRUIT The AP (Auto Power ontrol) circuit protects the power amplifiers on the PA unit from high SWR and excessive current. -- GENERAL The PLL unit generates a st LO frequency (..0 MHz), nd LO frequency (0 MHz) and a BFO frequency (.00.0 MHz) for the MAIN unit. The st LO PLL adopts a mixerless dual loop PLL system. The BFO uses a DDS and a nd LO as a fixed frequency double that the crystal oscillator. () SWR AP (FILTER BOARD AND MAIN UNIT) The reflected wave signal appears and increases on the antenna connector. When the antenna is mismatched, D0 of the power detector circuit (FILTER board; D0, D0, L) detects the signal and applies it to the AP amplifier (MAIN unit; Q). The amplified signal decreases the bias voltage of the RF AL amplifier to reduce the output power. -- ST LO PLL (PLL UNIT) The st LO PLL contains a main loop and reference loop as a dual loop system. The reference loop generates a 0. to 0. MHz frequency using a DDS circuit, and the main loop generates a. to.0 MHz frequency using the reference loop frequency. () URRENT AP (PA0W BOARD AND MAIN UNIT) The power transistor current is detected from the different voltages between both terminals of a 0.0 Ω resistor (R0) on the PA0W board. The detected voltage is applied to the differential amplifier (I00b). When the current of the final transistors is more than 0 A, the detected voltage is applied to the AP amplifier controller (MAIN unit; Q) to reduce the gate- voltage of the IF amplifier (MAIN unit; Q) and thus reduce the output power. () ERENE LOOP PLL The oscillated signal at the reference VO (Q00, D00) is amplified at the buffer amplifiers (Q00, Q0) and is then applied to the DDS I (I00, pin ). The signal is then divided and detected on phase with the DDS generated frequency. The detected signal output from I00 (pin ) is converted into a D voltage (lock voltage) at the loop filter (R0, R0, 0) and then fed back to the varactor diode (D00) in the VO circuit. -- TEMPERATURE DETETION (PA0W BOARD) Thermal switches (S00, S00) protect the final transistors from excessive temperatures. When the temperature of the final transistors exceeds 0 ( F), S00 is turned ON to start the cooling fan. When the temperature of the final transistors exceeds 0 (0 F), S00 is turned ON to control the PO line and sets the power to 0 W. () MAIN LOOP PLL The oscillated signal at the main loop VO (Q00, D00) is amplified at the buffer amplifiers (Q00, Q00), and is then applied to the PLL I (I00, pin ). The signal is then divided and detected on phase with the reference loop output frequency. --0 RF METER IRUIT (MAIN UNIT) The detected signal output from I00 (pins 00, 00) is converted into a D voltage (lock voltage) at the loop filter and then fed back to the varactor diode (D00) in the VO circuit. The output of the AL amplifier (Ia) is applied to the PU (pin ) to indicate the transmit power level on the display. For antenna current meter indication, the ANT signal from an optional AT-0E is applied to the PU (pin ). The oscillated signal is amplified at the buffer amplifiers (Q00, Q0, Q0) and then applied to the MAIN unit as a st LO signal. PLL IRUIT PLL I (I00) Main loop VO Q00 Phase detector Programmable Programmable divider divider Q0 LO (..0 MHz) Loop filter Q00/D00 Q MHz Q00 DDS I (I00) Q0 Q00 Doubler LO (0.0 MHz) Loop filter Phase detector Reference loop VO Q00/D00 Programmable divider Q0 Programmable divider DDS DDS I00 D/A convertor D/A convertor Reference OS (X00; 0.0 MHz) - BFO (.00.0 MHz)

11 -- ND LO AND ERENE OSILLATOR IRUITS - PORT ALLOATIONS The reference oscillator (X00) generates 0.0 MHz frequency used for the both DDS Is as a system clock and for the LO output. The oscillated signal is doubled at the driver (Q00) and picked up the 0 MHz frequency at the resonator circuit (L00, L00). The 0 MHz signal is applied to the MAIN unit as a nd LO signal. Pin number PU (MAIN unit; I) Port name Description RES Input port for the PU reset signal. When receiving a LOW pulse, the PU is reset. 0 RXDO Data input port from the sub PU in the FRONT unit. TXDO Data output port to the sub PU in the FRONT unit. NSEN Input port to the sub PU in the FRONT unit. PO Outputs low power control signal for 0 W power. PO Outputs low power control signal for 0 W power. - D-D converter IRUIT (REG UNIT; only) 0 WIN Input port for the W keying. High: When key is closed. The I-M0 version employs a floating grounding system which is not connected between transceiver s ground and ( ) terminal of the power supply. The PA unit separate grounding from the other units to obtain floating. ASEN Outputs a SEND control signal for the A () and A () sockets. SEN Outputs a SEND control signal for T and R voltage line control. Low : For transmit. ALMS Outputs an alarm control signal to activate the -tone emergency alarm encoder. High : Alarm ON. I00 is a switching control I which contains a V reference voltage regulator (pins, ), two error amplifiers (pins,, ), a saw tooth oscillator (pins ) and a comparator. The switching frequency is determined by R00 and 00 and is set at khz. ALM Outputs a tone switching signal for the -tone emergency alarm encoder. High : High tone. SL Outputs a clock signal for the EEPROM (I). A voltage appear on the secondary terminals of T00 and rectified by D00. The rectified D voltages are passed through the noise filter (L00, 00, 00), and are then applied to the MAIN unit as a. V D voltage line. SDA Data bus line for the EEPROM (I). SO Outputs a serial signal for the EEPROM (I). SDA Data bus line for the EEPROM (I). 0 RSM Input port for the S-meter indication. MFOR Input port for the RF-meter indication. ANT Input port for the antenna current meter indication for version. The ANT signal can be received when an optional AT-0E is connected. SQLS Input port for the squelch detected signal. High : When squelch is open. TR Input port for the transmit/receive switching signal. SAS Input port for the scan control signal from the A () socket. RFG Outputs RF gain control signal to the AG circuit. -- BFO IRUIT The DDS I (I00) generates a 0-bit digital signal using the 0 MHz system clock. The digital signal is converted to an analog wave signal at the D/A converter (R0 R). The analog wave is passed through the low-pass filter (L0, L0, ), and is then applied to the MAIN unit as the BFO signal. The PA unit separate grounding from the other units to obtain floating. The. V D from the D power connector passes through the noise filter (L00, 00 00), and is then applied to the switching transformer (T00). The MOS FET (Q00) is turned ON and OFF by D00 and Q00 respectively. -

12 (MAIN unit; I) ontinued Pin number Port name Description AFG Outputs AF gain control signal to the control (I). STAT Outputs the "tuner start" pulse to an optional AT-0E. 0 BEEP Outputs a BEEP signal ( khz or 00 Hz). STB Outputs a strobe signal to the main loop PLL I (00). STB Outputs a strobe signal to the reference loop DSS I (I00). STB Outputs a strobe signal to the BFO PLL I (I00). DATA Outputs a data signal to PLL and DDS Is. 0 K Outputs a clock signal to PLL and DDS Is. SQL Outputs an AF mute signal for squelch function. High : Squelch closed. NBS AGS Outputs an AG -OFF signal. High: AG deactivate. NMS Outputs an external NBDP equipment control signal. Low: During NBDP data output. P0 Outputs a strobe signal for an initial matrix. 0 Outputs a noise blanker signal. High : Noise blanker is on P P Input ports for an initial matrix. PD PA Output band signals for RF LPF and BPF selection. JB, RE, Outputs mode signals. HE KEY Input port for an optional AT-0E. Low : During tuning. W Outputs a mode signal. 0 TUNE Outputs an antenna tuner tuning control signal for transceiver s power/ mode control. FSEL Outputs a narrow filter selection signal. Low : Optional narrow filter selection. PROG Outputs a program scan control signal for AG fast and audio squelch deactivation. -

13 SETION ADJUSTMENT PROEDURES - PREPARATION BEFORE SERVIING REQUIRED TEST EQUIPMENT GRADE AND RANGE EQUIPMENT D power supply Output voltage urrent capacity :. V D : 0 A or more RF power meter (terminated type) Measuring range Frequency range Impedance SWR : 0 00 W :. 0 MHz : 0 Ω : Less than. : Frequency counter Frequency range Frequency accuracy Sensitivity : MHz : ± ppm or better : 00 mv or better GRADE AND RANGE EQUIPMENT Frequency range Measuring range : Hz : 00 mv Frequency range Output level : 0. 0 MHz : to dbm (0. µv mv) Oscilloscope Frequency range Measuring range : D 00 MHz : V A millivoltmeter Measuring range : 0 mv 0 V :Ω : W or more : 0 or 0 db : 0 W or more Audio generator Standard signal generator (SSG) RF voltmeter Frequency range Measuring range : MHz : V External speaker Input impedance apacity D voltmeter Input impedance : 0 kω/v D or better Attenuator Power attenuation apacity D ammeter Measurement capability : A/ A /0 A Spectram analyzer Frequency minimum Spectrum bandwidth : At least 0 MHz : ±00 khz or more Electronic load Input voltage Load current :. V or more : 0 A or more ONNETIONS to [EXT SP] A millivoltmeter Attenuator 0 or 0 db Speaker Audio generator Spectrum analyzer RF power meter 00 W/0 Ω Pin MIE Standard signal generator Pin MI onnect pins and for AF output D power suppy. V/0 A to the antenna connector [PTT] AUTION: DO NOT connect the signal generator while transmitting. to D power receptacle [D.V] [ANT] I-M0 to [MIROPHONE] -

14 - PLL ADJUSTMENTS ADJUSTMENT ADJUSTMENT ONDITION MEASUREMENT UNIT ERENE Display frequency Mode LOOP LOK Receiving VOLTAGE :. MHz : JE Display frequency : MHz Display frequency Receiving : MHz Display frequency :. MHz MAIN LOOP LOK VOLTAGE ERENE Wait for minutes after power ON. Terminate P00 on the PLL unit FREQUENY to ground with a 0 Ω resister. Receiving VALUE LOATION ADJUSTMENT POINT UNIT ADJUST PLL onnect a digital. V multimeter or oscilloscope to check point J00. More than. V PLL 0 PLL o n n e c t a d i g i -.0 V tal multimeter or oscilloscope to check point J00. PLL L0 R Verify More than.0 V PLL onnect an RF volt- Maximum level meter to check point (More than + dbm) P00. Verify PLL onnect a frequency MHz counter to check point P00. : [GEN-], [EUR-] L00 L00 X00 L00 : [GEN-], [GEN-], [EUR-] - POWER VOLTAGE ADJUSTMENT ADJUSTMENT ADJUSTMENT ONDITION MEASUREMENT UNIT. V VOLTAGE ( only) Turn power ON. MAIN LOATION onnect a D volt-. V meter to L0. : [EUR-], [EUR-] - VALUE ADJUSTMENT POINT UNIT REG ADJUST R0

15 MAIN AND PLL UNITS L0. V voltage check point 0 Reference loop lock voltage adjustment J00 Reference loop lock voltage check point P00 Reference frequency check point J00 Main loop lock voltage check point L00 L00 L00 R Main loop lock voltage adjustment Reference frequency Adjustment X00 Reference frequency Adjustment L0 Main loop lock voltage adjustment REG BOARD ( only) R0 -. V voltage adjustment

16 - TRANSMITTER ADJUSTMENTS ADJUSTMENT ADJUSTMENT ONDITION MEASUREMENT UNIT IDLING URRENT (For drive transistors) VALUE LOATION Display frequency :.00 MHz PA0W ut the lead wire 00 ma Mode : JE (W0) and connect Apply no audio signal to the a D ammeter ( A) [MIROPHONE] connector. to the cut points. Transmitting ADJUSTMENT POINT UNIT ADJUST PA0W R0 PA0W R0 PA0W R0 After adjustment, re-solder the lead wire (W0) on the PA0W board. (For final transistors) Display frequency :.00 MHz PA0W U n s o l d e r R 0 00 ma Mode : JE and connect the D Apply no audio signal to the ammeter ( A) to the [MIROPHONE] connector. unsoldered points. Transmitting After adjustment, re-solder R0 on the PA0W board. I AP Display frequency :.0000 MHz Mode : JE Preset R0 on the PA0W board to the maximum counterclockwise position. onnect an electronic load with 0 A load current (example: KIKUSUI PLZW) between lead of R0 (power line) and EP00 (ground) on the PA0W board. onnect an audio generator to the [MIROPHONE] connector and set as: Frequency :. khz Level : 00 mv rms onnect an RF power meter to the [ANT] connector. Transmitting Rear Panel o n n e c t a D 0A ammeter (0 A) b e t we e n t h e D power supply and D power receptacle (D input +). After adjustment, remove the electronic load on the PA0W board.. SWR DETETOR Display frequency :.0000 MHz Mode : JE Ground the lead of R on the MAIN unit with a wire. onnect an audio generator to the [MIROPHONE] connector and set as: Frequency :. khz Transmitting Rear Panel o n n e c t a n R F 0 W power meter to the [ANT] connector. Audio generator Output level MAIN onnect a D volt- Minimum level meter to R0. FILTER MAIN Adjust in sequence L, L, L, L, L After adjustment, remove the wire from R on the MAIN unit. TRANSMIT PEAK Display frequency :.00 MHz Mode : JE Ground the lead of R on the MAIN unit with a wire. onnect an audio generator to the [MIROPHONE] connector and set as: Frequency :. khz Level : mv Transmitting Rear Panel o n n e c t a n R F Maximum output power power meter to the [ANT] connector. After adjustment, remove the wire from R on the MAIN unit. -

17 PA AND FILTER BOARDS I AP check point Ammeter D power supply R0 Idling current (for drive transistors) adjustment R0 W0 Idling current (for drive transistors) check point Idling current (for final transistors) adjustment Ammeter EP00 EP00 W0 ut R0 Idling current (for final transistors) check point SWR detector adjustment Ammeter I AP preparation R0 EP00 EP00 Electronic load (0 A) Unsolder R0 R0 I AP adjustment MAIN UNIT R0 SWR detector check point Transmit peak adjustment R SWR detector Transmit peak preparation L L L L L -

18 TRANSMITTER ADJUSTMENTS (continued) ADJUSTMENT ADJUSTMENT ONDITION MEASUREMENT UNIT TRANSMIT GAIN OUTPUT POWER VALUE LOATION Display frequency :.00 MHz Mode : AA FA Transmitting Rear Panel o n n e c t a n R F 0 W power meter to the [ANT] connector. Display frequency :.0 MHz Transmitting MAIN onnect a digital 0. V multimeter to R. Display frequency :.00 MHz Mode : HE Apply no audio signal to the [MIROPHONE] connector. Transmitting Rear Panel o n n e c t a n R F W power meter to the [ANT] connector. ADJUSTMENT POINT UNIT ADJUST MAIN R R MAIN R Mode Transmitting : RE.0 W R Mode : FB AA 0 W 0 W R Transmitting ARRIER SUPPRESSION Display frequency :.00 MHz Mode : JE Apply no audio signal to the [MIROPHONE] connector. Transmitting Rear Panel onnect a spectrum Minimum carrier level analyzer or RF volt- (Less than 0 db) meter to the [ANT] connector via an attenuator. MAIN Adjust alternately R, R TUNE POWER Display frequency :.00 MHz Ground the lead of L0 (KEY line) on the MAIN unit with a wire. Transmitting Rear Panel o n n e c t a n R F 0 W power meter to the [ANT] connector. MAIN R0 POWER METER While pushing the [SQL] and [TX] switches, turn power ON. Display frequency :.00 MHz Mode : JE onnect an audio generator to the [MIROPHONE] connector and set as: Frequency :. khz Level : 00 mv Set the transmit power level: [GEN] versions : PO- versions : PO- Transmitting Rear Panel o n n e c t a n R F [GEN] versions: W Audio power meter to the versions: 0 W generator [ANT] connector. MI LIMITTER for, Push the [DIMMER] switch. Display frequency :.00 MHz MAIN Mode : JE Disconnect the BFO plug (J) on the MAIN unit. onnect an audio generator to the [MIROPHONE] connector and set as: Frequency :. khz Level : 0 mv Transmitting onnect an oscil- 0 mv PEP loscope to R. Output level Font Panel [DIMMER] LOGI R00 LOGI R0 After adjustment, connect the BFO plug to the J on the MAIN unit. MI GAIN Display frequency Mode onnect an audio [MIROPHONE] set as: Frequency Level Transmitting [GEN]: [GEN-], [GEN-], [GEN-] : [GEN-], [EUR-] :.00 MHz : JE generator to the connector and Rear Panel o n n e c t a n R F 00 W meter to the [ANT] connector. :. khz : 0 mv : [EUR-], [EUR-] -

19 MAIN AND LOGI UNITS Transmit R gain adjustment R Transmit R gain chack point MI limitter preparation L0 Tune power preparation R0 Tune power adjustment R R R Output power adjustment R R arrier suppression adjustment J R0 MI gain adjustment R00 MI limitter adjustment -

20 - REEIVER ADJUSTMENTS ADJUSTMENT ADJUSTMENT ONDITION MEASUREMENT UNIT ADJUSTMENT POINT VALUE LOATION REEIVER GAIN LARITY While pushing the [SQL] and [E] Set the [LARITY] control to the center position and push the [DIMMER] switch. switches, turn power ON. TOTAL GAIN Display frequency :.00 MHz Mode : JE onnect a standard signal generator to the [ANT] connector and set as: Frequency :. MHz Level : 0. mv* ( dbm) Modulation : OFF Receiving S-METER NOISE BLANKER Display frequency :.0 MHz Mode : JE Noise blanker : OFF Squelch : OFF Speaker : OFF AG : ON RF gain : R (MAIN unit) : Max. clockwise R (MAIN unit) : enter R00 (MAIN unit) : enter onnect a standard signal generator to the [ANT] connector and set as: Frequency :. MHz Level : 0. µv* ( dbm) Modulation : OFF Receiving Rear Panel Rear Panel o n n e c t a n A Maximum output level millivoltmeter to the [EXT SP] jack with a Ω dummy load. o n n e c t a n A.0 V millivoltmeter to the [EXT SP] jack with a Ω dummy load. UNIT ADJUST MAIN Adjust in sequence L, L, L, L, L, L, L, L, L Front Panel [LARITY] Front Panel [VOLUME] Set the signal generator to OFF (no output). 0 db ( mv) MAIN R While pushing the [SQL] and [RX] Function S/RF meter display switches, turn power ON. Display frequency :.00 MHz Mode : JE onnect a standard signal generator to the [ANT] connector and set as: Frequency :. MHz Level :. mv* ( dbm) Receiving Push the [DIMMER] switch and then verify the th dot just appears on the S/RF meter. Font Panel [DIMMER] MAIN L0, L Display frequency :.00 MHz Mode : JE onnect a standard signal generator to the [ANT] connector and set as: Frequency :. MHz Level :. µv* ( dbm) Add the following signal into the signal generator output. MAIN onnect an oscillo- Adjust the maximum noise wave displayed scope to R. on the oscilloscope. 00 msec. msec. Receiving *This output level of the standard signal generator (SSG) is indicated as SSG s open circuit. -

21 MAIN UNIT MAIN UNIT Noise blanker adjustment L0 L L Noise blanker check point Receiver gain adjustment R00 R R L L L L L L L L L Receiver gain preset R Total gain adjustment -

22 SETION PARTS LIST [LOGI BOARD] [FRONT UNIT] S SWITH JPZ0-00 (TV-) SP SPEAKER FG0-0 W0 W0 W0 W0 W OP- OP- OP- OP- OP- WS WS 0000 M.OTHER 0000 M.OTHER ABLE ABLE ABLE ABLE ABLE (N: L:00) (N: L:00) (N:0 L:0) (N: L:00) (N: L:00) SX P0FR SX P0FR [LOGI BOARD] I00 I00 I00 I00 I00 I00 I00 I I HDAF SX-SA HD00F S-0LUA-B-T µpl0t-e µpl0t-e TAAP NJMM-TE TAL0F (TER) Q00 Q00 Q00 Q00 Q00 Q00 Q00 Q0 Q0 Q TRANSISTOR S-TB-L SB0-Y S-TB-L S-TB-L DTEKA T DTEKA T S-TB-L DTEKA T DTEKA T DTEKA T D00 D00 D00 D00 D00 D00 D00 D00 D00 D S.ZENER SS (TER) RD.M-TB SS (TER) SS (TER) SS (TER) SS (TER) SS (TER) SS (TER) SS (TER) SS (TER) X XTAL R- (.0 MHz) L00 L00 L00 L00 L00 L00 L00 L00 L BL0RNADB BL0RNADB NL T-0J BL0RNADB NL T-0J NL T-0J NL T-0J NL T-0J LW- R00 R S. S. S. S. S. MR0EZHJ kω MR0EZHJ. kω [GEN]: [GEN-], [GEN-], [GEN-] : [EUR-], [EUR-] : [GEN-], [EUR-] : [GEN-], [GEN-], [EUR-] - R00 R00 R0 R0 R0 R0 R0 R0 R0 R0 R0 R00 R0 R0 R0 R0 R00 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R00 R0 R0 R0 R0 R0 R0 R00 R0 R0 R0 R0 R0 R0 R0 R0 R TRIMMER TRIMMER MR0EZHJ. kω MR0EZHJ kω MR0EZHJ kω MR0EZHJ MΩ MR0EZHJ kω MR0EZHJ kωω MR0EZHJ kω MR0EZHJ kω MR0EZHJ 00 kω MR0EZHJ kω MR0EZHJ 0 kω MR0EZHJ 0 kω MR0EZHJ 0 kω MR0EZHJ 00 kω MR0EZHJ JPW (000) MR0EZHJ kω MR0EZHJ kω MR0EZHJ. kω MR0EZHJ kω MR0EZHJ kω MR0EZHJ 0 kω MR0EZHJ 0 kω MR0EZHJ 0 kω MR0EZHJ. kω MR0EZHJ kω MR0EZHJ kω PSD/V Ω MR0EZHJ 0 kω MR0EZHJ Ω (00) MR0EZHJ kω PSD/V. Ω MR0EZHJ 00 Ω (0) MR0EZHJ. kω MR0EZHJ 0 Ω () MR0EZHJ kω MR0EZHJ 00 kω KVSFA 0 0 kω MR0EZHJ kω MR0EZHJ kω MR0EZHJ kω KVSFA 0 00 kω MR0EZHJ. kω MR0EZHJ 0 Ω () MR0EZHJ 0 Ω () MR0EZHJ kω MR0EZHJ 0 kω MR0EZHJ kω MR0EZHJ 0 kω MR0EZHJ kω MR0EZHJ 0 kω MR0EZHJ kω MR0EZHJ kω MR0EZHJ kω MR0EZHJ kω MR0EZHJ kω MR0EZHJ kω MR0EZHJ Ω (0) MYLAR 0 JB H K-T 0 JB H K-T 0 JB H K-T 0 H H 0J-T 0 H H 0J-T 0 JB H 0K-T 0 FD J 0 JB H 0K-T 0 MV 0 H 0 JB H K-T 0 JB H K-T 0 JB H K-T 0 JB H K-T 0 JB H K-T 0 JB H K-T 0 JB H K-T S.=Surface mount

23 [LOGI BOARD] [LOGI BOARD] MYLAR MV 000 H 0 JB H K-T MV 0 A 0 JB 0K-T MV H MV 00 H MV H 0 JB H K-T MV H MV H 0 JB H K-T 0 MV R H 0 MV H 0 MV H MV R H MV R H MV H MV R H MV 0 H 0 JB H K-T MV H 0 JB H K-T MV H 0 JB H K-T MV 0 H 0 JB 0K-T 0 JB 0K-T MV H 0 JB H K-T 0 JB H K-T MV H 0 FD 0J RL RELAY AG 0 J00 J00 J00 J00 J0 J0 J0 J0 J B0B-EH-S 0FE-BT-VK-N 0FE-BT-VK-N 0FE-BT-VK-N 0FE-BT-VK-N 0FE-BT-VK-N RTB-.-F RTB-.-F B0B-EH-S DS00 DS00 DS00 DS00 DS LAMP LAMP LAMP LD LAMP HRT-0A-F HRT-0A-F HRT-0A-F DL-P HRS-A S00 S00 S00 S00 S00 S00 S00 S00 S0 S0 S0 S0 S0 S0 S0 S0 S0 S00 S0 S0 S0 S0 S0 S0 S0 W0 W SWITH SWITH SWITH SWITH SWITH SWITH SWITH SWITH SWITH SWITH SWITH SWITH SWITH SWITH SWITH SWITH SWITH SWITH SWITH SWITH SWITH SWITH SWITH SWITH SWITH SW- (SKHHPM) SW- (SKHHPM) SW- (SKHHPM) SW- (SKHHPM) SW- (SKHHPM) SW- (SKHHPM) SW- (SKHHPM) SW- (SKHHPM) SW- (SKHHPM) SW- (SKHHPM) SW- (SKHHPM) SW- (SKHHPM) SW- (SKHHPM) SW- (SKHHPM) SW- (SKHHPM) SW- (SKHHPM) SW- (SKHHPM) SW- (SKHHPM) SW- (SKHHPM) SW- (SKHHPM) SW- (SKHHPM) SW- (SKHHPM) SW- (SKHHPM) SW- (SKHHPM) SW- (SKHHPM) MR0EZHJ JPW (000) MR0EZHJ JPW (000) W0 W0 W0 W MR0EZHJ MR0EZHJ MR0EZHJ MR0EZHJ JPW JPW JPW JPW (000) (000) (000) (000) WS WS WS M.OTHER M.OTHER M.OTHER M.OTHER EP PB SX SX SX SX P00*J00L0 P00*J00L0 P00L0 LEAD SET B G [SENSOR BOARD] J0 00 0FE-BT-VK-N S ENODER SRB00 K EP0 000 PB B A [SENSOR BOARD] J0 00 0FE-BT-VK-N S ENODER SRB00 K EP0 000 PB B A [MAIN UNIT] I I I I I I0 I I I I I I I0 I I I I I I I I I I I [GEN]: [GEN-], [GEN-], [GEN-] : [EUR-], [EUR-] : [GEN-], [EUR-] : [GEN-], [GEN-], [EUR-] I TDAF (S,EL) TDAF (S,EL) TDAF (S,EL) LA0N NJMV-TE NJMV-TE BU0BF-E TWF (TEL) NJMM-TE NJMM-TE NJMM-TE NJMM-TE NJMM-TE NJMM-TE BU00BF-E µpg-t TA0F (TEL) TLP (GB-TPL) M0BF-EL TSF (TER) TSF (TER) BU0UBF-E M0BF-EL MFP 0D S.=Surface mount

24 [MAIN UNIT] [MAIN UNIT] I I I I I I I TWF (TEL) TWF (TEL) TAL0F (TER) HDBF SX-A S-0LUA-B-T LBT-I/SN LBT-I/SN Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q0 Q Q Q Q Q Q0 Q Q Q Q0 Q0 Q0 Q0 Q0 Q Q Q S.FET S.FET S.FET S.FET S.FET S.FET S.FET S.FET S.FET S.FET S.FET SD-TD SK-T MAS SK-T MAS SK-T MAS SD-TD SK--TD SK--TD SK-T MAS SK0-GR (TER) SA-GR (TER) S-GR (TER) S-GR (TER) S-GR (TER) DTAEUA T0 DTEUA T0 SK-T MAS SD-T-TD S-GR (TER) SK-T MAS DTEUA T0 DTEUA T0 DTEUA T0 S-GR (TER) DTEUA T0 DTEUA T0 SA-GR (TER) S-GR (TER) DTEUA T0 S-GR (TER) S-B (TER) SK-T MAS SK-T MAS S-GR (TER) DTEUA T0 DTAEUA T0 DTEUA T0 S-B (TER) DTEUA T0 DTEUA T0 DTAEUA T0 S-GR (TER) DTEUA T0 S-GR (TER) SD-T-TD DTEUA T0 DTEUA T0 S-GR (TER) SS-TD S-GR (TER) S-GR (TER) SD-T-TD SD-T-TD S-GR (TER) DTEUA T0 DTEUA T0 S-GR (TER) DTAEUA T0 DTEUA T0 DTAEUA T0 S-GR (TER) DTEUA T0 DTEUA T0 S-GR (TER) DTEUA T0 DTEUA T0 SA-GR (TER) DTEUA T0 S-GR (TER) S-GR (TER) SA-GR (TER) SA-GR (TER) S-GR (TER) S-GR (TER) [GEN]: [GEN-], [GEN-], [GEN-] : [EUR-], [EUR-] : [GEN-], [EUR-] : [GEN-], [GEN-], [EUR-] - Q Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q S.FET DTEUA T0 S-GR (TER) S-GR (TER) DTEUA T0 DTEUA T0 DTEUA T0 DTEUA T0 SK0-GR (TER) S-GR (TER) DTEUA T0 DTAEUA T0 S-GR (TER) DTEUA T0 DTAEUA T0 S-GR (TER) SD-T-TD S-GR (TER) DTEUA T0 D D D D D D D D D D0 D D D D D D D D D D0 D D D D D D D D D0 D D D D D D D D D D0 D D D D D D D D D0 D D D D D0 D D D D D D D D0 D DIODE ZENER ZENER MA (TX) MA (TX) MA (TX) MA (TX) MA (TX) MA (TX) MA (TX) MA (TX) MA (TX) MA (TX) MA (TX) MA (TX) MA (TX) MA (TX) MA (TX) MA (TX) HSMASR-TR MA (TX) XBA0 SS0 (TER) MA (TX) MA (TX) MA (TX) MA (TX) MA (TX) MA (TX) SS0 (TER) SS0 (TER) MA (TX) HSMASR-TR DANTL MA (TX) DANTL SS0 (TER) SS0 (TER) SS0 (TER) RD.E B HSMASR-TR SS0 (TER) SS0 (TER) SS0 (TER) SS0 (TER) SS0 (TER) HSMASR-TR SS0 (TER) SS0 (TER) MA (TX) DANTL MA (TX) NDG SS0 (TER) SS0 (TER) SS0 (TER) SS0 (TER) SS0 (TER) SS0 (TER) SS0 (TER) SS0 (TER) SS0 (TER) SS0 (TER) SS0 (TER) RD.E B S.=Surface mount

25 [MAIN UNIT] [MAIN UNIT] D D D D D D D0 D D D D00 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D D D D D D D D0 D D D D D D D D D D D D D ZENER DIODE DIODE DIODE DIODE DIODE DIODE DIODE ZENER ZENER S.ZENER DIODE RD.E B SS0 (TER) SS0 (TER) SS0 (TER) HSMASR-TR SS0 (TER) SS0 (TER) SS0 (TER) SS0 (TER) MA (TX) SS0 (TER) SS0 (TER) SS0 (TER) SS0 (TER) SS SS SS SS SS SS SS SS0 (TER) SS0 (TER) SS0 (TER) SS0 (TER) SS0 (TER) SS0 (TER) SS0 (TER) SS0 (TER) SS0 (TER) RDE B SS0 (TER) SS0 (TER) RDE B SS0 (TER) SS0 (TER) SS0 (TER) SS0 (TER) UMF/TR UMF/TR MAS-(TX) MAS-(TX) MA0-M (TX) SS FI FI FI FI FI FILTER FILTER FILTER FILTER FILTER FILTER MB (FL-0) MD (FL-0) [GEN] MF (FL-0) M A (FL-) M A (FL-) FL- (.0000 MHz) X S.XTAL MA-0 (.0 MHz) L L L L L L L L0 L L L L L L L L L L0 L L L L L L L LR- LAL 0NA 0K NL T-RJ- NL T-RJ- NL T-0J NL T-RJ- NL T-RJ- NL T-RJ- NL T-RJ NL T-0J NL T-RJ- NL T-RJ- NL T-RJ- NL T-RJ- NL T-0J NL T-RJ- NL T-RJ- NL T-RJ- NL T-RJ- NL T-0J NL T-R0J NL T-R0J NL T-R0J NL T-RJ- NL T-0J S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. L L L0 L L L L L L L L L L0 L L L L L L L L0 L L L L L L L L L L0 L L L L L L L L L0 L L L L L L L L L L0 L L L L L L L L L L0 L L L L L L L00 L0 L0 L0 L0 L0 L0 L0 L0 L L L L L L0 L [GEN]: [GEN-], [GEN-], [GEN-] : [EUR-], [EUR-] : [GEN-], [EUR-] : [GEN-], [GEN-], [EUR-] S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. NL T-RJ- NL T-RJ- NL T-RJ- NL T-RJ- NL T-0J NL T-RJ- NL T-RJ- NL T-RJ- NL T-RJ- NL T-0J NL T-RJ- NL T-RJ- NL T-RJ- NL T-RJ- NL T-0J NL T-RJ- NL T-RJ- NL T-RJ- NL T-RJ- NL T-RJ NL T-RJ- LAL 0NA K LR- (RIBX.X A) LAL 0NA K NL T-0J NL T-R0J NL T-RJ- NL T-0J LR-0 (TRXX A) LS-A (-) LR- NL T-00J NL T-RJ- NL T-RJ- LS-B (-) LS-B (-) LR- (RIBX.X A) LR- (RIBX.X A) NL T-RJ- NL T-RJ- NL T-RJ- NL T-RJ- LR- LS-A (-) LS- LA- NL T-00J LS-B (-) LS-A (-) LS- LS- NL T-0J LS-A (-0) LS-A (-) LS-A (-) NL T-00J LR- LS- LS- NL T-0J NL T-0J LS-0 (-) LS-A (-) EX-ELDR LAL 0NA 0K LAL 0NA 0K NL T-RJ- EX-ELDR EX-ELDR EX-ELDR EX-ELDR - - LAL 0NA K LAL 0NA K NL T-0J NL T-0J LAL 0NA K LAL 0NA K LAL 0NA K LAL 0NA K LAL 0NA K S.=Surface mount

26 [MAIN UNIT] [MAIN UNIT] L L L L L L L L0 L L L L L L L L L L0 L L L L L L L L S. S. S. S. S. S. S. S. S. S. S. S. S. LAL 0NA K NL T-RJ- NL T-RJ- NL T-0J LAL 0NA 0K NL T-0J LAL 0NA 0K LAL 0NA 0K LAL 0NA 0K NL T-0J EX-ELDR EX-ELDR EX-ELDR EX-ELDR NL T-R0J EX-ELDR NL T-00J NL T-0J EX-ELDR LAL 0NA 0K EX-ELDR NL T-0J NL T-0J NL T-0J NL T-0J NL T-0J R R R R R R R R R R0 R R R R R R R R R R0 R R R R R R R R R R R R R R R R R R R R R R R R R R0 R R R R R R R R S.TRIMMER ERJGEYJ V (0 Ω) ELR0J Ω ERJGEYJ V (0 Ω) ELR0J Ω ERJGEYJ 00 V (0 Ω) ERJGEYJ V (. kω) ELR0J 0 Ω ERJGEYJ V (0 Ω) ERJGEYJ V (0 Ω) ERJGEYJ V (0 Ω) ERJGEYJ V (0 Ω) ERJGEYJ V (0 Ω) ERJGEYJ V (0 Ω) ERJGEYJ V (0 Ω) ERJGEYJ V (0 Ω) ERJGEYJ V (0 Ω) ERJGEYJ V (0 Ω) ERJGEYJ V (0 Ω) ERJGEYJ V (0 Ω) ERJGEYJ 0 V ( kω) ERJGEYJ 0 V ( kω) ERJGEYJ V (0 Ω) ERJGEYJ V (0 Ω) ERJGEYJ V (0 Ω) ERJGEYJ 0 V (0 kω) RV- (RH0AAS) ERJGEYJ 0 V ( kω) ELR0J 0 Ω ERJGEYJ V (. kω) ERJGEYJ V (0 Ω) ELR0J Ω ERJGEYJ V (0 Ω) ERJGEYJ V (. kω) ERJGEYJ V ( kω) ERJGEYJ 0 V ( kω) ERJGEYJ 0 V ( kω) ELR0J Ω ELR0J Ω ERJGEYJ V (. kω) ERJGEYJ 0 V ( Ω) ERJGEYJ V (. kω) ERJGEYJ 00 V (0 Ω) ERJGEYJ 0 V ( kω) ERJGEYJ V (. kω) ERJGEYJ 0 V ( kω) ERJGEYJ V (. kω) ERJGEYJ 0 V (00 Ω) ERJGEYJ 0 V (00 kω) ERJGEYJ V ( kω) ERJGEYJ V ( kω) ERJGEYJ 0 V (00 Ω) ERJGEYJ 0 V ( kω) ERJGEYJ V (. kω) ERJGEYJ 0 V (0 kω) R R0 R R R R R R R R R R0 R R R R R R R R R0 R R R R R R R R R R0 R R R R R R R R R00 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R R R R R R R R R0 R R R R R R R R R R0 R R R R R R R R R0 R R R0 R [GEN]: [GEN-], [GEN-], [GEN-] : [EUR-], [EUR-] : [GEN-], [EUR-] : [GEN-], [GEN-], [EUR-] THERMISTOR R0J 00 kω ERJGEYJ V ( kω) ERJGEYJ V (. kω) ERJGEYJ V (0 Ω) ERJGEYJ V ( kω) RR0P--D (0 Ω) ERJGEYJ 0 V ( Ω) ERJGEYJ 00 V (0 Ω) ERJGEYJ V (. kω) ERJGEYJ 0 V ( Ω) ERJGEYJ V (. kω) ERJGEYJ V (0 Ω) ERJGEYJ V (0 Ω) ERJGEYJ V (0 Ω) ERJGEYJ V ( kω) ERJGEYJ 0 V ( Ω) ELR0J Ω ERJGEYJ V ( kω) ERJGEYJ 0 V (0 kω) ERJGEYJ 0 V ( MΩ) ERJGEYJ 0 V (00 Ω) ERJGEYJ 0 V (00 Ω) ERJGEYJ V (. kω) ERJGEYJ V (. kω) ERJGEYJ V (. kω) ERJGEYJ V (0 Ω) ERJGEYJ 0 V ( kω) ERJGEYJ V ( kω) ERJGEYJ V ( kω) ERJGEYJ V (0 kω) ERT-DZGL 0S ERJGEYJ 0 V (00 Ω) ERJGEYJ 0 V (00 Ω) ERJGEYJ 0 V (0 kω) ELR0J Ω ELR0J Ω ERJGEYJ 0 V (00 Ω) ELR0J Ω ERJGEYJ V (. kω) ERJGEYJ V (. kω) ELR0J Ω ERJGEYJ 0 V ( kω) ERJGEYJ V ( kω) ERJGEYJ 0 V (00 Ω) ERJGEYJ 0 V ( kω) ERJGEYJ V (0 Ω) ERJGEYJ 0 V (0 kω) ERJGEYJ V ( kω) ERJGEYJ V (. kω) ERJGEYJ 0 V (00 Ω) ERJGEYJ V (0 Ω) ERJGEYJ 0 V (00 kω) ERJGEYJ 0 V (00 kω) ERJGEYJ V (0 kω) ERJGEYJ V (. kω) ERJGEYJ 0 V (0 kω) ERJGEYJ 0 V (0 kω) ERJGEYJ 0 V (00 Ω) [GEN] ERJGEYJ 0 V (00 Ω) [GEN] ERJGEYJ V (. kω) ERJGEYJ V (. kω) ERJGEYJ V (. kω) ERJGEYJ 0 V (00 Ω) ERJGEYJ 0 V (00 Ω) ERJGEYJ V (. kω) ERJGEYJ V (. kω) ERJGEYJ V (. kω) ERJGEYJ 0 V (00 Ω) ERJGEYJ 0 V (00 Ω) ELR0J 0 Ω ERJGEYJ V (. kω) ERJGEYJ V (. kω) ERJGEYJ V (. kω) ERJGEYJ 0 V (00 Ω) ERJGEYJ 0 V (0 kω) ERJGEYJ 0 V (00 kω) ERJGEYJ V ( kω) ERJGEYJ 0 V (00 kω) ERJGEYJ V ( kω) ERJGEYJ 00 V (0 Ω) R0J. kω ERJGEYJ V ( kω) S.=Surface mount