SERVICE MANUAL. VHF MARINE TRANSCEIVER ic-m422

Transcript

1 SERVICE MANUAL VHF MARINE TRANSCEIVER ic-m S-MZ-C-q Jul. 00

2 INTRODUCTION This service manual describes the latest service information for the IC-M VHF MARINE TRANSCEIVER at the time of publication. MODEL COLORS SYMBOL BLACK [BLK] IC-M SUPER WHITE [SW] To upgrade quality, all electrical or mechanical parts and internal circuits are subject to change without notice or obligation. DANGER NEVER connect the transceiver to an AC outlet or to a DC power supply that uses more than V. Such a connection could cause a fire or electric hazard. DO NOT reverse the polarities of the power supply when connecting the transceiver. DO NOT apply an RF signal of more than 0 dbm (00 mw) to the antenna connector. This could damage the transceiver's front end. ORDERING PARTS Be sure to include the following four points when ordering replacement parts:. 0-digit order numbers. Component part number and name. Equipment model name and unit name. Quantity required <SAMPLE ORDER> LCD A0 IC-M Main unit pieces Screw BO x NIxZU (BT) IC-M Chassis 0 pieces Addresses are provided on the inside back cover for your convenience. REPAIR NOTES. Make sure the problem is internal before dis-assembling the transceiver.. DO NOT open the transceiver until the transceiver is disconnected from its power source.. DO NOT force any of the variable components. Turn them slowly and smoothly.. DO NOT short any circuits or electronic parts. An insulated turning tool MUST be used for all adjustments.. DO NOT keep power ON for a long time when the transceiver is defective.. DO NOT transmit power into a signal generator or a sweep generator.. ALWAYS connect a 0 db to 0 db attenuator between the transceiver and a deviation meter or spectrum analyzer when using such test equipment.. READ the instructions of test equipment thoroughly before connecting equipment to the transceiver. Icom, Icom Inc. and logo are registered trademarks of Icom Incorporated (Japan) in the United States, the United Kingdom, Germany, France, Spain, Russia and/or other countries.

3 TABLE OF CONTENTS SECTION SPECIFICATIONS SECTION INSIDE VIEWS SECTION DISASSEMBLY INSTRUCTIONS SECTION CIRCUIT DESCRIPTION - RECEIVER CIRCUITS TRANSMITTER CIRCUITS PLL CIRCUITS DSC CIRCUITS PUBLIC ADDRESS (PA) CIRCUIT POWER SUPPLY CIRCUITS CPU PORT ALLOCATIONS SECTION ADJUSTMENT PROCEDURES - PREPARATION FREQUENCY ADJUSTMENT TRANSMIT ADJUSTMENT RECEIVE ADJUSTMENT SECTION PARTS LIST - IC-M HM-0B/SW SECTION MECHANICAL PARTS AND DISASSEMBLY SECTION SEMICONDUCTOR INFORMATION SECTION 9 BOARD LAYOUTS 9- LOGIC BOARD HM-0B/SW VR BOARD SQL BOARD MAIN UNIT SECTION SECTION SECTION 0 BLOCK DIAGRAM VOLTAGE DIAGRAM - MAIN UNIT LOGIC BOARD HM-0B/SW - MECHANICAL PARTS AND DISASSEMBLY VOLTAGE DIAGRAM

4 SECTION SPECIFICATIONS M GENERAL Frequency coverage Type of emission Antenna impedance Operating temperature range Power supply requirement Current drain (At. V DC ; approx.) Dimensions (Projections not included) Weight (Approx.) M TRANSMITTER Output power (At. V DC) Modulation Maximum frequency deviation Frequency error Spurious emissions Adjacent channel power Audio harmonic distortion Residual modulation Audio frequency response Microphone impedance M RECEIVER Receive system Intermediate frequencies Sensitivity Squelch sensitivity (At threshold) Adjacent channel selectivity Spurious response Intermodulation rejection ratio Hum and Noise Audio frequency response Audio output power Output impedance (Audio) : TX.0. MHz RX.00. MHz : K0GE, K0GB (DSC) : 0 Ω (Nominal) : F to +0 F :. V DC ±% (negative ground) : Receiving. A (at max. audio) Transmitting. A (at W) : / (W) (H) (D) in. : Ib oz. : W (High)/ W (Low) : Variable reactance frequency modulation : ±.0 khz : Less than ±0 ppm : Less than 0 dbc : More than 0 db : Less than 0% (at 0% deviation) : More than 0 db : + db to db of db oct. from 00 Hz to 00 Hz : kω : Double conversion superheterodyne system : st IF:. MHz, nd IF: 0 khz : dbµ typical at db SINAD : Less than dbµ : More than 0 db : More than 0 db : More than 0 db : More than 0 db : + db to db of db oct. from 00 Hz to 000 Hz :. W typical at 0% distortion with a Ω load : Ω Specifications are measured in accordance with TIA/EIA 0 All stated specifications are subject to change without notice or obligation. -

5 Channel list -

6 SECTION INSIDE VIEWS MAIN UNIT FRONT UNIT -

7 SECTION DISASSEMBLY INSTRUCTIONS REMOVING THE CASE Unscrew screws, A. Note: When replacing the screws, (N.m) of torque MUST be applied to ensure water resistance. Slide the case in the direction of the arrow to separate the front pannel. REMOVING THE MAIN UNIT Disconnect W from the J and J. Disconnect W and W from the J and J. Unsolder the antenna connector, C ( points). Unsolder bottom side D ( points), as shown below. Unscrew screws, E, and screws, F, and clips G to remove the MAIN unit from the chassis. Unscrew screws, B. Note: When replacing the screws, (N.m) of torque MUST be applied to ensure water resistance. Slide the case in the direction of the arrow to remove the case. -

8 SECTION CIRCUIT DESCRIPTION - RECEIVER CIRCUITS -- ANTENNA SWITCHING CIRCUIT The antenna switching circuit toggles the receive line and the transmit line. This circuit does not allow transmit signals to enter the receiver circuits. The received signals from the antenna connector (CHASSIS UNIT; J) are passed through a two-stage low-pass filter (LPF; L, L, C C0, C) and then applied to the λ / type antenna switching circuit (D, D). While receiving, no voltage is applied to D and D. Thus, the receive line and the ground are disconnected and L and C function as an LPF which leads received signals to the RF circuits. The received signals are applied to the RF circuits via the attenuator (D). -- RF CIRCUITS The RF circuits amplify received signals within the range of frequency coverage and fi lters out-of-band signals. The received signals from the antenna switch are passed through a tunable bandpass filter (BPF; D, L, C9, C, C, C) to suppress unwanted signals. The filtered signals are amplified at the RF amplifier (Q). The amplified signals are passed through another three-stage tunable BPF (D D, L, L, L9, C, C, C, C C) to suppress unwanted signals again. The fi ltered signals are then applied to the st IF circuits. -- st IF CIRCUITS The st IF circuits contain the st mixer, IF amplifier and the st IF fi lter circuits, and the st IF mixer converts the received signals into a fi xed frequency of the st intermediate frequency (IF) signal. The converted st IF signal is filtered at the st IF filters, then amplified at the st IF amplifier. The signals from the three-stage tunable BPF are converted into the. MHz st IF signal at the st mixer (Q) by being mixed with the st LO signal generated at the VCO (Q, Q, D, D). The converted st IF signal from the st mixer is passed through the monolithic fi lters (FI, FI) to suppress unwanted signals, and then amplifi ed at the st IF amplifi er (Q). The amplified st IF signal is applied to the FM IF IC (IC, pin ). -- nd IF AND DEMODULATOR CIRCUITS The st IF signal is converted into the nd IF signal and demodulated at the detector section in the FM IF IC. The FM IF IC contains nd mixer, limiter amplifi er, quadrature detector, etc. in its package. The st IF signal from the st IF amplifi er (Q) is applied to the mixer section in the FM IF IC (IC, pin ). The applied st IF signal is mixed with the. MHz nd LO signal from the PLL IC (IC, pin ) to be converted into the 0 khz nd IF signal. The nd IF signal from the mixer section is output from pin and passed through the ceramic fi lter (FI) to suppress the heterodyne noise. The fi ltered signal is applied to the FM IF IC (IC, pin ) again, and amplified at the limiter amplifier section and demodulated by the quadrature detector. The demodulated AF signals are output from pin 9, and applied to the AF cricuits. -- AF CIRCUITS The demodulated AF signals from the FM IF IC are amplifi ed and fi ltered in AF circuits. The AF signals from FM IF IC (IC, pin 9) are passed through the BPF (Q, Q) and AF mute switch (IC, pins, 9), and then applied to the volume control pot (VR BOARD; R) to be adjusted its level. The level adjusted AF signals are applied to the AF power amplifi er (IC9, pin) to obtain. W (typ.) of AF output power. The power amplifi ed AF signals are output from pin, and applied to the internal speaker (FRONT UNIT; SP) via J or connected external speaker/hailer. ND IF AND DEMODULATOR CIRCUITS FI. MHz PLL IC (IC) R demodulated signals to the AF circuits Quadrature detector 9 0 Filter amp. X Limiter amp. RV Noise detector X. MHz Mixer IC TAFN st IF signal from the IF amplifier (Q) + IC SQL signal to the CPU (LOGIC BOARD; IC, pin ) Squelch amp. -

9 -- SQUELCH CIRCUITS Noise squelch circuit mutes AF output signals when no RF signals are received. By detecting noise components in the demodulated AF signals, the squelch circuit switches the AF mute switch ON and OFF. A portion of the demodulated AF signals from the FM IF IC (IC, pin 9) are passed through the squelch adjustment pot (R) to be adjusted its level. The level adjusted AF signals are passed through the active filter (IC, pins, ; R R, C, C, C). The fi ltered signals are then applied to the noise amplifier section in the IC to amplify the noise components only. The amplified noise components are converted into the pulse-type signal at the noise detector section, and output from pin as the SQL signal. The SQL signal is applied to the squelch amplifi er (IC, pin ) to be amplifi ed its level, then output from pin. The amplifi ed SQL signal is applied to the CPU (LOGIC BOARD; IC, pin ). Then the CPU outputs RMUTEM signal from pin according to the SQL signal level to toggle the AF mute circuit (IC) ON/OFF. - TRANSMITTER CIRCUITS -- MICROPHONE AMPLIFIER CIRCUIT The microphone amplifi er circuit amplifi es the audio signals from microphone (MIC signals) within + db/oct pre-emphasis characteristic. The MIC signals from the microphone (HM-0B/SW; MC) are passed through the microphone mute switch (IC, pins 0, ) and amplifi ed at the microphone amplifi er (IC, pin ) to obtain + db/oct pre-emphasis characteristics. The amplifi ed MIC signals are limited its level at the IDC amplifi er (IC, pin ), and fi ltered out khz and higher audio signals at the LPF (IC, pins, ). The filtered MIC signals are passed through the deviation adjustment pot (R) to be adjusted its level. Then the level adjusted MIC signals are applied to the modulation circuit. -- MODULATION CIRCUIT The modulation circuit modulates the VCO oscillating signal with the audio signals from the microphone. The level adjusted MIC signals are applied to the modulation circuit (D) to modulate the VCO oscillating signal by changing the reactance of D at the VCO (Q, Q, D, D). The modulated VCO output signals are amplifi ed at the buffer amplifiers (Q, Q), then applied to the transmit amplifi ers via the TX/RX switch (D). -- TRANSMIT AMPLIFIERS The VCO output signals are amplified to transmit output power level by the transmit amplifi ers. The buffer-amplified VCO output signals from the TX/RX switch (D) are applied to the pre-drive (Q0), YGR (Q), and power (IC) amplifiers to be amplified to the transmit output power level. The power amplifi ed transmit signal is passed through the power detector (D, D), antenna switch (D) and a two-stage LPF (L, L, C C0, C), and then applied to the antenna connector (CHASSIS UNIT; J). -- APC CIRCUIT The APC (Automatic Power Control) circuit stabilizes transmit output power and controls transmit output power High ( W) or Low ( W). The power detector circuits (D, D) detect the transmit output signal level and converts it into DC voltage. The detected voltage is applied to the APC amplifier (IC, pin ). The voltage of the TV line is applied to another input (pin ) via the transmit output power adjustment pot (R) as the reference voltage. The output voltage from the APC amplifi er controls the bias of the power amplifier (IC) to control the output power by comparing the detected voltage and the reference voltage. Thus the APC circuit maintains a constant transmit output power. APC CIRCUIT TV from TX/RX switch (D) Q0 Pre-drive amp. Q YGR amp. IC Power amp. LPF D ANT SW to the anntena TV R TMUTE Q H/L + APC amp. IC D D Power detector TXDET -

10 - PLL CIRCUITS -- VCO CIRCUIT The VCO circuit (Q, Q, D, D) directly generates both of the st LO frequency for receiving (.. MHz) and the transmit frequency (.0. MHz). While receiving, the VCO output signal (st LO signal) is amplifi ed at the buffer amplifi ers (Q, Q) and passed through the TX/RX switch (D), then applied to the st mixer (Q). While transmitting, the VCO output signal (transmit signal) is amplified at the buffer amplifiers (Q, Q) and passed through the TX/RX switch (D), then applied to the pre-driver (Q0). A portion of the VCO output signal from the buffer amplifi er (Q) is fed back to the PLL IC (IC, pin ) as the comparison signal via the buffer amplifier (Q) and the LPF (L, C, C). - DSC CIRCUITS DECODING A portion of the demodulated AF signals from the FM IF IC (IC, pin 9) are passed through the LPF (Q) to fi lter DSC signal. The filtered DSC signal is applied to the DSC decoder (IC, pin ). The decoded DSC signal is output from pin, and then applied to the CPU (LOGIC BOARD; IC, pin ). Then the CPU controls the transceiver according to the DSC content. ENCODING The DSC signals (FSK) are generated by the CPU (LOGIC BOARD; IC) and output from pins. The DSC signals are applied to the buffer amplifi er (LOGIC BOARD; IC, pin ). The buffer amplifi ed DSC signals are output from pin, and passed through the LPF (IC, pins, ), and applied to the modulation circuit (D) via the deviation adjustment pot (R) to modulate the VCO oscillating signal. -- PLL CIRCUIT The PLL circuit provides stable oscillation of the transmit frequency and receive st LO frequency. The PLL circuit compares the phase of the divided VCO frequency with the reference frequency. The PLL output frequency is controlled by the divided ratio of the programmable divider. The buffer amplifi ed signals are applied to the PLL IC (IC, pin ) via the LPF (L, C, C). The applied signals are divided at the prescaler and programmable counter section according to the PDATA from the CPU (LOGIC BOARD; IC pin ). The divided signal is phase-compared with the reference frequency at the phase detector. The phase difference is output from pin as a pulse type signal after being passed through the charge pump section. The output signal is passed through the loop fi lter (R R9, R, C, C, C, C) to be converted into the DC voltage, and is then applied to the VCO circuits as the lock voltage. - PUBLIC ADDRESS (PA) CIRCUIT The Public Address (PA) circuit power amplifies the audio signals from the microphone. The power amplifi ed MIC signals are output to the connected external speaker or hailer. The MIC signals from the microphone (HM-0B/SW or optional HM-) are passed through the AF mute circuit (IC, pins 0, ), and applied to the microphone amplifier (IC, pin ). The amplified MIC signals are output from pin, and applied to the electric volume controller (IC, pin ) via the AF mute circuit (IC, pins, 9). The volume controlled MIC signals are then passed through the AF mute circuit (Q), and applied to the AF power amplifier (IC, pin ) to be amplified to obtain W (min.) of AF output power. The power amplifi ed AF signals are output from pin, and applied to the connected external speaker or hailer. If the oscillated signal drifts, its phase changes from that of the reference frequency, causing a lock voltage change to compensate for the drift in the oscillated frequency. PLL CIRCUITS UNLK LPF Buffer Buffer Q Q to the TX/RX switch (D, D) PSTB PCK PDATA X to the FM IF IC (IC, pin ) DATA interface Reference counter Phase detector Prescaler Programmable counter Charge pump IC µpd0gs Loop filter Buffer Q VCO Q, Q, D, D -

11 - POWER SUPPLY CIRCUITS Line Description The voltage from the connected DC power supply. Common V converted from the line at the LV regulator (LOGIC BOARD; IC). LV The converted voltage is applied to the CPU (LOGIC BOARD; IC) Same voltage as the line whitch is passed through the power control circuit (Q, Q). Common V converted from the line at the + regulator circuit (IC0). Transmit V controlled by the T control circuit (Q, Q) T using the "SEND" signal from CPU (LOGIC BOARD; IC, pin ). Receive V converted from the line at the R regulator R (Q, Q). The converted voltage is applied to the receiver circuits. Receive V controlled by the R control circuit (Q, Q) using the "RCV" signal from CPU (LOGIC BOARD; IC, R pin ). The controlled voltage is applied to the receiver circuits. - CPU PORT ALLOCATIONS Pin NO. Port name Description KEYM Input port for keys on HM-0B/SW. Approx..0 V: [Y] key is pushed. Approx..00 V: [Z] key is pushed. Approx.. V: [H/L] key is pushed. TXDET Input port for transmit detected voltage. LBAT Input port for low battery detecting. SQL Input port for "NOISE" signal from the squelch amplifi er (IC, pin ). SQLV Input port for squelch adjustment pot (SQL BOARD; R). WXDEC Input port for weather alert signal from the LPF (Q). PDATA Outputs data signal to the PLL IC (IC, pin ). 9 PCK Outputs clock signal to the PLL IC (IC, pin ). 0 PSTB Outputs strobe signal to the PLL IC (IC, pin). EVDATA Outputs volume control signal to the volume ccontroller (IC, pin ) for PA circuit. EVCK Outputs clock signal to the volume ccontroller (IC, pin ) for PA circuit. DSDEC Input port for the DSC decode signal from the DSC decoder (IC, pin )., 9 CONT, CONT0 COMTXD COMRXD ECK EDATA Output LCD contrast adjust signal to the CPU (IC, pin ). Outputs serial data signal to the connected HM- (Optional product). Input port for the serial data signal from the connected HM- (Optional product). Outputs clock signal to the EEPROM (LOGIC BOARD; IC, pin ). I/O port for the EEPROM (LOGIC BOARD; IC, pin ) control data. NMTXD Outputs NMEA command signal. Pin NO. Port name Description NMRXD Input port for the NMEA signal. PWR Input port for power switch (VR BOARD; R). Low: When [VOL] is pushed. 9 PAMUTE Outputs control signal to the AF (Public Address) mute circuit (Q). High: During mute. 0 PWRON Outputs power control signal to the power control circuit (Q, Q). High: While the transceiver is switched ON. TMUTE Outputs transmit mute signal to the APC circuit (IC, pin ). High: During mute. RCV Outputs control signal to the R control circuit (Q, Q). High: While receiving. H/L Outputs TX power control signal to the TX power control circuit (Q, D). High: W Low: W ATT PTT 0 UNLK DTRS RMUTEP RMUTES RMUTEM MMUTEP MMUTES MMUTEM PTTS 9 PTTM 0 LO/DX Outputs attenuator control signal to the attenuator (D). High: Attenuator ON. Input port for the [PTT] switch (HM-0B/SW; S). Low: [PTT] key is pushed. Input port for the "UNLK" signal from the PLL IC (IC, pin). High: PLL circuit is unlocked. Input port for the [DISTRESS] key (LOGIC BOARD; S9). Low: [DISTRESS] key is pushed. Outputs AF (Public Address) mute signal to the AF mute circuit (IC, pin). Low: During mute. Outputs AF mute signal to the AF mute circuit (IC, pin ) for the connected HM- (Optional product). Low: During mute. Outputs AF (internal speaker) mute signal to the AF mute circuit (IC, pin ). Low: During mute. Outputs microphone (Public Address) mute signal to the AF mute circuit (IC, pin ). Low: During mute. Outputs microphone mute signal to the AF mute circuit (IC, pin ) for the connected HM- (Optional product). Low: During mute. Outputs microphone (HM-0B/SW) mute signal to the AF mute circuit (IC, pin ). Low: During mute. Outputs AF/MIC control signal to the AF mute circuit (IC, pin ). High: PTT switch (HM-) is pushed Outputs AF/MIC control signal to the AF mute circuit (IC, pin ). Input port for the [LO/DX] key (LOGIC BOARD; S). Low: [LO/DX] key is pushed. -

12 - PORT ALLOCATIONS (continued) Pin NO. Port name DSC PA CH/WX SCAN Description Input port for the [DSC] key (LOGIC BOARD; S). Low: [DSC] key is pushed. Input port for the [PA] key (LOGIC BOARD; S). Low: [PA] key is pushed. Input port for the [CH/WX] key (LOGIC BOARD; S). Low: [CH/WX] key is pushed. Input port for the [SCAN] key (LOGIC BOARD; S). Low: [SCAN] key is pushed. CH Input port for the [] key (LOGIC BOARD; S). Low: [] key is pushed. DOWN Input port for the [Z] key (LOGIC BOARD; S). Low: [Z] key is pushed. UP Input port for the [Y] key (LOGIC BOARD; S). Low: [Y] key is pushed. DIM Outputs dimmer control signal to the LCD control circuit (LOGIC BOARD; Q, Q). 9 BEEP Outputs beep signal to the AF amplifier (IC9, pin ). DS/BPF While transmitting: Outputs DSC encode signal as "DSENC" to the LPF (IC, pin ) via the buffer amplifier (LOGIC BOARD; IC, pins, ). While receiving: Outputs tuning signal as "BPFV" to the tunable BPFs (D D) via buffer amplifier (LOGIC BOARD; IC, pins, ). -

13 SECTION ADJUSTMENT PROCEDURES - PREPARATION M REQUIRED TEST EQUIPMENTS EQUIPMENT GRADE AND RANGE EQUIPMENT GRADE AND RANGE Output voltage :. V DC Frequency range : Hz DC power supply Audio generator Current capacity : More than 0 A Measuring range : 00 mv Measuring range : 0 W Frequency range : MHz RF power meter Frequency range : MHz Standard signal Output level : 0. µv to mv (terminated type) Impedance : 0 Ω generator (SSG) ( to dbm) SWR : Less than. : Frequency range : MHz Frequency range : DC to 0 MHz Frequency counter Frequency accuracy : ± ppm or better Oscilloscope Measuring range : V Sensitivity : 00 mv or better Frequency range : 0 00 MHz FM deviation meter AC millivoltmeter Measuring range : 0 mv to 0 V Measuring range : 0 to ±0 khz Input impedance : Ω External speaker Capacity : More than W DC volt meter Input impedance : 0 kω /V DC or more Power attenuation : 0 or 0 db Attenuator Capacity : More than 0 W M CONNECTION Standard signal generator 0. µv to mv ( to dbm) RF power meter 0 W Frequency counter FM deviation meter Attenuator 0 db or 0 db To the antenna connector CAUTION: DO NOT transmit while SSG is connected to the antenna connector. DC power supply. V /0 A Black + To DC power connector Red To external speaker lead AC millivoltmeter Distortion meter Speaker ( Ω) SP+ (Yellow) SP (Black) -

14 - FREQUENCY ADJUSTMENT ADJUSTMENT LOCK VOLTAGE REFERENCE FREQUENCY ADJUSTMENT CONDITION Channel : CH (.00 MHz) Receiving Channel : CH (.00 MHz) Output power : Low Transmitting Channel : CH (.00 MHz) Output power : Low Connect a power meter to the antenna connector. Transmitting MEASUREMENT ADJUSTMENT VALUE POINT UNIT OPERATION UNIT ADJUST MAIN Connect a digital multimeter.. V MAIN Verify or oscilloscope to the check point "CP" V Verify Rear Panel Loosely couple a frequency counter to the antenna connector..00 MHz ±00 Hz MAIN C C Reference frequency adjustment CP Lock voltage check point -

15 - TRANSMIT ADJUSTMENT ADJUSTMENT OUTPUT POWER FREQUENCY DEVIATION ADJUSTMENT CONDITION Channel : CH (.00 MHz) Output power : High Transmitting Channel : CH (.00 MHz) Output power : Low Connect an audio generator to the pin of J (MAIN UNIT) and set as; Frequency : khz Level : 0 mv Set the FM deviation meter as; HPF : OFF LPF : 0 khz De-emphasis: OFF Detector : (P P)/ Transmitting MEASUREMENT ADJUSTMENT VALUE POINT UNIT OPERATION UNIT ADJUST Rear. W MAIN R Panel Rear Panel Connect an RF power meter to the antenna connector. Connect an FM deviation meter to the antenna con-nector through an attenuator. ±.. khz MAIN R R Output power adjustment R Frequency deviation adjustment 9 J Audio generator AC millivoltmeter + + -

16 - RECEIVE ADJUSTMENT ADJUSTMENT ADJUSTMENT CONDITION SENSITIVITY Channel : CH (.00 MHz) [SQL] : Max. counterclockwise Connect a distortion meter with a Ω load to the external speaker lead. Push [PA RX ] for sec. to turn the RX speaker mode ON. Connect an SSG to the antenna connector and set as ; Frequency :.00 MHz Level : +0 dbµ Modulation : khz Deviation : ± khz Receiving SQUELCH Channel : CH (.00 MHz) [SQL] : Max. counterclockwise Set the SSG as; Level : dbµ Receiving MEASUREMENT ADJUSTMENT VALUE POINT UNIT OPERATION UNIT ADJUST MAIN Connect a DC volt meter Maximum MAIN L, L, L, or oscilloscope to the voltage L9 check point "CP". (Repeate two times or more.) MAIN Connect a volt meter or oscilloscopeto the check point "CP"..0 V MAIN R L9 L L L Sensitivity adjustment R Squelch adjustment CP Sensitivity check point CP Squelch check point -

17 SECTION PARTS LIST - IC-M [REPLACEMENT UNITS] ORDER NO. UNIT NAME 000 U M #0 FRONT (FRONT+LOGIC+VR+SQL) 000 U M #0 FRONT (FRONT+LOGIC+VR+SQL) 000 U M #0 MAIN (MAIN+CHASSIS) [LOGIC BOARD] [BLK] [SW] REF ORDER H/V NO. NO. DESCRIPTION M. LOCATION IC 00 S.IC M00MA-RP (FX-A-) B./. IC 000 S.IC S-09CNMC-G9CTG B 9./. IC 0000 S.IC TAL0F (TER F) B./0. IC 0000 S.IC HNXTI B.9/. IC 0000 S.IC LM90PWR B 9./. IC 0000 S.IC PCNJ000F B./. IC 0000 S.IC KICWFK RTK/P B /. Q S.TR KTAY-RTF/P B /. Q 000 S.TR SC-BL (TER F) B 9./. Q 000 S.TR SC-BL (TER F) B 9./. Q S.TR KRC RTK/P B./. Q 000 S.TR SC-BL (TER F) B./. Q S.TR KRC0 RTK/P B./. Q 0009 S.TR SC-GR (TER F) B./9. Q 0000 S.TR SA-GR (TER F) B 9./ Q S.FET SK09--TL B./9. D 0000 S.DIO KDS RTK/P B./. D 0000 S.DIO KDSU RTK/P B./. D 0000 S.DIO KDS RTK/P B./. D 0000 S.ZEN KDZ.V-Y RTK/P B./9. X S.XTL CR-9 (9.0 MHz B 0./ R S.RES ERJGEYJ V ( k) B./. R S.RES ERJGEYJ V ( k) B.9/.9 R S.RES ERJGEYJ 0 V ( M) B./. R S.RES ERJGEYJ 0 V (00) B./0. R S.RES ERJGEYJ V ( k) B./0. R S.RES ERJGEYJ 0 V (0 k) B./. R S.RES ERJRKF X (0 k) B./. R S.RES ERJGEYF V ( k) B./.9 R S.RES ERJGEYJ 0 V (0 k) B./. R S.RES ERJGEYJ V (. k) B /. R S.RES ERJGEYJ V ( k) B./. R S.RES ERJGEYJ V (. k) B./. R S.RES ERJGEYJ 0 V (0 k) B 9./. R S.RES ERJGEYJ 0 V (0 k) B /.9 R S.RES ERJGEYJ 0 V (0 k) B 0./. R S.RES ERJGEYJ 0 V (0 k) B 0.9/.9 R S.RES ERJGEYJ V ( k) B./. R S.RES ERJGEYJ V ( k) B /0.9 R S.RES ERJGEYJ 0 V () B./. R S.RES ERJGEYJ V ( k) B.9/. R S.RES ERJGEYJ 0 V (0 k) B.9/.9 R S.RES ERJGEYJ V ( k) B./.9 R S.RES ERJGEYJ 0 V ( k) B /. R S.RES ERJGEYJ 0 V ( k) B./. R S.RES ERJGEYJ V (. k) B.9/. R S.RES ERJGEYJ 0 V (00 k) B./. R S.RES ERJGEYJ 0 V ( M) B./. R S.RES ERJGEYF 0 V (0 k) B./. R S.RES ERJGEYF V (. k) B./.9 R S.RES ERJGEYJ 0 V () B.9/. R S.RES ERJGEYJ 0 V () B./. R S.RES ERJGEYJ 0 V () B./. R S.RES ERJGEYJ 9 V (9 k) B./9. R S.RES ERJGEYJ V ( k) B./.9 R S.RES ERJGEYJ 0 V ( k) B./ R S.RES ERJGEYJ 0 V (0 k) B 9./9. R S.RES ERJGEYJ V (. k) B./. R S.RES MCR0EZHJ (0) B.9/. R S.RES MCR0EZHJ (0) B./. R S.RES MCR0EZHJ (0) B./. R S.RES MCR0EZHJ (0) B./0. R S.RES MCR0EZHJ (0) B./9 R S.RES MCR0EZHJ 9 (90) B./9 R S.RES MCR0EZHJ (0) B./.9 [LOGIC BOARD] REF ORDER H/V NO. NO. DESCRIPTION M. LOCATION R S.RES ERJGEYJ V (0) B./0 R S.RES ERJGEYJ V (. k) B./9. R S.RES ERJGEYJ 0 V ( k) B 0.9/ R S.RES ERJGEYJ 0 V (00 k) B./. R S.RES ERJGEYJ 0 V () B./. R S.RES ERJGEYJ V (. k) B./. R S.RES ERJGEYJ 0 V (00 k) B./. R S.RES ERJGEYJ V (. k) B 9./9. R S.RES ERJGEYJ 0 V () B./. R S.RES ERJGEYJ 0 V ( k) B./. R S.RES ERJGEYJ V ( k) B./. R S.RES ERJGEYJ 0 V ( k) B./9.9 R S.RES ERJGEYJ 0 V (00) B./. R S.RES ERJGEYJ V ( k) B /.9 C S.TAN TEESVA C 0MR B./0. C S.CER ECJ0EBC0K B./. C 0000 S.CER ECJ0ECH0J B./. C 0000 S.CER ECJ0ECH0J B./. C 0000 S.CER ECJ0EBE0K B.9/9. C 0000 S.CER ECJ0EBEK B.9/. C S.CER ECJ0EBA0K B./. C 0000 S.CER ECJ0EBE0K B./. C S.CER ECJ0EBAK B./. C S.CER ECJ0EBAK B./. C S.CER ECJ0EBAK B./. C S.CER ECJ0EBAK B./0. C S.CER ECJ0EBAK B./0. C S.CER ECJ0EBAK B./0. C S.CER ECJ0EBA0K B./. C S.CER ECJ0EBC0K B 0./0. C 0000 S.CER C0 JB A K-T B./.9 C S.CER ECJ0EBAK B 9./.9 C 0000 S.ELE CE 0 BS B 9./9. C S.CER C0 JB H 0K-T B 9./0. C 0000 S.ELE CE 0 BS B./. C S.CER ECJ0EBC0K B./ C S.CER ECJ0EBA0K B./. C S.CER C0 JB E 0K-T B./. C 0000 S.CER ECJ0ECHJ B./. C 0000 S.CER ECJ0ECH00C B 0./. C 0000 S.ELE CE 0 BS B./. C 0000 S.CER ECJ0EBE0K B 0./ C S.CER ECJ0EBA0K B./. C S.CER ECJ0EBAK B./. C S.CER ECJ0EBC0K B./ C S.CER ECJ0EBA0K B /. C S.CER ECJ0EBA0K B./. C 0000 S.CER ECJ0EBE0K B./.9 C 0000 S.CER ECJ0EBE0K B./. C S.CER ECJ0EBE0K B./0.9 C S.CER ECJ0EBE0K B./9.9 C S.CER ECJ0EBA0K B./. C S.CER ECJ0EBA0K B 9./.9 C S.CER ECJ0EBE0K B /. C S.CER ECJ0EBE0K B /.9 C S.CER ECJ0EBEK B./. C S.CER ECJ0EBE0K B./.9 C 0000 S.CER ECJ0EBE0K B./. C 0000 S.CER ECJ0EBE0K B 9/ C 0000 S.CER ECJ0EBE0K B./. C 0000 S.CER ECJ0EBEK B./. C S.CER ECJ0EBC0K B./. C 0000 S.CER ECJ0ECH0J B./0. C 0000 S.CER ECJ0EBE0K B./. C 0000 S.CER ECJ0ECH0J B./. C 0000 S.CER ECJ0EBE0K B./ C 0000 S.CER ECJ0ECH0J B.9/0. J 009 S.CNR BB-PH-SM-TB (LF) (SN) B./. J 00 S.CNR BB-PH-SM-TB (LF) (SN) B./ J 000 S.CNR 0FLT-SM-TB B./. J 000 S.CNR 0FLT-SM-TB B./. J 009 S.CNR BB-ZR-SM-TF (LF) (SN) B./. DS LCD IS0E00V DS S.LED SML-YTT T 9.9/. DS S.LED SML-YTT T./. DS S.LED SML-YTT T./. DS S.LED SML-YTT T /. DS S.LED SML-YTT T 9./. DS S.LED SML-YTT T 0./. M.=Mounted side (T: Mounted on the Top side, B: Mounted on the Bottom side) S.=Surface mount -

18 [LOGIC BOARD] REF ORDER H/V NO. NO. DESCRIPTION M. LOCATION DS S.LED RY-SP0UHY-M <VKH> T./0.9 DS S.LED RY-SP0UHY-M <VKH> T 0./0.9 DS S.LED RY-SP0UHY-M <VKH> T./. DS S.LED RY-SP0UHY-M <VKH> T 0./. DS S.LED RY-SP0UHY-M <VKH> T./. DS S.LED RY-SP0UHY-M <VKH> T 0./. EP 9000 LCT SRCN--SP-N-W EP 9000 S.BEA MMZ0Y 0BT B./. EP S.BEA MMZ0Y 0BT B /. [MAIN UNIT] REF ORDER H/V NO. NO. DESCRIPTION M. LOCATION IC 0000 S.IC µpd0gs-e (DS) T./0 IC 0000 S.IC TAFNG (EL) T 9./.9 IC 0000 IC RAHM- IC 000 S.IC CD0BPWR T.9/. IC 000 S.IC CD0BPWR T 9./ IC 000 S.IC CD0BPWR T./. IC S.IC NJMM-TE T /. IC S.IC NJMM-TE T./. IC IC LAA-E IC REG KIA0API U/P IC 0000 S.IC NJMF-TE T.9/. IC S.IC NJM0F-TE T./. IC S.IC M9FP 00C T./ IC IC LAA-E IC 0000 S.IC NJMM-TE T.9/. Q S.TR KTC0 BL-RTK/P T 9./. Q S.TR KRC0 RTK/P T./. Q 0000 S.TR SC-O (TER F) T./ Q S.TR SC-T R T.9/. Q S.TR SC-T R T 0./. Q 0000 S.TR SC-O (TER F) T 9./9.9 Q 0000 S.TR SC-O (TER F) T.9/ Q S.TR SC-T R T 0./. Q 000 S.TR SC--TB-E T./.9 Q S.TR KRC0 RTK/P T 9./. Q S.FET SK-T-LA T 0./. Q S.FET SK-T-LA T./. Q S.TR KTC0S Y-RTK/P T /. Q S.TR KTC0 BL-RTK/P T 0.9/ Q S.TR KTC0 BL-RTK/P T 9./0.9 Q S.FET SK09--TL T./. Q S.TR DTAEUA T0 T./. Q S.TR KTC0 BL-RTK/P T./. Q S.TR KRC0 RTK/P T./. Q S.TR KTA0Y-RTK/P T./9. Q S.TR KRC0 RTK/P T./. Q S.TR KTAY-RTF/P T 0./9. Q S.TR KTC0 BL-RTK/P T./.9 Q S.TR KTA0Y-RTK/P T./9. Q S.FET TPC0 (TEL F) T./. Q S.TR KRC0 RTK/P T./0. Q S.TR SC-B (TER F) T./. D S.DIO MA (TX) T 0./. D S.DIO MA (TX) T./. D 0000 S.VCP C0BTRF-E T.9/ D 0000 S.VCP C0BTRF-E T.9/. D S.DIO MA (TX) T./. D S.DIO MA (TX) T./0. D S.DIO KDS0E RTK/P T./. D 0000 S.DIO KDS0E RTK/P T./. D S.DIO HSMASRTR-E T./9. D S.DIO HSMASRTR-E T.9/. D DIO XBA0 D DIO XBA0 D 0000 S.DIO SV0 (TPH F) T./. D S.VCP KDVE RTK/P T 0./. D S.VCP KDVE RTK/P T 0./. D S.VCP KDVE RTK/P T 9./. D S.VCP KDVE RTK/P T.9/. D DIO DSAA FI MLH RAB (FL-) FI MLH RAB (FL-99A) FI CER LT0EW <JJE> X 000 S.XTL CR-0A (.0 MHz) T 9/9. X DCR JTB0C <JJE> [MAIN UNIT] REF ORDER H/V NO. NO. DESCRIPTION M. LOCATION L S.COL MLG0B R0J-T T./ L S.COL MLG0B NJ-T T./. L S.COL NLVT-RJ T./. L S.COL TL 0N T./. L S.COL MLG0B R0J-T T./. L S.COL MLG0B R0J-T T /. L S.COL MLG0B NJ-T T./. L S.COL MLG0B R0J-T T./. L 0000 S.COL ELJRE NGFA T./.9 L 0000 S.COL NLVT-0J T 0./. L S.COL MLG0B NJ-T T /. L S.COL NLVT-0J T 0./. L S.COL NLVT-0J T 9./. L COL LA- L COL LW- L COL LA- L COL LA- L 0000 S.COL NLVT-RJ T./. L COL LA- L 000 COL LS-0-LF L 000 COL LS-0-LF L 000 COL LS-0-LF L9 000 COL LS-0-LF L S.COL ELJND RJF T./. R S.RES ERJGEYJ 0 V ( k) T./ R S.RES ERJGEYJ 0 V ( k) T./. R S.RES ERJGEYJ 0 V ( k) T./9. R S.RES ERJGEYJ 0 V ( k) T./. R S.RES ERJGEYJ 0 V (00 k) T./. R S.RES ERJGEYJ V (0) T./. R S.RES ERJGEYJ 0 V ( k) T.9/. R S.RES ERJGEYJ 00 V (0) T 0./. R S.RES ERJGEYJ V (. k) T./. R S.RES ERJGEYJ V (0) T./. R S.RES ERJGEYJ 0 V ( k) T./ R S.RES ERJGEYJ 0 V ( k) T./. R S.RES ERJGEYJ V ( k) T./0. R S.RES ERJGEYJ 0 V ( k) T.9/9. R S.RES ERJGEYJ 0 V (00) T./. R S.RES ERJGEYJ V ( k) T 0./. R S.RES ERJGEYJ V ( k) T 0./. R S.RES ERJGEYJ V ( k) T./. R S.RES ERJGEYJ 0 V (00 k) T./. R S.RES ERJGEYJ V (0) T./.9 R S.RES ERJGEYJ V ( k) T.9/.9 R S.RES ERJGEYJ V (0) T./. R S.RES ERJGEYJ 0 V () T.9/. R S.RES ERJGEYJ V (0) T /. R S.RES ERJGEYJ V (0) T./.9 R S.RES ERJGEYJ V (. k) T./. R S.RES ERJGEYJ V (. k) T 0./9 R S.RES ERJGEYJ 0 V (00) T 9./ R S.RES ERJGEYJ 9 V (90) T./. R S.RES ERJGEYJ V (0) T./ R S.RES ERJGEYJ V (0) T./. R S.RES ERJGEYJ V ( k) T./. R S.RES ERJGEYJ 0 V (00) T./. R S.RES ERJGEYJ V ( k) T./. R S.RES ERJGEYJ V (. k) T./. R S.RES ERJGEYJ 0 V ( k) T./0. R S.RES ERJGEYJ 90 V (9) T 9./. R S.RES ERJGEYJ V (. k) T./. R S.RES ERJGEYJ 9 V (90) T./.9 R S.RES ERJGEYJ 00 V (0) T 0/. R S.RES ERJGEYJ 0 V (0 k) T /.9 R S.RES ERJGEYJ 0 V (0 k) T /. R S.RES ERJGEYJ 0 V (00) T 9/. R S.RES ERJGEYJ V (. k) T.9/9. R S.RES ERJGEYJ 0 V () T./0. R S.RES ERJGEYJ 0 V () T.9/0. R S.RES ERJGEYJ 0 V ( k) T./. R S.RES ERJGEYJ 90 V (9) T.9/. R S.RES ERJGEYJ 0 V (00) T 0./. R S.RES ERJGEYJ V ( k) T./. R S.RES ERJGEYJ V (. k) T /. R S.RES ERJGEYJ V ( k) T./. R S.RES ERJGEYJ 0 V (00) T./9. R0 000 S.TMR NTCG BH JT T./ R S.RES ERJGEYJ V (. k) T./. R S.RES ERJGE JPW V T./. R S.RES ERJGEYJ 0 V ( M) T 9./9. R S.TRI RH0ADCX (0 k) T./9 R S.RES ERJGEYJ V (. k) T /9. R S.RES ERJGEYJ V (. k) T./ R S.RES ERJGEYJ 9 V (90) T./. R S.RES ERJGEYJ 0 V ( k) T./. R S.RES ERJGEYJ 0 V ( k) T./. R S.RES ERJGEYJ 0 V ( k) T./. R S.RES ERJGEYJ 0 V ( k) T./. M.=Mounted side (T: Mounted on the Top side, B: Mounted on the Bottom side) S.=Surface mount -

19 [MAIN UNIT] REF ORDER H/V NO. NO. DESCRIPTION M. LOCATION R S.RES ERJYJ0U () T./9. R S.RES ERJGEYJ V ( k) T 0./9. R S.RES ERJGEYJ V (0 k) T./.9 R S.RES ERJGEYJ V (0 k) T./. R S.RES ERJGEYJ 0 V (00 k) T 0./. R S.RES ERJGEYJ 0 V (00) T 0./. R S.RES ERJGEYJ 0 V (00 k) T./9. R S.RES ERJGEYJ 9 V (9 k) T./ R S.RES ERJGEYJ V ( k) T./. R S.RES ERJGEYJ 0 V () T./. R S.RES ERJGEYJ R0 V () T 0./. R S.RES ERJGEYJ V (0) T 0./.9 R S.RES ERJGEYJ 0 V (00 k) T 00/9. R S.RES ERJGEYJ 0 V (00 k) T 9/. R S.RES ERJGEYJ 0 V (00 k) T 90./. R S.RES ERJGEYJ 0 V (0 k) T 9./9. R S.RES ERJGEYJ V (. M) T./. R S.RES ERJGEYJ V ( k) T 9.9/.9 R S.RES ERJGEYJ 0 V (0 k) T./9. R S.RES ERJGEYJ V (. k) T./. R S.RES ERJGEYJ 0 V () T./. R S.RES ERJGEYJ V ( k) T 9.9/. R S.RES ERJGEYJ 00 V (0) T /9.9 R S.RES ERJGEYJ 0 V ( k) T 9./. R S.RES ERJGEYJ V (. k) T.9/.9 R S.RES ERJGEYJ V (. k) T.9/. R S.RES ERJGEYJ V (0) T./. R S.RES ERJGEYJ 0 V (00 k) T./ R S.RES ERJGEYJ V (. k) T./ R S.RES ERJGEYJ V (. k) T 9./0.9 R S.RES ERJGEYJ 9 V (90) T./0. R S.RES ERJGEYJ V (. k) T./. R S.RES ERJGEYJ V (. k) T 90./ R S.RES ERJGEYJ V (0 k) T 9./. R S.RES ERJGEYJ V (0) T 00./. R S.RES ERJGEYJ V ( k) T 0.9/. R S.TRI RH0ADCJX ( k) T 99./. R 000 S.TMR NTCG BH 0JT T 0./. R S.RES ERJGEYJ V (. k) T 0./. R S.RES ERJGEYJ V (0 k) T 0./. R S.RES ERJGEYJ V ( k) T 0./. R S.RES ERJGEYJ V (0) T 0./0. R S.RES ERJGEYJ V (. k) T./. R S.RES ERJGEYJ V (. k) T./. R S.RES ERJGEYJ 0 V (0 k) T 0./. R S.RES ERJGEYJ V ( k) T 9./. R S.RES ERJGEYJ V ( k) T./. R S.RES ERJGEYJ V ( k) T 0/. R S.RES ERJGEYJ V ( k) T 0/. R S.RES ERJGEYJ 0 V ( k) T 0./. R S.RES ERJGEYJ V (0 k) T 0./0.9 R S.RES ERJGEYJ V (0 k) T 0./0.9 R S.RES ERJGEYJ V (0) T 0./0.9 R S.RES ERJGEYJ V (. k) T 99./0.9 R S.RES ERJGEYJ V ( k) T 99./.9 R S.RES ERJGEYJ V ( k) T 9/.9 R S.RES ERJGEYJ V (. k) T 9./.9 R S.RES ERJGEYJ 0 V (00 k) T./ R S.RES ERJGEYJ 0 V (00 k) T 0./0. R S.RES ERJGEYJ 0 V (00 k) T./ R S.RES ERJGEYJ 0 V (00 k) T./. R S.RES ERJGEYJ 0 V (00 k) T 0./9. R S.RES ERJGEYJ 0 V ( M) T 0./0. R S.RES ERJGEYJ 0 V ( k) T.9/9 R S.RES ERJGEYJ 0 V ( M) T./0. R S.RES ERJGEYJ 0 V ( M) T./. R S.RES ERJGEYJ 0 V (00 k) T 9./0. R S.RES ERJGEYJ 0 V (00 k) T.9/0. R S.RES ERJGEYJ 0 V ( M) T./9. R S.RES ERJGEYJ 0 V ( M) T 9./9. R S.RES ERJGEYJ V (. k) T./ R S.RES ERJGEYJ 0 V (00 k) T 0./9. R S.RES ERJGEYJ 0 V (00 k) T.9/9. R S.RES ERJGEYJ 0 V (00 k) T./0. R S.RES ERJGEYJ 0 V ( M) T./. R S.RES ERJGEYJ V (. k) T./. R S.RES ERJGEYJ V (. k) T 0./. R S.RES ERJGEYJ 0 V ( M) T 0./0 R S.RES ERJGEYJ 0 V ( M) T 0./. R S.RES ERJGEYJ 0 V ( M) T./0 R S.RES ERJGEYJ 0 V (00 k) T./. R S.RES ERJGEYJ V ( k) T./ R S.RES ERJGEYJ V ( k) T 9/. R S.RES ERJGEYJ 0 V (0 k) T./. R S.RES ERJGEYJ 0 V (0 k) T./ R S.RES ERJGEYJ 0 V (0 k) T./0. R S.RES ERJGEYJ 0 V ( k) T 9/. R S.RES ERJGEYJ 0 V (0 k) T 9/. R S.RES ERJGEYJ V (0 k) T./. R S.RES ERJGEYJ 0 V () T 0.9/. R S.RES ERJGEYJ 0 V (00 k) T.9/. [MAIN UNIT] REF ORDER H/V NO. NO. DESCRIPTION M. LOCATION R S.RES ERJGEYJ 9 V (9 k) T.9/0. R S.RES ERJGEYJ V ( k) T.9/. R S.RES ERJGEYJ V (. k) T.9/.9 R S.RES ERJGEYJ V (0 k) T.9/. R S.RES ERJGEYF 0 V (0 k) T.9/. R S.RES ERJGEYJ 00 V (0) T./9. R S.RES ERJGEYF V (. k) T./. R S.RES ERJGEYJ 0 V (00 k) T.9/9. R S.RES ERJGEYJ 0 V (0 k) T.9/0. R S.RES ERJGEYJ V (. k) T./. R S.RES ERJGEYJ V ( k) T./ R S.RES ERJGEYJ 0 V (00 k) T.9/.9 R S.RES ERJGEYJ 0 V (0 k) T./. R S.RES ERJGEYJ V (. k) T./. R S.RES ERJGEYJ V (0 k) T./. R S.RES ERJGEYJ 0 V (00 k) T.9/0. R S.RES ERJGEYJ V (. k) T./0. R S.RES ERJGEYJ V ( k) T./. R S.RES ERJGEYJ 0 V (00 k) T./. R S.RES ERJGEYJ V ( k) T./0. R S.RES ERJGEYJ V ( k) T./0. R S.RES ERJGEYJ V ( k) T./0. R S.RES ERJGEYJ V ( k) T./. R S.RES ERJGEYJ 0 V (00 k) T./.9 R S.RES ERJGEYJ V ( k) T./.9 R S.RES ERJGEYJ 0 V ( M) T./9. R S.RES ERJGEYJ V (. k) T./9. R S.RES ERJGEYJ 0 V (0 k) T./. R 000 S.TMR NTCG BH 0JT T 9./. R S.RES ERJGEYJ 0 V (0 k) T./. R S.RES ERJGEYJ V ( k) T./. R S.TRI RH0ADCSX ( k) T.9/. R S.RES ERJGEYJ V (. k) T./0. R S.RES ERJGEYJ V (0 k) T 9./0. R S.RES ERJGEYJ V ( k) T.9/. R S.RES ERJGEYJ V ( k) T./0. R S.RES MCR0EZHJ. (R) T./. R S.RES ERJGEYJ 0 V (0 k) T./9. R S.RES ERJGEYJ 0 V ( k) T./. R S.RES ERJGEYJ 0 V (0 k) T./9. R S.RES ERJGEYJ 0 V ( k) T./. R S.RES ERJGEYJ 9 V (.9 k) T./. R S.RES ERJGEYJ 9 V (.9 k) T./. R S.RES ERJGEYJ 0 V () T /0. R S.RES ERJGEYJ 0 V () T./. R S.RES ERJGEYJ 0 V () T /. R S.RES ERJGEYJ 0 V () T 0./. R S.RES ERJGEYJ 0 V (0 k) T./. R S.RES ERJGEYJ 0 V (00 k) T./ R S.RES ERJGEYJ V ( k) T./. R S.RES ERJGEYJ 0 V (0 k) T./. R S.RES MCR0EZHJ. (R) T./.9 R S.RES ERJGEYJ V ( k) T /9. R S.RES ERJGEYJ 0 V (00 k) T.9/. R S.RES ERJGE JPW V T./. C S.CER ECJ0EBCK T./0.9 C S.CER ECJ0EBC0K T /. C S.CER ECJ0EBA0K T /. C S.TAN TEESVA V MR T./. C S.TAN TEESVA C MR T./. C 0000 S.CER ECJ0EBE0K T./. C 0000 S.CER ECJ0ECH0J T./. C S.TRI TZCR00A0R00 T./. C S.CER ECJ0ECH0J T./. C S.CER ECJ0EBE0K T./.9 C 0000 S.ELE CE 0 BS T./. C S.CER ECJ0EBC0K T./. C 0000 S.CER ECJ0EBE0K T./9 C 0000 S.CER ECJ0EBEK T./. C S.CER ECJ0EBC0K T./. C S.CER C0 JB A 0K-T T 0./0. C S.CER ECJ0EBE0K T 9./ C 0000 S.CER ECJ0EBEK T./.9 C 0000 S.CER ECJ0ECH00B T./9. C S.CER ECJ0ECH0J T./. C 0000 S.CER ECJ0ECH0J T./ C 0000 S.CER ECJ0ECH0J T 9./. C 0000 S.CER ECJ0EBE0K T./. C 0000 S.CER ECJ0ECH0J T.9/. C 0000 S.CER ECJ0ECH90J T.9/. C S.TAN TEESVA V MR T 9.9/.9 C 0000 S.CER ECJ0EBE0K T./. C S.CER C0 CH H RB-T T./0. C S.CER C0 CH H RB-T T 0./0. C 0000 S.CER ECJ0EBE0K T./9 C 0000 S.CER ECJ0EBEK T 0./. C S.CER ECJ0EBEK T./. C 0000 S.CER ECJ0ECHRB T./0. C 0000 S.CER ECJ0EBEK T./. M.=Mounted side (T: Mounted on the Top side, B: Mounted on the Bottom side) S.=Surface mount -

20 [MAIN UNIT] REF ORDER H/V NO. NO. DESCRIPTION M. LOCATION C S.CER C0 JB H 0K-T T./. C 0000 S.CER C0 CH H 00B-T T./0. C S.CER C0 JB H K-T T./. C S.CER ECJ0ECH0J T./9. C 0000 S.CER ECJ0EBE0K T./.9 C 0000 S.CER ECJ0ECH00B T./. C S.CER ECJ0EBE0K T./. C 0000 S.CER ECJ0EBE0K T./9. C 0000 S.CER ECJ0EBE0K T./ C 0000 S.CER ECJ0ECH0J T./. C S.CER ECJ0ECH0J T /.9 C S.CER ECJ0ECH0J T./. C 0000 S.CER ECJ0EBE0K T./. C 0000 S.CER ECJ0ECH0J T 9./. C 0000 S.CER ECJ0EBE0K T 9./.9 C S.CER ECJ0ECH0J T 0/9. C S.CER ECJ0EBE0K T 9./. C S.CER ECJ0EBE0K T./. C S.CER ECJ0ECH00B T.9/. C S.CER ECJ0EBE0K T./. C S.CER ECJ0ECH0J T./. C S.CER ECJ0EBEK T./0 C S.CER ECJ0ECH0J T./. C S.CER ECJ0ECH0J T./. C S.CER ECJ0ECH90J T 0./. C S.CER ECJ0ECH0J T./. C S.CER ECJ0EBE0K T 0/. C S.CER ECJ0EBA0K T./. C S.CER ECJ0EBE0K T / C S.CER ECJ0EBE0K T 0/.9 C S.ELE CE 0 BS T./. C 0000 S.CER ECJ0ECH0J T 9/. C 0000 S.CER ECJ0EBEK T /. C 0000 S.CER ECJ0EBE0K T./. C S.CER C0 JB E 0K-T T./. C S.CER C0 JB E 0K-T T 9./9. C 0000 S.CER ECJ0ECH00C T./9. C 0000 S.CER ECJ0ECHJ T./0. C 0000 S.ELE CE BS T /. C S.CER ECJ0EBE0K T /9. C S.CER ECJ0EBE0K T 9./. C CER HM0SJ CH 0J 00V C S.CER C0 JB H 0K-T T./. C S.CER C0 JB H 0K-T T./. C CER HM0SJ CH 0J 00V C S.CER C0 JB H 0K-T T.9/.9 C CER RT-HM0SK YB 0K 00V C CER HM0SJ CH 0J 00V C CER HM0SJ CH 00D 00V C CER HM0SJ CH 0J 00V C CER HM0SJ CH 00C 00V C CER HM0SJ CH 00C 00V C 0000 S.CER ECJ0EBE0K T /. C S.CER ECJ0EBC0K T./ C 0000 S.CER ECJ0EBE0K T./. C S.CER C0 JB H 0K-T T./. C S.CER C0 JB H 0K-T T 0./. C S.CER ECJ0EBE0K T./. C CER HM0SJ CH 0J 00V C 0000 S.CER ECJ0EBE0K T.9/. C S.CER ECJ0ECH0RB T./. C S.CER C0 JB H 0K-T T 0./. C S.CER C0 CH H 00D-T T 9./. C S.CER C0 CH H 00D-T T 0./. C 0000 S.CER ECJ0ECH00B T /. C 0000 S.CER C0 CH H 00B-T T./. C 0000 S.CER ECJ0EBE0K T 0./0. C S.CER ECJ0EBA0K T 0./9. C 0000 S.CER ECJ0EBE0K T 09./.9 C S.CER C0 JB H 0K-T T./. C S.CER ECJ0EBE0K T./.9 C S.CER ECJ0EBA0K T 09./ C 0000 S.CER ECJ0ECHRB T 0./. C 0000 S.CER C0 CH H 00B-T T 0./. C 0000 S.CER ECJ0EBE0K T 0./0. C 0000 S.CER ECJ0ECH00B T 0./. C 0000 S.CER ECJ0EBE0K T 9./0. C 0000 S.CER C0 CH H 00B-T T 9.9/. C 0000 S.CER ECJ0ECH00B T 9/. C 0000 S.CER ECJ0ECH0RB T 9./. C 0000 S.CER ECJ0ECHRB T 9./9. C 0000 S.CER ECJ0ECH00B T /9. C 0000 S.CER C0 CH H 00B-T T 9./0. C S.CER ECJ0EBA0K T./ C S.CER C0 JB H 0K-T T./9.9 C S.CER C0 JB H 0K-T T 9./. C 0000 S.CER ECJ0EBE0K T./. C 0000 S.CER ECJ0ECH00B T./.9 C S.CER ECJ0EBC0K T./.9 C 0000 S.CER ECJ0ECH00B T.9/. C S.CER ECJ0ECH0J T./9.9 [MAIN UNIT] REF ORDER H/V NO. NO. DESCRIPTION M. LOCATION C S.CER ECJ0EBA0K T 9./. C 0000 S.CER ECJ0EBE0K T 9./. C S.CER ECJ0EBE0K T /.9 C S.CER C0 CH H 00B-T T./. C S.CER ECJ0EBE0K T./. C S.CER ECJ0EBCK T 9./. C S.CER ECJ0EBE0K T./. C S.CER ECJ0EBC0K T./. C S.CER ECJ0ECH0J T 9.9/0. C S.CER ECJ0EBE0K T./9.9 C S.ELE CE 0 BS T./.9 C S.CER ECJ0EBC0K T./0.9 C S.CER ECJ0EBE0K T 0./. C 0000 S.CER ECJ0EBEK T 9./. C 0000 S.CER ECJ0EBEK T 99./.9 C 0000 S.CER ECJ0EBE0K T 99./0.9 C S.CER ECJ0EBA0K T 0./. C S.CER C0 JB A 0K-T T 9./ C S.CER ECJ0EBA0K T 9./. C S.CER ECJ0ECH0J T 0./. C S.CER ECJ0EBA0K T 0./. C S.CER ECJ0EBE0K T 0./0. C S.CER ECJ0EBE0K T 9./. C S.CER ECJ0EB0JK T 9./0.9 C S.CER ECJ0EB0JK T./. C S.CER ECJ0EBA0K T./ C S.CER ECJ0EB0JK T 0/. C S.CER ECJ0EBA0K T 0./. C S.CER ECJ0EBCK T 0/0.9 C S.CER ECJ0EBCK T 0./. C 0000 S.ELE CE 0 BS T 0./9. C 0000 S.CER ECJ0EBHK T 9./.9 C 0000 S.CER ECJ0EBHK T 9./0.9 C 0000 S.ELE 0 CE R BS T 9./9.9 C 0000 S.ELE 0 CE R BS T 0./.9 C S.CER ECJ0EBC0K T 0./. C S.CER C0 JB A 0K-T T 9./0. C S.CER ECJ0EB0JK T.9/. C S.CER C0 JB A 0K-T T./9. C S.CER ECJ0EBC0K T./9. C 0000 S.CER ECJ0EBE0K T./. C 0000 S.ELE 0 CE R BS T./. C S.CER ECJ0EB0JK T 0./. C 0000 S.ELE 0 CE R BS T /. C S.CER ECJ0EBA0K T./. C S.CER ECJ0EBEK T 9/ C S.CER ECJ0EBC0K T./. C S.CER ECJ0EBCK T./. C 0000 S.CER ECJ0EBHK T 9/0. C S.CER ECJ0EBEK T 9/. C S.CER ECJ0EBA0K T./9. C S.CER ECJ0EB0JK T./. C S.CER ECJ0EBA0K T 0./. C 0000 S.ELE CE 0 BS T 0./0. C S.MLR ECHU C JX T 9/. C 0000 S.CER ECJ0EBHK T.9/. C S.CER ECJ0EBA0K T.9/9 C S.CER ECJ0EBC0K T.9/. C S.ELE CE 0 BS T.9/. C S.CER ECJ0EBC0K T 9.9/. C S.CER ECJ0EBE0K T 9./ C S.CER ECJ0EBA0K T.9/.9 C S.CER ECJ0EBC0K T.9/. C S.CER ECJ0EBEK T./. C S.CER ECJ0EBC0K T 0./0. C S.CER ECJ0EBA0K T./.9 C S.CER ECJ0ECH0J T./. C S.CER ECJ0EB0JK T./9. C 0000 S.CER ECJ0EBEK T./. C 0000 S.CER ECJ0EBEK T./. C S.CER ECJ0ECH0J T.9/.9 C S.CER ECJ0EBC0K T./9. C 0000 S.ELE CE 0 BS T.9/. C 0000 S.CER C0 JB A K-T T./0. C 0000 S.CER ECJ0ECH0J T./0. C S.CER C0 JB A 0K-T T /. C S.CER ECJ0EBEK T./. C S.CER ECJ0EBC0K T./. C 0000 S.CER ECJ0EBE0K T./. C S.CER C0 JB H 0K-T T./. C S.CER ECJ0ECH0J T./. C 0000 S.CER ECJ0EBE0K T /. C 0000 S.CER ECJ0EBE0K T./. C S.CER ECJ0ECH0J T./. C 0000 S.CER ECJ0EBE0K T./. C S.CER ECJ0ECH0J T./. C S.CER ECJ0ECH0J T./. C 0000 S.CER ECJ0ECH0J T./9. C 0000 S.CER ECJ0EBE0K T /. C 0000 S.CER ECJ0EBE0K T 0./. C 0000 S.CER ECJ0EBEK T./. M.=Mounted side (T: Mounted on the Top side, B: Mounted on the Bottom side) S.=Surface mount -

21 [MAIN UNIT] REF ORDER H/V NO. NO. DESCRIPTION M. LOCATION C 0000 S.CER ECJ0EBEK T /.9 C 0000 S.CER ECJ0EBE0K T 0./. C 0000 S.CER ECJ0ECH0J T 0./. C 0000 S.CER ECJ0ECH0J T./. C S.CER ECJ0EBE0K T./.9 C S.CER ECJ0EBC0K T 0./0 C S.CER C0 JB A 0K-T T /. C 0000 S.CER ECJ0EBE0K T./. C ELE WA 0M (X9) C 0009 ELE ME 0 HC+TS C S.CER C0 JB E 0K-T T./.9 C 0000 S.CER ECJ0ECH0J T./. C S.CER ECJ0ECH0J T./. C S.CER ECJ0EBE0K T 9./.9 C 0000 S.CER ECJ0EBE0K T 0./.9 C 0000 S.CER ECJ0EBE0K T./. C 0000 S.CER ECJ0ECH0J T./.9 C ELE ME 00 HC C S.CER C0 JB E 0K-T T 9./. C S.CER ECJ0ECH0J T./. C S.CER ECJ0ECH0J T 9./.9 C 0000 S.CER ECJ0ECH0J T /.9 C 0000 S.CER ECJ0EBEK T./.9 C 0000 S.CER ECJ0ECH0J T./0. C 0000 S.CER ECJ0EBE0K T./0. C S.CER ECJ0ECH0J T./. C S.CER ECJ0EBEK T./.9 C 0000 S.ELE CE 00 BS T./. C S.CER C0 JB H 0K-T T./. C S.CER C0 JB E 0K-T T./ C S.CER ECJ0EBA0K T /. C S.CER ECJ0EBC0K T./. C 0000 S.ELE CE 00 BS T./. C S.CER ECJ0EBA0K T 0/.9 C 0000 S.CER ECJ0EBE0K T /. C S.ELE CE 0 BS T.9/. C S.CER ECJ0EBA0K T /. C S.CER ECJ0EBE0K T 0/0. C S.ELE CE 0 BS T./. C S.ELE CE 0 BS T 9./. C S.CER C0 JB H 0K-T T 9.9/. C 0000 S.CER ECJ0ECH0J T./. C 0000 S.ELE 0 CE R BS T./. C 0000 S.ELE 0 CE R BS T 0/. C S.CER ECJ0EBA0K T./0. C 0000 S.CER ECJ0ECH0J T./0. C 0000 S.CER ECJ0ECH0J T /. C S.CER ECJ0EB0JK T /. C S.CER C0 JB A 0K-T T /. C 0000 S.CER ECJ0EBE0K T./9. C 0000 S.CER ECJ0EBE0K T./.9 C 0009 ELE ME 0 HC+TS C 0009 ELE ME 0 HC+TS C S.CER C0 JB E 0K-T T./. C 0000 S.CER ECJ0ECH0J T./. [VR BOARD] REF ORDER H/V NO. NO. DESCRIPTION M. LOCATION R 0000 VAR TP9N9A-.SK-0KB- W CBL OPC- [SQL BOARD] REF ORDER H/V NO. NO. DESCRIPTION M. LOCATION R 0000 VAR TP9N9-SK-0KB- - HM-0B/SW [MAIN UNIT] REF ORDER H/V NO. NO. DESCRIPTION M. LOCATION R RES K R0 R RES.K R0 R RES K R0 R RES K R0 C 0000 S.CER 0.0 C0 V B B 0.9/. MC MIC KUC-00 S 0000 SW SKHHLPA00 S SW KHHAMA00 S SW KHHAMA00 S SW KHHAMA00 W W /9/00/X9/X9 W W /9/00/X9/X9 W W /00/00/W0/W0 W W /0/00/W0/W0 M.=Mounted side (T: Mounted on the Top side, B: Mounted on the Bottom side) S.=Surface mount J 00 S.CNR BB-ZR-SM-TF (LF) (SN) T 9./. J 00 S.CNR BB-ZR-SM-TF (LF) (SN) T./. J 000 S.CNR 0FLT-SM-TB T /0. J 000 S.CNR 0FLT-SM-TB T.9/. W JMP ERDST0 W WIR /9/00/X99/X99 W JMP ERDST0 W CBL OPC-9 <TJM> W CBL OPC-9 <TJM> W JMP ERDST0 EP TUB IRRAX.0 (d) L= mm EP TUB IRRAX. (d) L=0 mm EP S.BEA MPZ0SA-T T 9.9/.9 EP S.BEA MPZ0SA-T T 9./. EP S.BEA MPZ0SA-T T 9./. EP S.BEA MPZ0SA-T T./. [FRONT UNIT] REF ORDER H/V NO. NO. DESCRIPTION M. LOCATION MC MIC HM-0B ACC <FG> [BLACK] MIC HM-0SW ACC <FG> [SW] W JMP ERDST0 W JMP ERDST0 -