SERVICE MANUAL. MF/HF MARINE TRANSCEIVER im802

Transcript

1 SERVICE MANUAL MF/HF MARINE TRANSCEIVER im0

2 INTRODUCTION This service manual describes the latest service information for the IC-M0 MF/HF MARINE TRANSCEIVER at the time of publication. MODEL IC-M0 VERSION U.S.A. Canada Other SYMBOL USA CAN OTH To upgrade quality, any electrical or mechanical parts and internal circuits are subject to change without notice or obligation. DANGER NEVER connect the transceiver to an AC outlet or to a DC power supply that uses more than V. This will ruin the transceiver. DO NOT expose the transceiver to rain, snow or any liquids. DO NOT reverse the polarities of the power supply when connecting the transceiver. DO NOT apply an RF signal of more than 0 dbm (00 mw) to the antenna connector. This could damage the transceiver s front end. ING PARTS Be sure to include the following four points when ordering replacement parts:. 0-digit order numbers. Component part number and name. Equipment model name and unit name. Quantity required <SAMPLE > S.IC µpc0t IC-M0 MAIN UNIT pieces 0000 Screw BiH M ZK IC-M0 Top cover 0 pieces Addresses are provided on the inside back cover for your convenience. REPAIR NOTES. Make sure a problem is internal before disassembling the transceiver.. DO NOT open the transceiver until the transceiver is disconnected from its power source.. DO NOT force any of the variable components. Turn them slowly and smoothly.. DO NOT short any circuits or electronic parts. An insulated tuning tool MUST be used for all adjustments.. DO NOT keep power ON for a long time when the transceiver is defective.. DO NOT transmit power into a signal generator or a sweep generator.. ALWAYS connect a 0 db to 0 db attenuator between the transceiver and a deviation meter or spectrum analyzer when using such test equipment.. READ the instructions of test equipment thoroughly before connecting equipment to the transceiver.

3 TABLE OF CONTENTS SECTION SECTION SECTION SECTION SECTION SPECIFICATIONS INSIDE VIEWS CIRCUIT ADJUSTMENT PROCEDURES PARTS LIST SECTION MECHANICAL PARTS AND DISASSEMBLY - RC SP HM IC-M SECTION SEMI-CONDUCTOR INFORMATION SECTION BOARD LAYOUTS - HM- - - SW BOARD MAIN BOARD RC- - - JACK BOARD CONNECT BOARD SENSOR BOARD VR BOARD DISPLAY BOARD IC-M0 - - DSP BOARD MAIN UNIT FILTER BOARD PLL UNIT PA UNIT DRIVER BOARD VARISTOR- BOARD VARISTOR- BOARD... - SECTION SECTION 0 BLOCK DIAGRAM WIRING DIAGRAM SECTION VOLTAGE DIAGRAMS - RC- and HM IC-M0 - - MAIN UNIT () MAIN UNIT () MAIN UNIT () PA UNIT PLL UNIT () PLL UNIT () DSP BOARD FILTER BOARD... -

4 SECTION SPECIFICATIONS IC-M0 GENERAL Frequency coverage : Mode : TX/RX JE (USB/LSB), JB (AFSK), FB (FSK), AA (CW) HE [OTH] RX HE DSC JB Antenna impedance : 0 Ω Frequency stability : ±0 Hz, ±0 Hz [OTH] Power supply requirement :. V DC ±% Negative ground Current drain (at. V DC) : RX;.0 A at Max. output power TX; 0 A typical at Max. audio output Usable temperature range : 0 C to + C; F to + F Dimensions (projections not included) : 0(W) (H).(D) mm; (W) (H) (D) in. Weight Receive Transmit DSC receive :. kg; 0. lb;. oz 00 khz. MHz.000. MHz MHz MHz MHz MHz MHz MHz MHz MHz. MHz,.0 MHz,.0 MHz,. MHz,.0 MHz,.0 MHz TRANSMITTER Output power Spurious emissions Carrier suppressions Unwanted sideband suppresion Microphone impedance : 0, 0, 0 W PEP : db : 0 db : db : 00 Ω RECEIVER Sensitivity : (Receiver) MODE JE, AA JB, FB HE FREQUENCY 0.. MHz.. MHz.. MHz.. MHz.. MHz.. MHz.. MHz.. MHz 0 db SINAD 0 dbµve.m.f. dbµve.m.f. dbµve.m.f. dbµve.m.f. dbµve.m.f. dbµve.m.f. 0 dbµve.m.f. dbµve.m.f. 0 db S/N dbµv dbµv dbµv dbµv dbµv 0 dbµv dbµv 0 dbµv (DSC) : 0 dbµve.m.f. (JB;.,.0,.0,.,.0,.0 MHz) Squelch sensitivity : MODE Threshold Tight JE at.0 MHz Less than +0 dbµv Less than +0 dbµv HE at.000 MHz Less than +0 dbµv Less than +0 dbµv Spurious response rejection Clarity variable range : More than 0 db : ±0 Hz -

5 RC- Remote controller GENERAL Microphone impedance Audio output power Audio output impedance Usable temperature range Dimension (projections not included) Weight : 00 Ω : More than mw at Ω headphone with 0 % distortion : Ω : 0 C to + C; F to + F : 0(W) 0(H).(D) mm; (W) (H) (D) in. : 0 g;. lb; oz SP- External speaker GENERAL Impedance : Ω Input power : Rated input; W Maximum input; W Usable temperature range : 0 C to +0 C; F to +0 F Dimension (projections not included) : 0(W) 0(H).(D) mm; (H) (H) (D) in. Weight : 0 g; 0. lb;. oz All stated specifications are subject to change without notice or obligation. -

6 SECTION INSIDE VIEWS RC- VR BOARD DISPLAY BOARD Reset IC (IC0: S-0ANMP) S-0CNMC) CPU (IC0: HDFAFA0) LCD unit (DS0: HLC0-000) HLC00-000) SENSOR BOARD Power amplifier (IC0: TAF) IC-M0 DSC st mixer D0: HSBWS [USA],[CAN] only DSC nd mixer IC0: TA0F [USA],[CAN] only PA UNIT MAIN UNIT DSP DSP BOARD BOARD CPU IC0: M0FGAFP CPU [USA],[CAN] (IC0: M00FCAFP M0MGA) [OTH] nd nd mixer mixer (D0: HSBWS) st st mixer circuit st st IF IF amplifier amplifier (Q0: (Q0: SK) SK) VARISTOR- BOARD FAN controller (IC0: TSID) DRIVER BOARD VARISTOR- BOARD -

7 SECTION CIRCUIT - RECEIVER CIRCUITS -- RF FILTER CIRCUIT (FILTER AND MAIN UNITS) Received signals from the antenna connector are applied to the transmit/receive switching and protection relay (FILTER unit; RL0) which is controlled by the CPU via the TRXS line. The signals pass through the 0 MHz cut-off low-pass filter (FILTER unit; L, C C, C), and then applied to the MAIN unit via the J. The signals pass through the transmit/receive switch (D) and. MHz cut off high-pass filter (L L, C, C, C, C, C C), and are then applied to one of the bandpass filters (including one low-pass filter for below.0 MHz). These filters are selected by the filter control signals (B0 B) as described in the table below. The filtered signals pass through the MHz cut-off lowpass filter (L0, L0, C0 C0), and are then applied to the st mixer circuit (Q0, Q0). Frequency (MHz) LPF ctrl signal L0 L L L L L L L BPF ctrl signal B0 B B B B B B -- ST MIXER AND IF CIRCUITS (MAIN UNIT) The st mixer circuit converts the received signals into a fixed frequency,. khz st IF signal using PLL output frequency. By changing the PLL frequency, only the desired frequency is picked up at the pair of crystal filters (FI0a, FI0b) via the. khz bandpass filter (FI0) at the next stage. B B The IF amplifier (Q0) and resonator circuits are designed between the filter pair. The PLL output signal (LO) enters the MAIN unit via the J0 and is amplified at the st LO amplifier (Q0). The amplified signal is passed through the 00 MHz cut-off low-pass filter (L0, L0, C0, C0 C0) to suppress harmonics components, and then applied to the st mixer circuit (Q0, Q0). -- ND MIXER AND IF CIRCUITS (MAIN UNIT) The st IF signal from the crystal filter (FI0b) is converted again into a khz nd IF signal at the nd mixer circuit (D0, L0, L0). The nd LO signal (LO) from the PLL unit enters the MAIN unit via the J0 to be applied to the nd mixer circuit. -- RD MIXER AND IF CIRCUITS (MAIN UNIT) The nd IF signal passes through the low-pass filter (L0, L0, C0 C), and then applied to the IF amplifier (Q0) via the ceramic bandpass filter (FI0). The amplified signal passes through the ceramic bandpass filter (FI0), and then applied to the rd mixer circuit via the IF amplifier (Q0). The nd IF signal is converted into a khz rd IF signal at the rd mixer circuit (IC0). The rd LO signal (LO) from the PLL unit enters the MAIN unit via the J0 to be applied to the rd mixer circuit. -- DSP RECEIVER CIRCUIT (MAIN AND DSP UNITS) The DSP (Digital Signal Processor) circuit enables digital IF filter, digital noise reduction, digital PSN (Pulse Shift Network), phase demodulation, digital automatic notich, and etc. The rd IF signal is applied to the IF amplifier (MAIN unit; IC00, pin ) after being passed through the low-pass filter (MAIN unit; IC00, pins, ). The amplified khz rd IF signal is amplified at the differential amplifiers (ICa/b), and is then applied to the A/D convertor section in the CODEC IC (IC0) on the DSP board (EX-). At the same time, the converted signal is level-shifted V to. V in the IC (IC0). RECEIVER CONSTRUCTION Antenna LPF FILTER unit 0.. MHz LPF BPF 0 MHz st LO MHz st mixer Q0 Q0 Crystal BPF FI0A FI0B nd LO MHz nd mixer Q0 Q0 rd LO khz Crystal BPF FI0 IF amp. Q0 to transmit/receiver switch DSP UNIT IF amp. IC00 LPF rd mixer IC0 IF amp. Q0 Crystal BPF FI0 -

8 The level-shifted signal is applied to the DSP IC (IC0) for the digital IF filter, demodulator, automatic notch and noise reduction, etc. The output signal from the DSP IC is applied to the D/A converter section in the CODEC IC (IC0) to convert into the analog audio signals. Also the signals are level-shifted. V to V at the level converter section in the IC (IC0). The level-shifted audio signals are passed through the active filter (IC0a), and then applied to the MAIN unit via J0 (pin ) as the DRAF signal. -- AGC CIRCUIT (DSP AND MAIN UNITS) The AGC (Automatic Gain Control) circuit reduces IF amplifier gain and attenuates IF signal to keep the audio output at a constant level. The receiver gain is determined by the voltage on the AGC line from the DSP unit. The D/A converter for the AGC (IC0) supplies control voltage to the AGC line and sets the receiver gain with the [RF/SQL] control. The rd IF signal from the CODEC IC (IC0) is detected at the AGC detector section in the DSP IC (IC0). The output signal from the DSP IC is level-shifted at the level converter (IC0) and applied to the D/A converter (IC0). The AGC voltage is amplified at the buffer amplifier section in the IC0 and applied to the MAIN unit to control the AGC line. When receiving strong signals, the detected voltage increases and the AGC voltage decreases. As the AGC voltage is used for the bias voltage of the IF amplifiers (MAIN unit; Q0, Q0, Q0), IF amplifier gain is decreased. -- AF AMPLIFIER CIRCUIT (DSP AND MAIN UNITS) The AF amplifier amplifies the audio signals to the suitable driving level for the speaker. The AF signals from the DSP unit are passed through the transmit/receive switch (MAIN unit; IC0, pins, ) via the DSPO signal, and then applied to the AF amplifier (MAIN unit; IC0, pin ) after being passed through the low-pass filter (MAIN unit; IC0, pins, ). The amplified signal passes through the the SQL gate (MAIN unit; IC0, pins, ) which is controlled by the CPU (IC0, pin ) via the SQLC signal. The signal is applied to the electronic volume IC (MAIN unit; IC0, pin ) which can control the volume attenuation by AFG voltage from the CPU (MAIN unit; IC0). Beep, tone, side tone, monitor signals are applied to the the elecronic volume IC too. The signal is applied to the AF mute swtich, and then amplified at the AF power amplifier (IC0, pin ). The amplified signal is applied to the speaker (SP-) after being passed through the speaker jack (J) via the AFO signal. DSP CIRCUIT rd IF signal DSPI ( khz) ICb/a Differential converter CODEC IC (IC0) A/D converter Level converter IC0 DSP IC D/A converter Level converter IC0a Active filter DSPO AF signals MAIN UNIT DSP UNIT AGC CIRCUIT From the antenna DSPI IC00 IF amp. Q0 IF amp. Q0 IF amp. Q0 IF amp. IC0 DSP UNIT AGC AGC AGC AGC From the DSC antenna DSPI IC0 AMP. IF amp. Q0 IF amp. Q0 RF amp. Q0 Q0 -

9 - TRANSMITTER CIRCUITS -- MICROPHONE AMPLIFIER CIRCUIT (RC-, MAIN AND DSP UNITS) The microphone amplifier circuit amplifies microphone audio signal to a level needed for the DSP circuit. Audio signals from the [MIC] connector (J0, pin ) are amplified at the AF amplifier (IC0, pin ), and then applied to the gate modulator IC (MAIN unit; IC00, pin ) via the J0, pin as FMOD signal. The signal is applied to the DSP unit after being passed through the limitter amplifier and low-pass filter IC (MAIN unit; IC0, pins, ) as DSPI signal. -- DSP TRANSMITTER CIRCUIT (DSP UNIT) The DSP (Digital Signal Processor) circuit enables PSN (Phase Shift Network)/Low Power/Phase modulator, transmitter monitor, side tone, and etc. The microphone audio signals from the MAIN unit via the DISPI line are amplified at the differential amplifiers (ICa/b), and are then applied to the A/D converter section in the CODEC IC (IC0). at the same time, the converted signals are level-shifted V to. V in the IC (IC0). The level shifted signals are applied to the DSP IC (IC0) and modulated at the DSP IC to p[roduce the khz transmitter IF signal. The modulated IF signal from the DSP IC is applied to the D/A convertor section in the CODEC IC (IC0) to convert into the analog IF signal. Also the signal is level-shifted. V to V at the level converter section in the IC (IC0). The level-shifted IF signal is passed through the active filter (IC0a), and then applied to the MAIN unit via J0 (pin ) as the DSPO signal. When the speech compressor function is ON, the level-shifted signal from the CODEC IC (IC0) is applied to the DSP IC (IC0) and compressed at the DSP IC to obtain an average audio level. At the same time, the compressed signals are modulated at the DSP IC and applied to the D/A converter section in the CODEC IC (IC0). -- IF AMPLIFIER AND MIXER CIRCUITS (MAIN UNIT) The modulated rd IF signal from the DSP unit ( DSPO signal: khz) passes through the transmit/receive swtich (IC0, pins, ), and then applied to the rd mixer circuit (IC0, pin ). The applied rd IF signal is mixed with the rd LO signal from the DDS circuit (PLL unit; IC0) to produce a khz nd IF signal. The nd IF signal is output from IC0, pin and passes through the ceramic bandpass filter (FL0) to suppress the unwanted signals via the D0. The filtered nd IF signal is amplified at the nd IF amplifier (Q0), and then applied to the nd mixer circuit after being passed through the D0 and low-pass filter (L0 L0, C0 C, R0). The nd IFsignal is mixed with MHz nd LO signal, coming from the PLL circuit, at the nd mixer circuit (D0) to obtain. MHz st IF signal. The st IF signal is passed through the crystal bandpass filter (FI0A, FI0B) to cut off the unwanted signals. The signal is applied to the transmitter mixer circuit (Q0, Q0) to obtain the desired signal via the transmit/receive switch (D0) and attenuator. The operating (transmitting) frequency is produced at the st IF mixer circuit (Q0, Q0) by mixing the st IF and st LO signals. The mixed signal is then applied to the RF circuit. -- SPEECH COMPRESSOR CIRCUIT (DSP UNIT) The DSP (Digital Signal Processor) circuit enables PSN The speech compressor compresses the transmitter audio input signals to increase the average output level (average talk power). TRANSMIT CONSTRUCTION IC00 MIC Controller AMP. VCA IC0 AMP. LPF DSPI IC00 DSP UNIT DSPO ( khz) rd LO ( khz) khz Ceramic BPF FI0 Q0 AMP. Antenna nd mixer D0 FI0b/a. khz Crystal BPF nd LO (.00 MHz) Bandwidth: khz st mixer Q0, Q0 st LO ( MHz) RF amp. Q0 0.. MHz LPF BPFs 0 MHz YGR IC PA UNIT AMPs Q0, Q0, Q, Q0, Q0 FILTER UNIT LPFs PWR DET D, D -

10 -- RF CIRCUIT (MAIN, PA UNITS AND DRIVER BOARD) The RF circuit amplifies operating (transmitting) frequency to obtain 0 W of RF output. The signal from the st IF mixer is passed through one of the low-pass filter or bandpass filters (Refer to page - bandpass filters used), and then applied to the YGR amplifier (IC, pin ) after being passed through the attenuator (R R). The amplified signal passes through the low-pass filter (L L, C C) and attenuator (R R), and then applied to the PA unit via J. The signal applied from the MAIN unit is amplified at amplifiers (PA unit; Q0 and Q0). A part of output signal from amplifiers are applied to the amplifiers to improve the frequency characteristic by feedback. The amplified signal is applied to the drive amplifier (DRIVER board; Q) via the J0 as DRVI signal. The signal from the DRIVER board passes through the impedance converter (PA unit; L0), and then applied to push-pull amplifiers (PA unit; Q0, Q0) to obtain a stable 0 W of RF output power. A part of the RF output power returns to the amplifiers to obtain a stable gain between. MHz and. MHz bands by using feedback transformer (L0). The output power is applied to the filter unit via the J0 as FLIN signal. The amplified signal is applied to the one of the low-pass filters which are composed chebychev type... MHz signal The signal is applied to the relay (FILTER unit; RL0) which is controlled by the band control IC (MAIN unit; IC0) as the LM signal via the buffer amplifier (MAIN unit; IC0, pin ). The signal passes through the lowpass filter (FILTER unit; L0 L0, C0 C0, C0 C0, C0), and then applied to the RL0.. MHz signal The signal is applied to the relay (FILTER unit; RL0) which is controlled by the band control IC (MAIN unit; IC0) as the LM signal via the buffer amplifier (MAIN unit; IC0, pin ). The signal passes through the lowpass filter (FILTER unit; L0 L0, C0 C0, C0, C0), and then applied to the RL0.. MHz signal The signal is applied to the relay (FILTER unit; RL0) which is controlled by the band control IC (MAIN unit; IC0) as the LM signal via the buffer amplifier (MAIN unit; IC0, pin ). The signal passes through the lowpass filter (FILTER unit; L0 L0, C0 C0, C0 C0, C0 C0), and then applied to the RL0.. MHz signal The signal is applied to the relay (FILTER unit; RL) which is controlled by the band control IC (MAIN unit; IC0) as the LM signal via the buffer amplifier (MAIN unit; IC0, pin ). The signal passes through the lowpass filter (FILTER unit; L L, C C, C, C), and then applied to the RL.. MHz signal The signal is applied to the relay (FILTER unit; RL) which is controlled by the band control IC (MAIN unit; IC0) as the LM signal via the buffer amplifier (MAIN unit; IC0, pin ). The signal passes through the lowpass filter (FILTER unit; L0 L0, C0 C0, C0, C0), and then applied to the RL. 0. MHz signal The signal is applied to the relay (FILTER unit; RL) which is controlled by the band control IC (MAIN unit; IC0) as the LM signal via the buffer amplifier (MAIN unit; IC0, pin ). The signal passes through the lowpass filter (FILTER unit; L L, C C, C), and then applied to the RL. RF FILTER CIRCUIT Transmitter signals from the PA unit. LPF Filter: L0.. MHz power detector Antenna LPF Filter: L. MHz LPF Filter: L. MHz LPF Filter: L. MHz LPF Filter: L. MHz LPF Filter: L 0. MHz LPF Filter: L. MHz LPF Filter: L 0. MHz low-pass filter control signals from the MAIN unit (LM, LM, LM, LM, LM, LM, LM) -

11 . MHz signal The signal is applied to the relay (FILTER unit; RL) which is controlled by the band control IC (MAIN unit; IC0) as the LM signal via the buffer amplifier (MAIN unit; IC0, pin ). The signal passes through the lowpass filter (FILTER unit; L L, C, C, C, C C), and then applied to the RL. 0. MHz signal The signal is applied to the relay (FILTER unit; RL) which is controlled by the band control IC (MAIN unit; IC0) as the LM signal via the buffer amplifier (MAIN unit; IC0, pin ). The signal passes through the lowpass filter (FILTER unit; L, L, L, C C, C C, C, C), and then applied to the RL. The filtered signal is applied to the antenna connector after being passed through the RL0 and J. -- ALC CIRCUIT (FILTER AND MAIN UNITS) The ALC (Automatic Level Control) circuit controls the gain of IF amplifiers in order for the transceiver to output a constant RF power set by the [RF PWR] control even when the supplied voltage shifts, etc. The RF power level is detected at the power detector circuit (Filter unit; D) to be converted into DC voltage and applied to the MAIN unit as the FOR signal. The FOR signal is applied to the comparator (IC0, pin ). The POCV signal, controlled by the [RF PWR] control via the I/O expander (IC0, pin ), is also applied to the other input (pin ) for reference. The compared signal is output from pin and applied to the IF amplifier in the MAIN (Q0) unit to control amplifying gain. When the FOR signal exceeds the POCV voltage, ALC bias voltage from the comparator controls the IF amplifiers. This adjusts the output power to a specified level from the [RF PWR] control until the FOR and POCV voltages are equalized. -- APC CIRCUIT (FILTER AND MAIN UNITS) The APC (Automatic Power Control) circuit protects the power amplifiers on the PA unit from high SWR and excessive current. SWR APC CIRCUIT (FILTER AND MAIN UNITS) The reflected wave signal appears and increases on the antenna connector. When the antenna is mismatched, D of the power detector circuit (D, D, L) in the FILTER unit detects the signal and applies it to the ALC amplifier (IC0, pin ) in the MAIN unit as signal. The output signal decreases the bias voltage of the RF APC amplifier to reduce the output power. CURRENT APC CIRCUIT (FILTER AND MAIN UNITS) The power transistor current is detected from the different voltage between both terminals of a 0.0 Ω resistor (R) on the PA board. The detected voltage is applied to the differential amplifier (IC0). When the current of the final transistors is more than 0 A, the detected voltage is applied to the APC amplifier controller (IC0) in the MAIN unit to reduce the gate- voltage of the IF amplifier (Q0) and thus reduce the output power. -- RF METER CIRCUIT (MAIN UNIT) The output of ALC amplifier (IC0, pin ) is applied to the CPU (IC0, pin ) as RFML signal to indicate the transmit power level on the display. For antenna current meter indication, the ANTM signal from the optional AT-0E is applied to the meter amplifier (IC0, pin ) via the J0 in the PA unit. -- MONITOR CIRCUIT (DSP AND MAIN UNITS) The micorphone audio signals can be monitored to check voice characteristics. A portion of the transmit IF signal from the DSP IC (IC0) is mixed with a khz LO signal to demodulate into the AF signals. The demodulated signals are level-shifted. V to V at the level converter (IC0) to convert into the analog AF signals. The AF signals are then applied to the MAIN unit as MONI signal. The MONI signal from the DSP unit is amplified at the AF amplifier (MAIN unit; IC0, pin ), and then applied to the VCA amplifier to control the AF volume (pin ). The amplified signal passes through to the AF mute circuit (MAIN unit; IC0, pins, ) which is controlled by the CPU via the expander IC (MAIN unit; IC0) as the AFMS signal. The AF signal is applied to the AF power amplifier circuit (MAIN unit; IC0, pin ) to drive a speaker. ALC CIRCUIT TX signals rd mixer nd mixer st mixer IF Q0 Crystal BPF RF LPF YGR PA BPFs PA UNIT FILTER UNIT LPFs D D Antenna Power detector ALC ALC amplifier ALC ALC IC0 -

12 - PLL CIRCUITS -- GENERAL The PLL circuits generate a reference frequency (.000 MHz); st LO frequencies (.. MHz); nd LO frequency ( MHz), rd LO frequency (.000 khz). The st LO PLL adopts a mixer-less dual loop PLL system. The BFO uses a DDS and a nd LO as a fixed frequency double that the crystal oscillator. -- ST LO PLL (PLL UNIT) The st LO PLL contains a main and reference loop as a dual loop system. The reference loop generates an approximate 0. MHz frequency using a DDS circuit, and the main loop generates a. to. MHz frequency using the reference loop frequency. () ERENCE LOOP PLL The oscillated signal at the reference VCO (Q0, D0) is amplified at the amplifiers (Q0, Q) and is then applied to the DDS IC (IC0, pin ). The signal is then divided and detected on phase with the DDS generated frequency. The detected signal output from the DDS IC (pin ) is converted into DC voltage (lock voltage) at the loop filter (R, R, C) and then fed back to the reference VCO circuit (Q0, D0). The detected signal output from the PLL IC (pin ) is converted into a DC voltage (lock voltage) at the loop filter and then fed back to one of the VCO circuits (Q, D, L). The oscillated signal from the buffer amplifier (Q0) is also applied to the MAIN unit as a st LO signal after being amplified at LO (Q0) and buffer (Q0) amplifiers or passed through the bandpass filter (L0 L0, C0 C). -- ND LO AND ERENCE OSCILLATOR CIRCUITS (PLL UNIT) The reference oscillator (X;, X; [OTH]) generates a.0 MHz frequency for the DDS circuits as a system clock and for the LO output. The oscillated signal is doubled at the doubler circuit (Q0) and the.0 MHz frequency is picked up at the double tuned filter (L0, L0). The.0 MHz signal is applied to the RF circuit as a nd LO signal. -- RD LO CIRCUIT (PLL UNIT) The DDS IC (IC0) generates a 0-bit digital signal using the MHz system clock. The digital signal is converted into an analog wave signal at the D/A converter (R0 R0). The converted analog wave is passed through the bandpass filter (L L, C C) and then applied to the MAIN unit as the rd LO signal (.000 khz) via the attenuator (R R). () MAIN LOOP PLL The oscillated signal at one of the main loop VCOs (Q, D, L) is amplified at the buffer amplifiers (Q0, Q0) and is then applied to the PLL IC (IC0, pin ). The signal is then divided and detected on phase with the reference loop output frequency. PLL CIRCUIT PLL IC (IC0) Programmable divider DDS IC (IC0) Phase detector Programmable divider D/A convertor Phase detector Programmable divider Programmable divider DDS MAIN loop VCO Q0 Loop filter Buff Loop filter AMP. Q LO Q, D, L Q0 Buff Reference loop VCO Q0, D0 Q0 Doubler Q0 LO Q0 DDS DDS Q0 DDS IC0 Q0 Buff Buff Q D/A convertor LO Q st LO ( MHz) nd LO ( MHz) DSC nd LO (0.0 MHz) only DSC st LO (..0 MHz) only rd LO ( khz) Reference OSC. ( MHz) X; X; [OTH] -

13 - DSC CIRCUITS ( ONLY) -- DSC BANDPASS FILTER AND RF AMPLIFIER CIRCUITS (MAIN UNIT) The RF circuit filters out-of-band signals and amplifiers signals within the range of frequency coverage. () MHz signals The signals from the antenna connector (J0) pass through the bandpass filter (L0, L0, L0, L0, L, L, L, L0, L, L, L, C0, C0, C0, C0, C, C, C, C, C, C, C, C0) to obtain desired MHz signals and suppress any undesired signals. () MHz signals The signals from the antenna connector (J0) pass through the bandpass filter (L0, L0, L, L, L, L, L, L, L, C0, C0, C0, C0, C, C, C, C0, C, C, C, C) to obtain desired MHz signals and suppress any undesired signals. () MHz signals The signals from the antenna connector (J0) pass through the bandpass filter (L L, L, L, C, C, C, C, C C0, C C, C, C) to obtain desired MHz signals and suppress any undesired signals. () MHz signals The signals from the antenna connector (J0) pass through the bandpass filter (L0, L0, L0, L, L, L, L, L, L0, L, C0, C0, C0, C, C, C, C, C, C, C, C, C) to obtain desired MHz signals and suppress any undesired signals. The filtered signals are amplified at the RF amplifiers (Q0, Q0), and then applied to the st mixer circuit (D0). -- DSC ST MIXER AND ST IF CIRCUITS (MAIN UNIT) The st mixer circuit converts the received signal into a fixed frequency of the st IF signal with a PLL output frequency. By changing the PLL frequency, only the desired frequency will pass through a crystal filter at the next stage of the st mixer. The signals from the RF circuit are mixed at the st mixer (D0) with a st LO signal coming from the PLL circuit to produce a 0. MHz st IF signal. The st IF signal is applied to the crystal bandpass filters (FI) to suppress out-of-band signals. The filtered st IF signal is amplified at the st IF amplifiers (Q0, Q0), then applied to the nd mixer circuit (IC0, pin ). -- DSC ND IF AND DSP CIRCUITS (MAIN AND DSP UNITS) The nd mixer circuit converts the st signal into a nd IF signal. A double conversion superheterodyne system (which converts receive signals twice) improves the image rejection ratio and obtain stable receiver gain. The st IF signal from the st IF amplifiers is applied to the nd mixer IC (IC0, pin ), and is mixed with the nd LO signal to the converted into a khz nd IF signal. The khz nd IF signal from the nd mixer (IC0, pin ) is applied to the nd IF amplifier (IC0, pin ), and then passes through the low-pass filter (IC0, pins, ). The signal is applied to the DSP unit as the DSPI signal. The signal is amplified at the differential amplifier (DSP unit; IC0), and is then applied to the A/D converter secition in the CODEC IC (DSP unit; IC0). At the same time, the converted signal is level-shifted V to. V in the IC (DSP unit; IC0). The level-shifted signal is applied to the DSP IC (DSP unit; IC0) for the digital IF filter, demodulator and noise reduction, etc. The output signal from the DSP IC is applied to the D/A converter section in the CODEC IC (DSP unit; IC0) to convert into the analog audio signals. Also the signals are level-shifted. V to V at the level converter section in the IC. The level-shifted audio signals are passed through the active filter (IC0b), and then applied to the MAIN unit via the J0 (pin ) as the DSPO signal. -- DSC AGC CIRCUIT (DSP AND MAIN UNITS) The receiver gain is determined by the voltage on the AGC line from the DSP unit. The D/A converter for the AGC (IC0) supplies control voltage to the AGC line and sets the DSC receiver gain. The rd IF signal from the CODEC IC (IC0) is detected at the AGC detector section in the DSP IC (IC0). The output signal from the DSP IC is level-shifted at the level converter (IC0) and applied to the D/A converter (IC0). The AGC voltage is amplified at the buffer amplifier section in the IC0 and applied to the MAIN unit to control the AGC line. When receiving strong signals, the detected voltage increases and the AGC voltage decreases. As the AGC voltage is used for the bias voltage of the IF amplifiers (MAIN unit; Q0, Q0), IF amplifier gain is decreased. - FRONT UNIT (RC-) -- LCD CIRCUIT (DISPLAY AND CONNECT BOARDS) The LCD (CONNECT board; DS0) is controlled by the LCD driver (CONNECT board; IC0) via the drive signals (CL, RES, CS, RS, WR, RD, DB0 DB) from the display board. The LCD s back light employs LED (DS00 DS). The LED are controlled by dimmer (Q00, Q0) and dimmer controller (IC0) circuits. -- MICROPHONE CIRCUIT (DISPLAY BOARD) The AF signals from the microphone are amplified at the AF amplifier (IC0) via the MIC signal. The signal is applied to the IC-M0 s main unit through the J0 via the MI signal. -

14 -- GROUP AND CHANNEL DIALS CIRCUIT (DISPLAY AND SENSOR BOARDS) GROUP DIAL The signals from the group dial (SENSOR board; S0) is applied to the FRONT CPU (IC0, pins, ) via the GPA and GPB signals. CHANNEL DIAL The signals from the channel dial (SENSOR board; S0) is applied to the FRONT CPU (IC0, pins, ) via the CHA and CHB signals. -- KEY S BACK LIGHTS CIRCUIT (DISPLAY BOARD) The key s back lights compose DS0 DS0, and are controlled by the dimmer circuit (Q0 Q). The dimmer circuit is controlled by the CPU via the DIMMER signal from the FRONT CPU. -- RESET CIRCUIT (DISPLAY BOARD) The reset IC (IC0) resets the FRONT CPU (IC0) when IC-M0 is power ON or OFF. - POWER SUPPLY CIRCUITS -- PA UNIT VOLTAGE LINE LINE HV HV SV PAV PAT The voltage from an external power supply. The same voltage as the HV line passed through the fuse (F0). The same voltage as the HV line passes through the switching relay (RL0). V for transmitter circuits regulated by the + regulator circuit (IC0). V for transmitter circuits regulated by the T regulator circuit (Q0, Q0). -- PLL UNIT VOLTAGE LINE LINE HV HV V VL The voltage from PA and MAIN units via the J00. Common V line from the MAIN unit via the J0. Common V converted from the V line and regulated by the + regulator circuit (IC00). Common V converted from the V line and regulated by the + regulator circuit (IC0). -- MAIN UNIT VOLTAGE LINE LINE SV RV V V T R V HV The voltage from the PA unit via the J0. Receive V converted from the SV line and regulated by the R regulator circuit (IC0). Common V converted from the V line and regulated by the + regulator circuit (IC0). Common V converted from the V line and regulated by the V DC-DC converter (IC, D, D) Transmit V converted from the SV line and regulated by the T regulator circuit (Q0). Receive V converted from the SV line and regulated by the R regulator circuit (Q0). Common V converted from the V line and regulated by the + regulator circuit (IC0). Common V converted from the V line and regulated by the + regulator circuit (IC0). -- DISPLAY BOARD (RC-) VOLTAGE LINE LINE HV 0V V The voltage from PA and MAIN units via the J0. Common 0 V converted from the V line and regulated by the +0 regulator circuit (IC0). Common V converted from the V line and regulated by the + regulator circuit (IC0). -

15 - PORT ALLOCATIONS -- MAIN CPU (MAIN UNIT; IC0) Pin number 0 0 Port name TXS RXS PSEL BEEP PDAT PCK UNLK PWRS DRES STBO RQO RQI DO NMEI NMEO NMEI LSTB DSTB LCK LDAT MSTB PSTB SQLC STAT KEYS EDT Description Outputs T regulator circuit (MAIN unit; Q0) control signal. Outputs R regulator circuit (MAIN unit; Q0) control signal. Outputs serial strobe signal to the latch control IC (IC0, pin ). Outputs beep audio signals. Outputs serial data signal for the PLL circuits. Outputs serial clock signal for the PLL circuit. Input port for PLL unlock signal. Outputs switching relay (PA unit; RL0) control signal. Outputs the RESET signal. Outputs strobe signal for the DSP unit. Outputs data signal for the DSP unit. Outputs serial data signal for the DSP unit. Input port for the serial data signal from the DSP unit. Input port for the NMEA signal. Outputs NMEA signal for PLL unit. Input port for the GPS signal from the PLL unit. Outputs serial strobe signal for the IC0, IC0. Outputs strobe signal for the D/A converter IC (IC0). Outputs serial clock signal for IC0 IC0, D/A converter IC (IC0) and DSP unit. Outputs serial data signal for the IC0, IC0 and D/A converter IC (IC0). Outputs serial strobe signal for the IC0, IC0. Outputs PLL strobe control signal for the LATCH controller (IC0). Outputs squelch control signal for the SQL switching IC (IC0). Outputs the optional antenna tuner start control signal for the PA unit via the J0. Input port for the optional antenna tuner key control signal via the PA unit. I/O port for the serial data signals from/to the EEPROM (IC0, pin ). MAIN CPU (MAIN UNIT; IC0) continued Pin number 0 Port name ECK ASEN TEMP NSEN RFML Description Outputs serial clock signal for the EEPROM (IC0, pin ). Input port for the SEND signal from the accessory connector (J0). Input port for the power amplifier temperature signal from the PA unit. Input port for the SEND signal from the AF/MOD connector (PLL unit; J0, pin ) via the J0. Input port for the RF/ANTC meter s voltage from the meter amplifier (IC0, pin ). -- OUTPUT EXPANDER IC FOR THE PLL STROBE (IC0) Pin number Port name PST PST PST PST PST Description Outputs strobe signal for the DDS IC (PLL unit; IC0, pin ). Outputs strobe signal for the PLL IC (PLL unit; IC0, pins ). Outputs strobe signal for the DDS IC (PLL unit; IC0, pin ). Outputs strobe signal for the DDS IC (PLL unit; IC0, pin ). Outputs strobe signal for the DDS IC (PLL unit; IC0, pin ). -- OUTPUT EXPANDER IC FOR THE FILTER UNIT (IC0) Pin number Port name L0S LS LS LS LS LS LS LS Description Outputs 0.. MHz low-pass filter control signal. Outputs. MHz low-pass filter control signal. Outputs. MHz low-pass filter control singnal. Outputs. MHz low-pass filter control signal. Outputs 0 0 MHz low-pass filter control signal. Outputs. MHz low-pass filter control signal. Outputs 0. MHz low-pass filter control signal. Outputs. MHz low-pass filter control signal. -

16 -- OUTPUT EXPANDER IC FOR BANDPASS FIL- TERS (IC0) Pin number Port name B0S BS BS BS BS BS BS BS Description Outputs 0.. MHz bandpass filter control signal. Outputs. MHz bandpass filter control signal. Outputs. MHz bandpass filter control singnal. Outputs. MHz bandpass filter control signal. Outputs. MHz bandpass filter control signal. Outputs. MHz bandpass filter control signal. Outputs 0. MHz bandpass filter control signal. Outputs. MHz bandpass filter control signal. -- D/A CONVERTER IC (IC0) Pin number Port name POCV AFG FANS TRXS Description Outputs transmit power control signal. The signal is applied to the ALC amplifier (IC0, pin ) and RF amplifier (Q0). Outputs the VCA control signal. The signal is applied to the VCA amplifier (IC0, pin ) and RC- controller via the J0, pin. Outputs the cooling fan control signal. The signal is applied to the fan controller (PA unit; IC0, Q0). Outputs the transmitter/receiver switching signal. The signal is applied to the switching relay circuit (FILTER unit; RL0). -- OUTPUT EXPANDER IC (IC0) Pin number Port name NMS EMS MMS NMRS AFMS CSEN Description Outputs NBDP MOD control signal for the gate mod IC (IC00, pin 0). Outputs external MOD control signal for the gate mode IC (IC00, pin ). Outputs microphone MOD control signal for the gate mode IC (IC00, pin ). Outputs NMEA/RS-C switching singnal. Outputs AF mute control signal. Outputs SEND control signal for the buffer amplifier (IC0, pin ). -- OUTPUT EXPANDER IC (IC0) Pin number Port name BS DBP DBP DBP DBP Description Outputs 0 MHz bandpass filter control signal. Outputs bandpass filter control signal for DSC circuit (For.,.0,.0 MHz). Outputs bandpass filter control signal for the DSC circuit (. MHz). Outputs bandpass filter control signal for the DSC circuit (.0 MHz). Outputs bandpass filter control signal for the DSC circuit (.0 MHz). - 0

17 -- FRONT CPU PORT ALLOCATIONS (RC-, DISPLAY BOARD; IC0) Pin number 0 0 Port name DSEL FUNK TXK RXK FCHK T0K ENTK PWRK PMUT FPTT AFGL MAD MAD MAD CL RS RD WR RES CS DB DB0 TK TK TK TK TK TK TK TK TK EMLK SETK MODK TUNK DALK CSCK DSTK Description Outputs DISTRESS LED control signal. Input port for the O switch. Input port for the [TX] switch. Input port for the [RX] switch. Input port for the [FREQ/CH] switch. Input port for the [0] switch. Input port for the [ENT] switch. Input port for the [POWER] switch. Input port for the phone plug insert detection signal. Input port for the [PTT] switch from the microphone connector (J0, pin ). Input port for the AF volume control. Input port for the using microphone detection signal. Input port for the switch signal on the microphone. Input port for the microphone connecting detection. Output LCD drive signals. Output LCD drive signals. Input port for the [] switch. Input port for the [] swtich. Input port for the [] swtich. Input port for the [] switch. Input port for the [] switch. Input port for the [] switch. Input port for the [] switch. Input port for the [] switch. Input port for the [] switch. Input port for [ ]/[dsc]/[ts] switches. Input port for the [SET] switch. Input port for the [MODE] switch. Input port for the [TUNE] switch. Input port for [CANCEL]/[TELCALL]/ [TXF] switches. Input port for [DSC]/[CALL]/[CH0]/ [SELCALL] switches. Input port for the [DISTRESS]/[CALL]/ [ALM] switches. -

18 SECTION ADJUSTMENT PROCEDURES - PREPARATION When adjusting the contents on page -, a JIG CABLE (see illustration as shown below) is required. Some adjustments must be performed on the ADJUSTMENT MODE. Entering the ADJUSTMENT MODE, see the next page. REQUIRED TEST EQUIPMENT EQUIPMENT GRADE AND RANGE EQUIPMENT GRADE AND RANGE DC power supply Output voltage Current capacity :. V DC : 0 A or more Audio generator Frequency range Output level : Hz : 00 mv RF power meter (terminated type) Frequency counter Measuring range : 00 W Frequency range : 0. 0 MHz Impedance : 0 Ω SWR : Less than. : Frequency range : 00 MHz Frequency accuracy : ± ppm or better Sensitivity : 00 mv or better Attenuator Standard signal generator (SSG) DC voltmeter Power attenuation Capacity Frequency range Output level Input impedance : 0 or 0 db : 00 W or more : 0. 0 MHz : µv mv ( to dbm) : 0 kω/v DC or better FM deviation meter Frequency range Measuring range : DC 00 MHz : 0 to ± khz Oscilloscope Frequency range Measuring range : DC 0 MHz : V Digital multimeter Input impedance : 0 MΩ/V DC or better AC millivoltmeter Measuring range : 0 mv 0 V CONNECTION Standard signal generator CAUTION! DO NOT transmit while an SSG is connected to the antenna connector. DC power supply Distortion meter Ammeter to antenna connector / to antenna connector Attenuator Modulation analyzer Spectrum scope RF power meter Speaker [MIC] connector + _ to [SP] to [CONTROLLER] -

19 ENTERING THE ADJUSTMENT MODE Turn the power OFF. Push and hold the HM- s [DOWN] key, [TX] and [RX] buttons, then turn the power ON. NOTE: Inserting the kω resistor between pin and pin of HM- works same as pushing and holding HM- s [DOWN] key (See the illustration on page -). [DOWN] key [TX] [RX] Connect to [MIC] connector. [POWER] OPERATING ON THE ADJUSTMENT MODE Enter the TX adjustment from the MAIN menu. Enter the RX adjustment from the MAIN menu. Enter the DSC adjustment from the MAIN menu. Change the next adjustment item. Return to the pre-adjustment item. [] [] [] : Push the [] button : Push the [] button : Push the [] button (except [OTH]) : Push the [0] button : Push the [CE] button *** ADJUST MODE *** RX JE *** ADJUST MODE *** []TX [] RX []DSC TX RX [CANCEL] BACK TO HERE DSC Main menu Push [] Push [] Push [] SET TX adjustment menu *** ADJUST MODE *** RX JE RX TOTAL GAIN (.) SET RX adjustment menu *** ADJUST MODE *** RX JE DSC ADJUSTMENT. FRQ SET DSC adjustment menu TX ADJUSTMENT ITEM CHANGING [] [0] [0] [0] [0] [0] MAIN menu TX set TX gain TX power (High) TX power (Middle) TX power (Low) [CE] [CE] [CE] [CE] [CE] [CE] TX tune power RX ADJUSTMENT ITEM CHANGING [] [0] [0] MAIN RX total S level menu gain zero [CE] [CE] [CE] S level DSC ADJUSTMENT ITEM CHANGING [] [0] [0] MAIN DSC *DSC menu adjustment demodulation [CE] [CE] [CE] DSC self check *NOTE: DO NOT adjust the DSC DEMODULATION. Thus, after adjusting the DSC adjustment, push the [0] button twice to skip it. -

20 - PLL UNIT ADJUSTMENT ADJUSTMENT ADJUSTMENT CONDITIONS UNIT MEASUREMENT LOCATION VALUE ADJUSTMENT UNIT ADJUST LPL LOCK VOLTAGE Operating frequency : MHz Mode : JE Receiving Operating frequency : 0. MHz Receiving PLL Connect a digital multi meter or oscilloscope to check point CP0..0 V Less than.0 V PLL C0 Verify HPL LOCK VOLTAGE Operating frequency :. MHz Mode : JE Receiving Operating frequency : MHz Receiving PLL Connect a digital multi meter or oscilloscope to check point CP0.. V More than 0. V PLL C Verify ERENCE FREQUENCY Wait for minutes after power ON. Terminate P0 on the PLL unit to ground with a 0 Ω resister. Receiving PLL Connect an RF voltmeter to check point P0. Maximum level PLL L0, L0 Connect a frequency counter to check point P0..0 MHz () MHz ([OTH]) X ([USA], [CAN]) C ([OTH]) -

21 IC-M0 BOTTOM VIEW PLL unit PLL UNIT TOP VIEW L0 L0 LPL lock voltage adjustment C Reference frequency adjustment (OTH) X Reference frequency adjustment (USA, CAN) C HPL lock voltage adjustment C0 LPL lock voltage adjustment CP0 HPL lock voltage check point P0 Reference frequency check point CP0 LPL lock voltage check point -

22 - PA AND FILTER UNITS ADJUSTMENT ADJUSTMENT ADJUSTMENT CONDITIONS UNIT MEASUREMENT LOCATION VALUE ADJUSTMENT UNIT ADJUST IDLING CURRENT (For drive FETs) Operating frequency :.0 MHz Mode : JE Apply no audio signal to the [MICRO- PHONE] connector. Disconnect J0. Preset R0 and R on the PA unit to max. counter clockwise. Connect a dummy load or RF power meter to the [ANT] connector. Transmitting Rear panel Connect an ammeter (0 A) between an external power supply and the transceiver..0 A PA R0 (For final transistors) Transmitting 0. A R After adjustment, connect J0 to the PA unit. SWR DETECTOR Operating frequency :.0000 MHz Mode : JE Connect the CP (FOR line) on the FILTER unit to ground. Connect an audio generator to the [MICROPHONE] connector and set as: Frequency :. khz Transmitting Rear panel FIL- TER Connect an RF power meter to the [ANT] connector. Connect a DC voltmeter to check point, CP. 0 W Minimum level Audio generator FIL- TER Output level C After adjustment, disconnect CP (FOR line) on the FILTER unit from ground. -

23 IC-M0 TOP VIEW R Idling current adjustment (For final transistors) R0 Idling current adjustment (For drive FETs) FILTER UNIT BOTTOM VIEW IC-M0 BOTTOM VIEW FILTER unit CP ( line) SWR detector check point CP (FOR line) Connect to ground C SWR detector adjustment -

24 - RECEIVER ADJUSTMENTS TOTAL GAIN, S-METER and DSC PEAK adjustments must be performed at ADJUSTMENT MODE. ADJUSTMENT ADJUSTMENT CONDITIONS UNIT MEASUREMENT LOCATION VALUE ADJUSTMENT UNIT ADJUST NOISE NULL POINT RECEIVER GAIN TOTAL GAIN S-METER DSC PEAK ([USA],[CAN] only) DSC SELF CHECK ([USA],[CAN] only) Operating frequency : 0. MHz Mode : HE Preset L0 and L0 to max. clockwise. Preset L0, L0, L0 and L0 to max. counter clockwise. Set the standard signal generator to OFF (no signal output). Receiving Operating frequency :.0 MHz Mode : JE Connect a standard signal generator to the [ANT] connector and set as: Frequency :.0 MHz Level : 0. µv* ( dbm) Modulation : OFF Receiving While pushing HM- s DOWN key, [TX] and [RX] switches, then turn power ON. Push [] swtich to enter the RX adjustment mode. Connect a standard signal generator to the [ANT] connector and set as: Frequency :.0 MHz Level : 0 µv* ( dbm) Modulation : OFF Receiving Set the standard signal generator to OFF (no signal output). Set the standard signal generator as: Frequency :.0 MHz Level : 0 mv* ( dbm) Receiving Push [] switch to enter the DSC adjustment mode. LCD displayed : DSC ADJUSTMENT. DSC frequency :. MHz Connect a standard signal generator to the [DSC ANT] connector and set as: Frequency :. MHz Level : 0. µv* ( dbm) Modulation : OFF Receiving LCD displayed : DSC SELF CHECK DSC frequency :. MHz Connect an RF power meter to the [DSC ANT] connector on the rear panel. Receiving Front panel Front panel Front panel Connect an AC millivoltmeter to the [SP] jack with a Ω dummy load. Connect an AC millivoltmeter to the [SP] jack with a Ω dummy load. Connect an AC millivoltmeter to the [SP] jack with a Ω dummy load. Minimum output level Maximum output level Maximum output level MAIN MAIN MAIN L0 L0, L0, L0, L0, L0, L0 Push the [ENT] switch to write the adjustment value in the memory. Push the [ENT] switch to write the adjustment value in the memory. Push the [ENT] switch to write the adjustment value in the memory. L0, L0 Push the [ENT] switch, and then verify to return to the Main menu on the LCD display. When this check is failure, displayed NG on LCD, and beep sound. *The output level of the standard signal generator (SSG) is indicated as the SSG s open circuit. -

25 IC-M0 TOP VIEW L0 L0 L0 L0 L0 L0 Receiver gain adjustment L0 L0 DSC peak adjustment L0 Noise null point adjustment RC- FRONT PANEL [ENT] -

26 - TRANSMITTER ADJUSTMENTS The following adjustments must be performed at ADJUSTMENT MODE after SWR DETECTOR and RECEIVER ADJUST- MENTS in the SECTION - and -. ADJUSTMENT ADJUSTMENT CONDITIONS UNIT MEASUREMENT LOCATION VALUE ADJUSTMENT UNIT ADJUST TRANSMIT PEAK AND TOTAL GAIN (TX PEAK) While pushing HM- s DOWN key, [TX] and [RX] switches, turn power ON. Connect an audio generator to the [MICROPHONE] connector and set as: Frequency :. khz Level : 0 mv Push [] swtich to enter the TX adjustment mode (LCD displayed: TX SET ). Push [ENT] switch, then the transceiver is transmitting. Rear panel Connect an RF power meter to the [ANT] connector. Maximum output power MAIN L0 (TOTAL GAIN) After setting W, push the [ENT] key to write the adjustment value in the memory. W RC- [CH] DIAL TX POWER (HIGH) LCD displayed : TX POWER HIGH Set the audio generator as: Frequency :. khz Level : 00 mv Rear panel Connect an RF power meter to the [ANT] connector. 0 W RC- [CH] DIAL After setting 0 W, push the [ENT] key to write the adjustment value in the memory. (MIDDLE) LCD displayed : TX POWER MID Set the audio generator as: Frequency :. khz Level : 00 mv Rear panel Connect an RF power meter to the [ANT] connector. 0 W RC- [CH] DIAL After setting 0 W, push the [ENT] key to write the adjustment value in the memory. (LOW) LCD displayed : TX POWER LOW Set the audio generator as: Frequency :. khz Level : 00 mv Rear panel Connect an RF power meter to the [ANT] connector. 0 W RC- [CH] DIAL After setting 0 W, push the [ENT] key to write the adjustment value in the memory. TUNE POWER LCD displayed : TX POWER TUNE Set the audio generator as: Frequency :. khz Level : 00 mv Rear panel Connect an RF power meter to the [ANT] connector. 0 W RC- [CH] DIAL After setting 0 W, push the [ENT] key to write the adjustment value in the memory. AM CARRI- ER POWER ([OTH] only) LCD displayed : TX POWER HE Set the audio generator as: Frequency :. khz Level : OFF Rear panel Connect an RF power meter to the [ANT] connector. W RC- [CH] DIAL After setting W, push the [ENT] key to write the adjustment value in the memory. -

27 TRANSMITTER ADJUSTMENTS(CONTINUE) ADJUSTMENT ADJUSTMENT CONDITIONS UNIT MEASUREMENT LOCATION VALUE ADJUSTMENT UNIT ADJUST IC-APC Operating frequency :.0 MHz Mode : JE Set the audio generator as: Frequency :. khz Level : 00 mv Preset R on the PA unit to center position. Connect the J0 pin (FOR line) on the MAIN unit to ground. Transmitting Rear panel Connect an ammeter (0 A) between an external power supply and the transceiver. After adjustment, disconnect J0 pin (FOR line) on the MAIN unit from ground.. A PA R IC-M0 TOP VIEW L0 Transmit peak and total gain adjustment J0 pin Connect to ground when adjusting IC-APC R Ic-APC adjustment RC- FRONT PANEL [ENT] [CH] - 0

28 SECTION PARTS LIST - IC-M0 [MAIN UNIT] IC S.IC µpc0t-e IC S.IC TA0F (TEL) IC S.IC TA0F (TEL) IC S.IC TCWFU (TEL) IC S.IC TSIDT IC S.IC TSIDT IC S.IC TSIDT IC S.IC NJM0AV-TE IC S.IC TDAF (TP) IC S.IC TDAF (TP) IC S.IC TDAF (TP) IC S.IC TAL0F (TER) IC S.IC TAM0F (TEL) IC S.IC µpcg-t IC IC LAA IC S.IC TCWFU (TEL) IC S.IC MFP 0CD IC S.IC TCWFU (TEL) IC S.IC TSIDT IC S.IC TCWFU (TEL) IC S.IC BU0BCFV-E IC S.IC TA0F (TEL) IC S.IC TSIDT IC S.IC TAL0F (TER) IC S.IC TCW0F (TEL) IC0 000 S.IC CATWCJ-TE [OTH] 0000 S.IC HNXFPI IC S.IC S-0CNMC-GC-T [OTH], [CAN] 0000 S.IC S-0ANMP-DD-T [USA] IC S.IC M00FCAFP [OTH] 000 S.IC M0FGAFP D IC S.IC BU0BCF-E IC S.IC BU0BCF-E IC S.IC BU0BCF-E IC S.IC BU0BCF-E IC S.IC BU0BCF-E IC S.IC MGP EC Q S.TRANSISTOR SC-B (TER) Q S.FET SK--TD Q S.FET SK--TD Q S.FET SK-T MAS Q S.FET SK-T MAS Q S.FET SK-T MAS Q S.TRANSISTOR SCD-TD Q S.FET SK-T MAS Q S.FET SK-T MAS Q S.FET SK-T MAS Q S.FET SK-T MAS Q S.TRANSISTOR SA-GR (TER) Q S.TRANSISTOR SA-GR (TER) Q S.TRANSISTOR SC-B (TER) Q S.TRANSISTOR SC-B (TER) [OTH] Q S.TRANSISTOR SA-GR (TER) [OTH] Q S.TRANSISTOR SD-T-TD Q S.TRANSISTOR SD-T-TD Q S.TRANSISTOR DTCEUA T0 Q S.TRANSISTOR DTCEUA T0 Q S.TRANSISTOR DTCEUA T0 Q S.TRANSISTOR SD-T-TD Q S.TRANSISTOR DTCEUA T0 Q S.TRANSISTOR SC-GR (TER) Q S.FET SK--TD Q S.FET SK--TD Q S.FET SK-T MAS Q S.FET SK-T MAS Q S.TRANSISTOR DTCEUA T0 Q S.TRANSISTOR SC-GR (TER) D S.DIODE UMF/TR D S.DIODE UMF/TR [MAIN UNIT] D 0000 S.DIODE MA0WK-(TX) D S.DIODE MA0WK-(TX) D S.DIODE MA0WK-(TX) D S.DIODE MA0WK-(TX) D S.DIODE MA0WK-(TX) D S.DIODE MA (TX) D S.DIODE MA0WK-(TX) D S.DIODE MA0WK-(TX) D S.DIODE MA0WK-(TX) D S.DIODE MA0WK-(TX) D S.DIODE MA (TX) D S.DIODE MA0WK-(TX) D S.DIODE MA0WK-(TX) D S.DIODE HSBWSTR D S.DIODE MA0WK-(TX) D S.DIODE MA (TX) D S.DIODE MA (TX) D S.DIODE MA (TX) D S.DIODE MA (TX) D S.ZENER MA0-M (TX) D S.DIODE MA0WK-(TX) D S.DIODE MA0WK-(TX) D S.DIODE MAS-(TX) D S.DIODE MAS-(TX) D S.DIODE MAS-(TX) D S.DIODE MAS-(TX) D S.DIODE MAS-(TX) D S.DIODE MAS-(TX) D S.DIODE MA (TX) D S.DIODE MAS-(TX) D S.DIODE RB0F-0T0 D S.DIODE RB0F-0T0 D 0000 S.ZENER MA0-M (TX) D 0000 S.DIODE RB0F-0T0 D 0000 S.ZENER MA0-M (TX) D S.DIODE MAS-(TX) D S.DIODE MAS-(TX) D S.DIODE MAS-(TX) D S.DIODE UMF/TR D S.DIODE UMF/TR D S.DIODE MA0WK-(TX) D S.DIODE MA0WK-(TX) D S.DIODE MA0WK-(TX) D S.DIODE MA0WK-(TX) D S.DIODE HSBWSTR D S.DIODE RB0F-0T0 D S.DIODE RB0F-0T0 D S.DIODE RB0F-0T0 D S.DIODE MAS-(TX) D S.DIODE RB0F-0T0 D S.DIODE RB0F-0T0 D S.DIODE MAS-(TX) D S.DIODE MAS-(TX) D 0000 S.DIODE MAS-(TX) D 0000 S.DIODE MAS-(TX) FI XTAL FL- (. MHz) FI MONOLITH FL- (0.00 MHz) FI XTAL FL- (.00 MHz) FI CERAMIC CFWLBKHFA-B0 (CFWMH) FI CERAMIC CFWLAKHFA-B0 (CFWSHT) X S.XTAL CR-A (. MHz) L S.COIL NL 0T-RJ L S.COIL NL 0T-RJ L S.COIL NL 0T-RJ L S.COIL NL 0T-RJ L S.COIL NL 0T-0J L S.COIL NL 0T-RJ L S.COIL NL 0T-0J S.=Surface mount -