SERVICE MANUAL. HF/ 50MHz ALL MODE TRANSCEIVER i703

Transcript

1 SERVICE MANUAL HF/ 0MHz ALL MODE TRANSCEIVER i0

2 INTRODUCTION This service manual describes the latest service information for the IC0 HF/0MHz ALL MODE TRANSCEIVER. MODEL IC0 VERSION Europe France Spain U.S.A. Korea Other Italy SYMBOL UT0 option UT0 equipped EUR EUR FRA FRA ESP ESP USA USA KOR KOR OTH OTH ITR ITR DANGER NEVER connect the transceiver to an AC outlet or to a DC power supply that uses more than V. This will ruin the transceiver. DO NOT expose the transceiver to rain, snow or any liquids. DO NOT reverse the polarities of the power supply when connecting the transceiver. DO NOT apply an RF signal of more than 0 dbm (00 mw) to the antenna connector. This could damage the transceiver s front end. To upgrade quality, any electrical or mechanical parts and internal circuits are subject to change without notice or obligation. ORDERING PARTS Be sure to include the following four points when ordering replacement parts:. 0digit order numbers. Component part number and name. Equipment model name and unit name. Quantity required <SAMPLE ORDER> S.IC µpc09t IC0 MAIN UNIT pieces Screw FH M. ZKIC0 Top cover 0 pieces Addresses are provided on the inside back cover for your convenience. REPAIR NOTES. Make sure a problem is internal before disassembling the transceiver.. DO NOT open the transceiver until the transceiver is disconnected from its power source.. DO NOT force any of the variable components. Turn them slowly and smoothly.. DO NOT short any circuits or electronic parts. An insulated tuning tool MUST be used for all adjustments.. DO NOT keep power ON for a long time when the transceiver is defective.. DO NOT transmit power into a signal generator or a sweep generator.. ALWAYS connect a 0 db to 0 db attenuator between the transceiver and a deviation meter or spectrum analyzer when using such test equipment.. READ the instructions of test equipment thoroughly before connecting equipment to the transceiver.

3 TABLE OF CONTENTS SECTION SPECIFICATIONS SECTION INSIDE VIEWS SECTION CIRCUIT RECEIVER CIRCUITS TRANSMITTER CIRCUITS PLL CIRCUITS ANTENNA TUNER CIRCUITS POWER SUPPLY CIRCUITS CPU PORT ALLOCATIONS SECTION ADJUSTMENT PROCEDURES PREPARATION BEFORE SERVICING PLL ADJUSTMENTS TRANSMITTER ADJUSTMENTS RECEIVER ADJUSTMENTS SET MODE ADJUSTMENTS (No.) PA UNIT ADJUSTMENTS SET MODE ADJUSTMENTS (No.) SECTION PARTS LIST SECTION MECHANICAL PARTS SECTION SEMICONDUCTOR INFORMATION SECTION BOARD LAYOUTS DISPLAY BOARD JACK BOARD VR BOARD MAIN UNIT PA UNIT SECTION 9 BLOCK DIAGRAM SECTION 0 WIRING DIAGRAM SECTION VOLTAGE DIAGRAMS FRONT UNIT MAIN UNIT PA UNIT

4 SECTION SPECIFICATIONS GENERAL Frequency coverage : Receive MHz* Transmit MHz* MHz* MHz* 00 0 MHz MHz.0. MHz MHz MHz MHz MHz* *Depending on version. Mode : USB, LSB, CW, RTTY (FSK), AM, FM Number of memory ch. : 0 (99 regular, scan edges) Antenna connector : SO9/0 Ω(at antenna tuner off) Power supply requirement :. V DC ±% (negative ground) Frequency stability : Temp. fluctuations 0 C to 0 C ( F to F) Less than ± 0. ppm. Temp. fluctuations 0 C to 0 C ( F to 0 F) Less than ±. ppm. Frequency resolution : General 0 khz shift Automatic 0 khz shifit Fine Less than Hz shift Current consumption : Transmit 0 W :.0 A (at. V DC) W :.0 A (at 9. V DC) Receive Standby : 00 ma (at 9. V DC) AF output : 0 ma (at 9. V DC)* AF output :. A (at. V DC)* * with 0 % distortion Usable temperature range : 0 C to 0 C ( F to 0 F) Dimensions : (W) (H) 00(D) mm (projections not included) 9 (W) 9 (H) (D) inch Weight :.0 kg ( lb oz) CIV connector : conductor. (d) mm ( /")/ Ω ACC connector : pin RECEIVER Receive system : Double superheterodyne Intermediate frequencies : st IF;. khz, nd IF; khz Receive sensitivity : (Preamp. is ON.) FREQUEY 0.. MHz. MHz* MHz 0 MHz band SSB/CW/RTTY µv µv µv AM µv* µv µv µv Note: SSB, CW and AM modes are measured at 0 db S/N. FM mode are measured at db SINAD. * Except. MHz, 9 MHz. * Preamp. is OFF. Squelch Sensitivity : (Preamp. is ON.) AM, SSB, CW, RTTY Less than. µv FM Less than 0. µv Selectivity* (Typical) : SSB, CW, RTTY More than. khz/ db Less than.0 khz/ 0 db AM, FMN More than 9.0 khz/ db Less than 0 khz/ 0 db FM More than khz/ db Less than 0 khz/ 0 db *Without an optional filter unit and with mid bandwidth selected. FM 0. µv 0. µv Spurious and image rejection ratio: HF band More than 0 db 0 MHz band More than db (except IF through) Audio output power : More than.0 W at 0% distortion with an Ω load,. V DC More than.0 W at 0% distortion with an Ω load, 9. V DC RIT variable range : ± 9.99 khz PHONES connector : conductor. (d) mm ( /")/ Ω EXT SP connector : conductor. (d) mm ( /")/ Ω TRANSMITTER Output power :. 0 MHz band SSB/CW/RTTY/FM 0 W* W* AM W* W* * at. V DC power supply, * at 9. V DC power supply Modulation system : SSB Balanced modulation AM Low level modulation FM Variable reactance modulation Spurious emissions : Below 0 MHz Less than 0 db Above 0 MHz Less than 0 db Carrier suppression : More than 0 db Unwanted sideband supp. : More than 0 db Microphone connector : pin modular jack (00 Ω) KEY connector : conductor. (d) mm ( /") RTTY connector : conductor. (d) mm ( /") All stated specifications are subject to change without notice or obligation.

5 SECTION INSIDE VIEWS DISPLAY BOARD Sub CPU (IC: HDRBH) HDRH) SW LED dimmer Q0: SB Q: SC0 regulator LCD driver (IC: SEDF0C) Back light dimmer Q: SB Q: SC0 VR board Main dial Reset IC (IC: S09CLMCGF) Key dimmer Q: SB Q: SC0 PA UNIT Pre drive amplifier (Q0: SK0) Drive amplifier (Q0: RD0MUS) Power amplifier (Q00, Q0: RD0MVS) TX/ RX switch (RL0: ATN0) Lowpass filter Expand IC (IC00: ISPLSI0VE) Comparator (IC0: TA9) Buffer (IC0: NJM90M)

6 MAIN UNIT nd mixer (D90: HSBWS) YGR amplifier (IC0: µpc09t) st IF filter (FI: FL) st IF amplifier (Q: SK0) st mixer (D0: HSBWS) VCO circuit PLL IC * (IC90: MC0DR) UT0 Noise blancer circuit nd IF amplifier (Q0: SK9) nd IF filter (FI0: CFWSE) DDS IC (IC900: AD9BRM) PLL IC * (IC90: LCM) Balanced modulator (IC0: TA0F) Automatic gain control circuit A/D converter * (IC0: BU0BCF) Main CPU (IC90: M00MCMWGP) M00FCMGP) Reset IC (IC9: RNA) AF power amplifier * (IC0: TDAD) D/A converter (IC0: MFP) * Located under side of the point

7 SECTION CIRCUIT RECEIVER CIRCUITS RF CIRCUIT (PA AND MAIN UNITS) HF/0 MHz RF filters pass only the desired band signals and suppress any undesired band signals. The HF/0 MHz RF circuit has lowpass filters and highpass filters for specified band use. HF/0 MHz RF signals from the [ANT] connector, pass through one of lowpass filters as below, the transmit/ receive switching relay (PA unit; RL0) and lowpass filter (PA unit; L00, L0, C0 C0), and are then applied to the MAIN unit via J00 (PA unit). Used RF lowpass filter (MAIN unit) Frequency Control Entrance Frequency (MHz) signal coil (MHz) 0.0 MHz F RL0 MHz MHz F RL 0 MHz MHz F RL 0 0 MHz MHz F RL Control signal F F F Entrance coil RL RL0 RL The signals from the PA unit are applied to or bypass the 0 db attenuator (MAIN unit; R, R). The signals pass through the highpass filter (MAIN unit; L0 L0, C0 C0) to suppress strong signals above. MHz and are then applied to the HPF section. () 0.0 MHz and 0 0 MHz The signals pass through a lowpass filter (L0, L0, C0 C0), and then applied to the preamplifier circuit on the MAIN unit. () 0 MHz The signals from the lowpass filter (L0, L0, C0 C0) are applied to one of highpass filters as at right above and are then applied to the preamplifier circuit on the MAIN unit. () 0 0 MHz The signals pass through the highpass filter (L0 L0, C0 C0) and the lowpass filter (L0, L0 L0 C0 C), and are then applied to the preamplifier circuit on the MAIN unit. Used RF highpass filter (MAIN unit) Frequency Control Entrance Frequency (MHz) signal coil (MHz) 0.0 MHz BTHH D MHz MHz BH D 0 MHz MHz BH D 0 0 MHz MHz BH D 0 0 MHz Control signal BH BH BTHH BRH Entrance coil D D9 D D0 PREAMPLIFIER CIRCUIT (MAIN UNIT) The preamplifier circuit in the IC0 has approx. db gain over a wideband frequency range. When the preamplifier is turned ON, the signals from the RF circuit are applied to the preamplifier (Q) via D or D. Amplified or bypassed (passes through the D0 and D0 when bypassed) signals are applied to the st mixer circuit (D0). ST MIXER CIRCUIT (MAIN UNIT) The st mixer circuit mixes the receive signals with the st LO signal to convert the receive signal frequencies to a. MHz st IF signal. The signals from the preamplifier circuit, or signals which bypass the preamplifier, are passed through a lowpass filter (L L, C C) and then applied to the st mixer (D0). The st LO signal (one of the.. MHz) is amplified at Q, filtered by a lowpass filter (L, C C9), passed through the attenuator (R R), and then applied to the st mixer. ST IF CIRCUIT (MAIN UNIT) The st IF circuit filters and amplifies the st IF signals. The st IF signals are applied to a Crystal Filter (FI) to suppress outofband signals. The. MHz st IF signals pass through the crystal filter (FI). Then the filtered signals are applied to the IF amplifier (Q). The AGC voltage is supplied to the Q s gate to obtain stable signal for AGC operation. ND IF AND DEMODULATOR CIRCUIT PA UNIT MAIN UNIT [ANT] MHz LPFs HPFs Preamp. Q amp. st LO: 9.0 MHz 0.0 MHz FI st mixer D0 Crystal filter. MHz nd LO: 0.0 MHz FI0 nd mixer D90 Ceramic filter 9.0MHz NB Det. FI0 SSB, CW filter FI AM, FMN filter FM mode to AM demod. circuit (D00) to BFO circuit (IC90) to FM demod. circuit (IC0) Optional filter

8 The amplified signals are then applied to the nd mixer circuit (D90). ND MIXER CIRCUIT (MAIN UNIT) The nd mixer circuit mixes the st IF signals and nd LO signal ( MHz) to convert the st IF to a nd IF. The st IF signals from the st amplifier (Q) are converted to khz nd IF signals at the nd mixer circuit (D90). The nd IF signals are applied to the bandpass filter (FI0) to suppress undesired signals, such as the nd LO signal, and are then applied to the noise amplifier (Q0). NOISE BLANKER CIRCUIT (MAIN UNIT) The noise blanker circuit detects pulse type noise, and turns OFF the signal line when noise appears. A portion of the signals from FI0 are amplified at the noise amplifiers (Q0 Q0), then detected at the noise detector (D00) to convert the noise components to DC voltages. The converted voltages are then applied to the noise blanker gate (Q00, Q00, Q0) by applying reversebiased voltage. The detected voltage from Q00 is also applied to the noise blanker AGC circuit (Q00, Q00) and is then fed back to the noise amplifier (Q0 Q0) as a bias voltage. The noise AGC circuit prevents closure of the noise blanker gate for long periods by nonpulsetype noise. The nd IF signals from the noise blanker gate are then applied to the nd IF circuit. ND IF CIRCUIT (MAIN UNIT) The nd IF circuit amplifies and filters the nd IF signals. Used nd IF filter Mode Used filter Control signal SSB, CW, RTTY AM nar. AM, FM nar. FM SSB nar. CW nar., RTTY nar. SSB wide FL (FI0) FL9 (FI) Bypassed Optional FL Optional FLA, FLA Optional FL F F0 FTH FOP FOP FOP The filtered or bypassed signals are applied to the amplifiers (Q0, Q0) and buffer amplifier (Q) to obtain a detectable level at the demodulator circuit The amplified signals from the buffer amplifier (Q) are shared between the SSB/CW/RTTY detector (IC90), AM detector (D00), FM detector (IC0) and AGC detector (D0). IF SHIFT CIRCUIT (MAIN UNIT) The IF shift circuit shifts the center frequency of IF signals to electronically shift the center frequency. The IF shift circuit shifts the st LO and BFO within ±. khz in SSB/CW/RTTY modes or ±0 Hz in CWN/RTTYN modes. As a result, the nd IF (also st IF) is shifted from the center frequency of the nd IF filter (FI0, FI or optional IF filters). This means nd IF signals do not pass through the center of the nd IF filter. Therefore, the higher or lower frequency components of the IF are cut out. Since the BFO frequency is also shifted the same value as the st IF, frequency is corrected at the detector. In the IC0, the st LO frequency is shifted to change the nd IF because a fixed nd LO frequency ( MHz) is used. The st IF filter (FI0) and nd IF filter (FI0) have khz passband widths, and do not affect IF shift operation. The nd IF signals from the ceramic bandpass filter (FI0) are amplified at the IF amplifier (IC0) and applied to a nd IF filter as shown right column via the Tx/Rx switch (D0). NOISE BLANKER CIRCUIT to the detector circuits Q0 IF D0 nd IF signal Q00 Q00 Q0 NB GATE "NBLV" signal IC0 "ALCL" signal "AGC" signal "T" signal D00 NB DET. Q0 Amp. Q0 Amp. Q0 Amp. Q00 Q00 AGC Q00 Q00 NB SWITCH "NBS" signal

9 9 AGC CIRCUIT (MAIN UNIT) The AGC (Automatic Gain Control) circuit reduces IF amplifier gain to keep the audio output at a constant level. The receiver gain is determined by the voltage on the AGC line (Q0). The nd IF signal from the buffer amplifier (Q) is detected at the AGC detector (D0) and applied to the AGC amplifier (Q0). Q0 sets the receiver gain with the [RF/SQL] control via the RFGV signal line. When receiving strong signals, the detected voltage increases and the AGC voltage decreases via the DC amplifier (Q0). The AGC voltage is used for IF amplifiers (Q, Q0) to attenuate the received signals. When AGC slow is selected, C0 and R0 are connected in parallel to obtain appropriate AGC characteristics. The AGC signal is also applied to the meter amplifier (IC0), and is then applied to the main CPU (IC90) to use the Smeter as SML signal. 0 SMETER CIRCUIT (MAIN UNIT) The Smeter circuit indicates the relative received signal strength while receiving by utilizing the AGC voltage which changes depending on the received signal strength. The output voltage of the meter amplifier (IC0, pin ) is applied to the main CPU (IC90) as an Smeter signal via the A/D converter (IC0) as the SML signal. The Smeter signal from the main CPU (IC90) is applied to the sub CPU, and is then displayed on the Smeter readout. SQUELCH CIRCUIT (MAIN UNIT) The squelch circuit mutes audio output when the Smeter signal is lower than the [RF/SQL] control setting level. In SSB/CW/RTTY modes, the Smeter signal is applied to the main CPU (IC90, pin ) and is compared with the threshold level set by the [RF/SQL] control. The [RF/SQL] setting is picked up at the sub CPU (DISPLAY board; IC, pin 9). The main CPU compares the Smeter signal and [RF/SQL] setting, and controls the AF selector switch (IC0) to cut out AF signals. In FM mode, a portion of the AF signals from the FM IF IC (IC0, pin 9) are applied to the active filter section (pin ) where noise components above 0 khz are amplified. The signals are rectified at the noise detector section and then output from pin. The noise squelch signal from pin is applied to the main CPU (IC90, pin ) via the A/D converter (IC0, pin ) as the NSQL signal. The CPU then controls the AF selector switch (IC0). DEMODULATOR CIRCUITS (MAIN UNIT) () SSB/CW/RTTY modes The nd IF signals from the buffer amplifier (Q) are mixed with the BFO signal from the PLL circuit at the SSB detector (IC90, pins, ). The detected AF signals from IC90 (pin ) are applied to the AF selector switch (IC0, pin ) via the SSAF signal. () AM mode The nd IF signals from the buffer amplifier (Q) are detected at the AM detector (D00). The detected AF signal is applied to the AF selector switch (IC0, pin ) via the AMAF signal. () FM/FM NARROW modes The nd IF signals from the buffer amplifier (Q) are applied to the FM IF IC (IC0, pin ) where the IF signals are converted into khz IF signals. The signals are applied to the quadrature detector section. X0 is used for quadrature detector. The detected AF signals from pin 9 pass through the deemphasis circuit (IC0), and are then applied to the AF selector switch (IC0, pin ) via the FMAF signal. AGC CIRCUIT RFGV (RF gain control) nd IF signal C0 R0 AGC det. D0 D0 R0 R0 Q0 R0 R0 R0 IC0 Amp. SML Smeter signal R0 C0 C0 C0 C0 Q0 Q0 V

10 AF SELECTOR SWITCH (MAIN UNIT) The AF signals from one of the detector circuits are applied to the AF selector switch (IC0). IC0 consists of dual channel analog switches which are selected with a mode signal and the squelch control signal. AF SELECTOR SWITCH SSB/CW/ RTTY AM FM X0 X X IC0 X AF signal to the AF amplifie Audio signals from the front or rear panel [MIC] connector enter the microphone amplifier IC (IC, pin ) and are then amplified at the microphone amplifier or speech compressor section via the R. The amplified or compressed signals are applied to the VCA section of IC0. The microphone gain setting from the D/A converter (IC0, pin ) is applied to the VCA control terminal (IC0, pin ). The resulting signals from pin 9 are then applied to the buffer amplifier (Q) via the analog switch (IC0). External modulation input from the [ACC] socket (J9, pin ) is also applied to Q. AFS, AFS SQL 9, 0 INH While in SSB mode, the amplified signals from the buffer amplifier (Q) are passed through the AF selector switch (IC) and are then applied to the balanced modulator (IC0). AF AMPLIFIER CIRCUIT (MAIN UNIT) The AF amplifier amplifies the demodulated signal to a suitable driving level for the speaker. The AF signals from the AF selector switch (MAIN unit; IC0) pass through the khz lowpass filter (IC0), and are then applied to the DSP switch (IC, pin ) which mute the beep sound when DSP unit s power ON or OFF. The AF signals are applied to the VCA (Voltage Controlled Amplifier) circuit (IC0). The AF gain setting from the main CPU is converted to DC voltage at the D/A converter (IC0) and applied to the VCA control terminal (IC0) via the AFGV signal line. The CW side tone/beep tone ( BEEP signal from the buffer amplifier IC00, pin ) and optional synthesized voice ( SPCH signal from the UT0) are also applied to the VCA circuit. The output AF signals from IC0 (pin 9) are poweramplified at IC0 to drive the speaker, and are then applied to the speaker (CHASSIS unit; SP) via J. While in AM/FM mode, the amplified signals from the buffer amplifier (Q) are applied to the IDC amplifier (IC0). The signals are then applied to the AF selector switch (IC) via the AM depth controller (R) in AM mode or to the varactor diode (D9) via the FM max deviation controller (R) and AF selector switch (IC) in FM mode. VOX CIRCUIT (MAIN UNIT) The VOX (VoiceOperatedTransmission) circuit sets transmitting conditions according to voice input. When the VOX function is activated, the microphone signals are amplified at microphone amplifier (IC, pin 0), and are then applied to the VOX comparator section in the main CPU (IC90, pin 9) via the VOXL line. A portion of the power amplified AF signals from the AF power amplifier (IC0) are amplified at the buffer amplifier (IC00, pin ) and applied to the antivox comparator section in the main CPU (IC90, pin 9) via the AVXL line. Then the main CPU compares these and controls the transmitter circuit. TRANSMITTER CIRCUITS MICROPHONE AMPLIFIER CIRCUIT (MAIN UNIT) The microphone amplifier circuit amplifies microphone input signals and outputs the amplified signals to the balanced modulator or FM modulation circuit. BALAED MODULATOR (MAIN UNIT) The balanced modulator converts the AF signals from the microphone amplifier to a 9 MHz IF signal with a BFO (Beat Frequency Oscillator) signal. Microphone signals from the AF selector switch (IC) are applied to the balanced modulator (IC0, pin ). The BFO signal is applied to IC0 (pin ) as a carrier signal. MICROPHONE AMPLIFIER CIRCUIT IC "COMS" signal AF signals from the microphone "VOXL" signal Amp. Comp. IC0 IC0 VCA IC0 SW to the modulation circuit 0 Amp. "VOXL" signal

11 IC0 is a double balanced mixer IC and outputs a double side band (DSB) signal with 0 db of carrier suppression. R0 and R0 adjust the balanced level of IC0 for maximum carrier suppression. The resulting signal passes through a 9 MHz IF filter (FI0 in SSB/CW/RTTY modes) to suppress unwanted sideband signals. In AM mode, R is connected to upset the balance of IC0 via Q0 for leaking the BFO signal as a carrier signal. The CW keying/rtty TX signal is applied to IC0 pin. FM MODULATION CIRCUIT (MAIN UNIT) The microphone signals from Q are applied to the IDC amplifier (IC0, pin ). The subaudible tone signal (.0. Hz) from the main CPU (IC90, pin ) is also applied to the same amplifier (IC0, pin ) for repeater use. The resulting signals are applied to the VCO circuit (Q9, D9) via IC to change the reactance of the varactor diode (D9) for FM modulation. The modulated signal is amplified at the buffer amplifier (Q9). TRANSMITTER IF CIRCUIT (MAIN UNIT) The 9 MHz IF signal from the modulation circuit passes through the 9 MHz IF filter (FI0 in SSB/CW/RTTY modes; FI in AM/FMN modes; through in FM mode). The signal is amplified at Q0, and then passes through the crystal filter (FI0). The signal is then applied to the nd mixer (D90). The signal is mixed with the nd LO signal (0 MHz) and converted to a 9 MHz IF signal at the nd mixer (D90). The 9 MHz IF signal passes through a bandpass filter(fi), IF amplifier (Q), and is then converted to the displayed frequency at the st mixer (D0) with the st LO signal. The mixers (D0) and bandpass filter (FI) are used commonly for both receiving and transmitting. RF CIRCUIT (MAIN AND PA UNITS) The RF circuit amplifies the displayed frequency signal to obtain 0 W of RF output power for HF/0 MHz bands. The HF/0 MHz RF signals from the st mixer (D0) via the lowpass filter pass through one of highpass filters (Refer to page for used RF highpass filter). The 0 MHz RF signals pass through a lowpass filter additionally. The filtered signals pass through the lowpass filter (except 0 MHz), are then amplified at the YGR amplifier (IC0) after being passed through the highpass filter to cut the unwanted signal below. MHz, and are then applied to the PA unit. The signals from IC0 enter the PA unit and is amplified at the pre drive and power amplifiers (Q0, Q0, Q00 and Q0) to obtain a stable 0 W of RF output power in sequence. The amplified signals are applied to the band switch (RL0). The poweramplified signals from the band switch (RL0) are then applied to the [ANT] connector via one of the lowpass filters. ALC CIRCUIT (PA AND MAIN UNITS) The ALC (Automatic Level Control) circuit reduces the gain of IF amplifiers in order for the transceiver to output a constant RF power set by the RF power setting even when the supplied voltage shifts, etc. The HF/0 MHz RF power signal level is detected at the power detector (D, D), bufferamplified at IC0 and applied to the MAIN unit as the FORL voltage. The FORL voltage is applied to the ALC amplifier (MAIN unit; IC0, pin ). The POCV voltage from the D/A converter (MAIN unit; IC0, pin ), determined by the RF power setting, is applied to the same amplifier (MAIN unit; IC0, pin ) as the reference voltage. TRANSMITTER CONSTRUCTION FI, FI, or optional filter MIC IC Amp. FM, AM FM tone SSB AM IC0 IDC FM BPFs Q9 D9 Amp. Q0 Q9 Amp. Crystal filter FI0 LPF nd mixer D90 FI Crystal filter IC IF st mixer D0 HPF HPF BPF 0 MHz Antenna LPF LPF Q00, Q0 Q0 Q0 IC0 Power Drive Pre. LPF YGR HPF LPF LPF

12 When the FORL voltage exceeds the POCV voltage, ALC bias voltage from IC0 (pin ) controls st and nd IF amplifiers (Q, Q0). This adjusts the output power to the level determined by the RF power setting until the FORL and POCV voltages are equalized. In AM mode, IC0 operates as an averaging ALC amplifier with Q0. Q0 turns ON and the POCV voltage is shifted for W AM output power. The ALC bias voltage from IC0 is also applied to the main CPU (IC90) via the A/D converter (IC0) as the ALCL voltage for ALC meter indication. An external ALC input (minus voltage) from the [ACC] socket (pin ) is shifted to plus voltage at D and is applied to the buffer amplifier (Q). External ALC operation is identical to that of the internal ALC. APC CIRCUIT (MAIN UNIT) The APC (Automatic Power Control) circuit protects the power amplifiers on the PA unit from high SWR and excessive current for the HF/0 MHz band. The reflected wave signal appears and increases on the antenna connector when the antenna is mismatched. The HF/0 MHz reflected signal level is detected at D (PA unit), and is amplified at the APC amplifier (IC0) and applied to the ALC circuit as the reference voltage. For the current APC, the driving current at the power amplifier is detected in the voltages ( IDH and IDL ) which appear at both terminals of a 0.0 Ω resistor (R) on the PA unit. The detected voltages are applied to the differential amplifier (IC0, pins 9, 0). When the current of the power amplifier exceeds allowed current, IC0 controls the ALC line via IC0 to prevent excessive current flow. 9 RF, ALC, SWR METER CIRCUITS (MAIN UNIT) While transmitting, RF, ALC or SWR meter readings are available and can be selected with the [MET] switch. () Power meter The FORL voltage is applied to the main CPU (IC90) via the A/D converter (IC0, pin ) for indicating the output power. FREQUEY CONSTRUCTION (0.0 0 MHz) Antenna st IF signal (. MHz) nd IF signal ( khz) st mixer D0 Q IF 9.0 MHz (WFM: 0. MHz) Crystal BPF Q IF nd mixer D90 to each detector circuits st LO signal (.0.0 MHz) nd LO signal (.0 MHz) db ATT * * Oscillates MHz Oscillates MHz Q90 D90 (* for HF bands) LPF LO HPF LPF Amp. Q Q90 Q9 D9 (* for 0 MHz band) Ref Oscillator X90 Amp. DDS PLL IC IC9 IC900 IC90 MAIN LOOP CIRCUIT PLL IC Amp. LPF ATT IC90 Q9 D9 Q9 (Oscillates.0 MHz) db SINGLE LOOP CIRCUIT

13 () ALC meter The ALC bias voltage from IC0 pin is applied to the main CPU (IC90) via the ALCV signal line for indicating the ALC level. () SWR meter The FORL and REFL voltages are applied to the main CPU (IC90) via the A/D converter (IC0, pins and ) respectively. The main CPU compares the ratio of FORV to REFV voltage and indicates the SWR for the [ANT] connector. ND LO AND REFEREE OSCILLATOR CIRCUITS (MAIN UNIT) The reference oscillator (IC90, Q9, X90) generates a MHz frequency used for the nd LO signal. The oscillated signal is amplified at the buffer amplifier (Q9), and is then passed through the lowpass filter (L9, C9, C9) to suppress the high harmonics components. The filtered MHz signal is applied to the nd mixer (D90) via the db attenuator (R9 R9) as a nd LO signal. PLL CIRCUITS GENERAL The PLL circuits generates a st LO frequency (.. MHz), a nd LO frequency ( MHz), a BFO frequency ( khz). The st LO PLL circuit adopts a mixerless dual loop PLL system and has VCO circuits. The BFO uses a DDS and the nd LO uses a MHz fixed frequency. ST LO PLL CIRCUIT (MAIN UNIT) The st LO PLL contains a main loop and reference loop forming a dual loop system. The reference loop generates a. MHz frequency using a DDS circuit, and the main loop generates a. to. MHz frequency using the reference loop frequency. () REFEREE LOOP PLL The oscillated signal at the reference passes through the lowpass filter (L9, L9, C9 C9), and is then amplified at the amplifier (IC9). The amplified signal is applied to the DDS IC (IC900, pin ) via the lowpass filters (L9, L9, C9 C90, L90, L90, C90 C90). The signal is then divided and detected on phase with the DDS generated frequency. The detected signals output from IC900 (pin 0) are amplified at the buffer amplifier (Q90), and then pass through the bandpass filter (L90 L90, C90 C90) to suppress spurious components. The signal is applied to the PLL IC (IC90, pin ) as PLL lock voltage. () MAIN LOOP PLL The oscillated signal at one of the main loop VCOs (HF: Q90, 0 MHz: Q9) is amplified at the buffer amplifier (Q90) and is then applied to the PLL IC (IC90, pin ). The signal is then divided and detected on phase with the reference loop output frequency. The detected signal output from the PLL IC (IC90, pin ) is converted into a DC voltage (lock voltage) at the active loop filter and then fed back to one of the varactor diodes (D90, D9) in the VCO circuits BFO CIRCUIT (MAIN UNIT) The DDS IC (IC90) generates a khz BFO signal. The signa is passed through the lowpass filter (L9, C9, C9, C9) to suppress high harmonics suprious components. The khz BFO signal is then applied to the SSB detector (IC90, pin ) and SSB modulator (IC0, pin ) via the BFO signal line. While transmitting in RTTY mode, the RTTY keying signal is applied to IC90 to shift the generated frequency and to obtain frequencies for FSK operation. CW receiving pitch control, RTTY receiving tone, RTTY transmitting mark are controled by changing BFO frequency. ANTENNA TUNER CIRCUITS ANTENNA MATCHING NETWORK CIRCUIT (PA UNIT) The antenna tuner circuit consists of the antenna matching network circuit, SWR detector circuit, impedance detector circuit, phase detector circuit, etc. When antenna tuning is ON, the antenna matching network circuit switches ON via the RL0 and RL. The attenuator s impedance is set to 0 Ω which is same as power amplifier s output impedance. The attenuator s input impedance is about SWR, however its output impedance changes variably. Therefore, attenuator s output impedance is matched to the antenna to become about SWR, then impedance matching is depended on input impedance. The antenna matching network circuit switches OFF via the RL0 and RL when the impedance is matched between the output impedance and antenna. The antenna matching network circuit is composed between RL0 and RL. Therefore, each detecting circuits work when antenna tuning is ON only. Thus, There isn t influence about loss of each detecting circuits when antenna tuning is OFF. In addition, the output power from the power amplifier (Q00, Q0) is applied to the this circuit as low power via the attenuator. Therefore, the output power doesn t effect to interference while impedance tuning. The oscillated signal passes through a lowpass and highpass filters, and is then applied to the st mixer (D0) as a st LO signal.

14 OUTPUT POWER DETECTING CIRCUIT (PA UNIT) The output power from the power amplifier (Q00, Q0) is divided at the C0 and C. The divided voltage is applied to the power detecting circuit (D0) as detecting voltage. The detected voltage is applied to the main CPU (MAIN unit; IC90) via the A/D convertor (MAIN unit; IC0) as TPZL signal after being passed through the switch circuit (IC, Q). IMPEDAE DETECTING CIRCUIT (PA UNIT) The output power from the power amplifier (Q00, Q0) is applied to the RL0. The signal is applied to the power detector (D0), and is then applied to the main CPU (MAIN unit; IC90) as the reference voltage. The voltage is also used for power detecting voltage when the antenna tuning is ON. The attenuator s output voltage is depended on the condition between power amplifier s output impedance and the antenna (For example, the voltage becomes high when the impedance is high, the votage becomes low when the impedance is low). The voltage is amplified at the Q, and is then detected at the impedance detector (D). The signal is applied to the main CPU (MAIN unit; IC90) to analyze whether the impedance is more than. or not. The output side signal is applied to the amplifiers (Q, Q). The amplified signal is applied to the phase detecting circuit (L). The detected signal is applied to the comparator circuit (IC0, pin ), and is then applied to the main CPU (MAIN unit; IC90, pin ) via the TPHK signal. SWR DETECTING CIRCUIT (PA UNIT) The SWR detecting circuit employs return loss bridge circuit (L, R R) which is also composed as db attenuator (inputoutput impedance is 0 Ω). The output power from the power amplifier (Q00, Q0) passes through the attenuator, and is then applied to the SWR detecting circuit (D). The signal is applied to the main CPU (MAIN unit; IC90) via the A/D convertor (MAIN unit; IC0) as TSWL signal. The main CPU is analyzed SWR to use the TSWL signal from the SWL detecting circuit and TPZL signal from the power detecting circuit. PHASE DETECTING CIRCUIT (PA UNIT) The phase detecting circuit is composed D, L0 and L. The input side signal passes through the C to shift the its phase for 90 degrees. The signal is applied to the phase detecting circuit (L0). ANTENNA TUNER CONSTRUCTION "TDTS" signal from the main CPU (MAIN unit; IC90, pin ) The signal from the power/swr detector (D0, D) to the antena RL0 RL ATT D SWR detector "TPZL" signal to the A/D convertor (MAIN unit; IC0, pin ) "TPZS" signal to the main CPU (MAIN unit; IC90, pin ) IC Q Switch D Impedance detector D Phase detector D0 Power detector Q Amp. Q Q Amp. IC0 Comparator "TSWL" signal to the A/D convertor (MAIN unit; IC0, pin ) "TPHK" signal to the main CPU (MAIN unit; IC90, pin )

15 POWER SUPPLY CIRCUITS VOLTAGE LINES (MAIN UNIT) Line HV V P P R T Line HV V Description Common V converted from the HV line by the regulator circuit (IC990). Common V converted from the V line by the regulator circuit (IC99). Common V converted from the V line by the regulator circuit (IC99). The same voltage as the line which is controlled by the switching circuit (Q99, Q99). The circuit is controlled by the PSS signal from the CPU (IC90, pin 90). Common V converted from the V line by the regulator circuit (IC99). The same voltage as the line which is controlled by the switching circuit (Q99, Q99). The circuit is controlled by the PSS signal from the CPU (IC90, pin 90). Receive V which is the same voltage as the line controlled by the switching circuit (Q, Q) using the RXS signal from the CPU (IC90, pin ). Transmit V which is the same voltage as the line controlled by the switching circuit (Q, Q) using the TXS signal from the CPU (IC90, pin ). PA UNIT VOLTAGE LINES Line Description The voltage from a DC power supply. The same voltage as the HV line which is controlled by the power switching circuit (Q0, Q). When the [POWER] switch is pushed, the CPU outputs the POWS control signal to the power switching circuit to turn the circuit ON. VOLTAGE LINES (DISPLAY BOARD) Description Common V line from the regulator circuit (MAIN unit; IC99). The voltage is applied to the microphone via the J, pin. Common V converted from the line by the regulator circuit (IC, Q0, Q, D9). The output voltage is applied to the SUBCPU (IC), LCD driver (IC), etc. CPU PORT ALLOCATIONS MAIN CPU PORT ALLOCATIONS (MAIN UNIT; IC90) Pin number Port name BEEP TONE PDT SNDK PCK NOP NTH TGK PWRK N0 N UNLK TDAT KDS MINH DPTK LRXD LTXD SLOS CTXD CRXD PST Description Outputs beep audio and CW side tone signals. Outputs CTCSS tone signal. Outputs the serial data to the PLL IC (IC90). Input port for transmitting signals from the microphone or ACC connector. Outputs the serial clock to the PLL IC (IC90). Outputs control signal for the optional nd IF filter. High : While the filter is selected. Outputs control signal for the nd IF filter. High : While the filter is bypassed. Input port for the shock detecting signal. Input port for the [POWER] swtich on the front panel. Low : While the [POWER] is pushed. Outputs control signal for the nd IF filter. High : While the khz filter is ON. Outputs control signal for the nd IF filter. High : While the. khz filter is ON. Input port for the PLL unlock signal. Low : While the PLL is unlocked. Outputs tuner data signal. Outputs CW key down signal. High : While transmitting on CW or RTTY modes. Output SSB modulation prohibitive signal. High : While transmitting on CW, FM or RTTY modes. Input port for the PTT signal from the data terminal (J, pin ). High : While data are transmitting. Input port for the data signal from the front unit. Outputs data signal to the front unit. Outputs LO level control signal. Outputs CIV signals. Input port for the CIV signals. Outputs strobe signal to the PLL IC (IC90) for the nd LO signal. 9

16 (MAIN unit; IC90) Continued Pin number Port name SBST PDST PMST DSTB FSKK AGFS FMS ANS NBS AFS AFS ATTS PROS PRES COMS D9S DSPS ECK EDT DRES DASK DOTK AFMS Description Outputs strobe signal to the BFO s DDS IC (IC90). Outputs strobe signal to the DDS IC (IC900) for main loop. Outputs strobe signal to the PLL IC (IC90) for main loop. Outputs strobe signal to the D/A convertor (IC0). Input port for the RTTY keying signal. High : While marking. Low : While spacing. Outputs AGC first control signal. Low : While AGC first is ON. Outputs FM mode select signal. High : While FM or FMN is selected. Outputs AM mode select signal. High : While AM or AMN is selected. Outputs noise blanker control signal. High : While noise blanker is ON. Outputs detecting output select signal. High : While AM or AMN is selected. Outputs detecting output select signal. High : While FM or FMN is selected. Outputs attenuator control signal. High : While attenuator is ON. Outputs the preamplifier ON/OFF control signal. High : While the preamplifier is OFF. Outputs the preamplifier ON/OFF control signal. High : While the preamplifier is ON. Outputs the speech compressor control signal. High : While the speech compressor is ON. Outputs 900 bps packet mode control signal. High : While 900bps packet mode is ON. Outputs optional DSP unit control signal. High : While the DSP unit is ON. Outputs the EEPROM clock signal. I/O port for the EEPROM data signal. Outputs reset signal. Input port for the external paddle dash signal. Input port for the external paddle dot signal. Outputs AF mute control signal. Low : While AF is muting. (MAIN unit; IC90) Continued Pin number Port name SPS VCCL PSS MUDL CTCL MSTB MDT MCK Description Outputs the speaker switching signal. High : The speaker is ON. Input port for supplied voltage detecting signal. Outputs power save control signal. Low : While power save is ON. Input port for the microphone [UP]/[DWON] signal from the rear panel. Input port for the CTCSS signal. Outputs strobe signal to the expander IC (IC0, pin ). Outputs serial data to the D/A convertor (IC0, pin ) and expander IC (PA unit; IC00, pin ). Outputs serial clock to the D/A convertor (IC0, pin ) and expander IC (PA unit; IC00, pin ). 0

17 SUB CPU PORT ALLOCATIONS (DISPLAY BOARD; IC) Pin number 9 0 Port name KLS KLS PHNK RSK MDAK MDBK SDAK PRED ATTD TUND RITD LCKD RXD TXD BLS BLS Description Output key backlight control signals. KLS KLS Lights Low Low OFF High Low Low High High High Input port for the phone plug insert detecting signal. High : While the phone plug is inserted. Input port for the [RIT/SUB] key. Input port for the main dial s A phase signal. Input port for the main dial s B phase signal. Input port for the sub dial s A phase signal. Outputs the P.AMP LED control signal. Outputs the ATT LED control signal. Outputs the TUNER LED control signal. Outputs the RIT LED control signal. Outputs the LOCK LED control signal. Outputs the RX LED control signal. Outputs the TX LED control signal. Output the LCD backlight control signals. BLS BLS Lights Low Low OFF High Low Low High High High (DISPLAY BOARD; IC) Continued Pin number Port name LTXD SDBK PRAK/ TUNK Outputs the communicating signal with the main unit. Input port for the subdial s B phase signal. Input port for [P.AMP/ATT] and [TUNER/CALL] keys. MENK/ Input port for [MENU] and [F] keys. FK FK/FK Input port for [F] and [F] keys. DISK/ Input port for [DISPLAY] and [LOCK] LCKK keys. MODK/ Input port for [MODE] and [TS] keys. TSK BUPK/ BDNK PTTL FUDL AFGL SQLL SFTL Description Input port for [BAND UP] and [BAND DN] keys. Input port for the microphone PTT signal. Input port for the microphone UP/DOWN signal. Input port for the AF volume control signal. Input port for the RS/SQL volume control signal. input port for the SHIFT volume control signal SUBD WR RD A0 COM COM DB DB0 SEG SEG LRES LRXD Outputs subdial s LED control signal. Output the LCD driver (IC) control signals. Output LCD common signals. I/O port for LCD driver s data signals. Output LCD segment signals. Outputs the LCD driver reset signal. Low : While the LCD driver is reset. Input port for the communicating signal with the main unit.

18 SECTION ADJUSTMENT PROCEDURES PREPARATION BEFORE SERVICING REQUIRED TEST EQUIPMENT EQUIPMENT GREDE AND RANGE EQUIPMENT GREDE AND RENGE DC power supply RF power meter (terminated type) Frequency counter RF voltmeter Standard signal generator (SSG) FM deviation meter Modulation analyzer Output voltage :. V DC Current capacity : A or more Measuring range : 0 W Frequency range :. 00 MHz Impedance : 0 Ω SWR : Less than. : Frequency range : 00 MHz Frequency accuracy : ± ppm or better Sensitivity : 00 mv or better Frequency range : 00 MHz Measuring range : V Frequency range : 00 MHz Output level : µv mv ( to dbm) Frequency range : 0 00 MHz Measuring range : 0 to ± khz Frequency range : At least 00 MHz Measuring range : 0 00 % Distortion meter Oscilloscope Digital multimeter AC millivoltmeter DC voltmeter DC ammeter Audio generator Spectram analyzer Attenuator External speaker Frequency range : khz ±0 % Measuring range : 00 % Frequency range : DC 00 MHz Measuring range : V Imput impeadance : 0 MΩ/DC or beter Measuring range : 0 mv 0 V Input impedance : 0 kω/v DC or better Measurement capability: A/0 A Frequency range : Hz Measuring range : 00 mv Frequency range : At least 000 MHz Spectraum bandwidth : 00 khz or more Power attenuation : 0 or 0 db Capacity : 0 W or more Input impedance : Ω Capacity : W or more CONNECTIONS Microphone connector (Rear panel view) Pin MIC Pin MIC INPUT Pin Audio generator Pin PTT to [MIC] to [EXT SP] AC millivoltmeter Speaker Spectrum analyzer Attenuator 0 or 0 db FM deviation AAmeter DC power supply AA. V/ A AM meter A, 0 A to [DC. V] RF power meter A00 W/0 Modulation aanalyzer Keyer to [ELEC KEY] to [ANT] Standard signal aagenerator Frequency counter i0 CAUTION: DO NOT connect the standard signal generator while transmitting.

19 PLL ADJUSTMENTS ADJUSTMENT REFEREE FREQUEY VCO LOCK VOLTAGE VCO LOCK VOLTAGE ADJUSTMENT CONDITION Display frequency: Any Receiving Display frequency: MHz Mode : USB Receiving Display frequency: MHz Mode : USB Receiving ADJUSTMENT MEASUREMENT VALUE POINT UNIT LOCATION UNIT ADJUST MAIN MAIN MAIN Connect an RF voltmeter to check point CP9. Connect a frequency counter to check point CP9. Connect a digital multimeter or oscilloscope to check point CP9. Connect a digital multimeter or oscilloscope to check point CP9... V MHz.0 V.0 V MAIN MAIN MAIN Verify R9 C90 C9

20 MAIN UNIT TOP VIEW CP9 CP9 Reference frequency check point R9 Reference frequency adjustment C90 VCO lock voltage adjustment C9 VCO lock voltage adjustment CP9 VCO and VCO lock voltage check point

21 TRANSMITTER ADJUSTMENTS ADJUSTMENT TRANSMIT PEAK POWER CARRIER SUPPRESSION TRANSMIT TOTAL GAIN OUTPUT POWER ADJUSTMENT CONDITION Display frequency:.0000 MHz Mode : USB [RF POWER] : H [MIC GAIN] : Preset R to o clock position. Preset R0, R0 and R0 to center position. Connect an audio generator to [MIC] connector and set as:. khz/ mv Transmitting Display frequency:.0000 MHz Mode : USB Apply no signal to [MIC] connector. Transmitting Transmitting Display frequency:.0000 MHz Mode : USB [MIC GAIN] : Connect an audio generator to [MIC] connector and set as:. khz/ mv Transmitting Display frequency:.0000 MHz Mode : USB [MIC GAIN] : Connect an audio generator to [MIC] connector and set as:. khz/0 mv Transmitting Display frequency: MHz Transmitting ADJUSTMENT MEASUREMENT VALUE POINT UNIT LOCATION UNIT ADJUST Rear Panel Rear Panel Rear Panel Rear Panel Connect an RF power meter to [ANT] connector. Connect a spectrum analyzer to [ANT] connector via an attenuator. Connect an RF power meter to [ANT] connector. Connect an RF power meter to [ANT] connector. Maximum RF power NULL point Minimum carrier level W 9. W 0 W MAIN MAIN MAIN MAIN L, L R0 R0 R R0 R0 Id APC Preset R to 9 o clock position. Display frequency:.000 MHz Mode : LSB Connect CP to ground. Connect an audio generator to [MIC] connector and set as:. khz/0 mv Transmitting Rear panel Connect an ammeter between the IC0 and the power supply..0 A MAIN R

22 MAIN UNIT TOP VIEW R Transmit total gain adjustment R0 R0 Transmit peak power adjustment R Id APC adjustment R0 R0 Carrier suppression adjustment R0 R0 Output power adjustment

23 TRANSMITTER ADJUSTMENTS (continued) ADJUSTMENT FM DEVIATION AM MODULATION CW CARRIER LEVEL ADJUSTMENT CONDITION Display frequency: MHz Mode : FM [RF POWER] : H [TON] : OFF [MIC GAIN] : Connect an audio generator to [MIC] connector and set as: khz/0 mv Transmitting Display frequency:.0000 MHz Mode : AM [RF POWER] : H [MIC GAIN] : Disconnect the plug from J on the MAIN unit. Apply no signal to [MIC] connector. Transmitting Connect the plug to J on the MAIN unit. Apply no signal to [MIC] connector. Transmitting Preset R to 9 o clock position. Connect an audio generator to [MIC] connector and set as: khz/0 mv Transmitting Display frequency:.0000 MHz Mode : CW [RF POWER] : H [KEY SPEED] : 0 [BRK] : BK (semi breakin) CW paddle : n Connect an RF power meter to [ANT] connector. Transmit dots for a while using a paddle. ADJUSTMENT MEASUREMENT VALUE POINT UNIT LOCATION UNIT ADJUST Rear Panel MAIN Rear Panel Connect an FM deviation meter to [ANT] connector via an attenuator. Connect an osilloscope to check point CP0. Connect an RF power meter to [ANT] connector. Connect a modulation analyzer to [ANT] connector via an attenuator. Connect an osilloscope to check point CP and [ANT] connector. ±. khz 00 mvpp. W 90 % ( peak) modulation At the point where the CW carrier completely comes up in a 0 msec. delay after CP voltage comes up. Keying (CP) MAIN MAIN MAIN R R R0 R R 0 msec.

24 MAIN UNIT TOP VIEW R0 R R AM modulation adjustment R FM deviation adjustment R CW carrier level adjustment

25 RECEIVER ADJUSTMENTS ADJUSTMENT RECEIVER PEAK RECEIVER TOTAL GAIN NOISE BLANKER ADJUSTMENT CONDITION Display freq. :.000 MHz Mode : USB [RIT] : OFF [AGC] : Fast (F AGC) [NB] : OFF [P.AMP/ATT] : Preamp ON Connect a standard signal generator to the [ANT] connector and set as: Frequency :.0 MHz Level : 0. µv* ( dbm) Modulation : OFF Receiving [P.AMP/ATT] : Preamp OFF Set an SSG as: Frequency :.0 MHz Level : 00 µv* ( dbm) and OFF Modulation : OFF Receiving Display freq. :.000 MHz Mode : USB [P.AMP/ATT] : Preamp ON [NB] : ON Connect an SSG to the [ANT] connector and set as: Frequency :.0 MHz Level : µv* ( dbm) Modulation : OFF and apply the following signal to the [ANT] connector. ADJUSTMENT MEASUREMENT VALUE POINT UNIT LOCATION UNIT ADJUST Rear Panel Rear Panel MAIN Connect an AC millivoltmeter to the [EXT SP] jack with an Ω dummy load. Connect an AC millivoltmeter to the [EXT SP] jack with a Ω dummy load. Connect an oscilloscope to check point CP00. Maximum AF output level 0 db of AF level difference Adjust the maximum noise wave displayed on the oscilloscope. MAIN MAIN MAIN L, L, L0, L0, L0 R0 L0, L0 00 msec. msec. Receiving [NB] : ON Set an SSG as: Level : 0 µv* ( dbm) Modulation : OFF Receiving At the point where the noise just reduces. Verify *This output level of the standard signal generator (SSG) is indicated as SSG s open circuit.

26 MAIN UNIT TOP VIEW R0 Receiver total gain adjustment L0 L0 Noise blanker adjustment L0 L0 L0 L L Receiver peak adjustment 9

27 SET MODE ADJUSTMENTS (No.) ADJUSTMENT ADJUSTMENT CONDITION DISPLAY OPERATION ENTERING ADJUSTMENT SET MODE SMETER FILTER CALIBRATION Enter adjustment set mode: Turn power OFF. Terminate the [REMOTE] jack with a.(d) mm shortenplug. While pushing [P.AMP/ATT] and [TUNER], turn power ON. Connect an SSG to [ANT] connector and set as: Frequency :. MHz Level : OFF Receiving Set an SSG as : Level : 0 µv ( dbm) Modulation : OFF Receiving Set an SSG as : Level : mv ( dbm) Modulation : OFF Receiving Turn power OFF, and then enter the TX adjustment set mode. Connect an RF power meter to [ANT] connector. Connect an audio generator to [MIC] connector and set as:. khz/ mv USB S0 LEVEL S9 LEVEL 0dB LEVEL GO FILTER CAL Push [F (RX)] to enter the S METER adj. setting mode, [F (TX)] to enter the TX adj. setting mode. Then advance to the following setting, or push [UP]/[DN] to scroll the display. Push [MENU] to set the "S0 level". Push [MENU] to set the "S9 level". Push [MENU] to set the "0 db level". The display returns to the same as the ADUSTMENT SET MODE above. Push and hold [MENU (GO)] to make the calibration. Transceiver transmits for a while. POWER METER ( MHz) Connect an RF power meter to [ANT] connector. Transmit using an external PTT switch. CHK 0 W Set to 0 W using [MAIN DIAL], then push [MENU] while transmitting. Transmit using an external PTT switch. SET W Set to W using [MAIN DIAL], then push [MENU] while transmitting. Transmit using an external PTT switch. SET. W Set to. W using [MAIN DIAL], then push [MENU] while transmitting. Transmit using an external PTT switch. SET W Set to W using [MAIN DIAL], then push [MENU] while transmitting. Transmit using an external PTT switch. SET 0. W Set to 0. W using [MAIN DIAL], then push [MENU] while transmitting. Transmit using an external PTT switch. SET POmin Set to W using [MAIN DIAL], then push [MENU] while transmitting. POWER METER (0 MHz) Connect an RF power meter to [ANT] connector. Transmit using an external PTT switch. CHK 0 W Set to 0 W using [MAIN DIAL], then push [MENU] while transmitting. Transmit using an external PTT switch. SET W Set to W using [MAIN DIAL], then push [MENU] while transmitting. Transmit using an external PTT switch. SET. W Set to. W using [MAIN DIAL], then push [MENU] while transmitting. Transmit using an external PTT switch. SET W Set to W using [MAIN DIAL], then push [MENU] while transmitting. Transmit using an external PTT switch. SET 0. W Set to 0. W using [MAIN DIAL], then push [MENU] while transmitting. Transmit using an external PTT switch. SET POmin Set to W using [MAIN DIAL], then push [MENU] while transmitting. 0