Clapton (EL7) AIO Block Diagram

lapton (EL) IO lock iagram 0 iamondville S G Xmm FS/ P, VI[0:] /- PU_LK /- HLK PU VORE P lock Gengerator P." Panel P LVS H0 P SVO GSE(GMH) FG X mm R(00/) Single-SOIMM P P,,,, RJ- P in Speaker P Ext HP Ext Mic Line out Giga Ethernet RTLL P ard Reader RTS H OE L P P US PORT X P PI-E US H udio US x MI 0GM (IHM) G x mm LP( MHz) E ITE 0 P 0,, P ST US US/PI-E O H/SS amera onn. WLN P 0 P 0 P P amera Module WLN Module PS/ K/ P SPI Flash P Quanta omputer Inc. Size ocument Number Rev lock iagram PROJET : EL ate: Friday, pril, 00 Sheet of

lock Generator.0V_V PM_STPPI# R.K_ V 0 V L PY00T-0Y-N_ () PLK_EUG () () LLK_E PLK_IH () LK_M_R () LKUS_ () M_IH () M_H0 Pin Pin Pin PLK_EUG PLK_IH V_K_V_PI V_K_V_ V_K_V_PI V_K_V_REF V_K_V_PI V_K_V_PU G_XIN PLK_PM_R PLK_OZ_R PLK_IH_R G_XOUT R _ R0 _ FS LK_SEL0 R.K_ LK_SEL FS LK_SEL R0 0K_ R0 _ FS R0 _ L=0p G_XIN G_XOUT ISLPRS RTMT-0 (LPRSK) (L000K0) PI/TME 0u/0V_ PI-/M_SEL PIF-/ITP_EN 0u/0V_ 0 T T p/0v_ p/0v_ R0 0_ R0 0_ R0 _ Y PI/TME internal P.MHZ PI-/M_SEL internal P PIF-/ITP_EN internal P 0u/0V_.0V_V PLK_EUG_R PI_LK_SIO_R PLK_0_R PULL HIGH NO OVERLOKING PULL OWN NORML RUN PIN / IS MHz PIN 0/ IS SR/OT PIN / IS PUITP 0u/0V_ U V_PI V_ V_PLL V_REF 0 0 V_SR V_PU (default) V IO V_PLL_IO V_SR_IO_ V_SR_IO_ V_SR_IO_ V_PU_IO PI0/R#_ PI/R#_ PI/TME PI PI/M_SEL PIF/ITP_EN XTL_IN XTL_OUT US_/FS K0 ISLPRSKLFT PIN / IS SR 0 IO_VOUT (default) (default) FS/TEST/MOE SR/R#_ SR#/R#_ REF0/FS/TESTSEL VSS_OY SR/ST VSS_PI SR#/ST# VSS_ VSS_IO SR/SE VSS_PLL SR#/SE VSS_PU VSS_SR SR0/OT 0 VSS_SR SR0#/OT# VSS_SR VSS_REF KPWRG/PWRWN# ISLPRSKLFT SLK S SR/PI_STOP# SR#/PU_STOP# PU0 PU0# PU PU# SR/ITP SR#/ITP# SR0# SR0 SR SR# SR SR# SR SR# 0 SR/R#_H 0 SR#/R#_G SR/R#_F SR#/R#_E 0 SMK SMT PM_STPPI# PM_STPPU# LK_MH_OE#_R NEW_LKREQ#_R V V V R R R R R R0 PM_STPPI# () PM_STPPU# () LK_PU_LK () LK_PU_LK# () LK_MH_LK () LK_MH_LK# () Modified 00/0/0 by Jimmy Hsu R R LK_PIE_GPLL# () LK_PIE_GPLL () PELK () PELK- () Modified 00/0/0 by Jimmy Hsu 0K_ *0K_ *0K_ 0K_ *0K_ 0K_ L PY00T-0Y-N_ RP *0X_ RP *0X_ RP *0X_ /F_ MH_LKREQ# () /F_ LKREQ_WLN# () RP *0X_ RP *0X_ RP *0X_ RP *0X_ RP *0X_ RP *0X_ PELK () PELK- () LK_PIE_IH () LK_PIE_IH# () LK_PIE_ST (0) LK_PIE_ST# (0) REFSSLK () REFSSLK# () REFLK () REFLK# () VR_PWRG_K0 () PLK_OZ_R LLK_E HIGH MHz LOW SR PLK_IH.0V To S To PU To N To G To N To WLN LK To G To LN To S To S To N To N To N.0V PM_STPPU# NEW_LKREQ#_R LLK_E LKUS_ M_IH PLK_IH LLK_E PLK_EUG LK_M_R LKUS_ R *0_ LK_SEL0 R K_ () PU_SEL0 MH_SEL0 () () ().0V PU_SEL.0V PU_SEL SEL SEL SEL0 R R LK_SEL R LK_SEL R0 *p/0v_ Frequence select FS FS FS PU SR PI R R R 0 00 00 0 0 00 0 00 0 0 00 00 0 0 0 00 0 0 00 0 00 00 Reserved R _ R R *K_ *K_ *0_ R 0_ R *K_ *0_ *0_ 0 *p/0v_ p/0v_ 0p/0V_ *p/0v_ *p/0v_ *p/0v_ *p/0v_.k_ 0K_ K_ K_ ES-0- efault MH_SEL () MH_SEL () lock Gen I V <MIN>:ISLPRSGLFT QI:LPRSK V <SEON>:SLGSPTTR: QI:LSPK0 () SMT Q N00E R.K_ SMT Q0 R.K_ SMK SMT (,) () SMK SMK (,) N00E Quanta omputer Inc. PROJET : EL Size ocument Number Rev LOK GENERTOR ate: Friday, pril, 00 Sheet of

().0V.0V.0V H_#[:] () H_ST#0 () H_REQ#[:0] () () H_#[:] H_ST# T (0) H_0M# (0) H_FERR# (0) H_IGNNE# (0) H_STPLK# (0) H_INTR (0) H_NMI (0) H_SMI# U H_# P H_# []# H0 H_# []# N0 H_# []# R0 H_# []# J H_# []# N H_# []# G0 H_#0 []# M H_# [0]# H H_# []# L0 H_# []# M0 H_# []# K H_# []# J0 H_# []# L []# K0 T H_P0 ST[0]# H_REQ#0 P0 N H_REQ# REQ[0]# J H_REQ# REQ[]# G H_REQ# REQ[]# P0 H_REQ# REQ[]# R REQ[]# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_P U T H_IGNNE# J R T R U R *K_ R *K_ Note: Place near PU F E 0 E0 0 M G H K K M L []# []# []# [0]# []# []# []# []# []# []# []# []# []# [0]# []# []# []# []# []# ST[]# P R GROUP 0M# FERR# IGNNE# STPLK# LINT0 LINT SMI# N N N N N N N R GROUP 0 N H LK THERM ONTROL XP/ITP SIGNLS S# NR# PRI# EFER# RY# SY# R0# IERR# INIT# LOK# RESET# RS[0]# RS[]# RS[]# TRY# HIT# HITM# PM[0]# PM[]# PM[]# PM[]# PRY# PREQ# TK TI TO TMS TRST# R# PROHOT# THRM THRM THERMTRIP# LK[0] LK[] RSV RSV RSV V Y U T T Y T0 F V W0 IERR# H_INIT#R W H_RS#0 Y H_RS# U0 H_RS# W V0 R _ R K/F_ iamondville_s_rev.0v..0v.0v.0v H_S# () H_NR# () H_PRI# () H_EFER# () H_RY# () H_SY# () H_REQ#0 () R 0_ H_LOK# () H_PURST# () H_RS#[:0] () H_TRY# () H_HIT# () H_HITM# ().0V H_INIT# (0).0V K J H XP_PM#0 XP_PM# XP_PM# T T T J XP_PM# T K XP_PM# T0 J XP_PM# XP_PM# XP_TK XP_TK N XP_TI XP_TI XP_TO L XP_TMS XP_TMS K XP_TRST# XP_TRST# V R# R PM_SYSRST# () *0_ R R.0V G H_PROHOT#_R H_PROHOT# () E H_THERM () E H_THERM () H V V PM_THRMTRIP# (,0) LK_PU_LK () LK_PU_LK# () PU.0V () H_#[:0] () H_STN#0 () H_STP#0 () H_INV#0 T () H_#[:0] () H_STN# () H_STP# () H_INV# T () () () R *K/F_ R0 *K/F_ T T T T T PU_SEL0 PU_SEL PU_SEL H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_P#0 H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_P# H_GTLREF LKPH LKPH H_INIT# EM EXTGREF FOREPR# H_HFPLL H_MERR H_RSP# PU P/N: JSLVT0 U Y [0]# W0 []# Y []# []# []# W []# []# Y0 []# Y []# Y []# W [0]# []# Y []# W []# []# W []# Y STN[0]# Y STP[0]# W INV[0]# V P#0 Y W U W W Y Y W V U T V W Y Y Y R U V T R M N N P T J H G []# []# []# []# [0]# []# []# []# []# []# []# []# []# []# [0]# []# STN[]# STP[]# INV[]# P# T GRP 0 T GRP GTLREF LKPH LKPH INIT# EM MIS EXTGREF FOREPR# HFPLL MERR# RSP# SEL[0] SEL[] SEL[] iamondville_s_rev T GRP T GRP []# []# []# []# []# []# []# []# [0]# []# []# []# []# []# []# []# STN[]# STP[]# INV[]# P# []# []# [0]# []# []# []# []# []# []# []# []# []# [0]# []# []# []# STN[]# STP[]# INV[]# P# OMP[0] OMP[] OMP[] OMP[] PRSTP# PSLP# PWR# PWRGOO SLP# ORE_ET H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_P# ORE_ET PU_MREF H_#[:0] () 0 H_STN# () H_STP# () H_INV# () H_# H_#[:0] () G H_# F H_#0 H_# H_# E H_# H_# H_# H_# F H_# H_# H_# H_#0 H_# H_# H_# E H_STN# () F H_STP# () H_INV# () H_P# T T OMP0 R0./F_ T OMP R./F_ F0 OMP R./F_ F OMP R./F_ H_PRSTP# (0,) H_PSLP# (0) H_PWR# () H_PWRG (0) H_PUSLP# (,0) MREF[] Layout note: omp0, connect with Zo=.ohm, make trace length shorter than 0." omp, connect with Zo=ohm, make trace length shorter than 0.". R R P N M P J N G H N L M J H J K K L M R R U V N T T R R R R0 R R0 R *K/F_H_NMI *K/F_H_SMI# *K/F_H_INTR *_ H_STPLK# *K_ H_PSLP# *K_ H_PRSTP# *K_ H_PWRG For defensive design reservation only in this initial release R *K_ H_PWR# R *K_ R K/F_ H_GTLREF R K/F_ 0 Layout note: Zo=ohm, 0." max for GTLREF R K/F_ EXTGREF R K/F_ u/0v_ Layout note: Zo=ohm, 0." max for EXTGREF R K/F_ PU_MREF R K/F_ 0 Layout note: Zo=ohm, 0." max for GTLREF R K/F_ H_# R0 K/F_ H_# R K/F_ H_# R K/F_ H_#.0V XP_TMS R _ XP_TI R _ XP_PM# R _ XP_TK R _ XP_TRST# R _ Size ocument Number Rev iamondville(/) Quanta omputer Inc. PROJET : EL ate: Friday, pril, 00 Sheet of

V.S_V TH_FN_POWER FNSIG_ FNSIG_.0V V_ORE.V V_ORE V_ORE V V VPU.0V VI0 () VI () VI () VI () VI () VI () VI () V_SENSE () VSS_SENSE () VFN () FNSIG () THERM_LERT# (,) Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : iamondville(/) Friday, pril, 00 EL Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : iamondville(/) Friday, pril, 00 EL Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : iamondville(/) Friday, pril, 00 EL PU- 0 PLE IN VITY PLE IN VITY PLE IN ORRIOR N LOSE TO PU 0m. egree Protection TO PWR FN 0 MIL Plan to remove in stage Fan module Q *N00E Q *N00E 0u/.V_ 0u/.V_ u/0v_ 0 u/0v_ 0 R 0R/ R 0R/ R *0K/F_ R *0K/F_ R *0_ R *0_ 0u/.V_ 0 0u/.V_ 0 0u/.V_ 0u/.V_ 0u/.V_ 0 0u/.V_ 0 *.u/.v_ *.u/.v_ u/0v_ u/0v_ 0u/.V_ 0u/.V_ 0u/0V_ 0u/0V_ u/0v_ u/0v_ u/0v_ u/0v_ U *G U *G FON# VIN VO VSET GN GN GN GN u/0v_ u/0v_ 0u/.V_ 0u/.V_ u/0v_ u/0v_ u/0v_ u/0v_ *0.0u/V_ 0 *0.0u/V_ 0 0u/.V_ 0u/.V_ u/0v_ u/0v_ u/0v_ u/0v_ 0 *000P/0V_ 0 *000P/0V_ u/0v_ 0 u/0v_ 0 0u/.V_ 0u/.V_ 0u/.V_ 0u/.V_ u/0v_ u/0v_ u/0v_ u/0v_ u/0v_ u/0v_ u/0v_ u/0v_ 0u/.V_ 0u/.V_ u/0v_ u/0v_ U iamondville_s_rev. U iamondville_s_rev. VQ VF V0 VP F VP E VP E VQ V VTT H VTT H VTT G VTT G VTT F VTT F VTT U VTT U VTT0 U VTT E VTT U VTT U0 VTT U VTT U VTT T VTT T VTT R VTT R VTT P VTT0 P VTT VTT N VTT N VTT M VTT M VTT L VTT L VTT K VTT K VTT J VTT0 J VTT VI[0] F VI[] VI[] E VI[] G VI[] G VI[] E VI[] G VSSSENSE VSENSE VP 0 VP VP VP 0 VP VP VP 0 VP VP VP0 0 VP VP VP E0 VP E VP E VP F0 VP L VP L VP L0 VP0 K VP K VP K0 VP J VP J VP J0 VP H VP H VP H0 VP G VP0 G VP G0 VP F VP F VP M0 VP M VP M VP N0 VP N VP N VP0 P0 VP P VP P VP R0 VP R VP R VP F 0u/.V_ 0u/.V_ u/0v_ u/0v_ P *0U-V E P *0U-V E u/0v_ u/0v_ N *FN N *FN 0u/.V_ 0u/.V_ u/0v_ u/0v_ *00P_ *00P_ R 0R/ R 0R/ u/0v_ u/0v_ 0 *.u/.v_ 0 *.u/.v_ u/0v_ 0 u/0v_ 0 0u/.V_ 0u/.V_ R *00K_ R *00K_ U iamondville_s_rev <NO_STUFF>. U iamondville_s_rev <NO_STUFF>. VSS VSS VSS VSS VSS 0 VSS VSS N VSS M VSS M VSS M VSS0 M VSS 0 VSS M VSS M VSS L VSS L VSS L VSS L VSS L VSS L VSS L VSS0 L VSS VSS L VSS L VSS K VSS K VSS K VSS K VSS K VSS K VSS K VSS0 J VSS VSS J VSS J VSS J VSS J VSS H VSS H VSS H VSS H VSS H VSS VSS H VSS H VSS H VSS G VSS G VSS G VSS VSS G VSS G VSS G VSS F VSS F VSS F VSS F VSS F VSS F VSS0 E VSS E VSS E VSS E VSS E VSS E VSS E VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS N VSS P VSS P VSS P VSS P VSS P VSS P VSS P VSS VSS P VSS P VSS P VSS P VSS R VSS R VSS R VSS R VSS R VSS0 R VSS 0 VSS T VSS T VSS T VSS T VSS T0 VSS T VSS T VSS T VSS T VSS0 U VSS VSS U VSS U VSS U VSS U VSS U VSS V VSS V VSS V VSS V VSS0 V VSS VSS V VSS V VSS V VSS V VSS W VSS W VSS W VSS W VSS W VSS0 W VSS VSS0 W VSS0 Y VSS0 Y VSS0 Y0 VSS0 Y VSS0 VSS0 VSS0 VSS0 VSS00 0 VSS0 VSS VSS N VSS0 N VSS N VSS N 0u/.V_ 0 0u/.V_ 0

GMS () H_#[:0] H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_XROMP 0 H_XSOMP H_XSWING H_YROMP J H_YSOMP K H_YSWING H H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_VREF H_VREF H_INV#0 H_INV# H_INV# H_INV# H_STN#0 H_STN# H_STN# H_STN# H_STP#0 H_STP# H_STP# H_STP# H_REQ#0 H_REQ# H_REQ# H_REQ# H_REQ# H_RS#0 H_RS# H_RS# H_#[:] () H_S# () H_ST#0 () H_ST# ().0V.0V H_XSWING H_YSWING H_NR# () 0mil wide, 0mil spacing H_PRI# () H_REQ#0 ().0V H_PURST# () H_PURST# has T topology LK_MH_LK# () LK_MH_LK () H_SY# () H_EFER# () H_INV#0 () H_INV# () H_INV# () H_INV# () H_PWR# () H_RY# () H_STN#0 () H_STN# () H_STN# () H_STN# () H_STP#0 () H_STP# () H_STP# () H_STP# () H_HIT# () H_HITM# () H_LOK# () H_REQ#[:0] () H_RS#[:0] () H_PUSLP# (,0) H_TRY# () 0mil wide, 0mil spacing H_VREF.0V./F_./F_./F_ 0mil wide, 0mil spacing./f_ 0mil wide, 0mil spacing Quanta omputer Inc. PROJET : Size ocument Number Rev GMS HOST ate: Friday, pril, 00 Sheet of 0 F H H F E K F J K H E K J J J N M K J H J N M M N N K N M V V R T R N N R U R T T R T V V W W V W W W V W U H0# H# H# H# H# H# H# H# H# H# H0# H# H# H# H# H# H# H# H# H# H0# H# H# H# H# H# H# H# H# H# H0# H# H# H# H# H# H# H# H# H# H0# H# H# H# H# H# H# H# H# H# H0# H# H# H# H# H# H# H# H# H# H0# H# H# H# HXROMP HXSOMP HXSWING HYROMP HYSOMP HYSWING HOST GMS H# H# H# H# H# H# H# H0# H# H# H# H# H# H# H# H# H# H0# H# H# H# H# H# H# H# H# H# H0# H# HS# HST0# HST# H_VREF HNR# HPRI# HREQ0# HPURST# HVREF HLKN HLKP HSY# HEFER# HINV0# HINV# HINV# HINV# HPWR# HRY# HSTN0# HSTN# HSTN# HSTN# HSTP0# HSTP# HSTP# HSTP# HHIT# HHITM# HLOK# HREQ0# HREQ# HREQ# HREQ# HREQ# HRS0# HRS# HRS# HPUSLP# HTRY# F E E J G F J E H G G E H E H G F0 H E G 0 E 0 H J T U G E F M T F M T G E G F G0 E E0 H_XSOMP R H_YSOMP R H_XROMP R H_YROMP R R /F_ R 00/F_ R /F_ R 00/F_ R 00/F_ R 00/F_ 0 * EL

M M M M0 M M M M M M M M M M M M M M M M M M0 M0 M M M0 M0 M M M M M M M M M M M M M M M M M M M M M M M M0 M M M M M M M0 M M M M M M QS QS QS- QS QM QS QM QM QS QS QS- QS- QS- QS0 QM QM QS0- QM QS- QS QS- QM QS- QM0 TP_S_RVENIN# TP_S_RVENOUT# GMS_FG S0 S S M M0 M M M M M0 M M M M M M M SRS# SS# SWE# M.0V.V V.0V QS () QM () QS () QM () QS () QM () QS () QS () QS0- () QS- () QS- () QS- () QS- () QS- () QS- () QS- () QM0 () QM () QS0 () QM () QS () QM () QS () QM () M[:0] () S[:0] () M[:0] () M () SS# () SRS# () SWE# () Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : GMS R Friday, pril, 00 EL Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : GMS R Friday, pril, 00 EL Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : GMS R Friday, pril, 00 EL GMS R GMS FG: LOW=Normal High=LNES REVERSE(GMS not support) 0 N P/N: JSLR0T00 R SYSTEM MEMORY U GMS R SYSTEM MEMORY U GMS S_Q0 S_Q S_Q E S_Q F S_Q S_Q S_Q S_Q E S_Q H S_Q K S_Q0 L S_Q K S_Q H0 S_Q L S_Q J S_Q J S_Q H S_Q F S_Q H S_Q F S_Q0 J S_Q G S_Q G S_Q G S_Q N S_Q M S_Q J S_Q J S_Q L S_Q N S_Q0 H S_Q G S_Q M S_Q L S_Q H S_Q K S_Q M S_Q K S_Q M S_Q K S_Q0 G S_Q F S_Q F S_Q K S_Q F S_Q G S_Q J S_Q H S_Q N S_Q M S_Q0 K S_Q L S_Q M S_Q L S_Q J S_Q J S_Q G S_Q F S_Q E S_Q F S_Q0 H S_Q G S_Q G S_Q F S_S# G S_RS# G S_WE# G0 S_M0 N0 S_M L S_M K S_M K S_M L S_M H S_M G S_M F S_M M S_M E S_M0 L0 S_M E S_M E S_M E0 S_S# J S_RS# K S_RVENIN N S_RVENOUT M S_WE H S_M0 J S_M M S_M M S_M H S_M K S_M N S_M J S_M F S_M N S_M L S_M0 G S_M L S_M G S_M L S_QS0# S_QS# K0 S_QS# J S_QS# M S_QS# N S_QS# J S_QS# M S_QS# E S_QS0 S_QS J0 S_QS K S_QS L S_QS N S_QS H S_QS M S_QS E S_M0 0 S_M L S_M F0 S_M K S_M L S_M G S_M K S_M H S_S_0 K S_S_ H S_S_ G S_S_0 H S_S_ J0 S_S_ E T T R *K_ R *K_ T T T0 T0 NTF UH GMS NTF UH GMS V_NTF T V_NTF R V_NTF P V_NTF N V_NTF M V_NTF P V_NTF N V_NTF M V_NTF Y V_NTF0 W V_NTF V V_NTF U V_NTF T V_NTF R V_NTF P V_NTF N V_NTF M V_NTF Y V_NTF W V_NTF0 V V_NTF U V_NTF T V_NTF R V_NTF P V_NTF N V_NTF M V_NTF Y0 V_NTF W0 V_NTF V0 V_NTF0 U0 V_NTF T0 V_NTF R0 V_NTF P0 V_NTF N0 V_NTF M0 V_NTF Y V_NTF P V_NTF N V_NTF M V_NTF0 Y V_NTF P V_NTF N V_NTF M V_NTF Y V_NTF P V_NTF N V_NTF M V_NTF Y V_NTF P V_NTF0 N V_NTF M V_NTF Y V_NTF P V_NTF N V_NTF M V_NTF Y VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF 0 VUX_NTF VUX_NTF0 VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF K VUX_NTF VUX_NTF Y VUX_NTF W VUX_NTF V VUX_NTF0 U VUX_NTF T VUX_NTF R VUX_NTF P VUX_NTF N VUX_NTF M VUX_NTF VUX_NTF Y VUX_NTF W VSS_NTF N VSS_NTF VSS_NTF V VSS_NTF U VSS_NTF VSS_NTF VSS_NTF 0 VSS_NTF VSS_NTF VSS_NTF0 VSS_NTF VSS_NTF VSS_NTF VTT_NTF T0 VTT_NTF R0 VTT_NTF P0 VTT_NTF N0 VTT_NTF L0 V_NTF W V_NTF V V_NTF U V_NTF0 T V_NTF R VUX_NTF V VUX_NTF0 U VUX_NTF T VUX_NTF R VUX_NTF P VUX_NTF N VUX_NTF M VUX_NTF VUX_NTF 0 VUX_NTF K0 V_NTF P V_NTF N V_NTF M VTT_NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF N VSS_NTF MH_RSV M0 MH_RSV MH_RSV 0 MH_RSV 0 FG K MH_RSV0 K MH_RSV K MH_RSV R MH_RSV T MH_RSV K MH_RSV K MH_RSV K0 MH_RSV K MH_RSV K MH_RSV J MH_RSV0 K MH_RSV K MH_RSV K MH_RSV K MH_RSV K MH_RSV K

MI, LVS, R LK () MI_TXN0 () MI_TXN () MI_TXP0 () MI_TXP () MI_RXN0 () MI_RXN () MI_RXP0 () MI_RXP () MLKO () MLKO () KE () KE () S# () S# () OT () OT MI_TXN0 MI_TXN MI_TXP0 MI_TXP MI_RXN0 MI_RXN MI_RXP0 MI_RXP T T T M_ROMP# M_ROMP R_VREF Y Y Y Y V V V V F G J M0 G F K N0 N N F F G F K H J F E F J J N N E U MI_RXN0 MI_RXN MI_RXP0 MI_RXP MI_TXN0 MI_TXN MI_TXP0 MI_TXP SM_K0 SM_K SM_K SM_K SM_K0# SM_K# SM_K# SM_K# SM_KE0 SM_KE SM_KE SM_KE SM_S0# SM_S# SM_S# SM_S# MI R MUXING FG/RSV SMOOMP0 SMOOMP IHSYN# M_USY# SM_OT0 EXT_TS0# SM_OT EXT_TS#/PRSLPVR SM_OT THRMTRIP# SM_OT PWROK RSTIN# SMROMPN SMROMPP SMVREF0 SMVREF REF_LKN REF_LKP REF_SSLKN REF_SSLKP LKREQ PM LK FG0 FG FG FG FG FG MH_RSV MH_RSV MH_RSV MH_RSV MH_RSV MH_SEL0 () E MH_SEL () G0 MH_SEL () G J0 GMS_FG J K K F FG RESERVE FG LOW MIX efault, HIGH MIX(GMS not support) FG RESERVE E G F R_PM_EXTTS#0 R H PM_EXTTS# R0 J W RST_IN#_MH R 00_ J H J R R R *.K_.K_ *.K_ MH_IH_SYN# () PM_MUSY# () *0_ PM_EXTTS#0 () *0_ PM_PRSLPVR (,) PM_THRMTRIP# (,0) IMVP_PWRG () PLTRST# (,,,,) REFLK# () REFLK () REFSSLK# () REFSSLK () MH_LKREQ# () () SVO_T () SVO_TLK () LK_PIE_GPLL# () LK_PIE_GPLL () INT_LVS_PWM () INT_LVS_LON () NE_LK () NE_T () INT_LVS_IGON () MLKO- () MLKO- () N_TXLLKOUT- () N_TXLLKOUT () N_TXLOUT0- () N_TXLOUT- () N_TXLOUT- () N_TXLOUT0 () N_TXLOUT () N_TXLOUT SVO_T SVO_TLK R L_TL_LK L_TL_T L_IG.K/F_ H J Y H0 H E F F H H0 G F E G H K0 K J J0 K 0 0 0 G F H G F F0 E F UF SVOTRL_T SVOTRL_LK GLKN GLKP LK T LUE LUE# GREEN GREEN# RE RE# VSYN HSYN REFSET LKLT_TRL LKLT_EN LTL_LK LTL_LK L_LK L_T LV_EN LIG LVG LVREFH LVREFL LLKN LLKP LLKN LLKP LTN0 LTN LTN LTP0 LTP LTP LTN0 LTN LTN LTP0 LTP LTP MIS LVS VG EXP_OMPI EXP_IOMPO SV0_TVLKIN# SVO_INT# SVO_FLSTLL# SVO_TVLKIN SVO_INT SVO_FLSTLL SVO SVO_RE# SVO_GREEN# SVO_LUE# SVO_LKN SVO_RE SVO_GREEN SVO_LUE SVO_LKP TV TV_ TV_ TV_ TV_REFSET TV_IRTN TV_IRTN TV_IRTN TV_ONSEL0 TV_ONSEL V.S_PIE R R PEG_OMP M./F_ N0 R0 T M0 P0 T0 P N P T SVO_TVLKN SVO_INTN SVO_STLLN SVO_TVLKP SVO_INTP SVO_STLLP SVO REN SVO GREENN SVO LUEN SVO LOKN N SVO REP M SVO GREENP P SVO LUEP R SVO LOKP 0 E0 G G J.V T T SVO_STLLN () T T SVO_STLLP () SVO REN () SVO GREENN () SVO LUEN () SVO LOKN () SVO REP () SVO GREENP () SVO LUEP () SVO LOKP () 0 GMS N P/N: JSLR0T00 V GMS.u/.V_ M_ROMP# M_ROMP R R0 0./F_ 0./F_.VSUS R R R R R 0K_ R_PM_EXTTS#0 *0K_ PM_EXTTS# 0K_ MH_LKREQ# 0K_ L_TL_LK 0K_ L_TL_T modify / Quanta omputer Inc. PROJET : EL Size ocument Number Rev GMS LVS, MI, R LK ate: Friday, pril, 00 Sheet of

V.S_VHY.0V.V.0V.V.V V.VSUS.0V.V V._RT.V.V V.S_GPLL V.S_PIE.V.V V.S_PLL V.S_PLL V.S_HPLL V.S_MPLL.V V.S_PLL V.S_PLL V.S_HPLL V.S_MPLL.V V.S_PIE V.S_GPLL.0V.V V._RT.0V.VSUS Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : GMS POWER Friday, pril, 00 EL Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : GMS POWER Friday, pril, 00 EL Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : GMS POWER Friday, pril, 00 EL GMS POWER PLE IN VITY ISLE TV PLE IN VITY PLE LOSE TO GMH 0 00m. 0. m 0m 0m 0m 0m 0m 0m m 0m 0m m 0m.. 0mils place under G * c,c,c,c under 0and inner * * c0,c0 under 0 inner * * c0,c0 under inner * * c,c under inner * modify / modify / modify / modify / L LMPGSN_ L LMPGSN_ 0U/.V_R_ 0U/.V_R_ 0u/0V_ 0 0u/0V_ 0 0u/0V_ 0 0u/0V_ 0 0u/0V_ 0 0u/0V_ 0.u/0V_.u/0V_ 0u/0V_ 0u/0V_ L LMPGSN_ L LMPGSN_.u/0V_.u/0V_ u/.v_ u/.v_.u/0v_ 0.u/0V_ 0.u/0V_.u/0V_ u/0v_ 0 u/0v_ 0 POWER U GMS POWER U GMS V0 T V R V P V N V M V V V U V T V W V V V0 T V R V_HMPLL E V_HMPLL V_PLL V_PLL J V_HPLL V_MPLL V_RT0 V_RT VSS_RT V_SYN J VTT0 VTT 0 VTT P VTT L VTT VTT P VTT L VTT VTT P VTT L VTT0 VTT VTT P VTT L VTT G VTT VTT U VTT P VTT L VTT G VTT0 V_GG N VSS_GG M V_GPLL V VG0 U VG T VTX_LVS VSM0 VSM M VSM N VSM M VSM L VSM K VSM J VSM H VSM G VSM F VSM0 E VSM N VSM M VSM L VSM K VSM J VSM H VSM G VSM F VSM E VSM0 N VSM N VHV0 E VHV VHV V_LVS V_LVS0 V_LVS V_LVS V_TV F0 VQ_TV F V_TVG VSS_TVG E V_TV0 0 V_TV 0 V_TV0 V_TV V_TV0 V_TV V W V U V R V W V V V T V R V V V0 U V T V_UX V_UX V_UX V_UX 0 V_UX V_UX V_UX V_UX V_UX V_UX0 V_UX V_UX E V_UX E V_UX F V_UX E V_UX F V_UX E V_UX F V_UX E V_UX0 J V_UX J0 V_UX V_UX V_UX VTX_LVS0 VSM M VSM L VSM K VSM J VSM N VSM M VSM L VSM K VSM0 J VSM H VSM G VSM F VSM E VSM N VSM M0 VSM L0 VSM K0 VSM H VSM0 H0 VSM G0 VSM F0 VSM E0 VSM N VTT U VTT P VSM M VTT L VTT G VTT VTT Y VTT U VTT P VTT0 L VTT G VTT VTT Y VTT U VTT L VTT P VTT G VTT VTT VTT Y V_UX H0 V_UX E V_UX V_UX U VSSLVS VTT U VTT P VTT L VTT G VTT0 F VSM L VSM K VSM J VSM H VSM0 N0 VSM J0 VTT Y 0u/0V_ 0u/0V_ R *0_ R *0_ 0u/.V_ 0u/.V_ 0u/0V_ 0 0u/0V_ 0 L LMPGSN_ L LMPGSN_ 0.u/.V_ 0.u/.V_ u/0v_ u/0v_ 0u/.V_ 0u/.V_ 0u/.V_ 0u/.V_ 0.u/.V_ 0.u/.V_ *0u/.V_ *0u/.V_ 0u/0V_ 0u/0V_.u/0V_ 0.u/0V_ 0 0 0 0u/0V_ 0u/0V_ 0 0 0.0u/V_ 0.0u/V_ H00H-0 H00H-0 R0 0_ R0 0_ u/0v_ u/0v_ u/0v_ u/0v_ 0.u/.V_ 00 0.u/.V_ 00 u/0v_ u/0v_ 0u/0V_ 0 0u/0V_ 0 u/.v_ u/.v_ u/0v_ u/0v_ 0 0 0.0u/V_ 0 0.0u/V_ 0.u/0V_.u/0V_ 0.u/.V_ 0.u/.V_ 0u/0V_ 0u/0V_ u/.v_ u/.v_ u/.v_ u/.v_ 0u/0V_ 0u/0V_ L0 LMPGSN_ L0 LMPGSN_ L nh L nh 0u/0V_ 0u/0V_ 0u/0V_ 0u/0V_.u/0V_.u/0V_ 0u/0V_ 0u/0V_ L LMPGSN_ L LMPGSN_ L LMPGSN_ L LMPGSN_ 0u/0V_ 0u/0V_

Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : GMS GN Friday, pril, 00 EL Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : GMS GN Friday, pril, 00 EL Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : GMS GN Friday, pril, 00 EL GMS GN 0 N UG GMS N UG GMS N W N M N L N N N N N N N N W N0 V N W N J N H N W N G N F N E N N K N0 N E N N N N M N L N N N0 Y N J N H N G N F N E N N N N G N F N E N N N N N N Y N0 M N F N N L N K N H N G N E N0 M N Y N L N Y N W0 MH_RSV Y MH_RSV Y MH_RSV MH_RSV MH_RSV0 MH_RSV MH_RSV MH_RSV MH_RSV W MH_RSV MH_RSV MH_RSV 0 MH_RSV MH_RSV MH_RSV0 MH_RSV N H N K N J N N0 Y N N W N J MH_RSV N Y0 N W0 N W N V N U N0 V0 N U0 N K VSS UE GMS VSS UE GMS VSS H VSS Y VSS V VSS R VSS K VSS G VSS E VSS VSS0 VSS U VSS H VSS E VSS VSS M VSS J VSS VSS U VSS T VSS0 R VSS P VSS N VSS M VSS J VSS F VSS L0 VSS G0 VSS E0 VSS 0 VSS0 0 VSS Y0 VSS V0 VSS U0 VSS G0 VSS E0 VSS 0 VSS VSS U VSS R VSS0 P VSS N VSS M VSS H VSS E VSS VSS K VSS H VSS E VSS VSS0 U VSS T VSS J VSS VSS M VSS F VSS VSS VSS Y VSS U VSS0 T VSS R VSS P VSS N VSS M VSS G VSS VSS VSS L VSS W VSS U VSS N VSS K VSS J VSS G VSS VSS0 H VSS F VSS J VSS L VSS G VSS W VSS R VSS F VSS VSS M VSS H VSS0 E VSS H VSS VSS F VSS VSS L VSS G VSS H VSS VSS N VSS0 J VSS E VSS M VSS VSS W VSS R VSS M VSS J VSS F VSS0 VSS VSS L VSS G VSS E VSS U VSS VSS V VSS R VSS N VSS0 H VSS E VSS VSS L VSS G VSS E VSS VSS W VSS T VSS M VSS0 K VSS N VSS J VSS VSS VSS V VSS R VSS N VSS K VSS H VSS0 E VSS L VSS VSS W VSS T VSS G VSS J VSS VSS K VSS H VSS F VSS VSS0 M VSS K VSS H VSS F VSS V VSS R VSS E VSS0 H VSS G VSS E VSS VSS J VSS F VSS G VSS M VSS E VSS J VSS H VSS0 F VSS M0 VSS00 F VSS H VSS M VSS W VSS 0 VSS F0 VSS K0 VSS H0 VSS R VSS0 U VSS0 H VSS0 VSS0 K VSS0 V VSS0 T VSS0 F VSS0 VSS0 H VSS0 U

IHM H O Z_SOUT Z_SYN Z_RST# Z_LK p/0v_ 0 Y.KHZ SIN0:OE p/0v_ () Z_SIN0 T (0) ST_RXN0 (0) ST_RXP0 (0) ST_TXN0 (0) ST_TXP0 LK_KX LK_KX R 0M_ RTRST# SM_INTRUER# IH_INTVRMEN Z_SIN0 Z_SIN Z_SOUT 00P_ 0 Z_LK Z_SYN Z_RST# ST_TXN0_ ST_TXP0_ (0) ST_RXN (0) ST_RXP ST_TXN_ (0) ST_TXN ST_TXP_ (0) ST_TXP 00P_ 00P_ () LK_PIE_ST# 00P_ () LK_PIE_ST R _ R _ R _ 0 *0p/0V_ *0p/0V_ *0p/0V_ Y W W Y Y W V U U V T U V V U R R T T T T F F E G H F E G H F E./F_ H0 R ST_IS G0 Place within 00 mils of IH mils/mils F H F IRQ# H PIORY G E R _ U RTX RTX RTRST# INTRUER# INTVRMEN EE_S EE_SHLK EE_OUT EE_IN LN_LK LN_RSTSYN LN_RX0 LN_RX LN_RX LN_TX0 LN_TX LN_TX Z_IT_LK Z_SYN Z_RST# Z_SIN0 Z_SIN Z_SIN Z_SOUT STLE# ST0RXN ST0RXP ST0TXN ST0TXP STRXN STRXP STTXN STTXP ST_LKN ST_LKP STRISN STRISP IOR# IOW# K# IEIRQ IORY REQ IH-M Z_SOUT_UIO () Z_SYN_UIO () Z_RESET#_UIO () Z_ITLK_UIO () RT LP LN PU -/ZLI ST IE S P/N: JSLY0T0 Enable (default) isable L0 L L L LRQ0# LRQ#/GPIO LFRME# 0GTE 0M# PUSLP# TP/PRSTP# TP/PSLP# FERR# GPIO/PUPWRG IGNNE# INIT_V# INIT# INTR RIN# NMI SMI# 0 0 0 S# S# INTVRMEN IH internal VR enable strap 0 Y E H G F H G G G G F F G H F E G F E F F H H H E F E LRQ#0 LRQ# G0 RIN# TP_H_PUSLP# R *0_ place near IHM H_PRSTP#_R H_PSLP#_R R R *0_ *0_ R./F_ H_SMI#_R VRT R T LP0 (,) LP (,) LP (,) LP (,) LPRQ# LPFRME# (,) R *0_ *0_ IH_INTVRMEN R0 *0_ G0 () H_0M# () H_PUSLP# (,) H_PRSTP# (,) H_PSLP# ().0V H_FERR# () H_PWRG () H_IGNNE# () H_INIT# () H_INTR () RIN# () H_NMI () H_SMI# () STPLK# H H_STPLK# () R0./F_ R.0V H_THERMTRIP_R./F_ THERMTRIP# F PM_THRMTRIP# (,) Should be " close IH R K/F_ Pull-UP RT VRT_ VPU H00H-0 VRT_ 0MIL GSE LRQ#0 LRQ# RIN# G0 PIORY IRQ# H00H-0 R00 K_ T R0-SOKET OMPONENTS IH-M VRT ate: Friday, pril, 00 Sheet 0 of V RTRST# SM_INTRUER# Quanta omputer Inc. PROJET : EL Size ocument Number Rev IH-M (PU, ST, IE,LP) 0MIL Modified 00/0/ RT attery P/N: HL00000 N0 0K_ 0K_ 0K_ 0K_ M_ u/0v_ P/N JSLVT0 JSLR0T00 JSLY0T0 0 R R R R R R0 R0 0K/F_ R0 u/0v_ *.K_ *.K_ G *SHORT_P

LN Mini card INT# INT# INT# INT# caps within 0mils () () () () () () () () T T T T T U E 0 F E E E 0 G G E 0 0 F F0 E E 0 E G H PERX- PERX PETX- PETX PERX- PERX PETX- PETX Remove 0 by Jimmy V_S V_S V R0 0K_ PI 0 R 0K_ R0 0K_ R 0K_ R 0K_ Interrupt I/F PIRQ# PIRQ# PIRQ# PIRQ# RSV[] RSV[] RSV[] RSV[] RSV[] IH-M MIS REQ0# GNT0# REQ# GNT# REQ# GNT# REQ# GNT# REQ#/GPIO GNT#/GPIO GPIO/REQ# GPIO/GNT# /E0# /E# /E# /E# IRY# PR PIRST# EVSEL# PERR# PLOK# SERR# STOP# TRY# FRME# PIE_TXN_ PIE_TXP_ E E F E0 E 0 F F F PIE_TXN_ PIE_TXP_ SPI_SLK SPI_E# SPI_R SPI_SI SPI_SO O0# O# O# O# O# O# O# O# REQ0# GNT0# REQ# GNT# REQ# GNT# REQ# REQ# REQ# IRY# EVSEL# PERR# PLOK# SERR# STOP# TRY# FRME# PLK_IH R *_ U F PERn F PERp E PETn E PETp H H G G K K J J M M L L P P N N T T R R R P P P P E PERn PERp PETn PETp PERn PERp PETn PETp PERn PERp PETn PETp PERn PERp PETn PETp PERn PERp PETn PETp SPI_LK SPI_S# SPI_R SPI_MOSI SPI_MISO IH-M T T T T T PI-Express SPI O0# O# O# O# O# O#/GPIO O#/GPIO0 O#/GPIO T 0 *0p/0V_ oot IOS select GNT, 0: SPI 0: PI : LP (efault) T irect Media Interface US MI0RXN MI0RXP MI0TXN MI0TXP MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP MI_LKN MI_LKP MI_ZOMP MI_IROMP USP0N USP0P USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP REQ# REQ# REQ# IRY# REQ0# SERR# INTG# INTE# INTF# INTH# R.V RI_IROMP_R./F_ Place within 00 mils of IH US_RIS_PN USRIS# R0./F_ USRIS mils/mils Place within 00 mils of IH V V V V V U U Y Y W W E E /mils F F G G H H J J K K L L M M N N MI_RXN0 () MI_RXP0 () MI_TXN0 () MI_TXP0 () MI_RXN () MI_RXP () MI_TXN () MI_TXP () LK_PIE_IH# () LK_PIE_IH () USP0- () USP0 () USP- () USP () USP- () USP () USP- () USP () USP- () USP () USP- () USP () USP- () USP () USP- () USP () Pull-UP resistor 0 0 RP RP.K_0PR.K_0PR Port Port Port PORT WLN PORT ard reader V TRY# STOP# FRME# REQ# V EVSEL# PLOK# PERR# REQ# V INT# INT# INT# INT# PLT_RST-R# PLTRST# PLT_RST-R# () PLK_IH PILK PLK_IH () PME# () KL use 0Kohm PME# V INTE# Platform Reset GPIO/PIRQE# G INTF# GPIO/PIRQF# F INTG# U GPIO/PIRQG# F INTH# GPIO/PIRQH# G PLT_RST-R# Stuff for XOR chain testing PLTRST# (,,,,) RSV[] E R0 RSV[] G *K/F_ R RSV[] H IH_TP TSH0FU RSV[] F 00K_ MH_SYN# H0 MH_IH_SYN# () 0 RP0.K_0PR 0 0 E E E E E F F F F F F G G G G G G G G G G G H H H H H H J J J J J J K K K L L L L L M M M M M M M M M M M M N N N N N N N N N N N N N N N P P P P P P P P P P VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] P R R R R R R R R R T T T T T T T U U U U U U U U U U V V V V V V W W W W Y Y Y Y E E E E E E E E E F F F F F F G G G G G G G0 G H H H H H H UE IH-M Quanta omputer Inc. PROJET : EL Size ocument Number Rev IH-M (US & MI & PIE & PI) ate: Friday, pril, 00 Sheet of

PT_SM S_WKE# PLK_SM SERIRQ LKRUN# PM_SYSRST# PM_TLOW#_R NSWON# SM_LERT# RI# L_LK SMLINK0 KSMI# SMLINK VS_IH_SUS VS_IH_SUS TPVSUSLN TPVSUSLN VREF GPLL_R_L VREF_SUS TP_IHVSUS TP_IHVSUS TP_IHVSUS VREF VREF_SUS.V_PIE_IH GPLL_R GPLL_R_L E_RSMRST# RYI RYI0 M_IH LKUS_ IH_PWROK E_SI# IOS_PW_SW# RISS_OOT# RYI0 RYI RISS_OOT# PT_SM LP_P# PM_TLOW#_R LKRUN# SMLINK0 SERIRQ S_WKE# VR_PWRG_K0 SMLINK E_SI# KSMI# L_LK NSWON# PM_RSMRST# M_IH LKUS_ PM_PRSLPVR SM_LERT# IH_PWROK RI# PM_SYSRST# PLK_SM IOS_PW_SW# SWI# RYI RYI0 MI MI MI MI MI MI MI MI MI V_S V V_S V V.V.V.V.V.V.V V_S VRT V_S V.0V V V V.0V V.V_PIE_IH V V V_S V_S.V.V_PIE_IH.V V_S V V V VPU VPU EPWROK () VR_PWRG_K0# () VR_PWRG_K0 () SMK () SMT () S_EEP () PM_SYSRST# () PM_MUSY# () PM_STPPI# () PM_STPPU# () SERIRQ () S_WKE# (,) THERM_LERT# (,) E_SI# () E_SMI# () SWI# () M_IH () LKUS_ () SUS# () SUS# () PM_PRSLPVR (,) NSWON# () PLTRST# (,,,,) E_RSMRST# () IOS_WP# () LN_ON_S () Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : IH-M (POWER & GN) Friday, pril, 00 EL Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : IH-M (POWER & GN) Friday, pril, 00 EL Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : IH-M (POWER & GN) Friday, pril, 00 EL 0mils S:m S:m S:0m S:m S:0m S:0m S:0m S:0m S:0m S:0m S:0m S:0m S:0m S:m S:u /mils /mils L:00m S:0m 0mils L:m 0mils S:0m VR PWRG IH PWROK LK GEN & PWR GPIO /Suspend rail is a HW strap, don't pull down. Rev. : Low W/ on board memory HIGH W/O on board memory GPIO Low pcs HIGH pcs GPIO Modify 0 for I SW Model I from EL MI MI MI MI 0 ER 0 xp e Machines Winnodws Linux Free OS 0 0 0 0 0 0 Packard ell Gateway Modify / OFF== Hi On= 0= Low GP GP GP GP Modify 00 0u/0V_ 0u/0V_ T T R _ R _ 0 0 T T ST SM SYS GPIO GPIO GPIO locks Power MGT U IH-M ST SM SYS GPIO GPIO GPIO locks Power MGT U IH-M GPIO/ST0GP F GPIO/STGP H GPIO/STGP H GPIO/STGP E SMLK SMT LINKLERT# SMLINK0 SMLINK SPKR SUS_STT# SYS_RST# GPIO0/M_USY# GPIO GPIO GPIO E GPIO E0 GPIO0 0 GPIO/SMLERT# GPIO F GPIO E GPIO R GPIO E GPIO/STPPI# 0 GPIO0/STPPU# F GPIO R GPIO 0 GPIO/LKRUN# G GPIO/Z_OK_EN# GPIO/Z_OK_RST# U GPIO GPIO 0 GPIO E0 WKE# F0 SERIRQ H THRM# F0 VRMPWRG LK LK SUSLK 0 SLP_S# SLP_S# SLP_S# F PWROK GPIO/PRSLPVR TP0/TLOW# PWRTN# LN_RST# RSMRST# Y RI# GPIO GPIO GPIO E R00 *0_ R00 *0_ R 00K/F_ R 00K/F_ T T 0.0u/V_ 0.0u/V_ H00H-0 H00H-0 R *_ R *_ * * 0 H00H-0 0 H00H-0 R0 K_ R0 K_ R *0_ R *0_ R *0K_ R *0K_ u/0v_ u/0v_ *0p/0V_ *0p/0V_ R 0K_ R 0K_ R0 0K_ R0 0K_ 0u/.V_ 0u/.V_ 0 0 0u/0V_ 0u/0V_ R *0_ R *0_ R *0K_ R *0K_ 0 u/0v_ 0 u/0v_ Q N00E Q N00E R 0K_ R 0K_ 0u/0V_ 0u/0V_ R 00/F_ R 00/F_ T T 0 0 T T R 0K_ R 0K_ T T R *00K_ R *00K_ R 0K_ R 0K_ R *.K_ R *.K_ T T 0 0 R.K_ R.K_ T T R 00/F_ R 00/F_ T T R 0K_ R 0K_ R 0K_ R 0K_ 0 0 00 00 R *K/F_ R *K/F_ R *0_ R *0_ T0 T0 R 0K_ R 0K_ R 00K/F_ R 00K/F_ R *0_ R *0_ R 0_ R 0_ R *0K_ R *0K_ R.K_ R.K_ R *0K_ R *0K_ 0 0 JP *JP JP *JP R *0K_ R *0K_ R0 *0_ R0 *0_ ORE VGP V PUX US TX RX IE US ORE PI UF IH-M ORE VGP V PUX US TX RX IE US ORE PI UF IH-M VREF[] G0 VREF[] VREF_Sus F Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [0] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] E Vcc [] E Vcc [] E Vcc [] F Vcc [] F Vcc [0] G Vcc [] G Vcc [] H Vcc [] H Vcc [] J Vcc [] J Vcc [] K Vcc [] K Vcc [] L Vcc [] L Vcc [0] M Vcc [] M Vcc [] N Vcc [] N Vcc [] P Vcc [] P Vcc [] R Vcc [] R Vcc [] R Vcc [] R Vcc [0] R Vcc [] T Vcc [] T Vcc [] T Vcc [] T Vcc [] T Vcc [] U Vcc [] U Vcc [] V Vcc [] V Vcc [0] W Vcc [] W Vcc [] Y Vcc [] Y Vcc_[] VccMIPLL G Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] E Vcc [] F Vcc [] F Vcc [] G Vcc [] H VccSTPLL Vcc_[] H Vcc [0] 0 Vcc [] Vcc [] 0 Vcc [] 0 Vcc [] E0 Vcc [] F0 Vcc [] F Vcc [] G Vcc [] H VccUSPLL VccSus_0/VccLN_0[] VccSus_0/VccLN_0[] Y Vcc_0[] L Vcc_0[] L Vcc_0[] L Vcc_0[] L Vcc_0[] L Vcc_0[] L Vcc_0[] M Vcc_0[] M Vcc_0[] P Vcc_0[0] P Vcc_0[] T Vcc_0[] T Vcc_0[] U Vcc_0[] U Vcc_0[] V Vcc_0[] V Vcc_0[] V Vcc_0[] V Vcc_0[] V Vcc_0[0] V VccSus_/VccLN_[] V VccSus_/VccLN_[] V VccSus_/VccLN_[] W VccSus_/VccLN_[] W Vcc_/VccH U VccSus_/VccSusH R V_PU_IO[] E V_PU_IO[] E V_PU_IO[] H Vcc_[] Vcc_[] Vcc_[] 0 Vcc_[] Vcc_[] Vcc_[] Vcc_[] G Vcc_[0] G Vcc_[] G Vcc_[] Vcc_[] Vcc_[] Vcc_[] Vcc_[] 0 Vcc_[] Vcc_[] F Vcc_[] G Vcc_[0] G Vcc_[] G VccRT W VccSus_[] P VccSus_[] VccSus_[] VccSus_[] VccSus_[] VccSus_[] G VccSus_[] K VccSus_[] K VccSus_[] K VccSus_[0] K VccSus_[] L VccSus_[] L VccSus_[] L VccSus_[] L VccSus_[] L VccSus_[] M VccSus_[] M VccSus_[] N Vcc [] Vcc [0] Vcc [] T Vcc [] F Vcc [] G Vcc [] Vcc [] VccSus_0[] K VccSus_0[] VccSus_0[] G0 Vcc [] Vcc [] H Vcc [] H Vcc [] J Vcc [0] J VccSus_[] E R 00/F_ R 00/F_ R.K_ R.K_ R 0K_ R 0K_ R 0K_ R 0K_ R _ R _ L uh_ L uh_ ON N *IPX SW-NHS-0-V-P-Og HNHS000 ON N *IPX SW-NHS-0-V-P-Og HNHS000 T0 T0 R0 0K_ R0 0K_ R 0K_ R 0K_ R 0K_ R 0K_ R0 00K_ R0 00K_ 0 0 R0 0K_ R0 0K_ u/0v_ u/0v_ 0 0 *0p/0V_ *0p/0V_ 0 u/0v_ 0 u/0v_ R 00K/F_ R 00K/F_ R 0/F_ R 0/F_.u/0V_.u/0V_ L LMPGSN_ L LMPGSN_ R 0K_ R 0K_ R0 0K_ R0 0K_ R 0K_ R 0K_ R 00/F_ R 00/F_ R *0K_ R *0K_ R.K_ R.K_ R *0_ R *0_ T T R 0K_ R 0K_ R 00K/F_ R 00K/F_

M QM M S M QM M S SS# M0 M QM SMT M0 QM SWE# M S0 M M M S# M OT M0 QM0 M QM M M M M SRS# M M M M0 M M QM QM QS- QS M M0 M M M M M M0 M M M M M M M M M M M PM_EXTTS#0 M M M M M M0 M M M0 M M M M M M M QS0- QS0 QS- QS M M M M M M M M M M M M M0 M M M M M M QS- QS QS QS- QS QS- QS QS- QS- QS S# S# OT KE KE OT S SRS# M0 M M M M M M M M SWE# S0 SS# S M M0 M M M SMK.VSUS.VSUS V.VSUS R_VREF V.VSUS V VTERM VTERM VTERM R_VREF VTERM QS0- () QS0 () QS- () QS () QS- () QS () KE () S# () OT () QS- () QS () QS- () QS () SMT (,) SMK (,) MLKO () MLKO- () PM_EXTTS#0 () QS- () KE () OT () QS () S# () QS- () QS () MLKO () MLKO- () QS- () QS () M () KE () KE () OT () S# () S# () M0 () SRS# () S () OT () S0 () M () M () M () S () M () M0 () M () M () M () M () M () M () M () SWE# () SS# () QM[:0] () M[:0] () M[:0] () Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R SO-IMM(00P) Friday, pril, 00 EL Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R SO-IMM(00P) Friday, pril, 00 EL Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R SO-IMM(00P) Friday, pril, 00 EL lose to IMM LOK, SMbus address KE, Termination resistor Standard Type H: mm P/N:GMK00000 *P/0V_ *P/0V_.u/.V_.u/.V_ 0.u/.V_ 0.u/.V_.u/.V_.u/.V_.u/.V_.u/.V_ RN X_ RN X_ *P/0V_ *P/0V_ RN X_ RN X_ RN X_ RN X_ R 0K_ R 0K_ R SRM SO-IMM (00P) N S0-NFSK-F R SRM SO-IMM (00P) N S0-NFSK-F VREF VSS Q0 Q VSS QS#0 QS0 VSS Q Q VSS Q Q VSS QS# QS VSS Q0 Q VSS0 VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS M N VSS Q Q VSS KE0 V N _ V V 0 V0 0 0/P 0 0 0 WE# 0 V S# S# V OT VSS Q Q VSS QS# QS VSS Q Q VSS Q0 Q VSS Q Q VSS M0 0 VSS Q Q VSS Q 0 Q VSS M VSS K0 0 K0# VSS Q Q VSS 0 VSS0 Q0 Q VSS N 0 M VSS Q Q VSS 0 Q Q VSS QS# QS 0 VSS0 Q0 Q VSS KE 0 V V 0 V 00 0 0 V 0 0 RS# 0 S0# 0 V OT0 V N 0 VSS Q Q VSS M 0 VSS Q Q VSS Q 0 Q VSS VSS M VSS Q Q VSS0 Q Q VSS NTEST VSS0 QS# QS VSS Q0 Q Q Q VSS M VSS Q Q VSS S SL V(SP) QS# QS VSS 0 Q Q VSS Q Q 0 VSS K K# VSS M 0 VSS Q Q VSS Q0 0 Q VSS QS# QS VSS 0 Q Q VSS S0 S 00 VSS VSS 0 VSS0 0 R 0K_ R 0K_.u/.V_.u/.V_.u/.V_.u/.V_ 0 0 RN X_ RN X_ RN X_ RN X_ *P/0V_ *P/0V_ *P/0V_ *P/0V_ 00 00 RN X_ RN X_ *P/0V_ *P/0V_ *P/0V_ *P/0V_.u/.V_.u/.V_ RN X_ RN X_ RN0 X_ RN0 X_.u/.V_.u/.V_ RN X_ RN X_ *P/0V_ *P/0V_

V R 0K_ R *0K V () PHL_T () PHL_LK Hi:write protection Lo:can write data Serial EEPROM U V 0 W# SL S GN 0 EMI R 0K_ 000P/0V_ V V R 0K_ ON R0 *POLY_SWITH 0 KZ00TFU0 LV *0u/0V_ * 0 TXLLKOUT- (,) TXLLKOUT (,) () USP- US F# () USP US F TXLOUT (,) 0 TXLOUT- (,) L *WM0-0 S_TXLOUT- () S_TXLOUT () (,) TXLOUT0- (,) TXLOUT0 (,) TXLOUT- (,) TXLOUT 000P/0V_ 0 L ONNETOR L MOULE VSUS MER POWER _POWER L_ON0-00x-0p-ldv US/ F *0.U *PESV0U *PESV0U *0.U *0-00 N -00-P-L FH0MR From ELV N L POWER SWITH () INT_LVS_IGON PR *0_ V 0.U/0V_ Q IN IN ON/OFF OUT GN GN L PWR_L_R FMJHM0 LV M/ US cable () IGON PR *0_ R 00K_ GTU GTU:L00000 OZ0I:L000000 0u/V_0 TO INVERTER POWER () L_ON () INT_LVS_LON () LON / modify SS PR0 *0_ PR *0_ V R 0K/F_ V R 00K_ KLIGHT ONTROL ISPON U TSH0FU N 0 ISPON VJ- () INT_LVS_PWM () ONTRST R VIN_L L *0_ VJ- F 0 0u/V_0 0.U_00 *0_ *000P/0V_ R0 EMI 0.U_00 EMI ISPON *000P/0V_ VIN 0u/V_0 Quanta omputer Inc. PROJET : EL Size ocument Number Rev LVS/luetooth ate: Friday, pril, 00 Sheet of

H H H H H (,) S_TXLLKOUT- (,) S_TXLLKOUT (,) S_TXLOUT- (,) S_TXLOUT (,) S_TXLOUT0- (,) S_TXLOUT0 (,) S_TXLOUT- (,) S_TXLOUT 0X_ 0X_ 0X_ 0X_ RN RN RN RN TXLLKOUT- TXLLKOUT TXLOUT- TXLOUT TXLOUT0- TXLOUT0 TXLOUT- TXLOUT TXLLKOUT- (,) TXLLKOUT (,) TXLOUT- (,) TXLOUT (,) TXLOUT0- (,) TXLOUT0 (,) TXLOUT- (,) TXLOUT (,) H-SP- H-SP- H-SP- H-SP- H-SP- H H-SP- H H-SP- () N_TXLLKOUT- () N_TXLLKOUT () N_TXLOUT- () N_TXLOUT () N_TXLOUT0- () N_TXLOUT0 () N_TXLOUT- () N_TXLOUT H h-cd0p () NE_LK () NE_T PHL_LK () PHL_T () () S_LK () S_T WLN SREW Note:lose to LVS NN:ON H h-cd0p- H h-cd0p- RN *0X_ *0X_ RN H h-cd0p H0 h-cd0p- *0X_ *0X_ RN *0X_ RN0 0X_ RN H h-cd0p- RN PU SREW Modify footprint 00/0/0 by Jimmy:h-cd0p- NUT is the same as JR:MJR0000 Quanta omputer Inc. PROJET : EL Size ocument Number Rev LVS ridge/holes ate: Friday, pril, 00 Sheet of

US on M/ () USP0- () USP0 Port RER USx K Side Port The same as EL PLE NER ONN L *WM0-0 PESV0U PESV0U US_0_F# US_0_F US F# US F N 0 X US 0 USV 00U/.V USV 00U/.V 0 mil F VSUS R0 POLY_SWITH KZ00TFU0 0 mil F VSUS R0 POLY_SWITH KZ00TFU0 () () USP- USP Port L *WM0-0 PESV0U PESV0U () () USP- USP USP- USP RER USx K Side Port The same as P Little board US F# US F ON GN GN GN GN GN USV 00U/.V R0 0 mil F VSUS POLY_SWITH KZ00TFU0 () () USTP- USTP USP- USP R R *0_ *0_ () () Port USP- USP Port RER USx L *WM0-0 L *WM0-0 Left Side Port PESV0U PESV0U PESV0U 0 PESV0U US F# US F The same as PF US OR / modify / modify US FH0MR00 usb-00mr00s0zr-p-l-v N US FHS0FR usb-c0-x0xx-x-p-r-v USV 00U/.V USV R0 0 mil F VSUS POLY_SWITH KZ00TFU0 0 mil F VSUS *touch panel connector USTP- USTP *WM0-0 L VSUS *PESV0U FOR EMI *PESV0U *0.u/V_ US TP# US TP *0-00 N -00-P-L () () USP- USP Port RER USx Left Side Port L *WM0-0 PESV0U PESV0U US F# US F The same as PF US OR / modify N US FHS0FR usb-c0-x0xx-x-p-r-v 00U/.V R0 POLY_SWITH KZ00TFU0 (,) THERM_LERT# V THMLK THMT R PU Thermal monitor -SYS_SHN- SMUS SLVE RESS 0K_ R *0_ THERM_LERT#_R V R _ <check list> G Layout Note:Routing 0:0 mils and away from noise source with ground gard P/N:L0000 U SLK S LERT# OVERT# V XP 0 LMV XN GN H_THERM () 00p/0V_ H_THERM () G G- V R *0_ V V R *.K_ THMT Q *N00E-LF MT MT () R 0K/F_ R 00 V -SYS_SHN- R *0_ SYS_SHN# () V R *.K_ THMLK MLK Q *N00E-LF MLK () MMT0 Q R *0_ Quanta omputer Inc. PROJET : EL Size ocument Number Rev US on oard/pu Thermal monitor Friday, pril, 00 ate: Sheet of

E R O GN TRL EV_R V_S R short00 LNV LNV EV_R EV 0 MI- N/MIP R *0_ N/MIN LKREQ PME# () SS LN_ON_E () LNV MI0 MI0- V MI MI- GN MI MI- V MI TRL LNV GN RSET TRL/V TRL/V TRL/V XTL XTL LNV V LE0 LNV E--0 V LE/EESK LE/EEI LE/EEO EES GN V LNV ISOLTE LN_REST# Reserve EEPROM for first stage. No stuff. R short00 L0.uH R u/.v_ U/.V_ short00 0 U/.V_ modified 00/0/ by Rich Power comment u/.v_ U 0.K/F_ V MIP0 MIN0 N/F MIP MIN GN N/MIP N/MIN V/V R short00 R VTRL/SROUT GN RSET VTRVSR N/VSR N/ENSWREG KTL KTL 0 N/V N/LV_PLL LE0 V RTLL V GN HSIP HSIN REFLK_P REFLK_N EV HSOP HSON EGN N/SMLK N/SMT Remove R if external power.v is used. Remove R if switching regulator is enable *0_ V LE/EESK LE/EEI LE/EEO EES GN 0 V V ISOLTE PERST LNWKE R EES LE/EESK LE/EEI LE/EEO R X'tal MHz KEIZZ000.K_ LNV S_WKE# (,) LNV Rich Power comment:no matter U mounted or not,r always shall be mounted! R0 R K/F_ U S SK I *T(.V) *0_ *0_ V ORG P Y P G000 XTL-_X_-_-_H R MHz/0pF/ppm XTL PLTRST# (,,,,) *0.U/V/YV_@N *0_ R K/F_ R K_ XTL V Modify 0 *SS LN_ON_S () V 0 LKREQ R *0K_ V LK G have't LKREQ function 0 0 00 LNV short00 R TRL/V () PETX () PETX- V GN EV GN GPP_TXN_LN GPP_TXP_LN 0 0 PELK- () PELK () PERX- () PERX () U LN_MX0- IO IO LN_MX GN REF IO IO *SRV0- LN_MX0 LN_MX- U LN_MX- IO IO LN_MX GN REF IO IO *SRV0- LN_MX LN_MX- EMI:NER N N Tramsformer ctive:yellow 0.0U/V/XR_ 0.0U/V/XR_ 0.0U/V/XR_ MI0 MI MI MI 0 U T TT T TT T TT T LN_MX0 LN_MT0 LN_MX LN_MT LN_MX- MI- MI- MI- MI0- LN_MX0- LN_MX- LN_MX LN_MT LN_MX- LN_MX 0.0U/V/XR_ LN_MT R0 /F_ TT MT NS0 MX MT MX- T- T- MX- MX- MX MT MX- MX MT T- T- MX 0 LNT LE/EESK 00:Green 000P/KV/NPO_ P/N:0TLN0 R0 R0 /F_ /F_ SS Q TEU LNV LE/EEO 000:mber SS LNV LNV R0 0 *0.U/0V/XR_ 0 R R 0 R0 /F_ Q TEU LE0 LN_MX- LN_MX LN_MX- LN_MX- LN_MX LN_MX LN_MX0- LN_MX0 0 MP LE_YN LE_YP LE_GN LE_GN/P LE_GP/N O HSGN HSGN Y G Quanta omputer Inc. PROJET : EL Size ocument Number Rev LN(RTL) Friday, pril, 00 ate: Sheet of

KEYOR For debug () MY[..0] TOP Side M Side *0-0-P-L 0 0 0 0 ON MY0 MY MX MX MY MX MX0 MY0 MX MX MY MX MX MY MY MY MY MY MY MY MY MY MY MY () MX[..0] MY0 () MY () MX () MX () MY () MX () MX0 () MY0 () MX () MX () MY () MX () MX () MY () MY () MY () MY () MY () MY () MY () MY () MY () MY () MY () From ELV 0 TOP Side 0 SWITH/ Side () PWR_LE0# () PWR_LE# () NSWON# VPU V PWR_LE0# PWR_LE# NSWON# Modify 0/0/0 :the same as N Power SW N 0-000L-0P-R rightness ontrol PS MOUSE Green close to conn to version: VSUS PUSH_SW SW rightness UP# rightness UP# () N 0 PESV0U MSLK () MST () rightness W# rightness W# () L LMPGSN_ L0 R.K_ LMPGSN_ PS midin00fr00t0xt-p-v FM0FR00 0P_ 0P_ FOR EMI HNGE P L LMPGSN_ VSUS :T :N :GN :V :LK :N PS KEYOR Purple close to conn to version: VSUS N PS PESV0U PESV0U R.K_ PUSH_SW SW PESV0U 0P_ L 0P_ R.K_ LMPGSN_ L LMPGSN_ R.K_ KLK () KT () :T :N :GN :V :LK :N midin00fr00t0xt-p-v FM0FR000 FOR EMI HNGE P L LMPGSN_ VSUS 0 Quanta omputer Inc. PROJET : EL Size ocument Number Rev K/TP ate: Friday, pril, 00 Sheet of

() USP- () USP () LK_M_R V R R.K/F_ 00K/F_ S_WP S_# S_T RREF USP- USP LK_M_R 0 U0 X_LE/F_ X_E#/F_ F_# X_LE/F_ GPIO0 F_0 S_T/X_RE#/F_ 0 F_ S_T/X_WE#/F_ F_ X_RY/F_ F_/SM_# S_T/X_WP#/F_ F_/X_# F_0/SM_WPM#/S_WP S_M F_0/S_# S_T/X_0/F_ F_MK# S_LK/X_/MS_LK/F_ X_/S_ S_T/X_/MS_/F_ F_MRQ F_S0# 0 MS_INS#/F_IOR# RREF S_T/X_/MS_/F_IOWR# S_T0/X_/MS_0/F_RST# X_/MS_ X_/MS_S/F_ M P V_PLL_IN XTLO XTLI VREG_OUT 0 V_IN V_ IN V_ IN S_T S_T S_M S_LK_MS_LK MS_T MS_# MS_T MS_T0_S_T0 MS_T MS_S VREG Vreg out.v from Internal.VLO U/.V_ V_RTS R.U/.V_ short00 V Note: S/MM MS X SP0 SP X_# SP S_WP SP S_# SP S_T X_ SP MS_S X_ SP S_T MS_ X_ SP S_T0 MS_0 X_ SP S_T MS_ X_ SP MS_INS# SP0 S_T MS_ X_ SP S_LK MS_SLK X_ SP S_T X_0 SP S_T X_WP# SP X_R/# SP S_T X_WE# SP S_T X_RE# SP X_LE SP X_E# SP X_LE V_OUT V () MOE_SEL R *P/0V_ *0_ For PLT_RST-R# R *0_ MOE_SEL RST# V_OUT R_V_OUT G G_PLL GN GN.U/.V_ VR U/.V_ 0 V VR UTO E-LINK mode(r 0Ω N) If no card inserting,chip will cut US connection,save power model Realtek RTSE P/N:L0000 IN ONN From P VR MS_S MS_T MS_T0_S_T0 MS_T MS_# MS_T S_LK_MS_LK *P R *0K R _ MS_S_# R _ MS_ R _ MS_0 R _ MS_ R *0_ MS_INS R _ MS_ R0 _ MS_LK VR ON MS-GN MS-S MS- MS-SIO(0) MS- MS-INS MS- MS-SLK MS-V 0 MS-GN S-/T S-M S-GN S-V S-LK S-GN S-T0 S-T S-T VR S_0 S_ S_ S_ S_M_ S_LK _ R _ R0 _ R _ R S_T _ R S_M _ R MS_T0_S_T0 S_T S_T S_LK_MS_LK 0 *P VR R *0K S_# R *0_ S 0 S-SW(RSV) S-SW(GN) S-SW(WP) S-SW(WP-GN) S_SW _ R S_WP VR VR Molex-000-R-REER Supporting MM/S/MS ards PL P/N:FHMS00 TTN P/N:FHMS0 Quanta omputer Inc. PROJET : EL Size ocument Number Rev RTSE IN R ate: Friday, pril, 00 Sheet of

ST H ST O 0 heck New O ONN Pin efine. N GN GN RXP RXN GN TXN TXP GN.V.V.V 0 GN GN GN V V V GN RSV GN V 0 V V GN ST_RXN0 ST_RXP0 0 00P_ 00P_ 0u/0V_ 0u/0V_ ST_TXP0 (0) ST_TXN0 (0) ST_RXN0 (0) ST_RXP0 (0) 0u/0V_ 0u/0V_ V V 0 N FWFMS0 0-00-p-r O_ONN / modify ST_RXN ST_RXP R 00P_ 0 00P_ K_ ST_TXP (0) ST_TXN (0) ST_RXN (0) ST_RXP (0) evice Present VST_O TOP View R 0 0u/0V_ short00 V TOP View K-0-L OP M SIE O OR SIE The same as EL ZT card connector Quanta omputer Inc. PROJET : EL Size ocument Number Rev ST-H/F/SS ate: Friday, pril, 00 Sheet 0 of

." MINI-ard I (WLN) V *0U/0V_ V 0u/0V_ 0.00u/0V_.V 0u/0V_ V () () () LKREQ_WLN# V () PLK_EUG R R () () () () *0_ V *0K_ R R R0 R R *0_ *0_ *0_ LKREQ_WLN# *0_ *0_ PLK_EUG N Reserved Reserved ebug(pirst#) ebug(pilk) GN.Vaux.Vaux GN GN PETp0 PETn0 GN GN PERp0 PERn0 GN Reserved Reserved GN PELK PELK- PETX PETX- PERX PERX- PELK PELK- GN REFLK REFLK- GN LKREQ# Reserved Reserved WKE#.V GN 0.V LE_WPN# LE_WLN# LE_WWN# GN 0 US_ US_- GN SM_T SM_LK 0.V GN.Vaux PERST# 0 W_ISLE# GN GN Reserved Reserved Reserved 0 Reserved Reserved.V GN.V V.V Rev. R *0_ RN stuff *0X_ R *0_ R *0_.V *0U/0V_ V RF_EN_WLN SS R0 0K_ V LP0 R *0_ LP R *0_ LP R *0_ LP R *0_ LPFRME# R *0_.V WLN_SENSE# () V USP () USP- () ES 00- SMT (,) SMK (,) PLTRST# (,,,,) RF_EN () LP0 (0,) LP (0,) LP (0,) LP (0,) LPFRME# (0,) Modify / *0U/0V_ V.V 0 0 0u/0V_ 0.00u/0V_ 0u/0V_ (,) S_WKE# V Q *N00E R WLN_WKE# *0K_ MINI-R_ ES P/N:FHMS0 P/N:FHMS From P or PF :Height mm Quanta omputer Inc. PROJET : EL Size ocument Number Rev Mini-ard/WL Friday, pril, 00 ate: Sheet of

VPU Layout Note: Place all capacitors close to IT. L (For PLL Power) K0HS-T VPU Pull Up for Low ctive Pin VPU 0 000P/0V_ 0 L K0HS-T 0 VPU WLN_SENSE# () V R 0_ SMUS WLN_SENSE# MLK MT R R0 R0 0K/F_ 0K/F_ 0K/F_ VPU (0) () () () (0) () R 0K PURST# (0,) (0,) (0,) (0,) () (0,) G0 SERIRQ E_SMI# E_SI# RIN# S_ON *0p/0V_ LP0 LP LP LP LI# LLK_E LPFRME# () () PLK_E R *_ SERIRQ PURST# R R MY[..0] MX[..0] Layout Note: net "VPU" and "RT_V" minimum trace width mils. 0K/F_ LI# PLK_E SS SS SS SS *00K/F_ T _SK _SO _SI _SE# MY0 MY MY MY MY MY MY MY MY MY MY0 MY MY MY MY MY U IT0E 0 0 0 0 0 0 0 00 0 G0/GP SERIRQ ESMI#/GP ESI#/GP WRST# KRST#/GP PWUREQ#/GP V VPU L0 L L L LPRST#/WUI/GP LPLK LFRME# LPP#/WUI/GPE GP0/RX GP/TX LP IR MX0 MX MX MX MX MX MX MX VRT Note : Since all GPIO belong to VSTY power domain, and there are some special considerations below: () If it is output to external V derived power domain circuit, this signal should be isolated by a diode such as KRST# and G0. () If it is input from external V derived power domain circuit, this external circuit must consider not to float the GPIO input. Note : () Each input pin should be driven or pulled. () Each output-drain output pin should be pulled. FLRST#/WUI/GPG0/TM FLLK/SK FL/GPG FL/SO FLSH FL/SI FL0/SE# FLFRME#/GPG KSO0/P0 KSO/P KSO/P KSO/P KSO/P KSO/P KSO/P KSO/P KSO/K# KSO/USY KSO0/PE KSO/ERR# KSO/SLT KSO KSO KSO V VSTY 0 VSTY VSTY VSTY VSTY KMX KSI0/ST# KSI/F# KSI/INIT# KSI/SLIN# KSI KSI KSI KSI 0 VT V VSTY T T0 GPE/ISLK GPE/ISS GPE/IS GPIO IT0 VSS VSS VSS VSS VSS VSS VSS 0 KSO/GP KSO/GP GINT/GP L0HLT/GPE0 L0LLT/GPE VSS R *0_ VOLMUTE# T T T 0 GPG/I GPH/I GPH/I GPH/I GPH/I GPH/I/R GPH/I/R0 GPH0/I0/SHM SM US WKE UP PS/ PWM URT / / J000F0 HWPG () SUS# () EPWROK () E_RSMRST# () VRON () MINON (,,) SUSON (,) LOK LQFP-X- SMLK0/GP SMT0/GP SMLK/GP SMT/GP SMLK/GPF SMT/GPF PSLK0/GPF0 PST0/GPF PSLK/GPF PST/GPF PSLK/GPF PST/GPF PWM0/GP0 PWM/GP PWM/GP PWM/GP PWM/GP PWM/GP PWM/GP PWM/GP TH0/GP TH/GP TMR0/WUI/GP TMR/WUI/GP PWRSW/GPE RI#/WUI0/GP0 RI#/WUI/GP WUI/GPE RING#/PWRFIL#/LPRST#/GP TX/GP RX/GP0 0/GPI0 /GPI /GPI /GPI /GPI /GPI /GPI /GPI 0/GPJ0 /GPJ /GPJ /GPJ /GPJ /GPJ 0 0 0 0 0 0 0 0 KKE KK / modify MLK MT RF_EN PWR_LE0# PWR_LE# L_ON () T / modify NSWON# NSWON# () SUS# SUS# () IN -PUHOL T RT. E. E. E E EVORE E0 PMUX PMUX VFN () PWR_LE0# () PWR_LE# () LN_ON_E () Layout Note:.kHz clock lines: a. If possible, please avoid using any through-hole. b. Please make the trace length short, and the trace width wide enough. c. The spacing to the closest neighbor should be wide enough. T T T0 T T T T T T T T R0 R0 R *0K/F_ *U/0V/XR_ SS SS 0 Y.KHZ 0p/0V_ 0K/F_ 0K/F_ U MLK () MT () NSWON# () RF_EN () KLK () KT () MSLK () MST () T rightness UP# () rightness W# () ONTRST () FNSIG () SWI# () 0p/0V_ *WZ 0 E. E. V_ORE.0V Note: Pin To G originally 00/0/0 Jimmy Hsu VPU R K R R VPU U *WZ R 0K/F_ () 0K/F_ 0K/F_ E 0 VPU=E*(.) IOS_WP# VOLMUTE#_elay ().V.VSUS VPU=E*(.) VRT=RT.*(.) EVORE=V_ORE E0=.0V E.=.V E.=.VSUS VPU MLK MT E _SE# _SK _SI _SO HWPG NSWON# IN LI# ER I Modify / R0.K/F_ R 0K/F_ R 0 U0 SL S WP *L0 VRT R0 /F_ R /F_ R _ V VPU R.K 0 rightness UP# rightness W# V GN R0 *.K/F_ VPU VPU RT. Use Mbit in -test V Mbit, SPI M Winbond P/N:KEGFP0N0 R.K Q TEU R R0 0K/F_ R0 R0 R R R R *0K/F_ U E# SK SI SO WP# WX0 * V HOL# VSS 0K/F_ 0K/F_ 0K/F_ 0K/F_ SOKET: G000000 0 00K/F_ 0K/F_ * Q N00E R 0K/F_ *U/0V_ R00 *0_ () NSWON# () SUS# NSWON# SS Q TEU -PUHOL 00/0/0 modified for stage () NSWON# NSWON# JP R 00K/F_ SHORT P Layout Note: Place R,R,R within 00 mils from SPI Flash.Place R within 00mils from R; R0 within 00mils from R and R0 within 00mils from R. NSWON# HWPG SUS# *P/0V_ *P/0V_ *P/0V_ Please reserve this connector for serial debug port & KS download usage. URT_TX URT_RX T T Quanta omputer Inc. PROJET : EL Size ocument Number Rev ITE 0E Friday, pril, 00 ate: Sheet of

HPOUT_R HPOUT_L emodulation Filter Place close to odec MI-VREFO-R MI-VREFO-L V L *TI00U0/00 V V Place next to pin V MP_GN Place next to pin P *0.U/V/XR/ V MP_GN Place next to pin MP_GN 0u/.V_ R *0_ R 0_ R 0_ 0u/.V_ 0u/.V_ nalog_ground Spilt by GN 0 V V MP_GN V MP_GN L_SPK L_SPK- R_SPK- L_SPK- R_SPK- R_SPK EP# L_GPIO0 P# 0V : Power down lass SPK amplifer.v : Power up lass SPK amplifer R *0_ R 0_ R 0_ MP_GN digital_ground Tied at one point only under the L or near the L.U/.V/XR/00 0 Place next to pin R 0.U/.V/XR/00 VSS V PV SPK-L PVSS PVSS 0-00 Internal SPK_L Internal SPK_L- Internal SPK_R- Internal SPK_R SPK-L- SPK-R- SPK-R PV R R (Vista Premium Version) 0u/.V_ R R P V short00 *0_ short00 *0_ N GPIO0/MI-T SPIFO/EP SPIFO PGN short00 PVEE GPIO/MI-LK R *0_ HP-OUT-R P# nalog_ground HP-OUT-L ST-OUT 0p/0V_ PVREF IT-LK MI-VREFO-R 0 VSS (0) MI-VREFO ST-IN () MI-VREFO-L V-IO VREF SYN 0 VSS RESET# R _ PEEP EEP_ Z_RESET#_UIO L_GPIO0 VOLMUTE#_elay Z_RESET#_UIO EP# Place next to pin V PEEP *0p/0V_ u/0v_ 00P/0V_ V *0u/.V_ LINE-R LINE-L MI-L MONO-OUT JREF MI-L LINE-L L R _ R R *SS U MI-R 0 Sense- MI-R LINE-R Sense IGITL R LINEOUT_R LINEOUT_L NLOG V MIIN-R MIIN-L Z_RESET#_UIO (0) Z_SYN_UIO (0) Z_SIN0 (0) Z_SOUT_UIO (0) Z_ITLK_UIO (0) *0_ S_EEP () Place next to pin P# HPSENSE# LINE-J V Place next to pin ES-00- Placement near udio odec R0 0K_ R0 K_ R 0_ *0K_ *0_ R 0K/F_ R R R U TSH0FU(F).K/F/ 0K/F_ 0K/F_ MISENSE# MMT0 Q 0u/.V_ 0u/.V_ V R0 u/.v_ 0K_ / Modify MIIN-L MIIN-R MISENSE# VPU P_MUTE L_SPK Modify 00/0/0 from EL R 0K_ 0 L,L,L,L,,, Q MMT0 *.U/0V_.U/0V_ R_SPK IN GN SHN U L00000 G-0TU R L *0_ LMPG00SN MP_GN L LMPG00SN L LMPG00SN MP_GN L LMPG00SN R R OUT SET MI-VREFO-R MI-VREFO-L K/F_ K/F_ R0 R 0K/F_ ES-00-000P/0V/XR/00 000P/0V/XR/00 R.K/F_.K/F/ 000P/0V/XR/00 000P/0V/XR/00 R.K/F_ L L Vset =.V Vout =Vset[R(,)/R(,GN)] P 0u/V_0 Internal Speaker Modify 00/0/0 the same as N or N From PF Max. 00mVrms input for Mic-IN 0P/0V/XR/ Normal Open SK00T-Y-N Pink SK00T-Y-N N 0P/0V/XR/ -00-P-L MIIN-L MIIN-R MI-IN Jack Normal Open Type SUYIN=00FR00G0JL ON FTJ0FS00 omment by RichPower Vic 00/0/ u/.v_0 LINEOUT_L R /F_ LINEOUT_L_L LINEOUT_L LINEOUT_R R /F_ LINEOUT_R_R LINEOUT_R u/.v_0 R P_MUTE R0 K/F 0K_0 SKPT Q R K/F R 0K_0 SKPT Q From PF Green SUYIN=00FR00G0HL L MN-00-000-NQ LINEOUT_L_L L MN-00-000-NQ LINEOUT_R_R LINE-J LINE-J ON Normal Open FTJ0FS00 Line-OUT P_MUTE HPOUT_L R /F_ HPOUT_R R0 /F_ HPSENSE# R *K/F *SKPT Q R *K/F *SKPT Q HPOUT_L L HPOUT_R L R *0K_0 R *0K_0 From PF Normal Open Green GML-00-000-N HPOUT_L GML-00-000-N HPOUT_R 00P/0V_ 00P/0V_ Headphone-OUT Normal Open Type SUYIN=00FR00G0HL ON FTJ0FS00 modified 00/0/ by Rich Power comment 00P or 00P Quanta omputer Inc. PROJET : EL Size ocument Number Rev Realtek L Friday, pril, 00 ate: Sheet of