ΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2017 ΔΙΑΛΕΞΗ 1: ΕΙΣΑΓΩΓΗ ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ ΧΑΡΗΣ ΘΕΟΧΑΡΙΔΗΣ (ttheocharides@ucy.ac.cy) [Προσαρμογή από Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al. ]
Διοικητικά Μαθήματος q Διδάσκων: Δρ. Χάρης Θεοχαρίδης Γραφείο: Green Park, #110 Tηλέφωνο: 22892259 email: ttheocharides@ucy.ac.cy qώρες Γραφείου: Τρίτη 11:00-13:00 και Παρασκευή, 11:00-13:00, ή με ραντεβού στο ΕΡΕΥΝΗΤΙΚΟ ΚΕΝΤΡΟ ΚΟΙΟΣ ή στο Green Park (110) Θα σας ενημερώννω αναλόγως. qδιαλέξεις: Τρίτη και Παρασκευή, 13:30 15:00 Αίθουσα Β106, ΧΩΔ 02 qurl: http://www.eng.ucy.ac.cy/theocharides/courses/ece307 qβοηθοσ ΔΙΔΑΣΚΑΛΙΑΣ: Γιώργος Πλαστήρας (gplast01@ucy.ac.cy) Ώρες Γραφείου: Τρίτη και Πέμπτη, 17:00 18:00. (Γραφείο στο Ερευνητικό Κέντρο ΚΙΟΣ, Πανεπιστιμιούπολη, κτ. Κοινωνικών Δραστηριοτήτων, πάνω από το εστιατόριο). qpaperless COURSE! Will post PDFs from lecture slides and other details on course website. YOU ARE RESPONSIBLE FOR D/L THE MATERIAL! ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.2 Θεοχαρίδης, ΗΜΥ, 2017
Περιεχόμενα Μαθήματος l Introduction to digital integrated circuits CMOS devices and manufacturing technology. CMOS logic gates and their layout. Propagation delay, noise margins, and power dissipation. Combinational (e.g., arithmetic) and sequential circuit design. Memory design. l Course goals Ability to design and implement CMOS digital circuits and optimize them with respect to different constraints: size (cost), speed, power dissipation, and reliability l Course prerequisites ECE 102, ECE 202 Circuit Design & Devices ECE 210, Digital Logic Design ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.3 Θεοχαρίδης, ΗΜΥ, 2017
Βαθμολογία l Ενδιάμεση Εξέταση Τρίτη 21 Μαρτίου 25% l l l Τελική Εξέταση Εβδομάδες Εξετάσεων Μαίου 40% Εργαστηριακές Ασκήσεις 5 Ασκήσεις με χρήση Η/Υ 30% Συμμετοχή στο Μάθημα και σποραδικές κατοίκον εργασίες 5% Θα μάθουμε να σχεδιάζουμε κυκλώματα με την χρήση τόσο εργαλείων Schematics αλλά και με χρήση γλώσσας περιγραφής υλικού. l Ο διδάσκων διατηρεί το δικαίωμα να ανακατανέμει την βαθμολογία αφού ενημερώσει τους φοιτητές και έπειτα από διαβούλευση! ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.4 Θεοχαρίδης, ΗΜΥ, 2017
Ακαδημαϊκό Υπόβαθρο l Basic circuit theory ΗΜΥ 102 / 202 resistance, capacitance, inductance Diode concepts, electrons, holes, etc. MOS gate characteristics l Hardware description language ΗΜΥ 210/211/213 VHDL or Verilog (basic knowledge) l Use of modern EDA tools ΗΜΥ 211/13 simulation, verification ( ECE 312, ECE 305) schematic capture tools ECE 210 l Logic design ECE 210 logical minimization, FSMs, component design ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.5 Θεοχαρίδης, ΗΜΥ, 2017
Εργαστηριακές Ασκήσεις l Θα χρησιμοποιήσουμε εργαλεία που είναι δωρεάν και μπορείτε να τα εγκαταστείσετε στους Η/Υ σας Magic VLSI (http://opencircuitdesign.com/magic/) The first one and a half lab will be given on Magic IRSIM (http://www.opencircuitdesign.com/irsim/) The second half and third lab will use IRSIM Qflow (http://opencircuitdesign.com/qflow/) The last two labs will feature a complete design using all three tools. Installation on Linux, but you can also port them in Windows using Cygwin ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.6 Θεοχαρίδης, ΗΜΥ, 2017
Εργαστηριακές Ασκήσεις l Η κάθε ομάδα θα λάβει ΔΙΑΦΟΡΕΤΙΚΟ κύκλωμα για τα τελευταία 2 εργαστήρια. Εργασία 1: Θα εγκαταστήσετε τα εργαλεία και θα σχεδιάσετε ένα απλό κύκλωμα (CMOS Inverter) Εργασία 2: Θα δημιουργήσετε μια «Standard Cell» βιβλιόθήκη με τις βασικές λογικές πύλες και θα διάφορα κομμάτια όπως latches και flip flops. Εργασία 3:Θα αυξήσετε τις επιλογές σας με διάφορα κυκλώματα όπως ADC, DAC, κλπ. Εργασία 4: Θα υλοποιήσετε ολοκληρωμένες μονάδες αριθμητικής και λογικής (adders, subtractors, multipliers, etc.) Εργασία 5: Θα υλοποιήσετε ένα ολοκληρωμένο ψηφιακό κύκλωμα, με σύστημα ελέγχου, καθώς και με εξωτερικές εισόδους και εξόδους (παράδειγματα: ALU, flash decoder/converter, reference voltage sampler, memory controller, etc.) ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.7 Θεοχαρίδης, ΗΜΥ, 2017
Περιεχόμενα Μαθήματος 2 weeks on the CMOS inverter 2 weeks on static and dynamic CMOS gates 2 weeks on C, R, and L effects 2 week on sequential CMOS circuits 2 weeks on design of datapath structures 2 weeks on memory design 1 week on design for test, margining, scaling, trends ΒΙΒΛΙΟΓΡΑΦΙΑ: Digital Integrated Circuits A Design Perspective 2 nd Edition! Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.8 Θεοχαρίδης, ΗΜΥ, 2017
Different Types of Integrated Circuits Classification of Circuits based on Different Criteria Ø Circuits can be classified into different types based on different criteria. Ø Based on connections: Series circuits and Parallel circuits. Ø Based on the size and manufacturing process of circuit: Integrated circuits and Discrete circuits. Ø Based on signal used in circuit: Analog circuits and Digital circuits ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.9 Θεοχαρίδης, ΗΜΥ, 2017
Different Types of Integrated Circuits Integrated Circuits Ø It is called Integrated circuit or IC or microchip or chip Ø It is a microscopic electronic circuit array formed by the fabrication of various electrical and electronic components. Ø Components (resistors, capacitors, transistors,)are placed on semiconductor material (silicon) wafer. Ø It can perform operations similar to the large discrete electronic circuits made of discrete electronic components. ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.10 Θεοχαρίδης, ΗΜΥ, 2017
Integrated Circuits Ø An arrays of components, microscopic circuits and semiconductor wafer material base are integrated together to form a single chip. Ø So, it is called as integrated circuit or integrated chip or microchip. ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.11 Θεοχαρίδης, ΗΜΥ, 2017
Different Types of Integrated Circuits Ø Ø Classification of Integrated Circuits is done based on various criteria. Based on the intended application, the IC are classified as follows Ø Ø Ø Analog integrated circuits. Digital integrated circuits Mixed integrated circuits. ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.12 Θεοχαρίδης, ΗΜΥ, 2017
Τα ολοκληρωμένα Κυκλώματα! l Introduction: Issues in digital design l The CMOS inverter l Combinational logic structures l Sequential logic gates l Design methodologies l Interconnect: R, L and C l Timing l Arithmetic building blocks l Memories and array structures ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.13 Θεοχαρίδης, ΗΜΥ, 2017
Τα ολοκληρωμένα Κυκλώματα! l Why is designing digital ICs different today than it was before? l Will it change in future? ΕΠΙΠΡΟΣΘΕΤΗ ΒΙΒΛΙΟΓΡΑΦΙΑ (ΠΡΟΑΙΡΕΤΙΚΗ!): CMOS Digital Integrated Circuits Analysis & Design By: Sung-Mo (Steve) Kang and Yusuf Leblebici ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.14 Θεοχαρίδης, ΗΜΥ, 2017
The First Computer The Babbage Difference Engine (1832) 25,000 parts cost: 17,470 ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.15 Θεοχαρίδης, ΗΜΥ, 2017
ENIAC - The first electronic computer (1946) ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.16 Θεοχαρίδης, ΗΜΥ, 2017
The Transistor Revolution First transistor Bell Labs, 1948 ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.17 Θεοχαρίδης, ΗΜΥ, 2017
The First Integrated Circuits Bipolar logic 1960 s ECL 3-input Gate Motorola 1966 ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.18 Θεοχαρίδης, ΗΜΥ, 2017
Intel 4004 Micro-Processor 1971 1000 transistors 1 MHz operation ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.19 Θεοχαρίδης, ΗΜΥ, 2017
Intel Pentium (IV) microprocessor ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.20 Θεοχαρίδης, ΗΜΥ, 2017
Moore s Law In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months. He made a prediction that semiconductor technology will double its effectiveness every 18 months ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.21 Θεοχαρίδης, ΗΜΥ, 2017
More recent Processors Ø2007 800 Million transistors 2 GHz operation 45nm technology Ø2010 Core i7 1.2 Billion transistors 3.3 GHz operation 32nm technology Ø2012 Core i7 (newer generations) 1.7 Billion transistors 4.0 GHz operation 22nm technology Ø2015 14nm, then 10nm in 20xx, and then??? 22 ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.22 Θεοχαρίδης, ΗΜΥ, 2017
VLSI Design l What is VLSI? Very Large Scale Integration Defines integration level 1980s hold-over from outdated taxonomy for integration levels Obviously influenced from frequency bands, i.e. HF, VHF, UHF Sources disagree on what is measured (gates or transistors?) l SSI Small-Scale Integration (0-10 2 ) l MSI Medium-Scale Integration (10 2-10 3 ) l LSI Large-Scale Integration (10 3-10 5 ) l VLSI Very Large-Scale Integration (10 5-10 7 ) l ULSI Ultra Large-Scale Integration (>=10 7 ) ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.23 Θεοχαρίδης, ΗΜΥ, 2017
Example System-on-a-chip (SOC) Source: TI ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.24 Θεοχαρίδης, ΗΜΥ, 2017
Example System-on-a-chip (SOC) iphone 3G board TI OMAP44x ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.25 Θεοχαρίδης, ΗΜΥ, 2017
History of the Transistor l Early ideas of transistors started with the theoretical studies of J.W. Lilienfelds in 1930s. l 1947: Bardeen and Brattain create point contact transistor at Bell Laboratories. (U.S. Patent 2,524,035) ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.26 Θεοχαρίδης, ΗΜΥ, 2017
History of the Transistor ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.27 Θεοχαρίδης, ΗΜΥ, 2017
History of the Transistor ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.28 Θεοχαρίδης, ΗΜΥ, 2017
History of Transistor ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.29 Θεοχαρίδης, ΗΜΥ, 2017
History of Transistor ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.30 Θεοχαρίδης, ΗΜΥ, 2017
History of Transistor ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.31 Θεοχαρίδης, ΗΜΥ, 2017
History of Transistor ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.32 Θεοχαρίδης, ΗΜΥ, 2017
Moore s Law LOG 2 OF THE NUMBER OF COMPONENTS PER INTEGRATED FUNCTION 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 Electronics, April 19, 1965. ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.33 Θεοχαρίδης, ΗΜΥ, 2017
Evolution in Complexity ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.34 Θεοχαρίδης, ΗΜΥ, 2017
Transistor Counts 1,000,000 K 1 Billion Transistors 100,000 10,000 1,000 100 10 8086 i486 Pentium i386 80286 Pentium III Pentium II Pentium Pro Source: Intel 1 1975 1980 1985 1990 1995 2000 2005 2010 Projected Courtesy, Intel ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.35 Θεοχαρίδης, ΗΜΥ, 2017
Moore s law in Microprocessors Transistors (MT) 1000 100 10 1 0.1 0.01 0.001 2X growth in 1.96 years! 8085 8086 4004 8008 8080 386 286 486 P6 Pentium proc Transistors on Lead Microprocessors double every 2 years 1970 1980 1990 2000 2010 Year Courtesy, Intel ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.36 Θεοχαρίδης, ΗΜΥ, 2017
Die Size Growth 100 Die size (mm) 10 8080 8085 8008 4004 8086 286386 486 P6 Pentium proc ~7% growth per year ~2X growth in 10 years 1 1970 1980 1990 2000 2010 Year Die size grows by 14% to satisfy Moore s Law Courtesy, Intel ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.37 Θεοχαρίδης, ΗΜΥ, 2017
Frequency Frequency (Mhz) 10000 1000 100 10 1 0.1 8085 8008 4004 8080 8086 Doubles every 2 years 286 386 P6 Pentium proc 486 1970 1980 1990 2000 2010 Year Lead Microprocessors frequency doubles every 2 years Courtesy, Intel ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.38 Θεοχαρίδης, ΗΜΥ, 2017
Power Dissipation 100 Power (Watts) 10 1 8085 8080 8008 4004 8086 286 386 486 P6 Pentium proc 0.1 1971 1974 1978 1985 1992 2000 Year Lead Microprocessors power continues to increase Courtesy, Intel ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.39 Θεοχαρίδης, ΗΜΥ, 2017
Power will be IS a major problem Power (Watts) 100000 10000 1000 100 10 1 0.1 8085 8086286 386 486 4004 80088080 Pentium proc 18KW 5KW 1.5KW 500W 1971 1974 1978 1985 1992 2000 2004 2008 Year Power delivery and dissipation will be prohibitive Courtesy, Intel ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.40 Θεοχαρίδης, ΗΜΥ, 2017
Power density Power Density (W/cm2) 10000 1000 100 10 1 4004 8008 8080 8086 Rocket Nozzle Nuclear Reactor Hot Plate 8085 286 386 486 P6 Pentium proc 1970 1980 1990 2000 2010 Year Power density too high to keep junctions at low temp Courtesy, Intel ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.41 Θεοχαρίδης, ΗΜΥ, 2017
Not Only Microprocessors Cell Phone (and that was back in early 2000 s Digital Cellular Market (Phones Shipped) 1996 1997 1998 1999 2000 Small Signal RF Power RF Power Management Units 48M 86M 162M 260M 435M Analog Baseband Digital Baseband (DSP + MCU) (data from Texas Instruments) ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.42 Θεοχαρίδης, ΗΜΥ, 2017
Challenges in Digital Design µ DSM µ 1/DSM Microscopic Problems Ultra-high speed design Interconnect Noise, Crosstalk Reliability, Manufacturability Power Dissipation Clock distribution. Everything Looks a Little Different? Macroscopic Issues Time-to-Market Millions of Gates High-Level Abstractions Reuse & IP: Portability Predictability etc. and There s a Lot of Them! ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.43 Θεοχαρίδης, ΗΜΥ, 2017
Productivity Trends 10,000,000 1,000,000 Complexity Logic Transistor per Chip (M) 10,000 1,000 100 100,000 10 10,000 1,000 1 0.1 100 0.01 10 Logic Tr./Chip Tr./Staff Month. x x x x x x x x 58%/Yr. compounded Complexity growth rate 21%/Yr. compound Productivity growth rate 100,000 100,000,000 10,000 10,000,000 1,000 1,000,000 100 100,000 10 10,000 1 1,000 0.1 100 Productivity (K) Trans./Staff - Mo. 0.001 1 0.01 10 1981 1983 1985 1987 1989 1991 1993 1995 1997 1999 2001 2003 2005 2007 2009 Source: Sematech Complexity outpaces design productivity Courtesy, ITRS Roadmap ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.44 Θεοχαρίδης, ΗΜΥ, 2017
Why Scaling? l Technology shrinks by 0.7/generation l With every generation can integrate 2x more functions per chip; chip cost does not increase significantly l Cost of a function decreases by 2x l But How to design chips with more and more functions? Design engineering population does not double every two years l Hence, a need for more efficient design methods Exploit different levels of abstraction ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.45 Θεοχαρίδης, ΗΜΥ, 2017
Design Abstraction Levels SYSTEM + MODULE GATE CIRCUIT S n+ G DEVICE n+ D ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.46 Θεοχαρίδης, ΗΜΥ, 2017
Design Metrics l How to evaluate performance of a digital circuit (gate, block, )? Cost Reliability Scalability Speed (delay, operating frequency) Power dissipation Energy to perform a function ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.47 Θεοχαρίδης, ΗΜΥ, 2017
Cost of Integrated Circuits l l NRE (non-recurrent engineering) costs design time and effort, mask generation one-time cost factor Recurrent costs silicon processing, packaging, test proportional to volume proportional to chip area ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.48 Θεοχαρίδης, ΗΜΥ, 2017
NRE Cost is Increasing ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.49 Θεοχαρίδης, ΗΜΥ, 2017
Die Cost Single die Wafer Going up to 12 (30cm) From http://www.amd.com ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.50 Θεοχαρίδης, ΗΜΥ, 2017
Cost per Transistor cost: -per-transistor 1 0.1 Fabrication capital cost per transistor (Moore s law) 0.01 0.001 0.0001 0.00001 0.000001 0.0000001 1982 1985 1988 1991 1994 1997 2000 2003 2006 2009 2012 ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.51 Θεοχαρίδης, ΗΜΥ, 2017
Yield p Dies per wafer = No. of good chips per wafer Y = 100% Total number of chips per wafer Wafer cost Die cost = Dies per wafer Die yield ( wafer diameter/2) die area 2 p wafer diameter - 2 die area ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.52 Θεοχαρίδης, ΗΜΥ, 2017
Defects die yield = æ defects per unit area die area ç1+ è a a is approximately 3 ö ø -a die cost = f 4 (die area) ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.53 Θεοχαρίδης, ΗΜΥ, 2017
Some EARLY Examples (1994) Chip Metal layers Line width Wafer cost Def./ cm 2 Area mm 2 Dies/ wafer Yield 386DX 2 0.90 $900 1.0 43 360 71% $4 Die cost 486 DX2 3 0.80 $1200 1.0 81 181 54% $12 Power PC 601 4 0.80 $1700 1.3 121 115 28% $53 HP PA 7100 3 0.80 $1300 1.0 196 66 27% $73 DEC Alpha 3 0.70 $1500 1.2 234 53 19% $149 Super Sparc 3 0.70 $1700 1.6 256 48 13% $272 Pentium 3 0.80 $1500 1.5 296 40 9% $417 ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.54 Θεοχαρίδης, ΗΜΥ, 2017
Intel Phi Co-Processor Family! ΗΜΥ307 Δ1 ΕΙΣΑΓΩΓΗ.55 Θεοχαρίδης, ΗΜΥ, 2017