BD9 FT3 Kabini Block Diagram

Transcript

1 P STK UP LYER : TOP LYER : LYER : IN FT Kabini lock iagram LYER : SV LYER : IN LYER : IN LYER : LYER : OT RIII-SOIMM RIII-SOIMM Page, X'TL MHz Single hannel R III ~ MHZ PU Port RTR Page For support PR x LVS ONN LVS Panel Page Transformer Page theros /M R Page PIe- PI-Express Kabini PU W/W So LVS ONN ep Panel Page RJ Page WLN on. Page PIe- Port HMI ONN Page ard Reader on. Page ST - H on. ST - O on. Support zero power O US/ US/ Page Page Genesys Logic GLL Page Page WLN Page Page Page US_ US_ US_ US_ US_ ST ST US. (Port ~ ) TTERY zalia onexant udio odec X-Z Page ST.mm X.mm G pin GFX US. US. +.V_RT IH LP PI-E x US. (Port ~ ) SPI X'TL.KHz X'TL MHz SPI Page SPI Nuvoton E NPEL dgpu Mars/Sun Pro mm X mm Page ~, US_ US_ US_ US_ X'TL.MHz VRM R-M* VRM R-M* US. w/ S& Page US. w/o S& Page Page VRM RIII Page, POWER SYSTEM ISL TPS TPSRUKR TPSSR ISL ischarge ISLHRTZ-T G-JFU HRGER +V +VPU +V_S +V +VPU +V_S +V +SMR_VTERM +SMR_VREF +.VSUS +.V_S +.V +.V_UL +.V +.V_S +.V +V_ORE +VN_ORE P P P P P P P P P P P P P Port- Port- MI JK HP SPK on. Page Page Page FN Page HLL Sensor Page LE Page K/ on. Page Touch Pad / on. Page Power / on. Page ISHRGE +VGPU_ORE P P +.V_GPU +.V_GPU +.V_GPU P Quanta omputer Inc. PROJET : Size ocument Number Rev lock iagram Tuesday, ecember, ate: Sheet of

2 Table of ontents PGE ESRIPTION OI-FUNTION Schematic lock iagram Power Stage - Processor PU Straps PU SO-IMM R SO-IMM R - Mars/Sun Pro(M) VG - VRM - R VG PX VG US U/US ep to LVS(RTR) LS HMI/Touch Screen HM/TSN LN(R) LN odec (X-Z) O MINI R (WLN) MNW R REER(GLL)/LE MM/LE LS/RT/ LS/RT/ H/O H/O K/TouchPad K/TP E L K harger (ISLHRTZ-T) HR System V/V PWM R.V PWM +.V_UL PWM +V_ORE PWM ischarge PWM GPU_ORE PWM +.V_GPU/+.V_GPU/+.V_GPU/+V_GPU PWM POWER PLNE VIN +VRT +V +V_S +VPU +V +V_S +VPU +WIMX_P +.VSUS +.V +.V_UL +.V +V_ORE +VGPU_ORE VOLTGE V~+V +.V +.V +.V +.V +V +V +V +.V +.V +.V +.V +.V ~ ONTROL SIGNL MIN S_ON / Insert enable MIN S_ON / Insert enable IO_EN SUSON MIN +.V_UL_EN MIN VRON +VN_ORE ~ VRON S GPU_MINON ^ PE_GPIO Power States TIVE IN S~S S~S S S~S S~S S S~S S~S S S~S +.V_S +.V PE_PWRG ^ PE_GPIO S~S S S~S S S S +.V_GPU +.V GPU_MIN S +.V_GPU +.V GPU_MINON ^ PE_GPIO S +V_GPU +.V GPU_MIN S +.V_GPU +.V GPU_MIN S PLNE PGE _SIGNL LL O Quanta omputer Inc. PROJET : Size ocument Number Rev POWER STGE & OI-FUNTION Tuesday, ecember, ate: Sheet of

3 U PIE oupling aps Note: XR is required. PIe-LN PIe-WLN [] [] [] [] PIE_RXP_LN PIE_RXN_LN PIE_RXP_WLN PIE_RXN_WLN PIE_RXP_LN PIE_RXN_LN PIE_RXP_WLN PIE_RXN_WLN R R R R N N P_GPP_RXP P_GPP_RXN P_GPP_RXP P_GPP_RXN P_GPP_RXP P_GPP_RXN P_GPP_TXP P_GPP_TXN P_GPP_TXP P_GPP_TXN P_GPP_TXP P_GPP_TXN L L K K J J PIE_TXP_LN_ PIE_TXN_LN_ PIE_TXP_WLN_ PIE_TXN_WLN_ LN@.U/V_X.U/V_X PIE_TXP_LN LN@.U/V_X PIE_TXN_LN.U/V_X PIE_TXP_WLN PIE_TXN_WLN PIE_TXP_LN [] PIE_TXN_LN [] PIE_TXP_WLN [] PIE_TXN_WLN [] PIe-LN PIe-WLN N N P_GPP_RXP P_GPP_RXN P_GPP_TXP P_GPP_TXN H H +.V R.K/F_ P_TX_ZV W P_TX_ZV_ P_RX_ZV_ W P_RX_ZV R K/F_ +.V [] [] [] [] [] [] [] [] PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN L L J J G G E P_GFX_RXP P_GFX_RXN P_GFX_RXP P_GFX_RXN P_GFX_RXP P_GFX_RXN P_GFX_RXP P_GFX_RXN P_GFX_TXP P_GFX_TXN P_GFX_TXP P_GFX_TXN P_GFX_TXP P_GFX_TXN P_GFX_TXP P_GFX_TXN G G F F E E PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ EV@.U/V_X EV@.U/V_X EV@.U/V_X EV@.U/V_X EV@.U/V_X EV@.U/V_X EV@.U/V_X PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP EV@.U/V_X PEG_TXN PEG_TXP [] PEG_TXN [] PEG_TXP [] PEG_TXN [] PEG_TXP [] PEG_TXN [] PEG_TXP [] PEG_TXN [] PEG X FT REV. FT +.V HT+ onnector +.V SPE X with HEK LIST J [] PU_TRST# PU_TRST# R *EUG@K_ R R R R EUG@_ EUG@K_ EUG@K_ EUG@K_ PU_VIO PU_TRST_L PU_RY PU_RY PU_RY PU_VIO PU_TK PU_TMS PU_TI PU_TO PU_PWROK_UF PU_RST_L_UF PU_RY PU_REQ_L PU_PLLTEST PU_PLLTEST PU_TK PU_TK [] PU_TMS PU_TMS [] PU_TI PU_TI [] PU_TO PU_TO [] PU_PWROK_UF PU_RST_L_UF PU_RY PU_RY [] REQ# R *EUG/EV@_ PU_REQ# PU_REQ# [] PU_TEST_PLLTEST PU_TEST_PLLTEST [] PU_TEST_PLLTEST PU_TEST_PLLTEST [] *EUG@HT+ HEER ebug only [] PU_RST# [] PU_PWRG PU_RST# PU_PWRG R *_ ebug only U Y V Y PU_RST_L_UF +.V PU_PWROK_UF *E@P/V_X R R *EUG@K_ *EUG@K_ +.V lose by HT+ onector PU_TI PU_TK PU_TMS PU_REQ# R R R R *EUG@.U/V_X *EUG@K_ *EUG@K_ *EUG@K_ *EUG@K_ +.V *EUG@.U/V_X *EUG@LVG R *_ *EUG@.U/V_X Rev dd ohm for debug *E@P/V_X Quanta omputer Inc. PROJET : Size ocument Number Rev PU /(PIE/GPP) ate: Tuesday, ecember, Sheet of

4 Place close to PU within " Rev dd cap M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q[:] M Q M Q M Q M Q M Q M Q M Q M S#[:] M S# M [:] M S# M S# M M[:] M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M RST# M LKP M OT M WE# M LKN M OT M S# M QSN M QSN M QSP M QSN M QSP M QSP M QSN M QSP M QSN M QSN M QSP M QSP M QSN M QSN M QSP M KE M S# M QSP M LKP M KE M RS# M LKN M S# M EVENT# M Q M Q M Q +M_ZVIO M LKP M LKN M LKP M LKN M S# M S# M KE M KE M OT M OT M Q[:] [,] M M[..] [,] M S#[..] [,] M [:] [,] M QSP [,] M QSP [,] M QSP [,] M QSP [,] M QSP [,] M QSP [,] M QSP [,] M QSP [,] M QSN [,] M QSN [,] M QSN [,] M QSN [,] M QSN [,] M QSN [,] M QSN [,] M QSN [,] M KE [] M KE [] M OT [] M OT [] M S# [] M S# [] M RS# [,] M RST# [,] M S# [,] M WE# [,] M LKP [] M LKN [] M LKP [] M LKN [] M EVENT# [,] M LKP [] M LKN [] M LKP [] M LKN [] M S# [] M S# [] M KE [] M KE [] M OT [] M OT [] +.VSUS +.VSUS +MEMVREF_PU +.VSUS +MEMVREF_PU +PU_M_VREFQ_SUS Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : PU /(R MEM) Tuesday, ecember, Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : PU /(R MEM) Tuesday, ecember, Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : PU /(R MEM) Tuesday, ecember, P/V_N TP U/.V_X FT REV. MEMORY FT U M_VREFQ M_VREF L M_WE_L L M_S_L J M_RS_L N M_S_L L M_S_L R M_S_L J M_S_L R M_OT N M_OT U M_OT N M_OT J M_KE J M_KE J M_KE L M_KE E M_EVENT_L G M_RESET_L M_LK_L M_LK_H E M_LK_L E M_LK_H M_LK_L M_LK_H M_LK_L M_LK_H Y M_QS_L M_QS_H M_QS_L Y M_QS_H Y M_QS_L M_QS_H P M_QS_L P M_QS_H H M_QS_L H M_QS_H P M_QS_L P M_QS_H H M_QS_L H M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H Y M_M Y M_M Y M_M N M_M G M_M N M_M G M_M M_M M_M N M_NK G M_NK J M_NK L M_ L M_ N M_ N M_ R M_ G M_ N M_ R M_ R M_ U M_ U M_ U M_ W M_ W M_ W M_ G M_ M_ZVIO_MEM_S M_HEK M_HEK V M_HEK U M_HEK M_HEK M_HEK W M_HEK V M_HEK Y M_T M_T Y M_T M_T Y M_T M_T Y M_T M_T Y M_T Y M_T V M_T U M_T Y M_T M_T W M_T V M_T T M_T R M_T M M_T L M_T U M_T T M_T N M_T M M_T J M_T J M_T E M_T E M_T K M_T K M_T F M_T F M_T T M_T R M_T M M_T L M_T U M_T T M_T N M_T M M_T J M_T J M_T E M_T E M_T K M_T K M_T F M_T F M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T R K/F_.U/.V_X R K/F_ *U/V_X R K/F_ R./F_ *P/V_N.U/V_X

5 [] [] HMI LVS PU_RST# PU_PWRG [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] INT_HMI_TXP INT_HMI_TXN INT_HMI_TXP INT_HMI_TXN INT_HMI_TXP INT_HMI_TXN INT_HMI_TXP INT_HMI_TXN R _ P/V_N INT_LVS_TXP INT_LVS_TXN INT_LVS_TXP INT_LVS_TXN INT_LVS_TXP INT_LVS_TXN INT_LVS_TXP INT_LVS_TXN +.V [] [] [] R _ P/V_N +.V PU_VN_RUN_F_H PU_V_RUN_F_H PU_VIO_RUN_F_H PU_V_RUN_F_L INT_HMI_TXP INT_HMI_TXN INT_HMI_TXP INT_HMI_TXN INT_HMI_TXP INT_HMI_TXN INT_HMI_TXP INT_HMI_TXN INT_LVS_TXP INT_LVS_TXN INT_LVS_TXP INT_LVS_TXN INT_LVS_TXP INT_LVS_TXN INT_LVS_TXP INT_LVS_TXN *E@.U/V_X [] [] [] [] [] [] [] +V PU_TI PU_TO PU_TK PU_TMS PU_TRST# PU_RY PU_REQ# R R HM@.U/V_X HM@.U/V_X HM@.U/V_X HM@.U/V_X HM@.U/V_X HM@.U/V_X HM@.U/V_X HM@.U/V_X.U/V_X.U/V_X.U/V_X.U/V_X ep@.u/v_x ep@.u/v_x ep@.u/v_x ep@.u/v_x Reserved for external clock Gen, leave unconnected. SVT SV SV PU_SI PU_SI PU_VN_RUN_F_H PU_V_RUN_F_H PU_VIO_RUN_F_H PU_V_RUN_F_L PU_RST# R _ PU_PWRG R _ K_ K_ INT_HMI_TXP_ INT_HMI_TXN_ INT_HMI_TXP_ INT_HMI_TXN_ INT_HMI_TXP_ INT_HMI_TXN_ INT_HMI_TXP_ INT_HMI_TXN_ INT_LVS_TXP_ INT_LVS_TXN_ INT_LVS_TXP_ INT_LVS_TXN_ INT_LVS_TXP_ INT_LVS_TXN_ INT_LVS_TXP_ INT_LVS_TXN_ PU_RST#_R PU_PWRG_R H_PROHOT PU_LERT# R _ PU_TI PU_TO PU_TK PU_TMS PU_TRST# PU_RY PU_REQ# VSS_SENSE K H G E G G E E U TP_TXP TP_TXN TP_TXP TP_TXN TP_TXP TP_TXN TP_TXP TP_TXN LTP_TXP LTP_TXN LTP_TXP LTP_TXN LTP_TXP LTP_TXN LTP_TXP LTP_TXN ISP_LKIN_H ISP_LKIN_L SVT SV SV SI SI PU_RST_L LT_RST_L PU_PWROK LT_PWROK PROHOT_L LERT_L TI TO TK TMS TRST_L RY REQ_L VSS_SENSE +.V +.V +.V +V +V +.V +.V +.V +.V +.V +.V +.V VR_N_SENSE VR_PU_SENSE VIO_MEM_S_SENSE ISPLY/SVI/JTG/TEST +V +V P_K_ZVSS +V P_LON +V P_IGON +VP_VRY_L +V +V +V +VLTP_UXP +VLTP_UXN +V +V +V +V +V P ZVSS TP_UXP TP_UXN TP_HP LTP_HP _RE _GREEN _LUE _HSYN _VSYN _SL _S _ZVSS TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST_H TEST_L TEST_H TEST_L TEST RSV TEST TEST TEST TEST TEST TEST TEST E H E H G E H H V U E H H J J R N P P ZVSS P_K_ZVSS PU_LON PU_IGON PU_VRY_L INT_HMI_UXP INT_HMI_UXN INT_HMI_HP INT_LVS_UXP_ INT_LVS_UXN_ INT_LVS_HP_Q PU_RT_RE PU_RT_GRE PU_RT_LU PU_RT_HSYN PU_RT_VSYN PU_LK PU_T _ZVSS PU_TEST PU_TEST PU_TEST PU_TEST PU_TEST PU_TEST PU_TEST PU_TEST_PLLTEST PU_TEST_PLLTEST PU_TEST_H PU_TEST_L PU_TEST_H PU_TEST_L PU_TEST PU_TEST PU_TEST PU_TEST PU_TEST PU_TEST PU_TEST PU_TEST PU_TEST R R R.U/V_X.U/V_X /F_ TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP /F_ K/F_ PU_L_EN [] PU_IGON [] PU_VRY_L [,] INT_HMI_UXP [] INT_HMI_UXN [] INT_HMI_HP [] INT_LVS_UXP INT_LVS_UXN PU_RT_RE [] PU_RT_GRE [] PU_RT_LU [] PU_RT_HSYN [] PU_RT_VSYN [] PU_LK [] PU_T [] PU_TEST_PLLTEST [] PU_TEST_PLLTEST [] LVS ack Light ontrol HMI UX INT_LVS_UXP [] INT_LVS_UXN [] layout trace reference EI PU.K onn ep to LVS Translator R place close to PU PU_RT_RE PU_RT_GRE PU_RT_LU INT_LVS_HP_Q +V R R R R LS@K_ /F_ +V LS@NKW_M Q /F_ /F_ R R LS@K_ Q INT_HMI_UXP INT_HMI_UXN LS@NKW_M ep@_ INT_LVS_UXP_ INT_LVS_UXN_ INT_LVS_UXP_ INT_LVS_UXN_ INT_LVS_HP R K_ R R R R R R For ep Panel *.K_ *.K_.K_.K_ *ep@k_ *ep@k_ INT_LVS_HP [,] +V TP TP TP V F_H V F_L V F_H V F_L.V &.V SENSE PIN PU_VIO_RUN_F_H V F_H V F_L V U V F_H V F_L FT REV. P_STEREOSYN FT E P_STEREOSYN R K_ +.V PU_TEST PU_TEST PU_TEST PU_TEST_PLLTEST PU_TEST_PLLTEST PU_TEST_H PU_TEST PU_TEST_L PU_TEST R R R R R R R R R R R *K_ *K_ *K_ K_ K_ /F_ *K_ *K_ /F_ *K_ *K_ Rev hange HMI strap setting from P to PU for HMI No display issue +V +.V PU_RT_HSYN R K_ PRO HOT +V Read PU Temperature +V +V R *K_ R *K_ R *K_ Note: To override VI,Remove Rd,Re, Rf, Rg, install Rc set VI via SV & SV option RES Ra, Rb R *K_ +VPU R [] H_PROHOT_E# +V_S R K_ K_ Q NK_M +V H_PROHOT [,] [,] N_MLK N_MT N_MLK N_MT Q R *_ Q R R K_ NKW_M PU_SI NKW_M PU_SI *_ R K_ SVT SV SV PU_PWRG SV SV OOT VOLTGE. R Rd _ R Re _ R Rf _ R Rg _ Ra R *_ Rb R *_ PU_SVT PU_SV PU_SV PU_PWRG_SVI_REG Rc R *_ *.U/V_X PU_SVT [] PU_SV [] PU_SV [] PU_PWRG_SVI_REG [] [] ORE_PWM_PROHOT# Q NK_M... Quanta omputer Inc. PROJET : Size ocument Number Rev PU /(P/SVI/JTG/Test) Tuesday, ecember, ate: Sheet of

6 +.VSUS MIL MIL pf: OG, NP Others: XR. Rev hange from short pad to mount +.V_S +PU_VV_S Rev hange from short pad to mount +VPU R +.V_S U/.V_X U/.V_X U/.V_X R _ R _ *P/V_N +VRT_ U/.V_X +.V_UL RT_VIN T--F_M U/.V_X U/.V_X P/V_N P/V_N.U/V_X.U/V_X U/.V_X.U/V_X.U/V_X +PU_VIO_Z_S U/.V_X NPSQTG U/.V_X VIN U R VOUT +.V_RT_R EN R _ P/V_N U/.V_X U@_ P/V_N U/.V_X.U/V_X.U/V_X R U/.V_X. P/V_N +PU_V_S.U/.V_X.. P/V_N.U/V_X.U/V_X +V US_S +V PHY_S +.V_RT K_.U/V_X.U/.V_X MIL N UF J VIO_MEM_S_ L VIO_MEM_S_ L VIO_MEM_S_ N VIO_MEM_S_ R VIO_MEM_S_ R VIO_MEM_S_ U VIO_MEM_S_ U VIO_MEM_S_ W VIO_MEM_S_ W VIO_MEM_S_ W VIO_MEM_S_ VIO_MEM_S_ VIO_MEM_S_ VIO_MEM_S_ VIO_MEM_S_ E VIO_MEM_S_ E VIO_MEM_S_ G VIO_MEM_S_ G VIO_MEM_S_ J VIO_MEM_S_ L VIO_MEM_S_ L VIO_MEM_S_ R VIO_MEM_S_ L V LW_ M V LW_ R V US_UL_ U V US_UL_ V V US_UL_ W V US_UL_ E V LW_ E V LW_ J V LW_ J V LW_ G V LW_ V LW_ VT_RT_G POWER L VIO_Z_LW_ L VIO_Z_LW_ +.V_S *SHORT_P FT REV. VR_PU_ L VR_PU_ L VR_PU_ L VR_PU_ L VR_PU_ L VR_PU_ N VR_PU_ N VR_PU_ N VR_PU_ R VR_PU_ R VR_PU_ R VR_PU_ U VR_PU_ U VR_PU_ U VR_PU_ W VR_PU_ W VR_PU_ W VR_PU_ VR_PU_ VR_PU_ VR_PU_ VR_PU_ VR_PU_ VR_PU_ E VR_PU_ E VR_PU_ E VR_N_ L VR_N_ L VR_N_ N VR_N_ N VR_N_ N VR_N_ R VR_N_ R VR_N_ R VR_N_ U VR_N_ U VR_N_ W VR_N_ W VR_N_ VR_N_ VR_N_ VR_N_ VR_N_ E VR_N_ E VR_N_ E VR_N_ G VR_N_ G FT. U/.V_X +VIO_V Rev hange EV@ U/.V_X U/.V_X U/.V_X U/.V_X U/.V_X U/.V_X U/.V_X U/.V_X U/.V_X U/.V_X +V_ORE +VN_ORE V L V HKF-T_. V V U/.V_X U/.V_X U/.V_X U/.V_X U/.V_X. V M +VIO_V V M V G V G U/.V_X V J U/.V_X P/V_N V J U/.V_X V L V L +V GPP V L Rev hange from short pad to mount V M M +VIO_V +V V. V GFX_ U +V GFX R EV@_ +.V R _ V GFX_ W V GFX_ EV@U/.V_X U/.V_X U/.V_X U/.V_X U/.V_X U/.V_X U/.V_X U/.V_X EV@U/.V_X U/.V_X U/.V_X P/V_N U/.V_X U/.V_X U/.V_X U/.V_X U/.V_X P/V_N U/.V_X U/.V_X U/.V_X U/.V_X P/V_N +.V UG VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ E VSS_ E VSS_ E VSS_ E VSS_ E VSS_ E VSS_ E VSS_ E VSS_ E VSS_ E VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ H VSS_ H VSS_ H VSS_ H VSS_ +.V FT REV. VSS_ J VSS_ J VSS_ J VSS_ J VSS_ K VSS_ K VSS_ K VSS_ K VSS_ K VSS_ K VSS_ K VSS_ K VSS_ K VSS_ K VSS_ L VSS_ L VSS_ L VSS_ L VSS_ L VSS_ L VSS_ L VSS_ L VSS_ L VSS_ L VSS_ M VSS_ M VSS_ N VSS_ N VSS_ N VSS_ N VSS_ N VSS_ N VSS_ N VSS_ N VSS_ P VSS_ P VSS_ R VSS_ R VSS_ R VSS_ R VSS_ R VSS_ R VSS_ R VSS_ R VSS_ U VSS_ U VSS_ U VSS_ U VSS_ U VSS_ U VSS_ U VSS_ U VSS_ U VSS_ U VSS_ U VSS_ U VSS_ W VSS_ W VSS_ W VSS_ W VSS_ W VSS_ W FT UH W VSS_ VSS_ L W VSS_ VSS_ L W VSS_ VSS_ M Y VSS_ VSS_ M Y VSS_ VSS_ M VSS_ VSS_ N VSS_ VSS_ N VSS_ VSS_ N VSS_ VSS_ P VSS_ VSS_ R VSS_ VSS_ R VSS_ VSS_ R VSS_ VSS_ R VSS_ VSS_ R VSS_ VSS_ R VSS_ VSS_ R VSS_ VSS_ R VSS_ VSS_ U VSS_ VSS_ U VSS_ VSS_ U VSS_ VSS_ U VSS_ VSS_ U VSS_ VSS_ U VSS_ VSS_ U E VSS_ VSS_ U E VSS_ VSS_ V E VSS_ VSS_ W E VSS_ VSS_ W E VSS_ VSS_ W E VSS_ VSS_ W G VSS_ VSS_ W G VSS_ VSS_ W G VSS_ VSS_ W G VSS_ VSS_ W G VSS_ VSS_ W G VSS_ VSS_ W G VSS_ VSS_ W G VSS_ VSS_ W G VSS_ VSS_ W G VSS_ VSS_ W G VSS_ VSS_ W G VSS_ VSS_ W H VSS_ VSS_ Y H VSS_ VSS_ Y J VSS_ VSS_ Y J VSS_ VSS_ Y J VSS_ VSS_ J VSS_ VSS_ J VSS_ VSS_ J VSS_ VSS_ J VSS_ VSS_ J VSS_ VSS_ J VSS_ VSS_ J VSS_ VSS_ J VSS_ VSS_ L VSS_ VSS_ L VSS_ VSSG_ L VSS_ VSS_ L L VSS_ VSS_ M L VSS_ L VSS_ L VSS_ FT REV. FT K_ +T MIL R K_.V level need a LO from V to.v Rev hange P/N to L P/V_N U/.V_X U/.V_X U/.V_X U/.V_X +V GPP U/.V_X U/.V_X L HKF-T_. L HKF-T_. U/.V_X U/.V_X N U/V_X -T--K +V_S +PU_V_S +V US_S +V PHY_S R _ U/.V_X U/.V_X Rev hange from short pad to mount P/V_N U/.V_X U/.V_X U/.V_X U/.V_X U/.V_X Rev hange for EO *U/.V_X U/.V_X U/.V_X Rev hange for EO U/.V_X U/.V_X Quanta omputer Inc. PROJET : Size ocument Number Rev PU /(POWER//) ate: Thursday, ecember, Sheet of

7 [] RSMRST_GTE# [,,] To PIE device LN, WLN, ardreader, GPU PU_PIE_RST# RSMRST_GTE# +.V_S +V_S R K_ R SYS_RST# G *SHORT_P RSMRST# K_ PU_PIE_RST# RV-_M U/.V_X U R +V_S *E@.U/V_X [] [,,] RSMRST#_R [] [] PIE_LKREQ#_GPU [,] US_NORML_O# [,] US_S_O# [] [,] +V_S *TSHFU(F) E@_ R R _ *.K_ O_PRSNT# US O# PLTRST# [] [] [] [,] [] [] [] [,] [] US_NORML_O# US_S_O# Rev dd US O# Haudio interface are +V_S PLTRST# PIE_RST# NSWON# FH_PWRG SYS_RST# PIE_WKE# SLP_S# SLP_S# E_KRST# E_GTE E_EXT_SI# PIE_LKREQ#_LN PIE_LKREQ#_WLN P/V_N P/V_N PIE_LKREQ#_GPU US O# _RST# PIE_RST#_R RSMRST#_R NSWON# R _ FH_PWRG SYS_RST# PIE_WKE# SLP_S# SLP_S# E_KRST# E_GTE E_EXT_SI# R _ R R _ R _ R _ R _ TP *KX PU_TEST PU_TEST PU_TEST GEVENT# OR_I PWR_TN# M Y W US_NORML_O#_R US_S_O#_R O_PRSNT# US O#_R Z_LK_R Z_SOUT_R Z_SIN Z_SIN Z_SIN Z_SIN Z_SYN_R Z_RST#_R Y Y Y Y U Y Y R R N L P V V PIE_LKREQ#_LN U PIE_LKREQ#_WLN W R LK_REQ# V R EV@_ PIE_LKREQ#_GPU_R Y Y W V Y N N K K M L M L U LP_RST_L PIE_RST_L RSMRST_L +V_S +.V_S PWR_TN_L PWR_GOO +.V_S SYS_RESET_L/GEVENT_L +V_S WKE_L/GEVENT_L +V_S SLP_S_L SLP_S_L TEST TEST/TMS TEST KRST_L +V_S +V_S +V_S +V GIN/GEVENT_L LP_PME_L/GEVENT_L LP_SMI_L/GEVENT_L +V +V_S +V_S _PRES/IR_RX/GEVENT_L +V_S IR_TX/GEVENT_L +V_S IR_TX/GEVENT_L +V_S IR_RX/GEVENT_L +V_S IR_LE_L/LL_L/GPIO +V_S LK_REQ_L/ST_IS_L/ST_ZP_L/GPIO LK_REQ_L/GPIO +V LK_REQ_L/GPIO +V LK_REQ_L/ST_IS_L/ST_ZP_L/GPIO LK_REQG_L/GPIO/OSIN +V US_O_L/SPI_TPM_S_L/TRST_L/GEVENT_L US_O_L/TI/GEVENT_L +V_S US_O_L/TK/GEVENT_L +V_S US_O_L/TO/GEVENT_L +V_S Z_ITLK Z_SOUT Z_SIN/GPIO Z_SIN/GPIO Z_SIN/GPIO Z_SIN/GPIO Z_SYN Z_RST_L +V +V PI/S/Z/GPIO/RT/MIS +V_S +V +V +V +V +V +V +V +V +V +V +V +V +V_S +V_S +V GPIO +V GPIO +V GPIO +V EVSLP[]/GPIO +V GPIO +V GPIO +V EVSLP[]/GPIO +V GPIO +V SPKR/GPIO +V GPIO +V GPIO +V GPIO +V GPIO +V_S GPIO +V_S GEVENT_L +V_S GEVENT_L +V_S GEVENT_L +V_S GEVENT_L +V_S GEVENT_L +V_S GEVENT_L +V_S LINK/GEVENT_L +V_S GEVENT_L +V +V +V +V S_PWR_TRL S_LK/GPIO S_M/GPIO S_/GPIO S_WP/GPIO S_T/GPIO S_T/GPIO S_T/GPIO S_T/GPIO S_LE/GPIO SL/GPIO S/GPIO SL/GPIO S/GPIO GENINT_L/GPIO GENINT_L/GPIO FNOUT/GPIO FNIN/GPIO Y Y Y Y Y Y U V Y P Y V P V Y U Y V M V R P P N U P V U Without S, Left Unconnected. SM_RUN_LK SM_RUN_T SM_LN_LK SM_LN_T OR_I OR_I PU_O_EN OR_I OR_I PEEP OR_I OR_I OR_I OR_I GEVENT# GEVENT# GEVENT# TP O_M# O_M# [] GEVENT# TP Rev O_M# R assign GEVENT PSSWLR R _ OR_I OR_I SM_RUN_LK [,] SM_RUN_T [,] SM_LN_LK [,,] SM_LN_T [,,] TP PU_O_EN [] PE_GPIO [] PEEP [] PE_GPIO [] TP GEVENT# [] +V PE_PWRG [,,] SM_RUN_LK SM_RUN_T SM_LN_LK SM_LN_T R K_ OR_I[:] G *SHORT_P +V.K_ R.K_ R +V_S.K_ R.K_ R OR_I[:] [,,] Net GPIO Function I/O Power Well OS PE_PWRG GPIO GPU_PWRG I +.V "->" PE_GPIO GPIO GPU_RST# O +.V "->" +V_S R *K_ PU_TEST R *K_ K_X J XK_X PE_GPIO GPIO GPU_PWREN O +.V "->" R R *K_ *K_ PU_TEST PU_TEST R R NEE TO HNGE P/N ebug Only *K_ *K_ P/V_ R Y.KHZ_ M_ K_X M recomanded pf P/V_ J XK_X FT REV. RTLK FT V RT_LK [,] USE GROUN GUR FOR K_X N K_X +V R K_ PIE_LKREQ#_LN R K_ PIE_LKREQ#_WLN R K_ PIE_LKREQ#_GPU_R R K_ LK_REQ# LK Source GPP_lk lk_req GPIO +V_S R ZRP@K_PU_O_EN Rev dd K PU to +V R K_ PWR_TN# R K_ PIE_WKE# R K_ US_NORML_O# R K_ US_S_O# R K_ O_PRSNT# R K_ O_M# R K_ US O# Rev dd US/ O# Pin PU GFX Lan WLan GFX_LKP/N GPP_LKP/N GPP_LKP/N lk_reqg lk_req lk_req GPIO GPIO GPIO zalia <O> To zalia Z_SOUT_R R _ Z_SOUT [] Z_SYN_R R _ Z_SYN [] Z_LK_R R _ Z_ITLK [] *P/V_N Z_RST#_R R _ Z_RST# [] Z_SIN Z_SIN [] Local Temp +VPU <THM> R _ HYST=V for degree Hys. HYST= for degree Hys. +VPU_HW_S.U/V_Y U V HYST GTU SET OT# Rset(Kohm)=.T*T-.T+. R EV@.K/F_ R IV@.K/F_ R *K_ +VPU S_ON [,,] FN ontrol <THM> Local Temp <THM> S_ON +V VIN +VPU +V MIL.U/.V_X [] VFN FNPWR =.*VSET U VIN VO /FON VSET PEM +V R *K_ MIL [] FNSIG FNSIG +V_FN.U/V_X.U/V_X *.U/V_X N -L +V_FN Q *MMT_M R *K_ VFN U OUT IN- IN+ V OUT IN- IN+ R *IV@NT_K_ R *EV@NT_K_ R *K/F_ Q *NKW_M R R *IV@M_ *EV@M_ FNSIG *VPORT K-V +V_FN *VPORT K-V Rev hange for EO R *K_ R *K/F_ *LM R *.K/F_ R *K/F_ Q *NKW_M Quanta omputer Inc. PROJET : Size ocument Number Rev PU /(PI/S/Z/GPIO/RT/MIS) Tuesday, ecember, ate: Sheet of

8 ST H ST O [] ST_TXP [] ST_TXN [] ST_RXN [] ST_RXP [] ST_TXP [] ST_TXN [] ST_RXN [] ST_RXP +.V R R K/F_ K/F_ ST_LRN ST_LRP UE ST_TXP Y ST_TXN ST_RXN Y ST_RXP Y ST_TXP ST_TXN Y ST_RXN ST_RXP R ST_ZVSS P ST_ZV_ LK/ST/US/SPI/LP USLK/M_M_M_OS W US_ZVSS G US_HSP L US_HSN L US_HSP J US_HSN J US_HSP G US_HSN G US_HSP G US_HSN G TP US_ZVSS R.K/F_ USP+ USP+ [] USP- USP- [] USP+ USP+ [] USP- USP- [] Rev dd USP for To US. aughter/ To US. aughter/ HU TP ST_LE# Integrated lock Mode: Leave unconnected. Y ST_T_L/GPIO ST_X ST_X +V US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN F F E E USP+ USP- USP+ USP- USP+_ USP-_ USP+ [] USP- [] USP+ [] USP- [] USP+_ [] USP-_ [] Touch Screen ard Reader on LVS HU Reference o not change layer and cross plane [] [] [] [] [] [] LK_PIE_VGP LK_PIE_VGN LK_PIE_LNP LK_PIE_LNN LK_PIE_WLNP LK_PIE_WLNN LK_PIE_VGP LK_PIE_VGN LK_PIE_LNP LK_PIE_LNN LK_PIE_WLNP LK_PIE_WLNN RP RP RP X X X INT_LK_PIE_VGP INT_LK_PIE_VGN INT_LK_PIE_LNP INT_LK_PIE_LNN INT_LK_PIE_WLNP INT_LK_PIE_WLNN U U E E GFX_LKP GFX_LKN GPP_LKP GPP_LKN GPP_LKP GPP_LKN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN USP+ USP- USP+ USP- USP+ USP- USP+ [] USP- [] USP+ [] USP- [] USP+ [] USP- [] WLN US./. S& US./. w/o S& HU For EMI PLK_EUG Integrated lock Mode: GPP_LKP US_SS_ZVSS E USSS_LRN R K/F_ Leave unconnected. GPP_LKN US_SS_ZV US_UL E USSS_LRP R K/F_ +.V_UL ardreader pass through PIE Leave unconnected. GPP_LKP US_SS_TXP T US_TXP US_TXP [] P/V_ M_X GPP_LKN US_SS_TXN T US_TXN US_TXN [] US. S& P XM_M_M_OS US_SS_RXP V US_RXP US_RXP [] Y US_SS_RXN V US_RXN US_RXN [] Rev hange cap value for vendor suggestion MHZ_ R N XM_X M_ US_SS_TXP R US_TXP US_TXP [] US_SS_TXN R US_TXN US_TXN [] US. Port P/V_ M_X N XM_X US_SS_RXP W US_RXP US_RXP [] US_SS_RXN W US_RXN US_RXN [] R _ [] PLK_EUG R _ [] PLK_ LP_LK LP_LK_R [] LP_LK R _ Y LPLK +V LP_LK LP_LK_R +V +V FH_SPI_LK_R FH_SPI_LK [] LP_LK R _ W LPLK SPI_LK/GPIO U R _ +V SPI_S_L/GPIO W FH_SPI_S#_R R _ FH_SPI_S# L T [,] L L +V_S +V SPI_S_L/GPIO R TP L T +V_S +V_S FH_SPI_SO_R FH_SPI_SO [,] L L SPI_O/GPIO R R _ L R +V_S +V_S FH_SPI_SI [,] L L SPI_I/GPIO R L R +V_S +V_S SPI_HOL# [,] L L SPI_HOL_L/GEVENT_L U LFRME# P +V_S +V_S FH_SPI_WP [,,] LFRME# LFRME_L SPI_WP_L/GPIO U TP P +V_S [] FH_SPI_S# LRQ_L SERIRQ V +V double check [] FH_SPI_LK [] SERIRQ SERIRQ/GPIO LKRUN# P [] FH_SPI_SO [] LKRUN# LP_LKRUN_L +V [] FH_SPI_SI LPP# V [] LPP# LP_P_L/GEVENT_L/SPI_TPM_S_L +V_S *P/V_ +V_S R K_ FT REV. FT FH_SPI_S# FH_SPI_LK FH_SPI_SO FH_SPI_SI R _ WQVSSIG:KEPN WQFVSSIQ:KEEFPN +V_S R K_ U R E# V K_ SK FH_SPI_SI_R SI SPI_HOL# SO HOL# WP# VSS *P/V_N WQVSSIG.U/V_X PLK_ *P/V_ +V_S R K_ FH_SPI_WP Rev hange from M to M [,,] OR_I[:] OR_I[:] OR I SETTING +V R R UM@K_ *K_ OR_I R OR_I R EV@K_ K_ Rev Modify oard I Rev hange oard I setting oard I UM SKU PX SKU VRM GHz VRM M US. US. " MTN " W/O S& W S& Metal/IMR TEXTURE RSV RSV I H L I H L N-METL (W/O KLE) lways PU METL (W/ KLE) N-rand lways PU rand (ONKYO) W/O HMI W HMI Reserve P N-rand rand(harman/kardon) I H L I L H I H L I H L I H L I H L I H L I H L I H L I I +V_S R R R R R R R R R U@K_ OR_I R *MTN@K_ OR_I R KLE@K_ OR_I R N-rand@K_ OR_I R NHM@K_ OR_I R K_ OR_I R Metal@K_ OR_I R *K_ OR_I R NS&@K_ OR_I R *NKLE@K_ *ONKYO@K_ HM@K_ *K_ Texture@K_ K_ S&@K_ Rev hange oard I for Harman-Kardon Stuff R, Remove R Quanta omputer Inc. PROJET : Size ocument Number Rev PU /(LK/ST/US/SPI) Wednesday, January, ate: Sheet of

9 STRPS PINS +V_S +V_S +V_S +V_S +V_S R *K_ R K_ R K_ R K_ R *K_ LP_LK [] LP_LK LP_LK [] LP_LK LFRME# [,,] LFRME# RT_LK [,] RT_LK GEVENT# [] GEVENT# [] SYS_RST# R R R R R [] VRM_PWRG K/F_ *K/F_ *K/F_ *.K_.K_ VRM_PWRG *SS_M SS_M +.V_S R K_ U/V_X +.V_S *.U/V_X U R *_ *SNLVGKR FH_PWRG FH_PWRG [] REQUIRE STRPS [] MPWROK MPWROK SS_M R _ LP_LK LP_LK LFRME# RT_LK GEVENT# [,] MINON *SS_M PULL HIGH PULL LOW OOT Fail Timer ENLE OOT Fail Timer ISLE EFULT Internal LKGEN ENLE Internal LKGEN ISLE SPI ROM LP ROM Normal Power Timing ENLE EFULT EFULT EFULT Normal Power Timing ISLE SPI Voltage.V SPI Voltage.V EFULT PWRG IRUIT Quanta omputer Inc. PROJET : Size ocument Number Rev PU /(STRP & PWRG) Tuesday, ecember, ate: Sheet of

10 R_ST(R) Place these aps near So-imm.. EMI Suggestion Reserve IT test point placed between JIM and JIM Rev hange for EO Rev hange for EO M OT M M M M M M M M M WE# M [:] M M M M M M M M M M OT SM_RUN_T SM_RUN_LK M S# M S# M LKP M LKN M LKP M LKN M KE M KE M S# M RS# M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSP M M M M M M M M M M M M M M M QSP[:] M QSN[:] M QSN M QSN M QSN M QSN M QSN M QSN M QSN M QSN M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q IMM_S IMM_S M Q[..] M S# M S# M S# M MEM_VREF_SUS M M[:] M S#[:] OP_OUT Q_OP- Q_OP+ M [:] [,] M LKN [] M LKP [] M S# [] M S# [] M KE [] M KE [] M LKN [] M LKP [] M QSP[:] [,] M WE# [,] M RS# [,] M S# [,] M Q[..] [,] M OT [] M OT [] M QSN[:] [,] M EVENT# [,] M RST# [,] SM_RUN_T [,] SM_RUN_LK [,] M M[..] [,] M S#[..] [,] +.VSUS +.VSUS +SMR_VTERM +V +.VSUS +.V_VREF_ +.V_VREF_Q +.V_VREF_ +.V_VREF_ +.V_VREF_Q +V +.VSUS +SMR_VTERM +SMR_VREF +.V_VREF_Q +.VSUS +SMR_VREF +PU_M_VREFQ_SUS +V_S +PU_M_VREFQ_SUS Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R IMM- Tuesday, ecember, Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R IMM- Tuesday, ecember, Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R IMM- Tuesday, ecember, *E@.U/V_X ES@P/V_N U/.V_X.U/V_X ES@P/V_N ES@P/V_N R K_.U/V_X R _ R _ U/.V_X U/V_X.U/V_X.U/V_X.U/.V_X R K/F_ R *_ *.U/V_X R *_ U/.V_X R *_ U/.V_X P R SRM SO-IMM (P) JIM RSK--TP /P /# S# S# K K# K K# KE KE S# RS# WE# S S SL S OT OT M M M M M M M M QS QS QS QS QS QS QS QS QS# QS# QS# QS# QS# QS# QS# QS# Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q ES@P/V_N U/.V_X U/.V_X R K_ U/V_X R *_ U/.V_X.U/.V_X R K/F_ P/V_X U/.V_X *U/.V_X R K/F_ P/V_X P R SRM SO-IMM (P) JIM RSK--TP V V V V V V V V V V V V V V V V V V VSP N N NTEST EVENT# RESET# VREF_Q VREF_ VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VTT VTT U/.V_X.U/V_X U/.V_X R *K_ - + V+ V- U *MPRT-E/OT ES@P/V_N ES@P/V_N *.U/V_X ES@P/V_N U/.V_X U/V_X R K/F_ U/.V_X U/V_X R *_ U/.V_X *U/.V_X R *_ R *_.U/V_X

11 R_ST(R) Place these aps near So-imm.. EMI Suggestion Reserve IT test point Rev hange for EO Rev hange for EO Rev hange for EO M OT M M M M M M M M M WE# M [:] M M M M M M M M M M OT SM_RUN_T SM_RUN_LK M S# M S# M LKP M LKN M LKP M LKN M KE M KE M S# M RS# M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSP M M M M M M M M M M M M M M M QSN M QSN M QSN M QSN M QSN M QSN M QSN M QSN M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q IMM_S IMM_S M Q[..] M S# M S# M S# M M QSP[:] M QSN[:] M S#[:] M M[:] M [:] [,] M LKN [] M LKP [] M S# [] M S# [] M KE [] M KE [] M LKN [] M LKP [] M QSP[:] [,] M WE# [,] M RS# [,] M S# [,] M Q[..] [,] M OT [] M OT [] M QSN[:] [,] M EVENT# [,] M RST# [,] SM_RUN_T [,] SM_RUN_LK [,] M S#[..] [,] M M[..] [,] +.VSUS +.VSUS +SMR_VTERM +V +.V_VREF_Q +.V_VREF_ +.V_VREF_ +.V_VREF_Q +V +.VSUS +SMR_VTERM +V Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R IMM- Tuesday, ecember, Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R IMM- Tuesday, ecember, Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R IMM- Tuesday, ecember, P/V_X U/.V_X ES@P/V_N U/V_X ES@P/V_N ES@P/V_N U/.V_X U/.V_X P R SRM SO-IMM (P) JIM RSK--TP V V V V V V V V V V V V V V V V V V VSP N N NTEST EVENT# RESET# VREF_Q VREF_ VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VTT VTT U/.V_X U/.V_X.U/V_X ES@P/V_N ES@P/V_N U/.V_X *U/.V_X *U/.V_X.U/V_X P/V_X U/.V_X U/.V_X ES@P/V_N U/.V_X U/.V_X U/.V_X U/V_X ES@P/V_N U/.V_X U/.V_X U/V_X P R SRM SO-IMM (P) JIM RSK--TP /P /# S# S# K K# K K# KE KE S# RS# WE# S S SL S OT OT M M M M M M M M QS QS QS QS QS QS QS QS QS# QS# QS# QS# QS# QS# QS# QS# Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q.U/V_X U/V_X R K_.U/V_X R K_

12 <VG> U PRT F [] [] [] [] [] [] PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN Y Y W W V PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_TXP Y PEG_RXP EV@.U/V_X PIE_TXN Y PEG_RXN EV@.U/V_X PIE_TXP PIE_TXN PIE_TXP PIE_TXN W W U U PEG_RXP PEG_RXN PEG_RXP PEG_RXN EV@.U/V_X EV@.U/V_X EV@.U/V_X EV@.U/V_X PEG_RXP [] PEG_RXN [] PEG_RXP [] PEG_RXN [] PEG_RXP [] PEG_RXN [] Mars Power-on sequence => +V_GPU => +V,+VI,+.V_GPU,+.V_GPU => +.V_GPU [] [] PEG_TXP PEG_TXN PEG_TXP PEG_TXN V U PIE_RXP PIE_RXN PIE_TXP PIE_TXN U U PEG_RXP PEG_RXN EV@.U/V_X EV@.U/V_X PEG_RXP [] PEG_RXN [] U T T R R P P N PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN T T T T P P P P PEG Intel platform: Lane ~ Lane razos platform: Lane ~ Lane omal and Sabine platform: Lane ~Lane Richland and Kabini platform: Lane ~ Lane N M M L L K K J N_PIE_RXP N_PIE_RXN N_PIE_RXP N_PIE_RXN N_PIE_RXP N_PIE_RXN N_PIE_RXP N_PIE_RXN PI EXPRESS INTERFE N_PIE_TXP N_PIE_TXN N_PIE_TXP N_PIE_TXN N_PIE_TXP N_PIE_TXN N_PIE_TXP N_PIE_TXN N N N N L L L L +VRUN/+VRUN/VR RUNPWROK Power Up Reset Sequence J H N_PIE_RXP N_PIE_RXN N_PIE_TXP N_PIE_TXN K K MVQ/V/VI.V_IO/PIE_V H G G F F E N_PIE_RXP N_PIE_RXN N_PIE_RXP N_PIE_RXN N_PIE_RXP N_PIE_RXN N_PIE_TXP N_PIE_TXN N_PIE_TXP N_PIE_TXN N_PIE_TXP N_PIE_TXN J J K K H H PWRGOO PIE_RST#(PERST) ms max ms min ms min [] [] LK_PIE_VGP LK_PIE_VGN LOK PIE_REFLKP PIE_REFLKN PIE lock us min ms max LIRTION PIE_LR_TX Y R R *EV@.K/F_ EV@.K/F_ sic in Reset Hardware Reset Sequence FG Space Ready [] PERST#_UF PERST#_UF R *E@.U/V_X R EV@_ EV@K_ PERST#_UF_R H TEST_PG PERST EV@Mars_M PIE_LR_RX Y R EV@K/F_ +.V_GPU Quanta omputer Inc. PROJET : Size ocument Number Rev Mars_M/ PEG* ate: Tuesday, ecember, Sheet of

13 <VG> [] [] GENIL_LK GENIL_VSYN MUTI GFX GENLK_LK GENLK_VSYN U PRT F N_TXP_PP N_TXM_PN U V V +.V_GPU nalog Power.V@m L Mars@LMSN_M J K SWPLOK SWPLOK P N_TXP_PP N_TXM_PN N_TXP_PP N_TXM_PN T R U V Mars@.U/V_X Mars@U/.V_X Mars@.U/.V_X [,] [,] N_MLK N_MT Q Q EV@NKW_M R EV@K/F_ R EV@K/F_ EV@NKW_M +V_GPU GPU_SMLK GPU_SMT.V GPIO Tempeature function: onnect to E GPU_SMLK GPU_SMT R U P W R R U U W P W U R W U T V N V T R W U P V T R W U P J H N_VPNTL_MVP_ N_VPNTL_MVP_ G_NTL N_VPNTL_ N_VPNTL_ N_VPLK G_T G_T G_T G_T G_T G_T G_T G_T G_T G_T G_T G_T G_T G_T G_T G_T G_T G_T G_T G_T G_T G_T G_T G_T SMLK SMus SMT P P P N_TXP_PP N_TXM_PN N_TXP_PP N_TXM_PN N_TXP_PP N_TXM_PN N_TXP_PP N_TXM_PN N_TXP_PP N_TXM_PN N_TXP_PP N_TXM_PN N_TXP_PP N_TXM_PN N_TXP_PP N_TXM_PN N_TXP_PP N_TXM_PN N_TXP_PP N_TXM_PN N_TXP_PP N_TXM_PN N_TXP_PP N_TXM_PN T R R T V U R T T U U V T R U V T R U T T R U V lose to SI igital Power.V@m R R R_pu EV@.K/F_ R_pu *EV@.K/F_ for Sun for Mars a VI V_T V_T V_T PS_ PS_ PS_ R_pd *EV@.U/V_X R EV@K/F_ a Mars@.U/V_X R_pd *EV@.U/V_X Mars@U/.V_X R EV@.K/F_ L Mars@.U/.V_X Mars@LMSN_M a Mars@.U/.V_X Rev dd for Mars R_pu R_pd EV@.U/V_X R *EV@K/F_ R EV@.K/F_ +V_GPU R R EV@.K_ EV@.K_ GPU_SL GPU_S K J SL S I N_TXP_PP N_TXM_PN T R [,,] S_ON Q On Mars only HP and GPIO HP are available for display hot-plug detection +.V_GPU R R *MENE_M R *EV@K_ [] [] GPIO TF [] [] [] [] [] Place close to hip EV@/F_ R EV@/F_ EV@K_ EV@.U/V_X [,] [] [] [] [] [] [] [] [] GPU_GPIO GPU_GPIO GPU_GPIO GPU_GPIO GPU_GPIO GPU_GPIO GPU_GPIO GPU_GPIO GPU_GPIO GFX_ORE_NTRL GFX_ORE_NTRL GFX_ORE_NTRL [] GPU_GPIO [] GPU_GPIO PIE_LKREQ#_GPU GFX_ORE_NTRL GFX_ORE_NTRL GPU_GENERI GPU_VREFG R T T T T T T T T *EV@.K_ H H N H J K J H J K L M M M K G N M L J K N G G J K J K J H H K H L GENERL PURPOSE I/O GPIO_ GPIO_ GPIO_ GPIO TT GPIO TH GPIO LON GPIO ROMSO GPIO ROMSI GPIO ROMSK GPIO_ GPIO_ GPIO_ GPIO HP GPIO PWRNTL_ GPIO_ GPIO THERML_INT GPIO_ GPIO TF GPIO PWRNTL_ GPIO_ GPIO ROMS LKREQ GPIO_ GPIO_ GENERI GENERI GENERI GENERI GENERIE GENERIF GENERIG E_ HP G_VREFG O PX_EN MLPS R VSSN# G VSSN# VSSN# HSYN VSYN RSET V VSSQ VI VSSI N# N# N_SVI N_SVI N# N_SVI N# N# N# N_TSVSSQ PS_ PS_ PS_ PS_ E F E E V U F G V VI N_TSVSSQ should be tied to on Thames/Whistler/Seymour F PS_ should be tied to on Thames/Whistler/Seymour M G R PS_ PS_ PS_ PS_ T T T T T T T T T T T T PS_,PS_, PS_ are N on Thames/Whistler/Seymour GPU_HSYN [] GPU_VSYN [] EV@/F_ PS_ [] System Memory perture size M M M Reserved PS[:] ROMIFG[:] MLPS R_pu N.K.K.K.K.K.K.K R_pd.K K K.K.K.K K N its [:] Ra K.K.K.K.K.K.K.K.K K P/N SF SF SF SF SF SF SF SF SF SF +.V_GPU L.V@m on-die thermal sensor power EV@LMSN_M +V_GPU +V_GPU PU:isable MLPS P:Enable MLPS EV@U/.V_X R R R R EV@U/.V_X EV@K_ *EV@.K/F_ T T T T T T T *EV@K/F_ EV@K/F_ TSV EV@.U/V_X M N K L M F G K L J J EUG TESTEN JTG_TRST JTG_TI JTG_TK JTG_TMS JTG_TO THERML PLUS MINUS GPIO FO TS_ TSV TSVSS /UX LK T UXP UXN LK T UXP UXN N_LK_UXP N_T_UXN N_LK_UXP N_T_UXN N_LK_UXP N_T_UXN N_LK_UXP N_T_UXN VGLK VGT EV@Mars_M M N M L M L N M L M L M N M K K J J a its [:] nf nf nf N P/N HK XR MLPS it its [:] HJE XS PS_ HK HK PS_ PS_ PS_ XXX Quanta omputer Inc. PROJET : Size ocument Number Rev Mars_M/ GPIO_P_RT_I Wednesday, January, ate: Sheet of

14 <VG> PE/PF/LVS UI UG PRT for Sun PRT F LVS ONTROL RSV RSV K J R R *EV@K/F_ *EV@K/F_ +.V_GPU PEF_V.V@m for Sun.V@m for Mars PLL_V L EV@PYT-Y-N_. PLL_V EV@U/.V_X EV@U/.V_X EV@.U/V_X M P_VR N P_V N P_VSSR XTLIN V GPU_XTLIN XTLOUT U GPU_XTLOUT R EV@M/F_ R EV@_ EV@P/V_N Y EV@MHZ_ EV@P/V_N TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN K L J K H J.V@m for Sun Memory phase-locked loop power..v@m for Mars edicated analog power pin for the memory PLLs. M FE suggest ohm +.V_GPU L EV@FMKF-T_M EV@U/.V_X EV@U/.V_X MPLL_PV EV@.U/V_X H MPLL_PV H MPLL_PV M SPLL_PV N SPLL_V PLLS/XTL XO_IN W XO_IN W T T LVTMP TXP_PP TXM_PN N_TXOUT_UP N_TXOUT_UN TXP_PP TXM_PN G H F G P R +.V_GPU.V@m for Sun.V@m for Mars Engine phase-locked loop power. edicated analog power pin for the engine and UV PLLs. SPLL_PV.V@m for Sun Engine phase-locked loop power..v@m for Mars edicated digital power pin for the engine and UV PLLs. M FE suggest ohm +.V_GPU L L EV@LMSN_M EV@U/.V_X EV@U/.V_X EV@LMSN_M EV@.U/V_X SPLL_V N SPLL_PVSS F N_XTL_PV F N_XTL_PVSS EV@Mars_M LKTEST LKTEST K L LKTEST LKTEST *EV@.U/V_X R *EV@./F_ *EV@.U/V_X R *EV@./F_ TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN N_TXOUT_LP N_TXOUT_LN EV@Mars_M W U R U P R N P EV@U/.V_X EV@U/.V_X EV@.U/V_X PEF_V R R *EV@_ *EV@_ Quanta omputer Inc. PROJET : Size ocument Number Rev Mars_M/ XTL_LVS Tuesday, ecember, ate: Sheet of

15 <VG> +V_GPU [,] [] GPU_GPIO GPU_GPIO R R *EV@K/F_ EV@K/F_ ONFIGURTION STRPS -- SEE EH TOOK FOR STRP ETILS LLOW FOR PULLUP PS FOR THESE STRPS N IF THESE GPIOS RE USE, THEY MUST NOT ONFLIT URING RESET [] GPU_GPIO R *EV@K/F_ STRPS MLPS GPIO PIN ESRIPTION OF EFULT SETTINGS efault Setting [] [] [] GPU_GPIO GPU_GPIO GPU_GPIO R R R *EV@K/F_ EV@K/F_ *EV@K/F_ MLPS_ISLE N GPIO FO Enable MLPS, N for Thames/Whistler/Seymour : Enable MLPS, disable GPIO PINSTRP : isable MLPS, enable GPIO PINSTRP [] [] GPU_GPIO GPU_GPIO R R *EV@K/F_ *EV@K/F_ STRP_TX_FG_RV_FULL_SWING PS_[] ontrol the transmitter full-/half- swing mode : % Tx output swing : Full Tx output swing [] GENIL_VSYN [] GPU_HSYN R R *EV@K/F_ *EV@K/F_ STRP_TX_EEMPH_EN PS_[] PIe transmitter, de-emphasis enable : Tx de-emphasis disabled : Tx de-emphasis enabled [] [] GPU_VSYN GENIL_LK R R *EV@K/F_ *EV@K/F_ STRP_IF_GEN_EN_ PS_[] PIe GEN apability : GEN not supported at power-on : GEN supported at power-on for Kabini [] GPU_GPIO R *EV@K/F_ STRP_IF_VG_IS PS_[] VG disable determines whether or not the card will be recognized as the system's VG controler (through the SULSS field in the PI configuration space) [] GPU_GPIO [] GPU_GENERI [] GPU_GPIO lose to SI R *EV@K/F_ R *EV@K/F_ R *EV@K/F_ V_T Rev dd for GHz VRM ROM_ONFIG[:] PS_[..] : VG controller capacity enabled : The device will not be recognized as the system's VG controller Serial ROM type or Memory perture Size Select If GPIO =, defines memory aperture size If GPIO =, defines ROM type - Kbit MP (ST) - Mbit MP (ST) - Mbit MP (ST) - Mbit MP (ST) - Mbit MP (ST) - Kbit PmLV (hingis) - Mbit PmLV (hingis) XXX [] PS_ XXX for Mars R_pu XXX for Sun PS_ a R_pd Mars@.U/V_X R HG@.K/F_ R HG@.K/F_ R SG@.K/F_ R SM@K/F_ R SG@.K/F_ R MIRON@.K/F_ R MG@.K/F_ R HGG@.K/F_ R MG@.K/F_ R SGG@K/F_ R HGG@.K/F_ R SGG@.K/F_ STRP_IOS_ROM_EN U[] U[] PS_[] N N HSYN VSYN Enable external IOS ROM device : isabled : Enabled - No audio function - udio for P only - udio for P and HMI if dongle is detected - udio for both P and HMI HMI must only be enabled on systems that are legally entitled. It is the responsibility of the system designer to ensure that the system is entitled to support this feature. XX N/ PS_[] Reserved for internal use only. Must be at reset Rev dd for Mars MLPS R_pu R_pd its [:] N/ STRP_IF_LK_PM_EN PS_[] PS_[] GENLK_LK GPIO Reserved PIe reference clock power management capability is reported in the PI : The LKREQ power management capability is disabled : The LKREQ power management capability is enabled N.K a its [:] P/N RESERVE RESERVE N N GPIO GENERI Reserved Reserved (for Thames/Whistler/Seymour only).k.k.k.k K K.K.K nf nf nf N HK HK HK U_PORT_ONN_PINSTRP[] U_PORT_ONN_PINSTRP[] U_PORT_ONN_PINSTRP[] PS_[] PS_[] PS_[] N N N STRPS TO INITE THE NUMER OF UIO PLE ISPLY OUTPUTS = usable endpoints = usable endpoints = usable endpoints = usable endpoints = usable endpoints = usable endpoints = usable endpoints = all endpoints are usable XXX.K.K.K.K K N Power Up Reset Sequence R Memory TYPE +VRUN/+VRUN/VR Ra P/N Vendor Vendor P/N /S P/N (QI P/N) Size MLPS RUNPWROK K.K.K.K.K.K.K.K.K K SF SF SF SF SF SF SF SF SF SF Hynix Micron Samsung HTQGFR- (M*) HTGFR- (M*) MTJMJT-G:K (M*) MTKMH-G:E (M*) KWGE- (M*) KWG-H (M*) KMGWTW * KPGWTW * KGSTL * KPGSTL * G G G G G G MVQ/V/VI.V_IO/PIE_V PWRGOO PIE_RST#(PERST) PIE lock ms max ms min ms min us min ms max sic in Reset Hardware Reset Sequence FG Space Ready Quanta omputer Inc. PROJET : Size ocument Number Rev Mars_M/ STRPS_Thermal Tuesday, ecember, ate: Sheet of

16 +.V_GPU <VG> V_GPU Sun R) R bits) Mars R bits) Level translation between core and I/O, excluding memory receivers. (.V@m for Sun, Mars) (.V@m for Sun, Mars) I/O power for.-v pins, such as GPIOs. M FE suggest ohm +V_GPU L EV@LMSN_M (.V@m for Mars; N for Sun) Power for all VP pins; VPT_[:] VO or GPIO. M FE suggest ohm +.V_GPU EV@U/.V_X EV@.U/.V_X *EV@.U/V_X *EV@.U/V_X L L *EV@.U/.V_X EV@.U/.V_X *EV@.U/V_X *EV@.U/V_X *EV@U/.V_X *EV@.U/.V_X EV@LMSN_M EV@U/.V_X Mars@FMKF-T_M + Mars@U/.V_X *EV@U/.V_X *EV@.U/.V_X EV@U/.V_P_Eb EV@U/.V_X EV@U/.V_X Mars@U/.V_X V_T EV@.U/.V_X EV@U/.V_X VR EV@U/.V_X VR Mars@.U/V_X V_T EV@.U/V_X EV@U/.V_X F G J K L G G G G G G G H J J K K K L L L L L L M N P R U U Y Y F F G G F F G G F F F F G G G MEM I/O VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR LEVEL TRNSLTION V_T V_T V_T V_T I/O VR VR VR VR VP VR VR VR VR VR VR VR VR PRT F UE PIE O N_PIE_VR N_PIE_VR N_PIE_VR N_PIE_VR N_PIE_VR N_PIE_VR N_IF_V N_IF_V PIE_PV ORE PIE_V PIE_V PIE_V PIE_V PIE_V PIE_V PIE_V PIE_V PIE_V PIE_V PIE_V PIE_V IF_V IF_V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V W Y V W G G H H J J L M N R T U N T F F F G G H H H M N R R R R T T T T U U U U U V V V V V Y Y Y Y Y Y On Mars except for, all other balls can be N PIE_VR EV@.U/V_X EV@U/.V_X EV@.U/V_X (.V@. for Sun, Mars) EV@U/.V_X EV@U/.V_X EV@U/.V_X EV@U/.V_X EV@U/.V_X EV@U/.V_X EV@U/.V_X EV@U/.V_X EV@U/.V_X +.V_GPU EV@U/.V_X PIe IO power. PIe digital power supply. (.V@. for Sun, Mars) EV@U/.V_X EV@U/.V_X EV@U/.V_X EV@U/.V_X EV@U/.V_X EV@U/.V_X *EV@U/.V_X EV@U/.V_X (.V@m for Sun, Mars) EV@U/.V_X lways connect to PIE_V for both O & non-o designs. edicated core power, provides power to the internal logic. EV@U/.V_X EV@U/.V_X EV@U/.V_X EV@U/.V_X (.V~.V@/Sun) +.V_GPU (.~.V@) EV@U/.V_X EV@U/.V_X Isolated (clean) core power for the l/o logic. L L EV@U/.V_X EV@U/.V_X EV@U/.V_X EV@HKF-T_. EV@U/.V_X EV@U/.V_X EV@U/.V_X EV@U/.V_X EV@U/.V_X EV@HKF-T_ +.V_GPU EV@U/.V_X +VGPU_ORE EV@U/.V_X EV@U/.V_X EV@U/.V_X EV@U/.V_X +VGPU_ORE EV@U/.V_X EV@U/.V_X EV@U/.V_X EV@U/.V_X EV@U/.V_X EV@U/.V_X EV@U/.V_X EV@U/.V_X EV@U/.V_X EV@U/.V_X [] VGPU_ORE_VSSENSE VORE_SEN/RTN route a differtial pair. [] VGPU_ORE_VSSSENSE R R EV@_ EV@_ VOLTGE SENESE F F_V G F_VI H F_ EV@Mars_M ISOLTE ORE I/O VI VI VI VI VI VI VI M VI M VI M VI M VI N VI N VI N VI N VI N VI R VI R VI R VI T VI T VI V VI Y VI *EV@U/.V_X *EV@U/.V_X EV@U/.V_X *EV@U/.V_X *EV@U/.V_X EV@U/.V_X L EV@HKF-T_ *EV@U/.V_X EV@U/.V_X EV@U/.V_X *EV@U/.V_X Quanta omputer Inc. PROJET : Size ocument Number Rev Mars_M/ MainPower Tuesday, ecember, ate: Sheet of

17 <VG> UH PRT F +.V_GPU (.V@m/link for Mars) L EV@PYT-Y-N_.PEF_V EV@U/.V_X PEF_V EV@U/.V_X R PEF_V_MRS MRS@_ EV@.U/V_X Reserve for Mars R R R *EV@/F_ *EV@/F_ EV@/F_ N P P P U V P P P P U V H J F G M L W W M P_VR N N N N N N N N N N N N P_VR P_VR P_VR P_VR P_VR P_VR LIRTION N_P_LR N_P_LR P_LR P_V P_V P_V P_V P_V N N N N P_V P_V P_V P_V P P_VSSR P_VSSR P_VSSR P_VSSR P_VSSR P_VSSR P_VSSR P_VSSR P_VSSR P_VSSR P_VSSR P_VSSR P_VSSR P_VSSR P_VSSR P_VSSR P_VSSR P_VSSR P_VSSR P_VSSR P_VSSR P_VSSR P_VSSR P_VSSR P_VSSR P_VSSR P_VSSR P_VSSR P_VSSR P_VSSR P_VSSR P_VSSR P_VSSR P_VSSR P P N P P T P P L M K K N P P W W N P P W W N P P W W N P P W W N P R U F H K L V R V R N M Mars@U/.V_X Mars@U/.V_X Mars@U/.V_X Mars@U/.V_X For ES (.V@m/link for Mars) PLL_V_MRS +.V_GPU Mars@.U/V_X Mars@.U/V_X R (.V@m/link for Mars) EV@P/V_N EV@P/V_N MRS@_ PLL_V EV@Mars_M Quanta omputer Inc. PROJET : Size ocument Number Rev Mars_M/ P_Powers ate: Tuesday, ecember, Sheet of

18 <VG> Mars G N Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : Mars_M/ Tuesday, ecember, Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : Mars_M/ Tuesday, ecember, Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : Mars_M/ Tuesday, ecember, PRT F EV@Mars_M UF Y Y Y Y Y Y W W V V V V V V U U U U U U U U T T T T T T T R R R R R R R R N N N N N N N M M M L L L L L L K K J J J J H G G F F F F F F F F F F F F Y PIE_VSS Y PIE_VSS W PIE_VSS W PIE_VSS V PIE_VSS V PIE_VSS U PIE_VSS U PIE_VSS T PIE_VSS T PIE_VSS T PIE_VSS R PIE_VSS P PIE_VSS P PIE_VSS P PIE_VSS N PIE_VSS N PIE_VSS M PIE_VSS M PIE_VSS L PIE_VSS L PIE_VSS K PIE_VSS K PIE_VSS K PIE_VSS J PIE_VSS J PIE_VSS H PIE_VSS H PIE_VSS H PIE_VSS G PIE_VSS G PIE_VSS F PIE_VSS F PIE_VSS E PIE_VSS PIE_VSS W VSS_MEH W VSS_MEH VSS_MEH F F E E R P P P N N N N N M M M L L L L L L L L L L K K K J J J J J H G G G N_EVQ G G G F F F F E E

19 <VG> VM_Q[..] [] VM_Q[..] VM_M[..] [] VM_M[..] VM_RQS[..] [] VM_RQS[..] VM_WQS[..] [] VM_WQS[..] VM_M[..] [] VM_M[..] VM_ [] VM_ VM_ [] VM_ VM_ [] VM_ Place MVREF dividers and aps close to SI +.V_GPU (.*VR) Ra R EV@./F_ Rb R EV@/F_ EV@U/.V_X +.V_GPU R R VM_Q VM_Q VM_Q VM_Q E VM_Q G VM_Q VM_Q F VM_Q E VM_Q VM_Q F VM_Q VM_Q VM_Q F VM_Q VM_Q VM_Q E VM_Q VM_Q F VM_Q VM_Q VM_Q F VM_Q VM_Q VM_Q E VM_Q VM_Q VM_Q F VM_Q VM_Q VM_Q F VM_Q VM_Q E VM_Q VM_Q VM_Q F VM_Q VM_Q VM_Q F VM_Q VM_Q E VM_Q F VM_Q VM_Q F VM_Q VM_Q VM_Q F VM_Q VM_Q VM_Q G VM_Q H VM_Q J VM_Q H VM_Q G VM_Q G VM_Q K VM_Q K VM_Q G VM_Q VM_Q VM_Q E VM_Q VM_Q VM_Q E VM_Q MVREF L MVREFS L L N G M EV@/F_ M *EV@/F_ H U PRT F GR/R Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ MEMORY INTERFE M_/M_ M_/M_ M_/M_ M_/M_ M_/M_ M_/M_ M_/M_ M_/M_ M_/M_ M_/M_ M_/M_ M_/M_ M_/M_ M_/M_ M_/M_ M_/M_ WK_/QM_ WK_/QM_ WK_/QM_ WK_/QM_ WK_/QM_ WK_/QM_ WK_/QM_ WK_/QM_ E_/QS_ E_/QS_ E_/QS_ E_/QS_ E_/QS_ E_/QS_ E_/QS_ E_/QS_ I_/QS_ I_/QS_ I_/QS_ I_/QS_ I_/QS_ I_/QS_ I_/QS_ I_/QS_ I/OT I/OT LK LK LK LK RS RS S S S_ S_ S_ S_ MVREF KE MVREFS KE N_MEM_LRN WE N_MEM_LRN WE N_MEM_LRN N_MEM_LRP M_/M_ MEM_LRP M_/M_ N_MEM_LRP M_/M_ M_/RSV G VM_M J VM_M H VM_M J VM_M H VM_M J VM_M H VM_M G VM_M H VM_M H VM_M L VM_M G VM_M J VM_M H VM_ J VM_ H VM_ VM_M VM_M VM_M E VM_M VM_M VM_M E VM_M VM_M VM_RQS VM_RQS VM_RQS E VM_RQS E VM_RQS E VM_RQS J VM_RQS VM_RQS VM_WQS E VM_WQS E VM_WQS VM_WQS VM_WQS VM_WQS J VM_WQS F VM_WQS J G H VM_LK G VM_LK# J VM_LK H VM_LK# K VM_RS# K VM_RS# K VM_S# K VM_S# K VM_S# K M VM_S# K K VM_KE J VM_KE K VM_WE# L VM_WE# H VM_M J VM_M M M VM_OT [] VM_OT [] VM_LK [] VM_LK# [] VM_LK [] VM_LK# [] VM_RS# [] VM_RS# [] VM_S# [] VM_S# [] VM_S# [] VM_S# [] VM_KE [] VM_KE [] VM_WE# [] VM_WE# [] VM_Q[..] [] VM_Q[..] VM_M[..] [] VM_M[..] VM_RQS[..] [] VM_RQS[..] VM_WQS[..] [] VM_WQS[..] VM_M[..] [] VM_M[..] VM_ [] VM_ VM_ [] VM_ VM_ [] VM_ Place MVREF dividers and aps close to SI +.V_GPU (.*VR) Ra R EV@./F_ Rb R EV@/F_ EV@U/.V_X +.V_GPU VM_Q Q_ VM_Q Q_ VM_Q E Q_ VM_Q E Q_ VM_Q F Q_ VM_Q F Q_ VM_Q F Q_ VM_Q G Q_ VM_Q H Q_ VM_Q H Q_ VM_Q J Q_ VM_Q K Q_ VM_Q K Q_ VM_Q L Q_ VM_Q M Q_ VM_Q M Q_ VM_Q M Q_ VM_Q M Q_ VM_Q N Q_ VM_Q P Q_ VM_Q P Q_ VM_Q R Q_ VM_Q T Q_ VM_Q T Q_ VM_Q U Q_ VM_Q V Q_ VM_Q V Q_ VM_Q V Q_ VM_Q Y Q_ VM_Q Y Q_ VM_Q Y Q_ VM_Q Y Q_ VM_Q Q_ VM_Q Q_ VM_Q Q_ VM_Q Q_ VM_Q Q_ VM_Q Q_ VM_Q Q_ VM_Q Q_ VM_Q F Q_ VM_Q F Q_ VM_Q F Q_ VM_Q G Q_ VM_Q H Q_ VM_Q H Q_ VM_Q J Q_ VM_Q K Q_ VM_Q F Q_ VM_Q F Q_ VM_Q G Q_ VM_Q G Q_ VM_Q K Q_ VM_Q L Q_ VM_Q M Q_ VM_Q M Q_ VM_Q K Q_ VM_Q L Q_ VM_Q M Q_ VM_Q M Q_ VM_Q N Q_ VM_Q P Q_ VM_Q P Q_ VM_Q P Q_ MVREF Y MVREF MVREFS MVREFS U PRT F GR/R MEMORY INTERFE M_/M_ M_/M_ M_/M_ M_/M_ M_/M_ M_/M_ M_/M_ M_/M_ M_/M_ M_/M_ M_/M_ M_/M_ M_/M_ M_/ M_/ M_/ WK_/QM_ WK_/QM_ WK_/QM_ WK_/QM_ WK_/QM_ WK_/QM_ WK_/QM_ WK_/QM_ E_/QS_ E_/QS_ E_/QS_ E_/QS_ E_/QS_ E_/QS_ E_/QS_ E_/QS_ I_/QS_ I_/QS_ I_/QS_ I_/QS_ I_/QS_ I_/QS_ I_/QS_ I_/QS_ I/OT I/OT LK LK LK LK RS RS S S S_ S_ S_ S_ KE KE WE WE M_/M_ M_/M_ M_/M_ M_/RSV RM_RST P VM_M T VM_M P VM_M N VM_M N VM_M N VM_M U VM_M U VM_M Y VM_M W VM_M VM_M VM_M VM_M VM_ Y VM_ VM_ H VM_M H VM_M T VM_M T VM_M E VM_M F VM_M K VM_M K VM_M F VM_RQS K VM_RQS P VM_RQS V VM_RQS QS[..] VM_RQS H VM_RQS J VM_RQS M VM_RQS G VM_WQS K VM_WQS P VM_WQS W VM_WQS QS#[..] VM_WQS H VM_WQS J VM_WQS M VM_WQS T VM_OT [] W VM_OT [] L VM_LK VM_LK [] L VM_LK# VM_LK# [] VM_LK VM_LK [] VM_LK# VM_LK# [] T VM_RS# Y VM_RS# [] VM_RS# VM_RS# [] W VM_S# VM_S# [] VM_S# VM_S# [] P VM_S# VM_S# [] L VM_S# VM_S# [] U VM_KE VM_KE [] VM_KE VM_KE [] N VM_WE# VM_WE# [] VM_WE# VM_WE# [] T VM_M W VM_M U V H GPU_RM_RST Ra R EV@./F_ (.*VR) EV@Mars_M Ra R EV@./F_ (.*VR) EV@Mars_M Rb R EV@/F_ EV@U/.V_X all Name Thames Seymour Mars Rb R EV@/F_ EV@U/.V_X mm (max) mm (max) mm (max) MEM_LRN MEM_LRN MEM_LRN R X R X R X X X X GPU_RM_RST R EV@/F_ R R EV@.K/F_ EV@P/V_N EV@/F_ MEM_RST# [,] *E@.U/V_X MEM_LRP R X R MEM_LRP MEM_LRP X R R X X X Place all these componets very close to GPU (within mm) and keep all components close to each other ** This basic topology should be used for RM_RT for R/GR These apacitors and Resistor values arre an example only The series R and cap values will depend on the RM loads and will have to be calculated for differrent Memory, RM loads and board to pass Reset Signal Spec Quanta omputer Inc. PROJET : Size ocument Number Rev Mars_M/ MEM Interface Tuesday, ecember, ate: Sheet of

20 HNNEL : M R (M**pcs) TOP Left TOP Right OT Left OT Right QS[..] QS#[..] Group- decoupling P MEM_ LK Group- VREF Group- VREF Group- decoupling P MEM_ LK <VG> MEM_RST# VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_Q[..] VM_M[..] VM_WQS[..] VM_RQS[..] MEM_RST# VREF_VM VREF_VM VREF_VM VREF_VM VM_ VM_ VM_ VM_OT VM_LK VM_LK# VREF_VM VREF_VM VM_KE VM_WE# VM_S# VM_S# VM_RS# VM_KE VM_WE# VREF_VM VREF_VM MEM_RST# VM_OT VM_LK VM_LK# VM_S# MEM_RST# VREF_VM VREF_VM VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M VREF_VM VREF_VM VM_M VM_ZQ VM_S# VM_RS# VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M VREF_VM VM_ VM_ VM_ VREF_VM VREF_VM VREF_VM VM_ VM_ VM_ VM_LK VM_LK# VM_ZQ VM_ZQ VM_ZQ VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_ VM_ VM_ VM_KE VM_WE# VM_OT VM_LK VM_LK# VM_S# VM_S# VM_RS# VM_OT VM_LK VM_LK# VM_KE VM_WE# VM_S# VM_S# VM_RS# VM_LK VM_LK# VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_RQS VM_WQS VM_M VM_RQS VM_WQS VM_M VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_WQS VM_RQS VM_WQS VM_M VM_RQS VM_M VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_WQS VM_M VM_WQS VM_M VM_RQS VM_RQS VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_M VM_RQS VM_WQS VM_M VM_WQS VM_RQS VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q[..] [] VM_M[..] [] VM_WQS[..] [] VM_RQS[..] [] MEM_RST# [,] VM_M [] VM_M [] VM_M [] VM_M [] VM_M [] VM_M [] VM_M [] VM_M [] VM_M [] VM_M [] VM_M [] VM_M [] VM_M [] VM_WE# [] VM_OT [] VM_S# [] VM_LK# [] VM_LK [] VM_KE [] VM_ [] VM_ [] VM_ [] VM_S# [] VM_RS# [] VM_WE# [] VM_S# [] VM_OT [] VM_LK [] VM_LK# [] VM_KE [] VM_S# [] VM_RS# [] VM_M [] VM_M [] +.V_GPU +.V_GPU +.V_GPU +.V_GPU +.V_GPU +.V_GPU +.V_GPU +.V_GPU +.V_GPU +.V_GPU +.V_GPU +.V_GPU +.V_GPU +.V_GPU +.V_GPU +.V_GPU +.V_GPU +.V_GPU +.V_GPU +.V_GPU +.V_GPU +.V_GPU Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : VRM_: R*PS Tuesday, ecember, Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : VRM_: R*PS Tuesday, ecember, Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : VRM_: R*PS Tuesday, ecember, Mars@.U/V_X R Mars@.K/F_ Mars@U/.V_X R Mars@./F_ -LL SRM R U Mars@VRM _R WE L RS J S K S L KE K K J K K QSU M N P N P P R R T R /P L R QL E QL F QL F QL F QL H QL H QL G QL H VSSQ# VSS# VSS#E E VSS# N#J J V# V# VQ# VQ# VQ# VQ# N#L L N#J J VQ#E E ZQ L RESET T QSL F MU ML E VSSQ# VSSQ# VSSQ# VSSQ#E E QSU VSSQ#E E QSL G VQ#F F VSSQ#F F VSSQ#G G VQ#H H VQ#H H VSSQ#G G VREF M VSS#G G V#G G OT K N P V#K K / N VSS#J J V#K K QU QU QU QU QU QU QU QU T T M M VREFQ H N#L L V#N N V#N N V#R R V#R R VSS#J J VSS#M M VSS#M M VSS#P P VSS#P P VSS#T T VSS#T T VQ# R Mars@./F_ Mars@.U/.V_X Mars@U/.V_X R Mars@.K/F_ Mars@U/.V_X Mars@.U/.V_X Mars@.U/.V_X Mars@U/.V_X R Mars@./F_ Mars@.U/.V_X Mars@.U/V_X Mars@U/.V_X Mars@U/.V_X R Mars@.K/F_ Mars@U/.V_X Mars@.U/V_X R Mars@/F_ Mars@U/.V_X Mars@.U/V_X Mars@U/.V_X R Mars@.K/F_ Mars@.U/.V_X Mars@U/.V_X Mars@U/.V_X Mars@U/.V_X -LL SRM R U Mars@VRM _R WE L RS J S K S L KE K K J K K QSU M N P N P P R R T R /P L R QL E QL F QL F QL F QL H QL H QL G QL H VSSQ# VSS# VSS#E E VSS# N#J J V# V# VQ# VQ# VQ# VQ# N#L L N#J J VQ#E E ZQ L RESET T QSL F MU ML E VSSQ# VSSQ# VSSQ# VSSQ#E E QSU VSSQ#E E QSL G VQ#F F VSSQ#F F VSSQ#G G VQ#H H VQ#H H VSSQ#G G VREF M VSS#G G V#G G OT K N P V#K K / N VSS#J J V#K K QU QU QU QU QU QU QU QU T T M M VREFQ H N#L L V#N N V#N N V#R R V#R R VSS#J J VSS#M M VSS#M M VSS#P P VSS#P P VSS#T T VSS#T T VQ# Mars@U/.V_X R Mars@.K/F_ Mars@U/.V_X R Mars@.K/F_ Mars@.U/.V_X Mars@.U/.V_X Mars@.U/V_X -LL SRM R U Mars@VRM _R WE L RS J S K S L KE K K J K K QSU M N P N P P R R T R /P L R QL E QL F QL F QL F QL H QL H QL G QL H VSSQ# VSS# VSS#E E VSS# N#J J V# V# VQ# VQ# VQ# VQ# N#L L N#J J VQ#E E ZQ L RESET T QSL F MU ML E VSSQ# VSSQ# VSSQ# VSSQ#E E QSU VSSQ#E E QSL G VQ#F F VSSQ#F F VSSQ#G G VQ#H H VQ#H H VSSQ#G G VREF M VSS#G G V#G G OT K N P V#K K / N VSS#J J V#K K QU QU QU QU QU QU QU QU T T M M VREFQ H N#L L V#N N V#N N V#R R V#R R VSS#J J VSS#M M VSS#M M VSS#P P VSS#P P VSS#T T VSS#T T VQ# Mars@U/.V_X R Mars@.K/F_ Mars@.U/V_X Mars@U/.V_X Mars@U/.V_X Mars@U/.V_X -LL SRM R U Mars@VRM _R WE L RS J S K S L KE K K J K K QSU M N P N P P R R T R /P L R QL E QL F QL F QL F QL H QL H QL G QL H VSSQ# VSS# VSS#E E VSS# N#J J V# V# VQ# VQ# VQ# VQ# N#L L N#J J VQ#E E ZQ L RESET T QSL F MU ML E VSSQ# VSSQ# VSSQ# VSSQ#E E QSU VSSQ#E E QSL G VQ#F F VSSQ#F F VSSQ#G G VQ#H H VQ#H H VSSQ#G G VREF M VSS#G G V#G G OT K N P V#K K / N VSS#J J V#K K QU QU QU QU QU QU QU QU T T M M VREFQ H N#L L V#N N V#N N V#R R V#R R VSS#J J VSS#M M VSS#M M VSS#P P VSS#P P VSS#T T VSS#T T VQ# Mars@U/.V_X Mars@U/.V_X Mars@.U/V_X R Mars@.K/F_ R Mars@.K/F_ Mars@.U/V_X R Mars@/F_ R Mars@.K/F_ R Mars@.K/F_ Mars@U/.V_X Mars@.U/V_X R Mars@.K/F_ R Mars@/F_ R Mars@.K/F_ Mars@U/.V_X Mars@U/.V_X R Mars@.K/F_ R Mars@.K/F_ Mars@U/.V_X Mars@U/.V_X Mars@U/.V_X Mars@U/.V_X R Mars@.K/F_ R Mars@/F_ R Mars@./F_ Mars@U/.V_X Mars@.U/.V_X Mars@U/.V_X Mars@U/.V_X Mars@U/.V_X Mars@.U/V_X Mars@.U/.V_X Mars@.U/.V_X Mars@U/.V_X