HOST 133/166MHz PCIE 100MHz VGA 96MHz USB 48MHz REF 14MHz PG 4,5,6,7 PCI-E, 1X PCI-E, 1X. LAN 25MHz Xtal PG 10,11,12,13 USB2.

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1 ES LOK IGRM RII-SOIMM PG, RII-SOIMM PG, / MHZ R II M S Sempron Rev.F Single-ore.G Single-ore W Normal, up to W ( Sg socket) PG,,, HOST /MHz PIE MHz VG MHz US MHz REF MHz LOK GENERTOR IS PG V_ORE +.V +VP PU VR PG +.V +VP PG Panel onnector PG VG ST - H PG PG Internal O -ROM PG LVS VG ST PT HT_LINK _LINK(-Lane) RSM FG S G PG,,, PI-E, X PI-E, X LN MHz Xtal US. (P,P,P,P) US. (P) Mini PI-E ard (WLN) PI Express Mini ard LN RTLE PG RJ US. I/O Ports PG -seg TV(optional) PG PG PG +.VSUS +.V SMR_VTERM +VPU +V_S +VSUS +VSUS +V +V +.VSUS SMR VTERM PG V/V PG HRGER PG PI us MHz MI. PG zalia udio mplifier MX PG PG INT. S.P. H.P PG PG zalia K/ ONN. PG LP VG/K Touch Pad PG K PG,,, Flash ROM PG PG SWITH LE PG RT.KHz Xtal ST MHz Xtal RT.KHz Xtal PMI RIHO R REQ#, GNT# INTE#, INTG#, INTH# PG IEEE N. PG PG, IN PG.MHz Xtal Quanta omputer Inc. PROJET : ES Size ocument Number Rev lock iagram ate: Thursday, May, Sheet of

2 Page : Page : Page : Page : Page : Page : Page : Page : Page : Page : Page : Page : Page : Page : Page : Page : Page : Page : Page : Page : Page : Page : Page : Page : Page : Page : Page : Page : Page : Page : Page : Page : Page : Page : Page : lock diagram System information lock generator IS M S HT M S R M S control&debug M S power R SOIMM X R Termination RSM HT interface RSM PIE interface RSM Sytem I/F & lock Gen. RSM Power S PIE/PI/RT/LP/PU/XTL Interface S US/PI/ZLI/ Interface S ST/PT/HW Monitor/Power Interface S Straps L PNEL RT R PI/ Interface R PMI/ IN Interface PI LN RTLE/RJ FN / MINI PIE / -seg TV LEs / TP ONNETOR ST H/PT O onnector OE L Mic/HP udio mplifier MX US onnector/keyoard onnector K P/IOS ROM PU ORE MX V/V MX.V S/.V/.V.V/.V TPS attery harger MX attery onnector Power VPU VPU VPU RV RV. VSUS VSUS.VSUS V V SMR_VTERM Power On Sequence IN VPU/VPU NSWON# PWRTN# RV_ON RSMRST# SUS#,SUS# SUSON MINON V V PU_V.V V..V V..V V..V Voltage V V V V.V V V.V.V Voltage Rails ON S~S ON S ON S ON S V V V V V V V V V V V V V V V V V V V V V V V V V V V V From From From From +VLW VRM_PWRG VRM_PWRG RV_ON RV_ON SUSON SUSON MINON MINON MINON MINON MINON V_ORE y PU V VR_ON VLT_RUN.V V VLT_ON V V V tl Signal SUSON MINON MINON RSMRST# PS_ON, SLP_S#, SLP_S# +V,V,.V V_N_PWRG N_PWRG S_PWRG P STK UP LYER : TOP LYER : GN LYER : IN LYER : IN LYER : V LYER : OT PI EVIES IRQ ROUTING ES PI EVIE ISEL# REQ# / GNT# R REQ# / GNT# ONEFISH POWER UP SEQUENE Interrupts INT E/F/G VSUS,V VR_ON VORE_PU From PU_PWRG PI_RST# PU_RST# N_PWRG T T T PWROK T>= ms ms < T < ms ms < T < ms PIRST# Quanta omputer Inc. PROJET : ES Size ocument Number Rev System information ate: Thursday, May, Sheet of

3 V L KHS-T LK_V LK_V L KHS-T V.U U.V.U.U.U.U.U.U.U.U U.V Put ecoupling aps close to lock Fen. power pin V L KHS-T LK_V_US LK_V U V L LK_V / for plane-split stitching cap For PIe_LN R K.VSUS.VSUS V.U.U, PT_SM For PULK KHS-T.U U_.V U_.V V V.U P LK_V_REF Parallel Resonance rystal.u Y.MHZ P Q MENE R * GLK_SM GT_SM R K R *M GT_SM LK_XIN LK_XOUT GLK_SM GT_SM Ioh = * Iref (.m) Voh ohm R K R /F LKREQ# ONTROL SR,, LKREQ# ONTROL SR,, TIG LKREQ# ONTROL SR, TIG,, EXT LK FREQUENY SELET TLE(MHZ) FS FS FS VPU V_SR V_SR V_SR V_SR V_ V_TIG V_REF VHTT GN_PU GN_SR GN_SR GN_SR GN_SR GN_ GN_TIG GN_REF GNHTT XIN XOUT RESET_IN# N SMLK SMT IREF IS PU SRLK HTT [:] V GN PULKT PULK PULKT PULK SRLKT SRLK TIGLKT TIGLK TIGLKT TIGLK TIGLKT TIGLK TIGLKT TIGLK SRLKT SRLK SRLKT SRLK SRLKT SRLK SRLKT SRLK SRLKT SRLK SRLKT SRLK SRLKT SRLK LKREQ# LKREQ# LKREQ# MHz_ MHz_ FS/REF FS/REF FS/REF HTTLK PI LK_V PULK_EXT_R PULK#_EXT_R SLINK_LKP_R SLINK_LKN_R NSR_LKP_R NSR_LKN_R SSR_LKP_R SSR_LKN_R GPP_LKP_R GPP_LKN_R GPP_LKP_R GPP_LKN_R LK_M R US RP RP RP S_OSIN_R N_OSIN_R HTREFLK_R OMMENT R R RP RP R * R._F._F X X X X X R.K R.K R.K R R R MINI_LKREQ# USLK R.K R./F LK_V R /F R.K R./F R./F R.K R./F S_OSIN N_OS R./F R * R * R * HTREFLK R./F R./F R./F R./F R./F PULK PULK# R./F SLINK_LKP SLINK_LKN NSR_LKP NSR_LKN SSRLK SSRLK# LK_PIE_MINI_WLN LK_PIE_MINI_WLN# LK_PIE_LN LK_PIE_LN#, PLK_SM Q MENE R * GLK_SM Hi-Z X Hi-Z Hi-Z X/ X/ Normal THLON operation Quanta omputer Inc. PROJET : ES Size ocument Number Rev LOK GENERTOR IS ate: Thursday, May, Sheet of

4 VLT_RUN U VLT_ VLT_ VLT_ VLT_ VLT_ VLT_ VLT_ VLT_ E E E E.U_ HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N N P M M L M K K H H G H F F E F N N L M L L J K G H G G E F E E L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_OUT_H L_OUT_L T T V U V V Y W T R U U V U W W HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N VLT_RUN HT_LKIN_P HT_LKIN_N HT_LKIN_P HT_LKIN_N J K J J L_LKIN_H L_LKIN_L L_LKIN_H L_LKIN_L L_LKOUT_H L_LKOUT_L L_LKOUT_H L_LKOUT_L Y Y Y W HT_LKOUT_P HT_LKOUT_N HT_LKOUT_P HT_LKOUT_N R R./F HT_TLIN_P P HT_PU_TLOUT_P HT_TLIN_N L_TLIN_H L_TLOUT_H T T P HT_PU_TLOUT_N L_TLIN_L L_TLOUT_L R T./F HT_TLIN_P N L_TLIN_H L_TLOUT_H R HT_TLOUT_P HT_TLIN_N P L_TLIN_L L_TLOUT_L R HT_TLOUT_N thlon S Processor Socket VLT_RUN / change p to p from M FE.U_.U_.U.U P P Quanta omputer Inc. PROJET : ES Size ocument Number Rev THLON HT I/F ate: Thursday, May, Sheet of

5 PLE THEM LOSE TO PU WITHIN ".VSUS R.F R.F, M_KE, M_KE, M_KE, M_KE, M [..] Processor R Memory Interface T, M S#, M S#, M S#, M S#, M S#, M S#, M S#, M S#, M S#, M S#, M S#, M RS#, M S#, M WE# M_ZN M_ZP PU_M_VREF.U W M K M K M V M K M L M R M L M L M L M M M M M M M M M N M N M R U.VSUS R P_V K/F MEMVREF VTT_SENSE Y VTT_SENSE E MEMZN F MEMZP V M_S_L J M_S_L V M_S_L T M_S_L Y M_S_L J M_S_L W M_S_L U M_S_L H M_KE J M_KE J M_KE J M_KE M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ K M_NK R M_NK T M_NK T M_RS_L U M_S_L U M_WE_L R K/F R II: M/TRL/LK thlon S Processor Socket VTT VTT VTT VTT VTT W VTT VTT VTT VTT M_LK_H Y M_LK_L M_LK_H E M_LK_L F M_LK_H F M_LK_L F M_LK_H M_LK_L M_OT W M_OT W M_OT V M_OT U M_ J M_ J M_ W M_ L M_ L M_ U M_ L M_ M M_ L M_ N M_ N M_ N M_ N M_ P M_ P M_ T M_NK K M_NK T M_NK U M_RS_L U M_S_L V M_WE_L U M M M M M M M M M M M M M M M M SMR_VTERM M_LKOUT M_LKOUT# M_LKOUT M_LKOUT# M_LKOUT M_LKOUT# M_LKOUT M_LKOUT# M_OT, M_OT, M_OT, M_OT, M [..], M S#, M S#, M S#, M RS#, M S#, M WE#, U M Q M Q M Q[..] M Q M_T M_T M Q[..] F M Q M Q M_T M_T F M Q M Q M_T M_T E M Q M Q M_T M_T Y M Q M Q M_T M_T W M Q M Q M_T M_T Y M Q M Q M_T M_T F M Q M Q M_T M_T F M Q M Q M_T M_T F M Q M Q M_T M_T M Q M Q M_T M_T F M Q M Q M_T M_T Y M Q M Q M_T M_T Y M Q M Q M_T M_T W E M Q M Q M_T M_T W M Q M Q M_T M_T M Q M Q M_T M_T Y M Q M Q M_T M_T F M Q M Q M_T M_T F M Q M Q M_T M_T F M Q M Q M_T M_T E M Q M Q M_T M_T M Q M Q M_T M_T M Q M Q M_T M_T Y E M Q M Q M_T M_T M Q M Q M_T M_T Y M Q M Q M_T M_T W M Q M Q M_T M_T W E M Q M Q M_T M_T M Q M Q M_T M_T M Q M Q M_T M_T M Q M Q M_T M_T Y G M Q M Q M_T M_T H G M Q M Q M_T M_T H M Q M Q M_T M_T E M Q M Q M_T M_T E G M Q M Q M_T M_T J G M Q M Q M_T M_T H E M Q M Q M_T M_T F E M Q M Q M_T M_T F M Q M Q M_T M_T M Q M Q M_T M_T M Q M Q M_T M_T F M Q M Q M_T M_T E M Q M Q M_T M_T E M Q M Q M_T M_T M Q M Q M_T M_T M Q M Q M_T M_T G M Q M Q M_T M_T G M Q M Q M_T M_T M Q M Q M_T M_T F M Q M Q M_T M_T E M Q M Q M_T M_T H M Q M Q M_T M_T E M Q M Q M_T M_T E M Q M Q M_T M_T H M Q M Q M_T M_T E M Q M Q M_T M_T E M Q M Q M_T M_T H G M Q M Q M_T M_T H M Q M Q M_T M_T G M Q M Q M_T M_T H M Q M Q M_T M_T F M Q M_T M_T G M M[..] M M[..] M M M M M M M_M M_M Y M M M M M_M M_M E M M M M M_M M_M Y M M M M M_M M_M E M M M M M_M M_M F M M M M M_M M_M E M M M M M_M M_M M M M_M M_M E M QS[..] M QS M QS F M QS M QS M QS M QS# M_QS_H M_QS_H W E M QS# M QS M QS M QS M_QS_L M_QS_L W E M QS M QS M QS M QS# M_QS_H M_QS_H Y M QS# M QS M QS M QS M_QS_L M_QS_L W F M QS M QS M QS M QS# M_QS_H M_QS_H F M QS# M QS M QS M QS M_QS_L M_QS_L M QS M QS M QS M QS# M_QS_H M_QS_H M QS# M QS M QS[..] M QS M_QS_L M_QS_L F M QS M QS#[..] M QS# M QS# M_QS_H M_QS_H G E M QS# M QS# M QS# M QS M_QS_L M_QS_L G M QS M QS# M QS# M QS# M_QS_H M_QS_H M QS# M QS# M QS# M QS M_QS_L M_QS_L M QS M QS# M QS# M QS# M_QS_H M_QS_H G M QS# M QS# M QS# M QS M_QS_L M_QS_L G M QS M QS# M QS# M QS# M_QS_H M_QS_H G M QS# M QS# M QS# M_QS_L M_QS_L H M QS# M QS#[..] To SOIMM socket (Far) To SOIMM socket (near) R: T thlon S Processor Socket SMR_VTERM.U_.U_.U_.U_.U.U.U.U P_V P_V P_V P_V P P P P Quanta omputer Inc. PROJET : ES Size ocument Number Rev THLON RII MEMORY I/F ate: Thursday, May, Sheet of

6 If M SI is not used, the SI pin can be left unconnected and SI should have a -Ω (±%) pulldown to VSS. V Vout =.(+R/R) =. (+K/K) =.V PULK PULK# P U_ PU SHN GN P VO SET G-TUF P R _F L PU_V KHS-T PR P K_F *U/.V_.U *.U *P_ PR K_F / change U to U, add L,, to meet M suggestion. PU_LKIN_S_P PU_LKIN_S_N V. R * R * R OREF+V To Power OREF-.VSUS PU_SI_R PU_SI_R place them to PU within " VLT_RUN T T PU_V T T T T T PU_V PU_HT_RESET# PU_LL_PWROK PU_LTSTOP# PU_SI_R PU_SI_R R.F R.F THLON ontrol and ebug PU_VIO_SUS_F_H PU_VIO_SUS_F_L PU_LKIN_S_P PU_LKIN_S_N PU_HTREF PU_HTREF F F F F F P R F E W Y U V V RESET_L PWROK LTSTOP_L SI SI HT_REF HT_REF V_F_H V_F_L VIO_F_H VIO_F_L LKIN_H LKIN_L THERMTRIP_L PROHOT_L VI VI VI VI VI VI PU_PRESENT_L PSI_L F H_THERMTRIP# H_PROHOT#.VSUS PU_PRESENT# R T.VSUS R.VSUS.VSUS PSI# R R K S_THERMTRIP# VI VI VI VI VI VI PSI_L is a Power Status Indicator signal. This signal is asserted when the processor is in a low powerstate. PSI_L should be connected to the power supply controller, if the controller supports skipmode, or diode emulation mode. PSI_L is asserted by the processor during the and S states. MMT Q, PU_PWRG LT_STOP# LT_RST# PWROK N_PWRG V. V. V. R R R * R * V.VSUS R R.K.U.VSUS.VSUS U TSZFU.U U TSZFU.U U TSZFU PU_LL_PWROK PU_LTSTOP# PU_HT_RESET# PU_TEST_SINGLEHIN PU_TEST_URNIN# PU_PRESENT# PU_TEST_H_YPSSLK_H PU_TEST_SNEN PU_TEST_SNLK PU_TEST_SNLK PU_TEST_SNSHIFTEN PU_TEST_SNSHIFTEN PU_TEST_P PU_TEST_P PU_TEST_L_YPSSLK_L PU_TEST_PLLTEST PU_TEST_PLLTEST.VSUS R * R * R * R * R * R R R K/F R /F R R R R R R R R /F R R HT ONNETOR IF no use which Net need pull-up or down PU_REQ# PU_RY PU_TK PU_TMS PU_TI PU_TRST# PU_TO LT_RST# T T T T T T T T PUT LOSE ON LYOUT NOTE: HT TERMINTION IS REQUIRE FOR REV. x SILION ONLY. T T T T T T T T T T T T T T PU_RY G PU_TMS PU_TK PU_TRST# PU_TI F PU_TEST_H_YPSSLK_H E PU_TEST_L_YPSSLK_L E PU_TEST_PLLTEST G PU_TEST_PLLTEST H PU_TEST_P PU_TEST_P E PU_TEST_P F PU_TEST_P PU_TEST_SNSHIFTEN PU_TEST_NLOG_T PU_TEST_IERKMON H_THERM W H_THERM W PU_TEST_GTE Y PU_TEST_RIN PU_RSV_M_LK_P P PU_RSV_M_LK_N P PU_RSV_M_LK_P N PU_RSV_M_LK_N N PU_RSV_M_LK_P R PU_RSV_M_LK_N R PU_RSV_M_LK_P P PU_RSV_M_LK_N R RY TMS TK TRST_L TI TEST_H TEST_L TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST RSV RSV RSV RSV RSV RSV RSV RSV REQ_L TO TEST_H TEST_L TEST TEST TEST TEST TEST TEST_H TEST_L TEST TEST TEST TEST RSV RSV RSV RSV RSV RSV MIS RSV RSV RSV RSV RSV RSV RSV M NPT S SOKET Processor Socket E E E E F J H F E K H H G R W R H H PU_REQ# PU_TO PU_TEST_H_FLKOUT_P PU_TEST_L_FLKOUT_N PU_TEST_SNLK PU_TEST_TSTUP PU_TEST_SNSHIFTEN PU_TEST_SNEN PU_TEST_SNLK PU_TEST_H_PLLHRZ_P PU_TEST_L_PLLHRZ_N PU_TEST_SINGLEHIN PU_TEST_URNIN# PU_TEST_NLOGOUT PU_TEST_IG_T PU_M_RESET# PU_M_RESET# PU_RSV_VISTR PU_RSV_VISTR PU_RSV_VN_F_P PU_RSV_VN_F_N PU_RSV_ORE_TYPE R.F PLE IT LOSE TO PU WITHIN " ROUTE S Ohm IFFERENTIL PIR T T T T T T T T T T T T V.U R _ THERM_V U V V.U SMLK THMLK Thermal Senser V R K THMT V Q MENE MT MT, V R K H_PROHOT# R * SYS_SHN# R Q MENE R K_ SYS_SHN# Q MENE P_ H_THERM H_THERM SYS_SHN# XP XN -OVT SMT -LT GN THMT THERM_LERT# THERM_LERT# V R K THMLK MLK Q MENE MLK,.U MX MSOP-_- Quanta omputer Inc. PROJET : ES Size ocument Number Rev THLON TRL & EUG Thursday, May, ate: Sheet of

7 PROESSOR POWER N GROUN V_ORE G H J J J K K K K L L L L L M M M M N N N P P R R R R T T T T T T U U U U V V V UE V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V POWER thlon S Processor Socket thlon Sg upg Top View V V V V V W V Y V J V K V L V M V P V T V U V V VIO H VIO J VIO K VIO K VIO K VIO K VIO L VIO M VIO M VIO M VIO M VIO N VIO P VIO P VIO P VIO P VIO R VIO T VIO T VIO T VIO T VIO U VIO V VIO V VIO V VIO V VIO Y V_ORE.VSUS UF VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS E VSS E VSS E VSS E VSS E VSS E VSS E VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS E VSS F VSS F VSS F VSS F VSS F VSS F VSS F VSS F VSS F VSS H VSS H VSS H VSS H VSS J VSS GROUN thlon S Processor Socket VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS J J J J J J J K K K K K K K L L L L L L L M M M M N N N N N P P P P P R R R R T T T T T T U U U U U U U U V V V V V V V W Y Y N / change to u to meet M design guide V_ORE V_ORE.VSUS.VSUS.VSUS OTTOMSIE EOUPLING U.V U.V U.V U.V U.V U.V U.V U.V U.V.U EOUPLING ETWEEN PROESSOR N IMMs PLE LOSE TO PROESSOR S POSSILE / add.u cap betweenr and PU for EMI *.U.U.U U.V U.V.U_.U_ P.U.U_.U.U_.U.U.U.U.U.U P P F Turion X TL- Rev.F (TMTLHXT) JTLVG Sempron- Single core Rev.F (SMSHXM) JVG Quanta omputer Inc. PROJET : ES Size ocument Number Rev THLON PWR & GN ate: Thursday, May, Sheet of

8 GLK_SM M Q GT_SM M Q M M M M M Q M M M M Q M M_LKOUT M M M_LKOUT# M_LKOUT M M M_LKOUT# M M M Q MVREF_IM M Q M MVREF_IM M Q M Q M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS# M Q M Q M Q M Q M_LKOUT# M_LKOUT M_LKOUT M_LKOUT# M Q M Q M Q M Q M Q M Q M Q M M M M Q MVREF_IM M M M M M M M M M M M QS M M M M M QS M QS M QS M QS M QS M QS M QS M Q M Q M Q M Q M Q M Q M Q M M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M M Q M Q M GLK_SM M Q M M Q M M M Q M Q M M M Q M Q M QS# M QS# M QS# M QS# M QS# M QS# M QS# M M M M M M M M M M M M M M M QS# M M QS M QS M QS M QS M QS M QS M QS M QS M M M Q M Q M M M Q M Q M M M Q M M Q M M Q M_LKOUT# M_LKOUT M_LKOUT M_LKOUT# M Q M Q GT_SM M Q M Q M M Q M Q M Q M Q M Q M Q M Q M Q GLK_SM GT_SM V V SMR_VREF.VSUS.VSUS.VSUS V.VSUS.VSUS.VSUS.VSUS M [..], M_KE, M_KE, M RS#, M S#, M WE#, M S#, M S#, M_OT, M Q[..] M_LKOUT M_LKOUT# M_LKOUT M_LKOUT# M_OT, M S#, M S#, M S#, M QS#[..] M QS[..] M M[..] M_LKOUT M_LKOUT# M_LKOUT M_LKOUT# M_OT, M_KE, M_KE, M_OT, M [..], M S#, M S#, M S#, M QS#[..] M QS[..] M M[..] M RS#, M S#, M WE#, M Q[..] M S#, M S#, M S#, M S#, M S#, M S#, Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : ES RII SOIMMx Thursday, May, Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : ES RII SOIMMx Thursday, May, Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : ES RII SOIMMx Thursday, May, REVERSE.This part should not contain any substances which are specified in SS--.Purchase ink, paint, wire rods and molding resins only from the business partners that Sony approves as Green Partners. (H=.) REVERSE (H=.) For EMI / Stuff R, non-stuff R,R Vref =.*VQ in R module spec / change U to U to meet M suggestion. Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q N N N N N/TEST M M M M M M M M QS QS QS QS QS QS QS QS K K K K KE KE VREF RS S WE S S S S S SL Vspd V V V V V V V V V V V V VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS QS QS QS QS QS QS QS QS OT OT VSS VSS VSS VSS VSS VSS VSS VSS VSS SO-IMM N RII_SOIMM_R SO-IMM N RII_SOIMM_R.U.U.P+-.P.P+-.P.U.U.U.U.U.U Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q N N N N N/TEST M M M M M M M M QS QS QS QS QS QS QS QS K K K K KE KE VREF RS S WE S S S S S SL Vspd V V V V V V V V V V V V VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS QS QS QS QS QS QS QS QS OT OT VSS VSS VSS VSS VSS VSS VSS VSS VSS SO-IMM N RII_SOIMM_R SO-IMM N RII_SOIMM_R *U_ *U_ R R R *K/F R *K/F.U.U.U_.V.U_.V.U.U R K R K.U_.V.U_.V.U.U U_ U_.U.U.U.U.U.U.U.U.U.U.U.U.U.U.U.U.U.U.U.U.U.U.U.U U_.V U_.V.P+-.P.P+-.P.U.U.U.U.U.U.U.U.U.U U_ U_.U.U.U.U R *K/F R *K/F.U.U.U.U.P+-.P.P+-.P.U.U.P+-.P.P+-.P.U.U *U_ *U_

9 / combine R* to RP* to make decouple P close to SOIMM socket SMR_VTERM, M, M, M_OT, M S#, M WE#, M S#, M S#, M_KE, M S#, M S#, M_OT, M S#, M S#, M RS# M WE# M S# M S# M M M S# M RS# RP -X RP -X RP -X RP -X RP -X RP -X RP -X, M, M_OT, M S#, M WE#, M S#, M S#, M_KE, M S# M WE# M S# M S# M M S# RP -X RP -X RP -X RP -X SMR_VTERM *U_ *U_.U.U.U.U.U.U.U.U.U *.U *.U.U.U.U.U.U *.U.U.U.U *.U.U.U.U *.U.U, M, M S#, M S#, M_OT, M RS#, M S#, M_KE, M_KE, M S#, M S#, M, M, M, M, M, M, M, M, M, M, M, M, M, M M M RS# M S# M S# M M M M M M M M M M M M M M RP -X RP -X RP -X R _ R _ R _ R _ RP -X RP -X RP -X RP -X RP -X RP -X RP -X / there is no layout space for decouple cap between.vsus and SMR_VTERM., M, M, M, M, M, M, M, M, M, M, M, M, M, M M M M M M M M M M M M M M M RP -X RP -X RP -X RP -X RP -X RP -X RP -X Quanta omputer Inc. PROJET : ES Size ocument Number Rev RII TERMINTION ate: Thursday, May, Sheet of

10 U VHT_PKG HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_LKOUT_P HT_LKOUT_N HT_LKOUT_P HT_LKOUT_N HT_TLOUT_P HT_TLOUT_N R./F R./F HT_RXLP HT_RXLN R R R R U U U U W W Y T R U U V U V V W W Y W P P HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXLKP HT_RXLKN HT_RXLKP HT_RXLKN HT_RXTLP HT_RXTLN HT_RXLP HT_RXLN PRT OF HYPER TRNSPORT PU I/F HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXLKP HT_TXLKN HT_TXLKP HT_TXLKN HT_TXTLP HT_TXTLN HT_TXLP HT_TXLN P P P P M M M M L L G G J J F F N N L M K K J K G H F F E F E E L L J J N P HT_TXLP HT_TXLN R HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_LKIN_P HT_LKIN_N HT_LKIN_P HT_LKIN_N HT_TLIN_P HT_TLIN_N F RSM Quanta omputer Inc. PROJET : ES Size ocument Number Rev RSM HT LINK I/F ate: Thursday, May, Sheet of

11 U RSM only support two general purpose PI-E links GPP_TX[:]P GPP_RX[:]P GPP_TX[:]N GPP_RX[:]N PRT OF G GFX_RXP GFX_TXP J G GFX_RXN GFX_TXN H J GFX_RXP GFX_TXP K J GFX_RXN GFX_TXN K J GFX_RXP GFX_TXP K J GFX_RXN GFX_TXN L L GFX_RXP GFX_TXP L L GFX_RXN GFX_TXN L L GFX_RXP GFX_TXP N L GFX_RXN GFX_TXN N M GFX_RXP GFX_TXP P M GFX_RXN GFX_TXN P M GFX_RXP GFX_TXP P M GFX_RXN GFX_TXN R P GFX_RXP GFX_TXP R P GFX_RXN GFX_TXN R P GFX_RXP GFX_TXP T P GFX_RXN GFX_TXN U R GFX_RXP GFX_TXP V R GFX_RXN GFX_TXN V R GFX_RXP GFX_TXP V R GFX_RXN GFX_TXN W U GFX_RXP GFX_TXP W U GFX_RXN GFX_TXN W W GFX_RXP GFX_TXP Y W GFX_RXN GFX_TXN Y GFX_RXP GFX_TXP Y GFX_RXN GFX_TXN V GFX_RXP GFX_TXP Place these caps W GFX_RXN GFX_TXN close to connector GFX_RXP GFX_TXP E GFX_RXN GFX_TXN E PIE_TXP_ PIE_RXP W GPP_TXP.U GPP_RXP PIE_TXP PIE_TXN_.U PIE_RXN W GPP_RXN GPP_TXN E PIE_TXN PIE_TXP_ PIE_RXP GPP_TXP.U GPP_RXP PIE_TXP PIE_TXN_.U PIE_RXN GPP_RXN GPP_TXN PIE_TXN PIE I/F GPP E Y GPP_RXP GPP_TXP GPP_RXN GPP_TXN E GPP_RXP GPP_TXP GPP_RXN GPP_TXN _TXP RXP W S_TXP E.U S_RXP _TXP _TXN_.U _RXN W S_RXN PIE I/F S S_TXN _TXN _TXP RXP S_RXP S_TXP.U _TXP _TXN_.U _RXN S_RXN S_TXN _TXN R K/F V_PKG PE_ISET(PE_LI) PE_PL(PE_LRP) R /F R.K_F PE_TXISET(N) PE_NL(PE_LRN) E R F PIE I/F GFX / SI : PIE_TXP/N, PIE_RXP/N change layer V..U V..U RSM Quanta omputer Inc. PROJET : ES Size ocument Number Rev RSM PIE LINK I/F ate: Thursday, May, Sheet of

12 V. HTPV / close to LVS signal via to keep return path continuous. (The stitching caps are connected to on SV layer and GN vias.) L KHS-T U_.V.U_ V. R _ V.U_.V.U_V.U_V V. V. V V. L KHS-T L KHS-T L KHS-T L *KHS PLLV VQ U_.V U_.V R _ GN_VSSQ V_N.U_ RT_R RT_G RT_ VGVSYN VGHSYN LK T,, LINK_RST# N_PWRG LLOW_LTSTOP HTREFLK N_OS NSR_LKP NSR_LKN SLINK_LKP SLINK_LKN LO_ROM#: LO ROM STRP ENLE / M suggestion, internal pull-up R *K V..U High, LO ROM STRP ISLE Low, LO ROM STRP ENLE R K.U_.U_.V V R K /F R /F R /F R GN_VSSQ VQ PLLV HTPV MREQ# LVS_LK LVS_T.U V_N V R R R R R T T T R R T T T _F TV_SWITH PLLV STRP_T V V G VSSN H VSSN VI VSSI _R Y_G OMP_ E RE F GREEN G LUE VSYN HSYN PLLV(PLLV) PLLVSS HTPV HTPVSS SYSRESET# LT_STOP#_N POWERGOO LTSTOP# LLOW_LTSTOP K HTTSTLK HTREFLK TVLKIN OSIN OSOUT(PLLV) F GFX_LKP E GFX_LKN G S_LKP G S_LKN *.K FT_GPIO LO_ROM# FT_GPIO *.K FT_GPIO FT_GPIO *.K FT_GPIO FT_GPIO *.K FT_GPIO FT_GPIO *.K FT_GPIO FT_GPIO FT_GPIO MREQb RV I_LK I_T T THERMLIOE_P T THERMLIOE_N U VQ VSSQ RSET SL S TMS_HP _T TESTMOE STRP_T RT/TVOUT PM PLL PWR PRT OF LOKs MIS. VO LVS TXOUT_LP TXOUT_LN TXOUT_LP TXOUT_LN TXOUT_LP TXOUT_LN TXOUT_LP TXOUT_LN TXOUT_UP TXOUT_UN TXOUT_UP TXOUT_UN TXOUT_UP TXOUT_UN TXOUT_UP TXOUT_UN TXLK_LP TXLK_LN TXLK_UP TXLK_UN LPV LPVSS LVR_ LVR_ LVR_ LVR_ LVSSR LVSSR LVSSR LVSSR LVSSR LVSSR LVSSR LVSSR LVS_IGON LVS_LON LVS_LEN VO_(GPP_TXP) VO_(GPP_TXN) VO_(N) VO_(GPP_RXP) VO_(GPP_RXN) VO_(N) VO_(N) VO_(GPP_TXN) VO_(GPP_TXP) VO_(GPP_RXN) VO_(GPP_RXP) VO_(N) VO_VSYN(N) VO_E(N) VO_HSYN(N) VO_IKP(N) VO_IKN(N) H G E E H G E F F E G F E E E E E E E LVR LVR TXLOUT+ TXLOUT- TXLOUT+ TXLOUT- TXLOUT+ TXLOUT- T T / removed upper LVS data channel T T T T T T T T TXLLKOUT+ TXLLKOUT- LPV T / removed upper LVS clk T L.U.U_ IGON LON T T T T T T T T T T T T T T T T T T.U.U_ GN_LPVSS L RS: LVR=.V V..U V. KHS-T KHS-T R _ R _ L KHS-T.U_ GN_LVSSR GN_LPVSS LT_STOP# Q MMT LT_STOP#_N R.K RSM V R K/F STRP_T R K TV_SWITH Quanta omputer Inc. PROJET : ES Size ocument Number Rev RSM SYSTEM I/F & LKGEN ate: Thursday, May, Sheet of

13 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS PR OF M V V V F V H G J H E J E F L M M J P T N P R U T U U Y Y W Y Y Y R G Y Y UE RSM GROUN F E G Y P R E M J G J L L L L M M M M N N L P P P R R R W Y U H W Y G H R E T T E R H M F M ohm() V. VLT_RUN ohm() V L FJHS V V. L ohm (m) V L V. L V U.V R _ U.V U_.V SW SW FM- RS: Ohm RESISTOR SW.U_ RS: V=.V V. L LMPGSN U.V U.V VR FM-.U_ FM- U_.V V VVO.U_ U_.V VPLL U_.V.U_ U_.V U_.V U_.V U_.V U_.V U_.V U_.V V U_.V U_.V VHT_PKG V_PKG V_PKG V_PKG U_.V U.V U E V_HT PRT OF V_HT V_HT V_HT E V_HT Y V_HT W V_HT V_HT V_HT V_HT V_HT V_HT V_HT V_HT E V_HT J V_ J V_ POWER E V_(V_) V_(V_) U V_(V_) W V_(V_) V_(V_) V_(V_) V_(V_) E V_(V_) E VR_ VR_ V_VO(VR_) V_VO(VR_) E V_VO(VR_) E V_(VPLL_) F V_(VPLL_) F VSS(VSSPLL_) G VSS(VSSPLL_) VHT_PKG M V_PKG V_PKG RSM V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ G E E M F L E L L L M R M N N N J H P P R R U U P L J G U U U_.V U_.V U.V U/.V_ U_.V U.V V. U.V U.V U_.V U_.V U_.V U_.V U/.V_ U_.V U_.V U_.V N RSM POWER STTES Power Signal S S VHT VR V V V V V ON ON ON ON ON ON ON ON ON ON ON ON ON ON VI ON ON PLLV ON ON HTPV ON ON VR ON ON LPV ON ON LVR ON ON S S/S LVR ON ON G Quanta omputer Inc. PROJET : ES Size ocument Number Rev RSM POWER ate: Thursday, May, Sheet of

14 V. VPU,, LINK_RST# PIE Power L FM- RT VRT V. / Remove,, VPU connection VRT_ change to VRT R K_ R.K R R.K U.V.U att holder: K type L VRT T ML-SOKET ML-R VRT_ VRT.U LINK_RST# LMPGSN VRT_.U U_.V JP *lear P R _ VSUS PIE_PV U_.V.U.U TI recommand have internal pull-up FOR S, ONNET TO PU_PG/LT_PG FOR S, ONNET TO SSMUXSEL/GPIO Q MMT.U U TSZFU, PU_PWRG T T T T T T T T LLOW_LTSTOP T T T LT_RST# PIE_VR PU_PWR_S m / TX G +-ppm SEG G +-ppm p R.K SSRLK SSRLK SSRLK# SSRLK#.U _RXP RXP.U _RXN RXN.U _RXP RXP.U _RXN RXN T T T T _TXP _TXP _TXN _TXN _TXP _TXP _TXN _TXN T T T T R _F PIE_LRP R _F PIE_LRN PIE_VR R.K_F PIE_LI U_.V.U.U R M.U R.U Y.KHZ R *K M.U H_IGNNE# H_M# H_FERR# LLOW_LTSTOP STP_PU# K_X K_X K_X R * H_INTR H_NMI H_INIT# PRSLPVR LT_RST# p K_X U G _RST# J PIE_RLKP J PIE_RLKN P PIE_TXP P PIE_TXN M PIE_TXP M PIE_TXN K PIE_TXP K PIE_TXN H PIE_TXP H PIE_TXN T PIE_RXP T PIE_RXN T PIE_RXP T PIE_RXN M PIE_RXP M PIE_RXN M PIE_RXP M PIE_RXN E PIE_LRP E PIE_LRN E PIE_LI U PIE_PV U PIE_PVSS F PIE_VR_ F PIE_VR_ F PIE_VR_ G PIE_VR_ G PIE_VR_ G PIE_VR_ G PIE_VR_ J PIE_VR_ J PIE_VR_ L PIE_VR_ L PIE_VR_ L PIE_VR_ N PIE_VR_ X X PU_PG/LT_PG W INTR/LINT W NMI/LINT W INIT# SMI# SLP#/LT_STP# IGNNE#/SI M#/SI Y FERR# STPLK#/LLOW_LTSTP H PU_STP#/PSLP_V# PSLP_O#/GPIO W PRSLPVR LT_RST#/PRSTP#/PROHOT# S S S xmm XTL PILK Part of PILK PILK PILK PILK PILK PILK SPIF_OUT/PILK/GPIO PI EXPRESS INTERFE PU LP PI INTERFE PIRST# /ROM /ROM /ROM /ROM /ROM /ROM /ROM /ROM /ROM /ROM /ROM /ROM /ROM /ROM /ROM /ROM /ROM /ROM /ROM /ROM /ROM /ROM /ROM /ROM E#/ROM E#/ROM E#/ROMWE# E# FRME# EVSEL#/ROM IRY# TRY#/ROMOE# PR/ROM STOP# PERR# SERR# REQ# REQ# REQ# REQ#/GPIO REQ#/GPIO GNT# GNT# GNT# GNT#/GPIO GNT#/GPIO LKRUN# LOK# INTE#/GPIO INTF#/GPIO INTG#/GPIO INTH#/GPIO L L L L LFRME# LRQ# LRQ#/GNT#/GPIO MREQ#/REQ#/GPIO SERIRQ RTLK RT_IRQ#/GPIO VT RT_GN RT PI LKS U T U V W U V T J W Y W W Y J E J H J H H H G G F J G H G F Y G J E G H H F H G G F F F F G G H H F J H W F F E PILK R PLK_R PILK R PLK_LP PILK R PLK_ PILK PILK PILK PILK S_SPIF_OUT PIRST#_ /E# /E# /E# /E# FRME# EVSEL# IRY# TRY# PR STOP# PERR# SERR# REQ# REQ# REQ# REQ# REQ# GNT# GNT# GNT# GNT# GNT# LKRUN# PI_LOK# INTE# INTF# INTG# INTH# L L L L LFRME# LRQ# LP_RQ# MREQ# SERIRQ RT_LK UTO_ON# U_.V /E# /E# /E# /E# FRME# EVSEL# IRY# TRY# PR STOP# PERR# SERR# REQ# GNT# T T T T LKRUN#, INTE# INTF# INTG# PIRST#_ L, L, L, L, LFRME#,, LP_RQ# MREQ# SERIRQ, RT_LK UTO_ON# *U_ [..], VRT *P PLK_R, PLK_LP PLK_ PILK PILK PILK PILK S_SPIF_OUT R.K V PI_LOK# INTE# INTF# INTG# INTH# SERIRQ STOP# TRY# FRME# IRY# REQ# EVSEL# REQ# REQ# REQ# SERR# REQ# PERR# L L L L.U LKRUN# LP_RQ# LRQ# MREQ# PIRST# U TSZFU R RN RN RN R *P R.K R.K R.K R.K R.K R R R R RN P K.KX_.KX_.KX_ K PIRST# V V K K K K KX_.U.U.U K Lion batt: HL TTERY LI V MH(ML) HL TTERY LI V MH(ML) / add for long trace from VRT Quanta omputer Inc. PROJET : ES Size ocument Number Rev S PIE/PI/PU/LP I/F ate: Thursday, May, Sheet of

15 S_OSIN RI# SUS_STT# SUS# SUS# NSWON# PI_PME# SWI# GPM# GEVENT# PIE_WKE# S_L# S_THERMTRIP# EXTEVNT# GPIO PLK_SM PT_SM L_ON RIN# GPIO S_GPIO GPIO RST_H# GPIO GPIO PU_PWRG PU_PROHOT# EMIL_LE# / M suggestion _SYN_R _RST# Z_SIN I_STIN I_STIN _ITLK_R Z_RST# Z_SYN Z_SOUT Z_ITLK I_RESET#_UIO I_SYN_UIO I_ITLK_UIO I_STO_UIO R * R K R.K R.K R K R.K R K R K R K R K R.K R K R K R K R.K R.K R.K R K R K R K R K R K R K R K R K R *K R K R K R K R K RV V R K R K Z_ITLK R K Z_SOUT R K R K T Z_SYN R K R K T R K _ITLK_R T _SOUT _SOUT I_STIN I_STIN I_STIN I_STIN Z_SIN SI suggestion : follow S design guide ohm T _SYN_R / stuff p Ps for EMI T _RST# / T M suggestion R Z_RST# RV R *K GPIO P T S_GPIO S_GPIO GPIO R Z_SYN H_PSLP# H_PSLP# GPIO S_L# P, LT_STOP# R Z_ITLK T P R P *P Z_SOUT.U.U PI_PME# RI# SUS# SUS# NSWON# PWROK GTE RIN# SWI#, PIE_WKE# S_THERMTRIP# RSMRST# S_OSIN L_ON SPKR, PLK_SM, PT_SM, PU_PWRG T US_OP# T T T T SI# KSMI# R R PU_PWR_S R K PI_PME# RI# SUS# SUS# NSWON# PWROK SUS_STT# K K GTE RIN# SWI# EXTEVNT# GEVENT# GPM# PIE_WKE# EMIL_LE# S_THERMTRIP# RSMRST# GPIO GPIO PU_PROHOT# L_ON RST_H# GPIO SPKR PLK_SM PT_SM OR_I OR_I PU_PWRG S_LL# US_OP# US_OP# Z_RST# US_OP# US_OP# US_OP# SI# KSMI# U PI_PME#/GEVENT# Part of RI#/EXTEVNT# F SLP_S# SLP_S# E PWR_TN# PWR_GOO SUS_STT# F TEST E TEST G TEST F GIN G KRST# LP_PME#/GEVENT# LP_SMI#/EXTEVNT# S_STTE/GEVENT# F SYS_RESET#/GPM# E WKE#/GEVENT# LINK/GPM# G SMLERT#/THRMTRIP#/GEVENT# E RSMRST# OS / RST M_OS ST_IS#/GPIO ROM_S#/GPIO GHI#/ST_IS#/GPIO W_PWRG/GPIO SMRTVOLT/ST_IS#/GPIO SHUTOWN#/GPIO SPKR/GPIO SL/GPO# S/GPO# SL/GPO# F S/GPO# _SL/GPIO _S/GPIO SSMUXSEL/ST_IS#/GPIO LL#/GPIO US_O#/SLP_S/GPM# US_O#/Z_OK_RST#/GPM# US_O#/GEVENT# US_O#/GEVENT# US_O#/R_RST#/GPM# US_O#/GPM# US_O#/GPM# US_O#/GPM# US_O#/GPM# US_O#/GPM# N Z_ITLK M Z_SOUT K Z_SIN/GPIO L Z_SYN K Z_RST# L _ITLK/GPIO L _SOUT/GPIO L Z_SIN/GPIO J Z_SIN/GPIO J Z_SIN/GPIO M _SYN/GPIO L _RST#/GPIO E N N N E N N T N N N S S xmm ZLI US O GPIO PI / WKE UP EVENTS US INTERFE US PWR USLK US_ROMP US_TEST US_TEST US_HSP+ US_HSM- US_HSP+ US_HSM- US_HSP+ US_HSM- US_HSP+ US_HSM- US_HSP+ US_HSM- US_HSP+ US_HSM- US_HSP+ US_HSM- US_HSP+ US_HSM- US_HSP+ US_HSM- US_HSP+ US_HSM- VTX_ VTX_ VTX_ VTX_ VTX_ VRX_ VRX_ VRX_ VRX_ VRX_ V VSS VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ H G E E G H E E G H G H E G H E E F F F F F F F G G H H J J J J J J US_ROMP USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- R * *P R R T T T T T T T T V_US *_.K_F T T USP+ USP- T T USP+ USP- USP+ USP- USP+ USP- USLK V_US Z_RST# KSMI# US_OP# SI# US_OP# US_OP# US_OP# US_OP# USP+ USP- / demo board is u + u V US power +.V_V.U.U_.V R *K R *K.U OR_I R OR_I R US power use S power,ut Over current signal datasheet is S only,ut TI FE say use S is ok R *K R.K RP RN U.V U_.V U_.V.U L KX_.U RV RV KX_.U K K.U L FM-.U LMPGSN VSUS H_PSLP# S Quanta omputer Inc. PROJET : ES Size ocument Number Rev S PI/GPIO/US/ ate: Thursday, May, Sheet of

16 ST_X ST_X V_VREF V_.V PS# P P P PS# PIOR# PK# P PREQ PIOW# IRQ P P P P P P P P P P PIORY P P P P P ST_TXP_ ST_TXN_ ST_RXP ST_RXN V_VREF ST_L ST_X ST_X S_S_V S_S_.V VQ_V PK#, PREQ PIOR# PIOW# PS# PS# P P P PIORY IRQ ST_TXP ST_TXN ST_RXP ST_RXN P[..] ST_LE#, V. V. V. V. V_K_.V RV..VUS_PHY +.V_T PLLV_T XTLV_T XTLV_T PLLV_T +.V_T PU_PWR_S V. RV V.VUS_PHY.VSUS.VUS_PHY V V V. Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : ES S H/POWER/EOUPLING Thursday, May, Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : ES S H/POWER/EOUPLING Thursday, May, Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : ES S H/POWER/EOUPLING Thursday, May, ohm/ ohm/ ST clock Option V_VREF.VUS_PHY S- ST Power / modify Remove OS. option to save layout space.u.u.u.u VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ W VSS_ V VSS_ V VSS_ V VSS_ V VSS_ V VSS_ U VSS_ T VSS_ R VSS_ R VSS_ P VSS_ P VSS_ P VSS_ N VSS_ N VSS_ M VSS_ M VSS_ L VSS_ L VQ_ VQ_ VQ_ VQ_ VQ_ L VQ_ L VQ_ M VQ_ P VQ_ P VQ_ T VQ_ V VQ_ W VQ_ W VQ_ W VQ_ W VQ_ VQ_ VQ_ VQ_ VQ_ PU_PWR V_VREF E S_.V_ H US_PHY_.V_ V_ N V_ M V_ N V_ R V_ U V_ R V_ M V_ N V_ U VSS_ J VSS_ J VSS_ G VSS_ F S_.V_ G S_.V_ H S_.V_ H VK_.V VSSK VSS_ G VSS_ J VSS_ J VSS_ J V_ U V_ V V_ V S_.V_ VQ_ E VQ_ E VQ_ E VQ_ H VQ_ J VSS_ U S_.V_ S_.V_ F S_.V_ J S_.V_ J S_.V_ K US_PHY_.V_ US_PHY_.V_ US_PHY_.V_ VSS_ Y VSS_ E VQ_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ F VSS_ E VSS_ M VSS_ M US_PHY_.V_ VK_.V VQ_ J VQ_ J PIE_VSS_ PIE_VSS_ PIE_VSS_ PIE_VSS_ G PIE_VSS_ G PIE_VSS_ G PIE_VSS_ H PIE_VSS_ J PIE_VSS_ J PIE_VSS_ K PIE_VSS_ L PIE_VSS_ L PIE_VSS_ L PIE_VSS_ L PIE_VSS_ L PIE_VSS_ M PIE_VSS_ M PIE_VSS_ M PIE_VSS_ N PIE_VSS_ N PIE_VSS_ P PIE_VSS_ P PIE_VSS_ P PIE_VSS_ P PIE_VSS_ P PIE_VSS_ P PIE_VSS_ T PIE_VSS_ T PIE_VSS_ T PIE_VSS_ T PIE_VSS_ T PIE_VSS_ U PIE_VSS_ V PIE_VSS_ V PIE_VSS_ V PIE_VSS_ V PIE_VSS_ V PIE_VSS_ V PIE_VSS_ V VSS_ R VSS_ T VSS_ V VSS_ W VSS_ E PIE_VSS_ F PIE_VSS_ J PIE_VSS_ V Part of S S xmm POWER U S Part of S S xmm POWER U S U.V U.V.U_.V.U_.V R K/F R K/F U_.V U_.V.U.U.U.U U.V U.V T T.U.U L LMPGSN L LMPGSN.U.U.U.U T T T T T T P P T T.U.U U_.V U_.V Y MHZ Y MHZ.U.U U_.V U_.V.U.U.U_.V.U_.V.U.U.U.U.U.U.U.U U_.V U_.V.U.U L LMPGSN L LMPGSN T T PJMZV(SOT-) PJMZV(SOT-) SW SW U.V U.V U.V U.V U_.V U_.V.U.U R M R M T T T T.U.U.U.U.U.U L LMPGSN L LMPGSN L LMPGSN L LMPGSN L FJHS L FJHS R K/F R K/F R R U_.V U_.V.U.U U_.V U_.V U/.V_ U/.V_ IE_IORY IE_IRQ IE_ IE_ IE_ Y IE_K# IE_RQ IE_IOR# IE_IOW# IE_S# W IE_S# W IE_/GPIO IE_/GPIO IE_/GPIO E IE_/GPIO F IE_/GPIO G IE_/GPIO H IE_/GPIO J IE_/GPIO J IE_/GPIO H IE_/GPIO G IE_/GPIO G IE_/GPIO F IE_/GPIO F IE_/GPIO E IE_/GPIO IE_/GPIO V_ST_ E XTLV_ST V_ST_ E PLLV_ST_ J VSS_ST_ E VSS_ST_ F VSS_ST_ F V_ST_ E PLLV_ST_ VSS_ST_ F VSS_ST_ F VSS_ST_ G VSS_ST_ G VSS_ST_ G VSS_ST_ G VSS_ST_ G VSS_ST_ G VSS_ST_ V_ST_ E ST_TX+ H ST_TX- H ST_RX+ J ST_RX- H ST_TX+ J ST_TX- H ST_RX+ J ST_RX- H ST_TX+ H ST_TX- J ST_RX- H ST_RX+ J ST_TX+ H ST_TX- J ST_RX- H ST_RX+ J ST_L F ST_X ST_X ST_T#/GPIO V_ST_ F V_ST_ F V_ST_ G V_ST_ G VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_ E SPI_I/GPIO J SPI_O/GPIO J SPI_LK/GPIO G SPI_HOL#/GPIO G SPI_S#/GPIO G FNOUT/GPIO T FNOUT/GPIO V FNIN/GPIO N FNIN/GPIO P FNIN/GPIO W LN_RST#/GPIO ROM_RST#/GPIO G /GPIO V /GPIO L /GPIO M /GPIO V /GPIO M /GPIO P /GPIO M /GPIO V TEMPIN/GPIO P TEMPIN/GPIO P TEMPIN/GPIO T TEMPIN/TLERT#/GPIO T FNOUT/GPIO M V N VSS M TEMP_OMM P V_ST_ H V_ST_ H V_ST_ J V_ST_ J VSS_ST_ G VSS_ST_ G VSS_ST_ G V_ST_ J VSS_ST_ G VSS_ST_ H V_ST_ J VSS_ST_ H V_ST_ J T / Part of S S xmm SERIL T POWER SERIL T SPI ROM HW MONITOR U S T / Part of S S xmm SERIL T POWER SERIL T SPI ROM HW MONITOR U S.U.U P P.U.U T T.U.U.U.U.U.U L FM- L FM-.U.U.U.U L LMPGSN L LMPGSN.U.U.U.U U.V U.V T T.U.U.U.U U/.V_ U/.V_ *ES SO *ES SO.U.U.U.U U_.V U_.V.U.U.U.U.U.U L LMPGSN L LMPGSN.U.U.U.U L FJHS L FJHS U.V U.V.U.U.U.U.U.U.U.U.U.U T T.U.U U_.V U_.V.U.U T T.U.U

17 Edison-/--hange to S V RV V V V V RV V V V V / M suggestion V REQUIRE STRPS _SOUT RT_LK PILK PILK, PLK_R PLK_LP R *K R K R *K R K R K R *K UTO_ON# S_SPIF_OUT PLK_ PILK PILK,, LFRME# R K R *K R *K R *K R K R K R K R *K R K R *K R *K R K R *K R K R K R K R *K R *K PLK_R PLK_LP UTO_ON# S_SPIF_OUT PLK_ PILK PILK LFRME# _SOUT RT_LK PILK PILK PI_LK PI_LK PWRON SPIF_OUT PI_LK PI_LK PI_LK LFRME# PULL HIGH USE EUG STRPS INTERNL RT EFULT USE INT. PLL PU IF=K ROM TYPE: H, H = PI ROM H, L = LP TYPE I ROM L, H = LP TYPE II ROM EFULT PULL HIGH MNUL PWR ON EFULT SIO MHz XTL MOE NOT SUPPORTE US PHY POWEROWN ISLE EFULT PIE_M_SET LOW EFULT ENLE THERMTRIP# EFULT PULL LOW IGNORE EUG STRPS EFULT EXTERNL RT USE EXT. MHZ EFULT PU IF=P EFULT L, L = FWH ROM NOTE:FOR S,PILK[:] RE ONNETE TO SUSTRTE LLS PILK[:] PULL LOW UTO PWR ON SIO MHz EFULT MHZ OS MOE EFULT US PHY POWEROWN ENLE PIE_M_SET HIGH ISLE THERMTRIP# IOS ENLE FTER STRTUP EUG STRPS V R K V V V V V V R R R R R R *K *K *K *K *K *K PK#,,,,,, R *K R *K R K R K R K R K R *K PK# PI_ PI_ PI_ PI_ PI_ PI_ PULL HIGH USE LONG RESET EFULT YPSS PI PLL YPSS PI LK YPSS IE PLL USE EEPROM PIE STRPS S- PULL LOW USE SHORT RESET USE PI PLL EFULT USE PI LK EFULT USE IE PLL EFULT USE EFULT PIE STRPS EFULT Quanta omputer Inc. PROJET : ES Size ocument Number Rev S STRPS ate: Thursday, May, Sheet of

18 L ONNETOR V V _L F U_.U_V HM R *.U_V *U_ <PRT NUMER> EMI ISPON P LVS_T LVS_LK TXLOUT- TXLOUT+ LVS_T LVS_LK TXLOUT- TXLOUT+ R K R K ON L_ON VJ- ISPON TXLOUT- TXLOUT+ V TXLOUT- TXLOUT+ TXLLKOUT- TXLLKOUT+.U TXLOUT- TXLOUT+ TXLOUT- TXLOUT+ TXLLKOUT- TXLLKOUT+ LV VJ.U VJ V VJ- L LMPGSN EMI P EMI *P *P -x-p-ldv / change p to p, remove upper channel nets KLIGHT ONTROL L_ON LON L_ON LON V R _ R.U ISPON U TSZFU QIPN:LWZ V PNEL V ONTROL V Q IN OUT.U IN IGON ON/ GN LV.U LI ON LI# - --P-L.U LI# K.U GTU GTU:L Quanta omputer Inc. PROJET : ES Size ocument Number Rev L PNEL ate: Thursday, May, Sheet of

19 RT / modify X ML---N OS X T ( hm Q) X KE#FM---T( ohm) - current use (PL) / modify F KTPU - SMPTF(KWS) to KZTFU(littlefuse) to KWSSSZSS(V,M) to PLSSMZSSMPT(V,) RT_R RT_G RT_ RT_R RT_G RT_ RSM: K // K = K /F R /F R /F R P P P L FM---T L FM---T L FM---T P_ P_ P_ V RT_R_ RT_G_ RT / to meet OM usage / demo board VG_V_ L VG_V LMPGSN ON SSM F L V / modify: add U Integrated ES I Remove discrete ES diodes V T_L LK_L RT_HSYN_L R.K_ R.K_ L KHS L KHS L KHS T_L LK_L RT_HSYN_L crt-frscr-p-v FHSFR T LK T LK R.K_ R.K_ RT_VSYN_L *P_ L KHS *P_ P_ P_ P_ RT_VSYN_L P_ *.U V RT_HSYN_L R / P for ES RT_VSYN_L R VGHSYN VGVSYN EMI VGHSYN VGVSYN *.U U SYN_OUT V_SYN SYN_OUT V_ YP SYN_IN SYN_IN V_VIEO.U R * V.U LK_L T_L _IN VIEO IN VIEO_ VIEO OUT _OUT GN M-QR RT_R_ RT_G_ RT U : Placed closed to VG conn as possible Quanta omputer Inc. PROJET : ES Size ocument Number Rev RT ate: Thursday, May, Sheet of

20 V VSUS V_PHY R LOSE HIP U.U.U.U U.U.U TPIS VSUS U V_PHY R./F R./F.U.U/V VSUS R K U_.V U, [..] /E# /E# /E# /E#, FRME# IRY# TRY# EVSEL# STOP# REQ# GNT# PERR# SERR# PR, PLK_R, LKRUN# PMSPK#.U.U GRSET# PMSPK#.U.U R R *K ISEL_ PM_RST# R R V_PI R V_PI W V_PI F V_V G V_V J V_V K V_V W V T W V T W V R W V T R W V T V U U T T R R R P P N N N N M M T /E# W /E# W /E# P /E# P ISEL V FRME# V IRY# W TRY# T EVSEL# V STOP# M REQ# M GNT# W PERR# T SERR# V PR G GRST# L PIRST# K PILK L LKRUN# G PME#/RI_OUT# F SPKROUT R V_PHYV V_PHYV V_PHYV V_PHYV TPN TPP TPN TPP TPIS TPN TPP TPN TPP TPIS PS VREF REXT FIL X XO GN GN GN GN GN GN HWSPN# TEST INT# INT# INT# UIO/SRIRQ# UIO UIO UIO UIO UIO GN GN GN GN GN GN GN GN GN GN E E _TP+ _TP- _TP+ _TP- _TP- _TP+ _TP- _TP+ TPIS F F J K K J H H H H G J J K E R T V W L M V_PHY.U R _XOUT _XIN V K.U R K R _ Y.MHz NWS--F R *_ INTE# INTF# INTG# SERIRQ P P _SLK _ST R.K/F S_GPIO SUS# VSUS R R K K R./F TP_F R./F P LP _TP+ _TP- _TP+ _TP- LP / change to size low-profile ohm LWHNSQL LWHNSQL L_TP+ L_TP- L_TP+ L_TP- S LOSE S POSSILE TO ONNETOR. PJL PJL N -FRSXZX-P-H VSUS PIRST# R *K R _ VSUS P R K R R *_ *_ PI_PME# RI# R pin to pin compatible with R Quanta omputer Inc. PROJET : ES Size ocument Number Rev R PI/ ate: Thursday, May, Sheet of

21 Shield GN _V _VPP R R R R R R R R R R R R R R R R R R R R R R R R R R T T T T T T T T T T T T T T T T OE# WE# E# E# REG# RESET WIT# IOIS# IREQ# SPKR# HSTS# VS VS # # INPK# IOR# IOWR# VPPEN VPPEN VEN# VEN# PMI onn. U/V U/V Place near the Power I RV pins R.U.U U E R F R F R G R G R H R H R J R P R R R U R R R K R N R N R K R L R P R N R N R M R L R L R K R J R J R E T T T R T T T W T W T W T T T T V T V T V T W T U T T OE# M WE# T E# V E# F REG# H RESET G WIT# WP/IOIS M RY/IREQ# F V E V H VS# R VS# # T # G INPK# P IOR# P IOWR# V USP W USM V _VPPEN W _VPPEN T _VEN# R _VEN# VSUS.U Not-Support V R VSUS VSUS VSUS.U VPPEN VPPEN VEN# VEN# VSUS.U _V.U VSUS.U U N EN EN V_EN V_EN RV _VPP.U *U VOUT VOUT VOUT VPPOUT # T T T T T E# VS IOR# IOWR# R R R R R N N FLG GN R R R R VS RESET WIT# INPK# REG# SPKR# HSTS# T T T # T T T T T E# R OE# R R R R R WE# IREQ# R R R R R R R R R R R T T T IOIS# pf pf _V _VPP VSUS / change Footprint to K ardus symbol, FHSFR P ard Frame N PI-G-WR-F-P Shield GN GN GN - GN V - GN - GN / This is for MS-PRO short issue - GN Q - GN MIO E#-/E# GN MIO_S V MIO_INV - GN MIO_INV OE MIO_S OE#- GN OE MIO - GN GN - GN NWKX_NL -/E# GN -PR GN -PERR# GN U WE/PGM-GNT# GN RY/SY-IRQ/IN GN V IN OUT V N VPP -LK -IRY# -/E# RFU WP/IOIS-LKR GN GN #-# RFU - E#- VS#/RFSH-VS RSV- RSV- - -RFU -LOK# -STOP# -EVSEL# V VPP/VPP -TRY# -FRME# - - VS#/RSV-VS RESET-RST WIT#-SERR# RSV-REQ# REG#-/E# V/SP-UIO# V-STSHG #-# GN.U.U U/V VSUS R.U VSUS GN GN GN GN U _V _VPP VSUS U U MIO.U Place near the Slot V pins.u Place near the Slot VPP pins *P_ VPPEN K R V_RIN S_#/MIO E V_RIN MS_#/MIO MIO S_WP/MIO S/MS_PWR/MIO L V_ROUT S_PWR/MIO E V_ROUT S/MS_LE#/MIO S/MS_EXTLK_MIO S_M/MS_S/MIO V_MV S/MS_LK/MIO S/MS_T/MIO S/MS_T/MIO E S/MS_T/MIO S/MS_T/MIO.U MIO MIO E MIO MIO K MIO R REGEN# MIO E R R *P_.U EN GN GTU L.U MIO MIO MIO MIO MIO MIO MIO MIO MIO MIO MIO MIO MIO MIO MIO MIO MIO MIO MIO MIO E Q MENE T MIO R V R MIO_INV MIO MIO MIO MIO MIO MIO MIO MIO MIO MIO MIO MIO MIO MIO MIO MIO MIO MS_# MIO S/MS_V / ohm to ohm p stuff for EMI S issue R K.U U/V P X_E# MIO_S X_ X_WE# X_ MIO_S MIO X_R# S/MS_V For EMI R X_ R X_ R R X_ X_ R R R X_ X_ X_ R X_ R X_WP# R X_WE# R X_LE R X_LE R X_E# R X_RE# R X_R# MIO X_ MS_# X_ X_ X_ X_WE# R K R R R R V V MIO MIO S/MM L H MS x L H L L R R K For EMI S/MS_V NWS--F Q MENE NWS--F R K NWS--F ate: Thursday, May, Sheet of S/MS_V R R P K P For EMI V S/MS_V R K X_# Quanta omputer Inc. PROJET : ES Size ocument Number Rev R PMI/ IN P P MS Socket IN-R--XX-P MS-GN MS-V MS-SLK MS-T MS-# MS-T MS-T MS-T MS-S MS-GN ON S Socket ON S-T S-T S-M S-GN S-V S-LK S-GN N S-T S-T S-# S--OM S-WP-SW S-WP-OM P P IN-R--XX-P X Socket IN-R--XX-P IN-R--XX-P N X-V X- X- X- X- X- X- X- X- X-GN X-WP X-WE X-LE X-LE X-E X-RE X-R/ X-GN X-# ON

22 LN_XTL LN_XTL RTLE P Y MHz P U.U / R K/F_% TRL V V coil transformer: OT TS LF (YVLN) YT F-(ESLN) THERE IS ONE EGN PLNE UNER I V V V V RV V R *K TRL TRP TRM TRP TRM U VTRL V MIP MIN V MIP MIN V MIP MIN V MIP MIN V V V GN RSET VTRL GV KTL KTL V V LE LE LE LE V V RTLE-GR N N V N N LNWKE PERST V EV HSIP HSIN EGN REFLK_P REFLK_N EV HSOP HSON EGN V EESK EEI V EEO EES V N V N N V V ISOLTE N N V EESK EEI EEO EES ISOLTE V V V V off during S and S ISOLTE#, ctive Low, when Low, RTLE<->PIE is isolated. except LNWKE# V R K/F R K V V_.U V V_.U TRP TRM TRP TRM T hange to ead XHS R KHS-T V_ U T+ R+ RT TS LF T- R- TX+ T TX- RX+ T RX- / for LN EMI issue remove choke X-INT_TRP X-INT_TRM R R _F _F X-INT_TRP X-INT_TRM P/KV_/XR, PIE_WKE# R LN_PME_WKE# V R.K These parts only for RTLE application,, LINK_RST# PIE_TXP PIE_TXN LK_PIE_LN LK_PIE_LN# PIE_RXP PIE_RXN.U.U PIE_TXP PIE_TXN LK_PIE_LN LK_PIE_LN# LN_RXP LN_RXN EGN EV EES EESK EEI EEO S V SK N I ORG O GN U T.U TRM TRP TRM TRP RP RP._PR TMI.U._PR TMI.U POWER SUPPLY RV POWER SUPPLY.W L *U_ LMPGSN U_.U MILS.U.U.U.U V LOSE RTLE V pins (,, and ) <mils TRE <" WITH > MILS TRL *U_ L LMPGSN MILS U_ L hange to ead XHS R LMPGSN.U KHS-T.U.U.U.U V V EV LOSE RTLE V pin pin <mils LOSE RTLE V pins ( and ) <mils LOSE for RTLE EV pins ( and ) <mils X-INT_TRM X-INT_TRP X-INT_TRM X-INT_TRP ON RJ-FRGZL--P-V TRE <" WITH > MILS TRL *U_ MILS L LMPGSN U_ L LMPGSN L LMPGSN ISOLTE EGN N GN.U.U.U.U.U_.U.U.U.U EGN V.U.U LOSE RTLE V pins (,,,, and ) <mils RTLE P/N:LE RTLE is / ase, RTL is Giga ase RTLE and RTL are pin to pin compatible Quanta omputer Inc. PROJET : ES Size ocument Number Rev LN RTLE ate: Thursday, May, Sheet of

23 Mini PI-E ard WLN VSUS V V. / N change to.mm high for TV function V V V. VSUS / when working, LE always ON: R nostuff, Q stuff Normal pulse: R stuff, Q nostuff.u, PIE_WKE# U_.V VSUS.U PIE_TXP PIE_TXN PIE_RXP PIE_RXN, PLK_LP PIRST# LK_PIE_MINI_WLN LK_PIE_MINI_WLN# Q MENE U_ MINI_LKREQ#.U.U PIE_TXP PIE_TXN PIE_RXP.U PIE_RXN.U PLK_LP PIRST# LK_PIE_MINI_WLN LK_PIE_MINI_WLN# MINI_LKREQ# U_ N GN PETp PETn GN GN PERp PERn GN MINI PI EXPRESS ONN. - GN REFLK+ REFLK- GN LKREQ# WKE# +.V GN +.V LE_WPN# LE_WLN# LE_WWN# GN US_+ US_- GN SM_T SM_LK +.V GN +.Vaux PERST# GN +.V GN +.V WLN_LE R * R * PT_SM PLK_SM LINK_RST# L L L L LFRME# V R K USP+ USP- PT_SM, PLK_SM, LINK_RST#,,, L, L, L, L, LFRME#,, R * R dd for ebug K_ NWS--F WLN_LE# Q MENE V WLN_LE# WLSW P / placed close to N, for EMI FN ONN V One segment TV (Pixela) / U MX LT- is open drain pin F *FUSEV_POLY *U.V *.U *.U THERM_LERT# THERM_LERT# V R K VFN V U VO FON# GN GN GN VSET GN G L FNPWR =.*VSET VPU +V_FN U.V.U V ON -L USP+ USP- LP *LWHNSQL *PJL ON VV VV US_+ US_- GN GN *-seg TV ONN --P-L FNSIG R K FNSIG Q MENE R K / for IN- OT Layer change return path placed it in the back of LP at TOP *.U_V P_ Quanta omputer Inc. PROJET : ES Size ocument Number Rev FN / MINI PIE / -seg TV ate: Thursday, May, Sheet of

24 SWR SWL TPLK TPT TPLK TPT V SWR SWL Module PIN ONN Pin T/P SYSTEM LEs.U SW.U.V SW L F L R_SW L_SW FM- R R *P *P R R / Follow Module PIN onnector is at TOP ON TW-TPV TOUH P P NSWON# NSWON# PWRLE# SW O_LE# Power SW R K VPU GN V U TSZFU U TSZFU -SYG/S-E/TR LE-VG-TR lue -U//TR R LE-VG-TR -SYG/S-E/TR LE-VG-TR Green R Green R V VPU VPU, ST_LE# V U TSZFU -SYG/S-E/TR LE-VG-TR Green R WLN_LE# -SYG/S-E/TR LE-VG-TR Green R.U_V.U_V.U_V.U_V.U_V.U_V.U_V.U_V.U_V VPU V V.U.U.U.U.U.U.U.U / dd for LN borad EMI VSUS / dd for LN borad EMI.U.U.U TLE# R K GN U TSZFU Green/mber LELTST-KGJRKT-P -UYOSYG R R VPU.U.U.U.U.U.U.U VPU R K VPU.U.U.U.U / dd for LN borad EMI VPU.U.U_V.U_V V_ORE.U_V.U_V TLE# GN U TSZFU / reserved for LE power V VPU *.U *.U / for EMI decoupling POWER LE TT LE Wireless LE H LE O LE POWER SWITH Quanta omputer Inc. PROJET : ES Size ocument Number Rev LEs / TP ONNETOR ate: Thursday, May, Sheet of

25 -ROM ONNETOR ST H O_V IN for Master N for Slave IERST# P P P P P P P P PIOW# PIORY IRQ P P PS# O_LE# R _ SMT TYPE NN ON -ROM P P P P P P P P PREQ PIOR# PK# IG# P PS#.U R-T--P-RV-ES / minize P and hole size for routing R *K mils P_V.U V O_V U_ N GN TXP TXN GN RXN RXP GN.V.V.V GN GN GN V V V GN RSV GN V V V +.VST ST_TXP ST_TXN ST_RXN_ ST_RXP_ +.VST H_ON FHSFR.U ST-FRGZ-P-R-ES *.U_.U R.U.U *_ U_.U V ST_TXP ST_TXN ST_RXN ST_RXP H_V O_V mils R _ V H_V mils R _ V P[..] P[..] PREQ PIOW# PIOR# PIORY PK# IRQ P P PS# P PS# PREQ PIOW# PIOR# PIORY PK# IRQ P P PS# P PS# O_LE# V R K V R K O_LE#, ST_LE# ST_LE# ST_LE#,, LINK_RST# LINK_RST# R IERST# Quanta omputer Inc. PROJET : ES Size ocument Number Rev O/ST H ate: Thursday, May, Sheet of

26 GN V_LO ucio odec V EP SPIF R *K *K R R K/F.U SF SPIFO SPIFI/EP N N GPIO GPIO VSS HP_OUT_R JREF HP_OUT_L V MONO_OUT U_.V GN U HP_OUT_R HP_OUT_L / modify odec nalog Power V_LO From MX Internal LO.V or.v Try.V I_STO_UIO I_ITLK_UIO I_STIN I_SYN_UIO I_RESET#_UIO OE_RESET# _ R _ R R IN.nH p P_EEP.U R R U.U _ R K K *.U.U.U V GPIO GPIO VSS ST_OUT IT_LK VSS ST_IN V SYN RESET# P-EEP L SENSE LINE-L LINE-R MI-L MI-R -L _GN _R MI-L MI-R LINE-L LINE-R LINE_OUT_R LINE-OUT-L SENSE VOL MI-VREFO-R LINE-VREFO MI-VREFO LINE-VREFO MI-VREFO-L VREF VSS V LVOL UIOVREF GN U L-GR TQFP-X- R.U V_LO GN K.U OUT_R OUT_L V_LO MIVREFR MIVREFL UIOVREF U_.V U MIVREFL MIVREFR PMSPK# SPKR P-EEP R * NWS--F V HP-J R K R *.K V MI-J R HP-J R SF U SH GN GN GN GN Q TEU K/F.K/F P_EEP SENSE *.U *.U_ *.U_ U.V U.V.U_.U_.U_ LINE-L LINE-R MI-L MI-R _L _GN _R MIIN-L MIIN-R LINE-L LINE-R.U_.U_ GN U/.V U/.V GN *P MIIN-L MIIN-R GN *P.U L GN SKT-Y-N L SKT-Y-N / stuff R R for EMI SPRY THE RIGE ON THE GP OF /GN UNIFORMLY. SJ R SJ R SJ R SJ R SF SJ R R <PRT NUMER> R * SJ SJ R R R.K R.K MIIN-LL MIIN-RL MI-J R *_ GN GN.U GN EXT MI(Pink) SUYIN=FRGJL ON / FRGJL is going EOL FTJMS SUY FRGJL / modify MN---NQ OS / ohm XM MUR#LMS / ohm (Q) XT LN#SKT-Y-N / ohm - current use ENEEP GN GN For EMI / modify MN---NQ OS / ohm XM MUR#LMS / ohm (Q) XT LN#SKT-Y-N / ohm - current use HPOUT_L HPOUT_R HPOUT_L HPOUT_L_L R HPOUT_R HPOUT_R_R R L SKT-Y-N L SKT-Y-N HP-J HP-J HPOUT_L_L HPOUT_R_R SUYIN=FRGHL / FRGHL is going EOL FTJMS SUY FRGHL GN R *_ GN ON Quanta omputer Inc. PROJET : ES Size ocument Number Rev UIO L MI/HP ate: Thursday, May, Sheet of

27 OUT_L OUT_R HP_OUT_L HP_OUT_R / SPK disable by HP-J VMP HP-J V R *K VMP GN R K Q MENE U U U U GN R R R R K K U_SPK_ENLE# R *K *P/V *P/V *P/V *P/V GN GN VMP U GN GN U_.V U_.V GN U_SPK_ENLE# HP_EN MP_SHN# U_MP_GIN U_MP_GIN U GN U GN U SPKR_INL SPKR_INR HP_INL HP_INR IS SPKR_EN# HP_EN MUTE# GIN GIN HPV PV P N PGN PVSS PVSS MX MX TQFN PIN GN GN OUTL+ OUTL- OUTR+ OUTR- HPL HPR REGEN SET VOUT V PV_ PV_ GN_ PGN_ PGN_ U_SPK_L+ U_SPK_L- U_SPK_R+ U_SPK_R- HPOUT_L HPOUT_R REGEN SET VMP GN V_LO VMP VMP HPOUT_L HPOUT_R V F_ohm+-%_MHz.ohm L LMPGSN VMP GN VMP Layout Note: U_.V ead closed to V power source P placed close to pin. U_.V U GN Layout Note: Place close to pin. U R K For internal LO voltage in VMP HP_EN VMP Head phone MP always ON VOLMUTE# NWS--FMP_SHN# EP NWS--F / V or.v m(max) For internal LO output V_LO V_LO U_.V U_.V U_.V U_.V GN.U Layout Note: Place close pin OE_RESET# VMP R NWS--F K R R *K/F *.U GN Layout Note: Place close chip. SET R R K/F VMP For EMI VMP GN R *K R K R *K U_MP_GIN U_MP_GIN R K GIN GIN GIN d d.d.d GN V_LO_OUT=Vset(+R/R) =.V Vset=.V When SET connected to GN, V_LO_OUT =.V V_LO_OUT= fix.v Iout(max) = m, rop V = mv V_LO_OUT(actual) =.V - % =.V V_LO_OUT(worst_case) =. - mv =.V REGEN GN R.U Enable Internal LO U_SPK_L+ U_SPK_L- U_SPK_R- U_SPK_R+ SJ R SJ R SJ R SJ R INSPKL+ INSPKL- INSPKR- INSPKR+ INSPKL+ INSPKL- INSPKR+ INSPKR- -L ON P P P P Headphone gain is.d GN Quanta omputer Inc. PROJET : ES Size ocument Number Rev UIO MP/SPEKER ate: Thursday, May, Sheet of

28 VSUS VSUS VSUS / USV, and USV, swapped to use different P/ swap pin net to correct footprint mils F L F L F L USV mils USV mils USV mils USP+ USP- USP+ USP- LP LWHNSQL LP LWHNSQL PJL PJL USV *P USV *P *P *P ON GN GN GN GN GN US usb-mrszl-c-p-l-h ON GN GN GN GN GN US P *EMIPX P *EMIPX P *EMIPX P *EMIPX P *EMIPX P *EMIPX P *EMIPX P *EMIPX P *EMIPX P *EMIPX F L USV mils PJL usb-mrszl-c-p-l-h / remove OT P for TV.U.U + U/.V HMJ USP- USP+ LP LWHNSQL USV *P *P ON GN GN GN US Vertical Type H H H H H H-P H-P h-tcbexdp H-P H-PT H H H H H H-P h-tcbexdp h-tcbexdp H-P H-P USV u to u USV u to u PJL.U U/.V_.U U/.V_ USP- USP+ LP / stuff LP,LP,LP,LP for EMI LWHNSQL USV *P *P -L ON To US wire H H H H H-P H-P H-P H-P heck Pin efine ON MY MY MY MY MY MY MY MY MY MY MY MY MY MY MY MY MY MY MY MY MY MY MY MY MY MY MY MY MY MY MY MY MX MX MX MX MX MX MX MX MX MX MX MX MX MX MX MX --P-L Keyoard onnector ot contact??? Px P Px P Px P Px P Px P Px P MY MY MY MY MY MY MY MY MY MY MY MY MY MY MY MY MX MX MX MX MX MX MX MX MY MY MY MY MX MX MX MX MY MY MY MY VPU RP KX RP KX RP KX MY MY MY MY MX MX MX MX MY MY MY MY / for ME copper contact H H-P H H H H H-P H-IP H-P H-IP NPTH hole / for -seg TV H H H h-cdn h-cdn H-N H H H-TP H-TP H H / for US wire GN P P H-TP H-TP *P-NPT *P-NPT H h-tcbcdp Quanta omputer Inc. PROJET : ES Size ocument Number Rev KEYOR/US/SREW ate: Thursday, May, Sheet of