4 Maintenance and Service Guide,Service Manual,Motherboard Schematics for Laptop/notebook ZHG SYSTEM DIAGRAM. AMD Brazos2.

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1 P STK UP LYER : TOP LYER : LYER : IN LYER : IN LYER : V LYER : OT EP@ -----> ep panel LVS@ -----> LVS panel HT@ -----> HT fucntion G@ -----> G function U@ -----> US.0 only U@ -----> US.0 function S@ -----> ES L@ -----> EL PU (PROHOT) E.. (PUFN#) R- SOIMM R-0 PGE FN SH. PGE R hannel PU Sideand TemperatureSense I SYSTEM IGRM M razos.0 0 FT mmxmm pin G UMI x TP~W PGE,, TP VG LTP0 PI-Expresss HMI RT LVS ep (Optional) PGE P PGE PGE PGE P P0 PLK_EUG ST - H PGE ST0 0M Gb/s M Hudson-ML.mmX.mm, pin G TP~.W Mini ard WLN & ebug PGE Mini ard G PGE SIM PGE LN Realtek RTL0 (0/00) PGE MHz RJ PGE US.0 P P P P Web-amera PGE P0 US.0/.0 Port M x PGE IO / P FF P P0 HRGER (Q0) PGE M PU ORE (OZ0) PGE.-0V (TPS) PGE R.V(TPS) PGE PU N LK_PI_E PU Sideand TemperatureSense I.KHz MHz K NPE LP PGE 0 US.0 PGE,,,0, zalia udio OE Realtek LX-V PGE P0 ardreader U MHz INT MI US.0 Port x UIO ONN ombo Jack SYSTEM V/V (RTP) PGE PGE.V(TPS) PGE ischarge /Thermal protection PGE Keyboard TouchPad (Image Sensor) PGE SPI ROM PGE Speaker PGE Quanta omputer Inc. PROJET : Size ocument Number Rev lock iagram ate: Tuesday, January 0, 0 Sheet of

2 INEX Power Sequence 0 PGE# 0 ESRIPTION LOK IGRM SYSTEM INFORMTION ONTRIO MEM & PIE I/F(/) ONTTIO ISPLY/LK/MI(/) ONTRIO POWER & EOUP(/) R SO-IMM (ST=.) FH /(GPIO/US/Z) FH /(PI/PI/LK) FH /(ST/VG/SPI) FH /(POWER/) FH /(Strap/PWRG) RT / L / Hall I / HMI NOTE IN V/VPU NSWON# NSWON# S_ON/S RSMRST# PIE_WKE# SUS SUS SUSON Hudson ML SMUS M SMUS Pin NO. SMUS Function efine PLK_SM R / WLN / G / Image Sensor PT_SM E (V) SLK T Not used ST R (V_S) SM_E_LK H harger / attery SM_E_T G (V_S) S_SLK G PU S_ST G (V_S) LN RTL0T-V-G MINON 0 MINI R / G / SIM udio odec L H/LE/PWR Sequence conn US Port//HOLE K/TP/TPM/FN NPE/FLSH harger (Q0) SYSTEM V/V (RTP) PU_ORE_razos (OZ0).V_S(TPS).0V(TPS) VR_ON PU_ORE VRM_PWRG HWPG EPWROK S_PWRG_IN PU RESET PU POWER OK K(E) SMUS NPE SMUS Pin NO. MLK 0 MT (VPU) PU_SI_E PU_SI_E (VPU) SMUS Function efine attery / harger PU R.V(TPS).V/ischarge /Thermal HNGE LIST Quanta omputer Inc. PROJET : Size ocument Number Rev System Information Tuesday, January 0, 0 ate: Sheet of

3 (PU) () M [:0] () M S[..0] () M M[..0] () M QSP0 () M QSN0 () M QSP () M QSN () M QSP () M QSN () M QSP () M QSN () M QSP () M QSN () M QSP () M QSN () M QSP () M QSN () M QSP () M QSN () M LKP0 () M LKN0 () M LKP () M LKN () M RST# () M EVENT# () M KE0 () M KE () M OT0 () M OT () M S#0 () M S# M 0 R M H M J M H M H M G M H M G M F M E M 0 T M F M E M W M E M G M EVENT# M KE0 M KE M S0 R M S T M S F M M0 M M M M M M H M M P M M V M M 0 M M 0 0 E E J J R P W V 0 M M M M N N L L L N F E W V U W T W U V M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_ M_ M_ M_ M_ M_NK0 M_NK M_NK M_M0 M_M M_M M_M M_M M_M M_M M_M M_QS_H0 M_QS_L0 M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L M_LK_H0 M_LK_L0 M_LK_H M_LK_L M_LK_H M_LK_L M_LK_H M_LK_L M_RESET_L M_EVENT_L M_KE0 M_KE M0_OT0 M0_OT M_OT0 M_OT M0_S_L0 M0_S_L M_S_L0 M_S_L ONTRIO (.0) PRT OF MEMORY I/F UE M_T0 M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T0 M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T0 M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T0 M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T0 M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T0 M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T0 M_T M_T M_T M_VREF M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 0 M Q M Q M Q M Q 0 M Q M Q M Q F M Q F M Q M Q0 M Q F0 M Q F M Q H M Q H M Q K M Q K M Q G M Q H0 M Q K0 M Q0 K M Q N M Q P M Q T0 M Q T M Q M0 M Q P0 M Q R M Q T M Q V0 V M Q0 M Q Y M Q Y M Q T M Q U M Q W M Q Y M Q Y0 M Q M Q M Q0 M Q M Q 0 M Q M Q Y M Q M Q Y M Q M Q M Q M Q0 M Q M Q M Q M M Q[0..] () K/F_ ON_ZV U PIE_TXP0_LN_ () PIE_RXP0_LN P_GPP_RXP0 P_GPP_TXP0 0.u/0V_ PIE_TXP0_LN () PIE_TXN0_LN_ () PIE_RXN0_LN Y P_GPP_RXN0 P_GPP_TXN0 0.u/0V_ LN PIE_TXN0_LN () ONTRIO (.0) PRT OF PIE_TXP_ () PIE_RXP P_GPP_RXP P_GPP_TXP 0.u/0V_ PIE_TXP () PIE_TXN_ WLN () PIE_RXN P_GPP_RXN P_GPP_TXN 0.u/0V_ PIE_TXN () PIE_TXP_ () PIE_RXP P_GPP_RXP P_GPP_TXP Y 0 0.u/0V_ PIE_TXP () PIE_TXN_ 0.u/0V_ () PIE_RXN P_GPP_RXN P_GPP_TXN Y PIE_TXN () V_0 Y P_GPP_RXP P_GPP_TXP V Y P_GPP_RXN P_GPP_TXN V () () () () () () () () R M_VREF UMI_RXP0 UMI_RXN0 UMI_RXP UMI_RXN UMI_RXP UMI_RXN UMI_RXP UMI_RXN R K/F_ R K/F_ M_VREF.VSUS Y Y 0 Y u/0V_ P_ZV_0 P_UMI_RXP0 P_UMI_RXN0 P_UMI_RXP P_UMI_RXN P_UMI_RXP P_UMI_RXN P_UMI_RXP P_UMI_RXN 000p/0V_ PIE I/F UMI I/F FT_ONTRIO.VSUS.VSUS P_ZVSS ON_ZVSS P_UMI_TXP0 UMI_TXP0_ P_UMI_TXN0 UMI_TXN0_ P_UMI_TXP UMI_TXP_ P_UMI_TXN UMI_TXN_ P_UMI_TXP P_UMI_TXN Y P_UMI_TXP P_UMI_TXN R R M EVENT# UMI_TXP_ UMI_TXN_ UMI_TXP_ UMI_TXN_ *.K_ K/F_ UMI_TXP0 () UMI_TXN0 () UMI_TXP () UMI_TXN () UMI_TXP () UMI_TXN () UMI_TXP () UMI_TXN () 0 This page is different M Nile R0.K/F_ Q *MMT0 R 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ *0_ G PU_MEMHOT# () () () () M RS# M S# M WE# U V V M_RS_L M_S_L M_WE_L FT_ONTRIO? M_ZVIO_MEM_S M./F_ R.VSUS P/N Item escription J000VT00PU(P)M0FPGV.0G(G) J000VT0PU(P)M0FPGV.0G(G)STN SQ Quanta omputer Inc. PROJET : Size ocument Number Rev ONTRIO MEM & PIE I/F(/) ate: Tuesday, January 0, 0 Sheet of

4 PU_TI PU_TO PU_TK PU_TMS PU_TRST# RY (PU).V 0 R R K/F_ K/F_ PU_SV PU_SV V () (0) () (0) V R 00_ R 00_ R0 R R00 INT_RT_RE INT_RT_GRE INT_RT_LU LVS@.K_ LVS@.K_ S_SLK PU_SI_E S_ST PU_SI_E K/F_ K/F_ K/F_ R R R R R0 R R LT_RST# PU_PWRG PU_THERMTRIP# PU_LERT# H_PROHOT# 0/F_ 0/F_ 0/F_ *0_ R 0_ *0_ R 0_ V Q *N00W R 0_ R0 0_ R0 K/F_ L_LK_EPUX L_T_EPUX- () TX_HMI () TX_HMI- () TX_HMI () TX_HMI- () TX0_HMI () TX0_HMI- () TX_HMI () TX_HMI- () TXLOUT_EPTX0 () TXLOUT-_EPTX0- () TXLOUT_EPTX () TXLOUT-_EPTX- () TXLOUT0_EPTX () TXLOUT0-_EPTX- () TXLLKOUT_EPTX () TXLLKOUT-_EPTX- () LK_PU_P () LK_PU_N () LK_P_P () LK_P_N (,) LT_RST# (,) PU_PWRG (,0) H_PROHOT# R0 K/F_ PU_SI PU_SI 0.u/0V_ PEG_HMI_TXP 0.u/0V_ PEG_HMI_TXN 0.u/0V_ PEG_HMI_TXP 0.u/0V_ PEG_HMI_TXN 0.u/0V_ PEG_HMI_TXP0 0.u/0V_ PEG_HMI_TXN0 0.u/0V_ PEG_HMI_TXP 0.u/0V_ PEG_HMI_TXN PU_SV PU_SV PU_SI PU_SI R0 0_ LT_RST#_R R 0_ PU_PWRG_R H_PROHOT# PU_THERMTRIP# PU_LERT# PU_TI PU_TO PU_TK PU_TMS PU_TRST# RY REQ# U NLOG/ISPLY/MIS TP_TXP0 TP_TXN V V J J P P T T U U T N N P P M M M F G F F W V TP_TXP TP_TXN TP_TXP TP_TXN TP_TXP TP_TXN LTP0_TXP0 LTP0_TXN0 LTP0_TXP LTP0_TXN LTP0_TXP LTP0_TXN LTP0_TXP LTP0_TXN LKIN_H LKIN_L ISP_LKIN_H ISP_LKIN_L SV SV SI SI RESET_L PWROK PROHOT_L THERMTRIP_L LERT_L TI TO TK TMS TRST_L RY JTG TRL SER ISPLYPORT 0 ISPLYPORT LK P MIS TEST VG REQ_L VR_N_SENSE VR_PU_SENSE VIO_MEM_S_SENSE VSS_SENSE RSV_ RSV_ ONTRIO (.0) RSV_ PRT OF FT_ONTRIO? P_ZVSS P_LON P_IGON P_VRY_L TP_UXP TP_UXN TP_HP LTP0_UXP LTP0_UXN LTP0_HP _RE _RE _GREEN _GREEN _LUE _LUE _HSYN _VSYN _SL _S _ZVSS TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST_H TEST_L TEST_H TEST_L TEST TEST_H TEST_L TEST_H TEST_L TEST TEST TEST TEST MTIVE_L H G H H E E F R R R T E K L L M K K L M M J J U T H N R K T _RSET R INT_ePI_HP R PU_THERM T PU_THERM T PU_TEST_IRERKMON T PU_P0_TSTLK_USLK0 T T PU_P_SNSHIFTEN_UST T PU_P_SNSHIFTEN_UST0 T TEST R K/F_ TEST R K/F_ R0 0/F_ R 0/F_ PU_TEST_H_PLLHRZ T PU_TEST_L_PLLHRZ T PU_TEST_MEM_TEST T PU_TEST_H_M_LKTST_H 0.u/0V_ PU_TEST_H_M_LKTST_L 0.u/0V_ PU_TEST_H_TSTLKIN_H T PU_TEST_L_TSTLKIN_L T PU_TEST R *K/F_ PU_TEST R K_ PU_TEST_GIO_TSTTM0_LKINIT T PU_FO ON_MTIVE# 0/F_ /F_ R 0_ HMI_LK () HMI_T () INT_HMI_HP () L_LK_EPUX () L_T_EPUX- () INT_ePI_HP () INT_RT_RE () INT_RT_GRE () INT_RT_LU () INT_RT_HSYN () INT_RT_VSYN () INT_LK () INT_T () R K/F_ R T0 R0 K/F_ 00K_ R R.V.V INT_LVS_LON () INT_LVS_IGON () INT_LVS_PWM () /F_ /F_ LLOW_LTSTP () HMI LVS Panel ep Panel 0 lock H0 H H lock H0 H H ML ML ML ML0 P UX lock lock UX ata ata P UX- UX- V VSS_SENSE R 0_ VR_PU_SENSE R 0_ VIO_SUS_SENSE R *0_ VSS_SENSE R 0_ VR_N_SENSE R 0_ PU_V0_F_L () PU_V0_F_H ().VSUS_SR () PU_VN_F_L () PU_VN_F_H ().V Eliminate the HMI Output isable Strapping onfiguration TEST (ball H) Remove "K pull down" to VSS Enable HMI Output TEST (ball H) dd K "pull up" to the V_ power rail R0 0K/F_ IFFERENTIL ROUTING (,,) SYS_SHN# R 0_ Q MMST0--F V PU_THERMTRIP# VI Override ircuit.v R *0K/F_ R *00_ R *00_ R *.K_ () FH_THERMTRIP# R *0_ Q *MMST0--F PU_SV PU_SV R 0_ R 0_ PU_SV () PU_SV () PU_PWRG R *0_ PU_PWRG_SVI_REG PU_PWRG_SVI_REG () for normal operation open all switches R *0/F_ R *0/F_ R0 *0/F_ V () THERM_LERT# THERM_LERT# R 0_ R *0_ R 0K/F_ Q MMST0--F PU_LERT# V R0 *0K/F_ Q *MMST0--F H_PROHOT# HT onnector(pu).v.v HT HEER / PLE ON TOP.V R HT@K/F_ PU_TRST# R R R0 R HT@0_ HT_TRST# HT@0K_ HT@0K_ HT@0K_ N PU_VIO PU_TK PU_TMS PU_TI PU_TO PU_TRST_L PU_PWROK_UF 0 PU_RY PU_RST_L_UF PU_RY PU_RY0 PU_RY PU_REQ_L PU_PLLTEST0 PU_VIO PU_PLLTEST 0 HT@HT PU_TK PU_TMS PU_TI PU_TO PU_PWRG_UF LT_RST#_UF RY REQ# J0_PLLTST0 J0_PLLTST R R R R R0 R0 HT@K/F_ HT@K/F_ HT@K/F_ HT@K/F_ HT@0_ HT@0_ TEST TEST LT_RST#_R PU_PWRG.V HT@0.u/0V_ U V Y LT_RST#_UF Y PU_PWRG_UF HT@SNLVG0KR R R.V HT@K/F_ HT@K/F_ Quanta omputer Inc. PROJET : Size ocument Number Rev ONTTIO ISPLY/LK/MI(/) Wednesday, January, 0 ate: Sheet of

5 (PU) VORE 0 NORE.VSUS 0mil viax 0 00mil viax0 0mil viax E VR_PU_ E VR_PU_ F VR_PU_ F VR_PU_ G VR_PU_ G VR_PU_ H VR_PU_ H VR_PU_ J VR_PU_ J VR_PU_0 L VR_PU_ M VR_PU_ M VR_PU_ N VR_PU_ R VR_PU_ E VR_N_ E VR_N_ E VR_N_ F VR_N_ F VR_N_ G VR_N_ G VR_N_ H VR_N_ H VR_N_ K VR_N_0 K VR_N_ L0 VR_N_ L VR_N_ L VR_N_ M VR_N_ M VR_N_ M VR_N_ N0 VR_N_ N VR_N_ N VR_N_0 P VR_N_ P VR_N_ G VIO_MEM_S_ G VIO_MEM_S_ E VIO_MEM_S_ J VIO_MEM_S_ L VIO_MEM_S_ L VIO_MEM_S_ N VIO_MEM_S_ R VIO_MEM_S_ R VIO_MEM_S_ W VIO_MEM_S_0 U VIO_MEM_S_ FT_ONTRIO U ONTRIO (.0) PRT OF POWER? V V V V V V V V VPL_0 V_0_ V_0_ V_0_ V_0_ V_ U W U U W T V W U U W V T VPL_0 00 0u/.V_ V_ u/.v_ 0u/.V_ 0 00m 0mil viax 0mil viax u/.v_ VN 0u/.V_ 00m 0mil viax 0.u/0V_ 0 u/.v_. 0mil viax 0 0u/.V_ V 0.u/0V_ 0m 0mil viax 0u/.V_ 0.u/0V_ 0 0u/.V_ R 0_ 0 u/.v_ u/.v_ 0.u/0V_.0V 0.u/0V_ 0 0 u/.v_ L u/.v_ LMPGSN/./0ohm_ V_0 R 0_ u/.v_.v 0.u/0V_.0V.V 00-- change R0 P/N and footprint add R R 0_ R 0_ 0.u/0V_ 0.u/0V_ 0 0.u/0V_ 0 0u/.V_ 0.u/0V_ 0 0.u/0V_ 0u/.V_ 0.u/0V_ 0.u/0V_ 0u/.V_ 0 0.u/0V_ 0u/.V_ 0.u/0V_ 0u/.V_ 0.u/0V_ 0u/.V_ 0.u/0V_ 0u/.V_ 0.u/0V_ 0u/.V_ 0.u/0V_ 0u/.V_ 0.u/0V_ 0u/.V_ 0.u/0V_ 0 VORE VORE NORE NORE 0u/.V_ 0.u/0V_ 0u/.V_ 0 0.u/0V_ u/.v_ u/.v_ u/.v_ This page is different M Nile 0 u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ VORE NORE u/.v_ u/.v_.vsus.vsus u/.v_ u/.v_ 0p/0V_ u/.v_ 0u/.V_ 0u/.V_ U.VSUS VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ E VSS_ E VSS_ E VSS_ E0 VSS_ F VSS_ F VSS_0 F VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G0 VSS_ G VSS_ H VSS_ H VSS_0 H VSS_ J VSS_ J VSS_ J VSS_ J0 VSS_ K0 VSS_ K VSS_ L VSS_ L VSS_ L VSS_0 L VSS_ L VSS_ L0 VSS_ L VSS_ M VSS_ N VSS_ N VSS_ N VSS_ N VSS_ ONTRIO (.0) PRT OF GROUN VSS_0 N VSS_ N0 VSS_ N VSS_ P0 VSS_ P VSS_ R VSS_ R VSS_ R0 VSS_ T VSS_ T VSS_0 T VSS_ T VSS_ U VSS_ U VSS_ U VSS_ U VSS_ U0 VSS_ U VSS_ V VSS_ V VSS_0 V VSS_ V VSS_ W VSS_ W VSS_ W VSS_ W VSS_ W VSS_ W VSS_ W0 VSS_ Y VSS_0 Y VSS_ Y VSS_ Y VSS_ Y VSS_ Y VSS_ Y VSS_ Y VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSSG_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0p/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ place capacitors under G EM PS.VSUS VORE NORE.VSUS 0p/0V_ 0p/0V_ 0.u/0V_ 0 0 0p/0V_ 0p/0V_ 0p/0V_ 0p/0V_ 0.u/0V_ V_ VN V_0 VPL_0 V 0 0p/0V_ 0p/0V_ 0p/0V_ 0p/0V_ 0p/0V_ 0.u/0V_ FT_ONTRIO? Quanta omputer Inc. PROJET : Size ocument Number Rev ONTRIO POWER & EOUP(/) Tuesday, January 0, 0 ate: Sheet of

6 R_VREF PLK_SM PT_SM IMM0_S M 0 M S M S M S0 MEM HOT# M M0 M QSN0 M QSP0 M OT0 M OT M S# M RS# M WE# M S#0 M S# M LKN0 M LKP0 M LKN M LKP M KE M KE0 M M M M M M M M M M 0 M M M M M M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q0 M Q M Q M M M M M M M M M M M M M M M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSN M QSN M QSN M QSN M QSN M QSN M QSN R_VREF IMM0_S0 R_VREF R_VREF R_VREF R_VREF M Q[0..] () M [0..] () M S[0..] () M M[0..] () M QSP[:0] () M QSN[:0] () M OT0 () M OT () PLK_SM (,,) PT_SM (,,) M RS# () M S# () M WE# () M S#0 () M S# () M LKP0 () M LKN0 () M LKP () M LKN () M KE0 () M KE () M RST# () M EVENT# ().VSUS.VSUS.VSUS.VSUS V 0.V_R_VTT.VSUS SMR_VREF.VSUS SMR_VREF.VSUS Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R SO-IMM (ST) Tuesday, January 0, 0 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R SO-IMM (ST) Tuesday, January 0, 0 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R SO-IMM (ST) Tuesday, January 0, 0 0 SM_MEM US RESS SO-IMM US_ 00m m m (R) 0.u/0V_ 0.u/0V_ 0 0.u/0V_ 0 0.u/0V_ 0.u/0V_ 0.u/0V_ R *0_ R *0_.u/.V_.u/.V_ 0p/0V_ 0p/0V_.u/.V_.u/.V_ 0.u/0V_ 0.u/0V_ R0 K/F_ R0 K/F_ 0 0.u/0V_ 0 0.u/0V_.u/.V_.u/.V_ 0.u/0V_ 0.u/0V_ u/.v_ u/.v_ 0.u/0V_ 0.u/0V_ R 0K/F_ R 0K/F_ *000p/0V_ *000p/0V_.u/.V_.u/.V_.u/.V_.u/.V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ R K/F_ R K/F_ P00 R SRM SO-IMM (0P) N R-IMM_H=._ST P00 R SRM SO-IMM (0P) N R-IMM_H=._ST 0 0 0/P 0 /# S0# S# K0 0 K0# 0 K 0 K# 0 KE0 KE S# RS# 0 WE# S0 S 0 SL 0 S 00 OT0 OT 0 M0 M M M M M M 0 M QS0 QS QS QS QS QS QS QS QS#0 0 QS# QS# QS# QS# QS# QS# QS# Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q 0 Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q 0 Q Q 0 Q Q0 Q Q Q Q Q Q Q 0 Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q Q R 0K/F_ R 0K/F_ R K/F_ R K/F_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ R K/F_ R K/F_ 0 0.u/0V_ 0 0.u/0V_ 0.u/0V_ 0.u/0V_ u/.v_ u/.v_ 0.u/0V_ 0.u/0V_ R 0_ R 0_ u/.v_ u/.v_ 000p/0V_ 000p/0V_.u/.V_.u/.V_ 0.u/0V_ 0.u/0V_ R *0_ R *0_ P00 R SRM SO-IMM (0P) N R-IMM_H=._ST P00 R SRM SO-IMM (0P) N R-IMM_H=._ST V V V V V V V V V V0 00 V 0 V 0 V V V V V V VSP N N NTEST EVENT# RESET# 0 VREF_Q VREF_ VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 0 VSS VSS VTT 0 VTT 0 0 0

7 (LG) 0 V_S N,no install by default V V_S V_S R R R R R R R0 R R R0 R R R R R R *.K_ *.K_ *.K_.K_.K_ *0K_ *.K_.K_.K_ *0K/F_ *0K/F_ 0K_ 0K_ 0K_ 0K_ 0K_ FH_TEST0 FH_TEST FH_TEST PLK_SM PT_SM GPIO VG_P SLK ST S_SLK S_ST SYS_RST# FH_THERMTRIP# O_# O_0# FH_JTG_TK Internal have P For imm, WLN, TP Integrated.-kΩ PU () () PU_MEMHOT# (0) E_WLN_WKE# T0 (,0) SUS# (,0) SUS# (,0) NSWON# () FH_PWRG (0) SIO_0GTE (0) SIO_RIN# (0) SIO_EXT_SI# (0) SIO_EXT_SMI# () LPP# T (,) PIE_WKE# T FH_THERMTRIP# 0 () () () VG_P for power control PIE_REQ_G# PIE_REQ_LN# () OR_I () OR_I () (,,) (,,) SPKR PLK_SM PT_SM T PIE_REQ_WLN# () p/0v_ T SPI_HOL# V PU_MEMHOT# O_PLUGIN# SUS# SUS# NSWON# R 0_ FH_PWRG FH_TEST0 FH_TEST FH_TEST SIO_RIN# SIO_EXT_SMI# SYS_RST# PIE_WKE# GEVENT0# FH_THERMTRIP# R 0K/F_ W_PWRG PH_RSMRST#_R PIE_REQ_G# PIE_REQ_LN# OR_I OR_I SPKR PLK_SM PT_SM GPIO PIE_REQ_WLN# GPIO VG_P SPI_HOL# GPIO PWR_TN# SLK ST R W T W J N T T0 V E G R T U K V R0 F U G E E F H G F T R G G J G V W Y V0 F U PIE_RST#/GEVENT# RI#/GEVENT# SPI_S#/GE_STT/GEVENT# SLP_S# SLP_S# PWR_TN# PWR_GOO RSMRST# HUSON-M Part of TEST0 TEST/TMS TEST G0IN/GEVENT0# KRST#/GEVENT# PME#/GEVENT# LP_SMI#/GEVENT# LP_P#/GEVENT# SYS_RESET#/GEVENT# WKE#/GEVENT# IR_RX/GEVENT0# THRMTRIP#/SMLERT#/GEVENT# W_PWRG LK_REQ#/ST_IS0#/GPIO LK_REQ#/ST_IS#/GPIO SMRTVOLT/ST_IS#/GPIO0 LK_REQ0#/ST_IS#/GPIO0 ST_IS#/FNOUT/GPIO ST_IS#/FNIN/GPIO SPKR/GPIO SL0/GPIO S0/GPIO SL/GPIO S/GPIO LK_REQ#/FNIN/GPIO LK_REQ#/FNOUT/GPIO IR_LE#/LL#/GPIO SMRTVOLT/SHUTOWN#/GPIO R_RST#/GEVENT#/VG_P GE_LE0/GPIO SPI_HOL#/GE_LE/GEVENT# GE_LE/GEVENT0# GE_STT0/GEVENT# LK_REQG#/GPIO/OSIN/ILEEXIT# GPIO US MIS PI / WKE UP EVENTS US. USLK/M_M_M_OS US.0 US_ROMP US_FSP/GPIO US_FSN US_FS0P/GPIO US_FS0N US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HS0P US_HS0N US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN G H H H H H0 G0 K0 J G F K K E0 F0 0 0 H G F E US_ROMP_S USP USP- USP0 USP0- USP USP- USP USP- USP USP- USP USP- R.K/F_ T T T T USP0 () USP0- () USP () USP- () USP () USP- () USP () USP- () USP () USP- () USP () USP- () Note: US P/N pairs with trace lengths up to 0" M co-lay US.0 port SIM WLNT ard Reader / HU HU HU (,0) V_S R R PH_RSMRST# *0K_ *.K_ PIE_WKE# PWR_TN# Note:LL#, WKE# and PWR_TN need pull up to VPU only if S mode is supported R 0_ PH_RSMRST#_R R 0K_ () () GEVENT# ~# are V_S O_# O_0# Haudio interface are V_S () T T T T T R 0_ R0 0_ OR_I0 R *0K_ R0 0 *0K_0PR FH_LINK SMLERT#_R GEVENT# O_EJ FH_JTG_TO FH_JTG_TK FH_JTG_TI FH_JTG_RST# Z_LK_R Z_SOUT_R Z_SIN0 Z_SIN Z_SIN_R Z_SIN_R Z_SYN_R Z_RST#_R T M R T P F P J T Y Y Y E K J J LINK/US_O#/GEVENT# US_O#/IR_TX/GEVENT# US_O#/IR_TX0/GEVENT# US_O#/IR_RX0/GEVENT# US_O#/_PRES/TO/GEVENT# US_O#/TK/GEVENT# US_O#/TI/GEVENT# US_O0#/SPI_TPM_S#/TRST#/GEVENT# Z_ITLK Z_SOUT Z_SIN0/GPIO Z_SIN/GPIO Z_SIN/GPIO Z_SIN/GPIO0 Z_SYN Z_RST# H UIO PS_T/S/GPIO PS_LK/E/SL/GPIO SPI_S#/GE_STT/GPIO US O US.0 US_HSP US_HSN US_HS0P US_HS0N USSS_LRP USSS_LRN US_SS_TXP US_SS_TXN US_SS_RXP US_SS_RXN US_SS_TXP US_SS_TXN US_SS_RXP US_SS_RXN US_SS_TXP US_SS_TXN US_SS_RXP US_SS_RXN E E E F F G H G USP USP- USP0 USP0- USSS_LRP USSS_LRN R R0 USP () USP- () USP0 () USP0- () U@K/F_ U@K/F_ G debug port FH_V SSUS_S V_S V T0 V_S R *0K_ KSO_ Provided test points from checklist 0 F E0 F0 E 0 J H G K PSK_T/GPIO PSK_LK/GPIO0 PSM_T/GPIO PSM_LK/GPIO KSO_0/GPIO0 KSO_/GPIO0 KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_0/GPIO KSO_/GPIO0 KSO_/GPIO KSO_/GPIO KSO_/X0/GPIO KSO_/X/GPIO KSO_/X/GPIO KSO_/X/GPIO EMEE TRL US_SS_TX0P US_SS_TX0N US_SS_RX0P US_SS_RX0N SL/GPIO S/GPIO SL_LV/GPIO S_LV/GPIO E_PWM0/E_TIMER0/GPIO E_PWM/E_TIMER/GPIO E_PWM/E_TIMER/WOL_EN/GPIO E_PWM/E_TIMER/GPIO00 KSI_0/GPIO0 KSI_/GPIO0 KSI_/GPIO0 KSI_/GPIO0 KSI_/GPIO0 KSI_/GPIO0 KSI_/GPIO0 KSI_/GPIO0 J H J K H G G G E H J H K K F F E F US_TXP0 US_TXN0 US_RXP0 US_RXN0 SM_E_LK SM_E_T E_PWM US_TXP0 () US_TXN0 () US_RXP0 () US_RXN0 () S_SLK () S_ST () E_PWM () US.0 GPIO ~ are V_S SM_E_LK SM_E_T R *0K_ R *0K_ Q *N00W MLK MT MLK (0,) MT (0,) () SMLERT# R *0K_ Q0 *N00K SMLERT#_R To zalia E Ie_(M) Ie_(M) Ie_(M) FH evice If_(M) harger attery PU I_evice(S) LL/S LL E will onflict with FH. o not mount Z_SOUT_R Z_SYN_R Z_LK_R R _ R0 _ R _ Z_SOUT_UIO Z_SYN_UIO Z_ITLK_UIO Z_SOUT_UIO () Z_SYN_UIO () Z_ITLK_UIO () If_(M) If_(M) PU S S *p/0v_ If_0(M) R WLN/G Image Sensor S0 Z_RST#_R R _ Z_RESET#_UIO Z_RESET#_UIO () Z_SIN0 Z_SIN0 () Quanta omputer Inc. PROJET : Size ocument Number Rev FH /(GPIO/US/Z) Tuesday, January 0, 0 ate: Sheet of

8 (LG) 0 0P/0V_ UE HUSON-M PIE_RST# (,) PIE_RST# R _ E F _RST#_R PIE_RST# PILK0 PI_LK_R PI_LK () _RST#_R Part of F R 0 RST# PILK/GPO PI_LK () F UMI_RXP0 UMI_RXP0_ PI_LK_R PI_LK () UMI_RXP0 0 0.u/0V_ PILK/GPO E0 G R0 0_ PI_LK () UMI_RXN0 UMI_RXN0_ PI_LK_R PI_LK () UMI_RXN0 0.u/0V_ UMI_TX0P PILK/GPO E F R0 0_ PI_LK () UMI_RXP UMI_RXP_ () UMI_RXP 0.u/0V_ UMI_TX0N PILK/M_OS/GPO UMI_RXN UMI_RXN_ () UMI_RXN 0.u/0V_ UMI_TXP UMI_RXP UMI_RXP_ UMI_TXN PIRST# T () UMI_RXP 0.u/0V_ UMI_RXN UMI_RXN_ () UMI_RXN 0.u/0V_ UMI_TXP UMI_RXP UMI_RXP_ () UMI_RXP 0.u/0V_ UMI_TXN 0 J UMI_RXN UMI_RXN_ () UMI_RXN 0.u/0V_ UMI_TXP 0/GPIO0 L UMI_TXN /GPIO G UMI_TXP0 /GPIO () UMI_TXP0 L UMI_TXN0 UMI_RX0P /GPIO () UMI_TXN0 H UMI_TXP UMI_RX0N /GPIO () UMI_TXP J UMI_TXN UMI_RXP /GPIO () UMI_TXN L UMI_TXP UMI_RXN /GPIO () UMI_TXP Y N UMI_TXN UMI_RXP /GPIO () UMI_TXN Y N UMI_TXP UMI_RXN /GPIO () UMI_TXP Y J UMI_TXN UMI_RXP /GPIO () UMI_TXN Y L UMI_RXN 0/GPIO0 L R 0/F_ PIE_LRP /GPIO F M PIE_LRN.V_PIE_VR R K/F_ PIE_LRP /GPIO F J PIE_LRN /GPIO K /GPIO V N GPP_TX0P /GPIO V G GPP_TX0N /GPIO W0 M GPP_TXP /GPIO W J0 GPP_TXN /GPIO L V GPP_TXP /GPIO K GPP_TXN 0/GPIO0 Note: LK_FH_SRP/N is 00MHZ SS N GPP_TXP /GPIO G GPP_TXN /GPIO Note: LK_P_NSSP/N is 00MHZ non-ss E PI_ /GPIO PI_ () PI_ PI_ () R GPP_RX0P /GPIO Note: LK_PIE_TRVISP/N is 00MHZ non-ss E PI_ PI_ () *.K_ GPP_RX0N /GPIO W F PI_ Note: LK_PU_HLKP/N is 00MHZ SS GPP_RXP /GPIO PI_ () V H PI_ GPP_RXN /GPIO PI_ () Note: LK_PIE_VGP/N is 00MHZ SS V H PE_PWRG GPP_RXP /GPIO HUSON_MEMHOT# T W Note: GPP_LK(0:)P/N is 00MHZ SS capable GPP_RXN /GPIO W GPP_RXP 0/GPIO0 W E GPP_RXN /GPIO N E0# J E# N0 LK_LRN.V_KV R K/F_ E# F LK_LRN E# G0 FRME# K INT_LK_FH_SRP EVSEL# TP G0 L0 INT_LK_FH_SRN PIE_RLKP IRY# TP G F0 PIE_RLKN TRY# LK_P_P LK_P_P_R PR E0 () LK_P_P RP 0_PR R H LK_P_N LK_P_N_R ISP_LKP STOP# () LK_P_N T M ISP_LKN PERR# H SERR# H G ISP_LKP REQ0# H G ISP_LKN REQ#/GPIO0 F LK_PU_P LK_PU_P_R () LK_PU_P RP 0_PR REQ#/LK_REQ#/GPIO T M LK_PU_N LK_PU_N_R PU_LKP REQ#/LK_REQ#/GPIO T () LK_PU_N T PU_LKN GNT0# GNT#/GPO J0 SLT_GFX_LKP GNT#/S_LE/GPO K K SLT_GFX_LKN GNT#/LK_REQ#/GPIO T LKRUN# LKRUN# LKRUN# (,0) H H GPP_LK0P LOK# H GPP_LK0N F LK_PIE_WLNP INT_LK_PIE_WLNP INTE#/GPIO () LK_PIE_WLNP RP 0_PR J E LK_PIE_WLNN INT_LK_PIE_WLNN GPP_LKP INTF#/GPIO () LK_PIE_WLNN K GPP_LKN INTG#/GPIO INTH#/GPIO F R _ GPP_LKP PLK_TPM () F R _ GPP_LKN PLK_EUG () R _ LK_PIE_LNP INT_LK_PIE_LNP LK_PI_E (0) () LK_PIE_LNP RP 0_PR E LK_PIE_LNN INT_LK_PIE_LNN GPP_LKP LP_LK0_R LP_LK0 () LK_PIE_LNN E R0 _ GPP_LKN LPLK0 LP_LK0 () LP_LK_R R _ LP_LK LPLK LP_LK () M LP_L0 GPP_LKP L0 LP_L0 (,,0) M LP_L LP_L (,,0) G@0_PR GPP_LKN L LP_L LP_L (,,0) LK_PIE_GP INT_LK_PIE_GP LP_L () LK_PIE_GP RP L M LP_L (,,0) LK_PIE_GN INT_LK_PIE_GN GPP_LKP L LP_LFRME# () LK_PIE_GN M GPP_LKN LFRME# LP_LFRME# (,,0) LRQ#0 LRQ0# LRQ# T N E GPP_LKP LRQ#/LK_REQ#/GPIO T N E SERIRQ GPP_LKN SERIRQ/GPIO SERIRQ (,0) PI EXPRESS INTERFES LOK GENERTOR PI LKS PI INTERFE LP RT ircuitry(rt) V_RT 0MIL u/0v_ For EMI PLK_EUG LK_PI_E 0MIL VRT Net GPIO I/O Power Well PE_PWRG PE_GPIO0 PE_GPIO R GPIO GPIO GPIO 0/F_ GPU_PWRG GPU_RST# GPU_PWREN *p/0v_ *p/0v_ I O O.V.V.V *R00V-0 R0 0_ *R00V-0 T OS "0->" "0->" "0->" VRT_ 0MIL R K/F_ 0MIL T VPU N RT SOKET () LK_M_R M_X M_X R0 M/F_ 0 0p/0V_ R _ Y MHZ 0p/0V_ M_OS M_X M_X R R N R J GPP_LKP GPP_LKN GPP_LKP GPP_LKN M_M_M_OS M_X M_X PU S PLUS M_TIVE# PROHOT# PU_PG LT_STP# PU_RST# K_X K_X S_ORE_EN RTLK INTRUER_LERT# VT_RT_G G E E G F G G H F F E LLOW_LTSTP H_PROHOT# PU_PWRG PU_STOP# LT_RST# K_X K_X S_ORE_EN RT_LK INTRUER_LERT# V_RT 0MIL T T R R 0_ *0.u/0V_ *M/F_ 0.u/0V_ V_RT V_RT LLOW_LTSTP () H_PROHOT# (,0) PU_PWRG (,) LT_RST# (,) RT_LK () K_X R 0M_ K_X INTRUER_LERT# Left not connected (FH has 0-kohm internal pull-up to VT). USE GROUN GUR FOR K_X N K_X S_ORE_EN is necessary to connect enable pin of VPU/VPU regulator for S mode implementation Y.KHZ_0 0 p/0v_ p/0v_ G V_S *SHORT_P (,,,0) PLTRST# 0p/V_ R _ (0) E RST#_L _RST#_L R 0_ R *0_ U TSH0FU *0.u/0V RST#_R Quanta omputer Inc. PROJET : Size ocument Number Rev FH /(PI/PI/LK) Tuesday, January 0, 0 ate: Sheet of

9 (LG) 0 ST H/SS () () () () ST_TXP0 ST_TXN0 ST_RXN0 ST_RXP0 TP TP TP TP PLE ST OUPLING PS LOSE TO HUSON-M/M 0.0u/V_ 0.0u/V_ PLE ST_L RES VERY LOSE TO LL OF HUSON-M/M ST_TXP0_ ST_TXN0_ ST_TXP_ ST_TXN_ ST_RXN ST_RXP K M L0 N0 N L H0 J0 J H M K H J N L L N J H N L K M L N L L H H U ST_TX0P ST_TX0N ST_RX0N ST_RX0P ST_TXP ST_TXN ST_RXN ST_RXP ST_TXP ST_TXN ST_RXN ST_RXP ST_TXP ST_TXN ST_RXN ST_RXP ST_TXP ST_TXN ST_RXN ST_RXP ST_TXP ST_TXN ST_RXN ST_RXP N N N N N0 N HUSON-M SERIL T S R SPI ROM GE LN Part of S_LK/SLK_/GPIO S_M/SLO_/GPIO S_#/GPIO S_WP/GPIO S_T0/STI_/GPIO S_T/STO_/GPIO S_T/GPIO S_T/GPIO0 GE_OL GE_RS GE_MK GE_MIO GE_RXLK GE_RX GE_RX GE_RX GE_RX0 GE_RXTL/RXV GE_RXERR GE_TXLK GE_TX GE_TX GE_TX GE_TX0 GE_TXTL/TXEN GE_PHY_P GE_PHY_RST# GE_PHY_INTR SPI_I/GPIO SPI_O/GPIO SPI_LK/GPIO SPI_S#/GPIO ROM_RST#/SPI_WP#/GPIO VG_RE VG_GREEN VG_LUE L N J H K M H J W0 H F E G F G E W V V V T V L0 L M GE_PHY_INTR FH_SPI_SI FH_SPI_SO FH_SPI_LK FH_SPI_S0# FH_SPI_WP TP TP TP0 R 0K_ V_S FH_SPI_S0# FH_SPI_LK FH_SPI_SO FH_SPI_SI R R R R R R R R S@0_ TP S@0_ TP S@0_ TP S@0_ TP L@0_ SPI_S L@0_ SPI_SK L@0_ SPI_SO L@0_ SPI_SI V_S TP TP TP TP R R _ 0K S (0) _SK (0) _SO (0) _SI (0) SPI_S (0) SPI_SK (0) SPI_SO (0) SPI_SI (0) FH_SPI_SI_R *p/0v_ FH_SPI_WP U E# SK SI SO WP# V HOL# VSS WQVSSIG(SOI) V_S 0.u/0V_ R 0K_ SPI_HOL# ().V_V_ST R /F_ V R R K/F_ *0K/F_ ST_LRP ST_LRN ST_LE# J J F F N N ST_LRP ST_LRN ST_T#/GPIO VG VG_HSYN/GPO VG_VSYN/GPO VG S/GPO0 VG SL/GPO VG RSET UX_VG_H_P UX_VG_H_N M N0 M N K V V TP TP TP TP TP TP TP0.VSUS R *K/F_ V_S R *K/F_ V R *0K/F_ TP Integrated lock Mode: Leave unconnected. OR_I FH_O_EN FH_PROHOT#_ OR_I OR_I OR_I OR_I OR_I OR_I TEMPIN R 0K_ F G H M J K N L K K K M ST_X ST_X FNOUT0/GPIO FNOUT/GPIO FNOUT/GPIO FNIN0/GPIO FNIN/GPIO FNIN/GPIO TEMPIN0/GPIO TEMPIN/GPIO TEMPIN/GPIO TEMPIN/TLERT#/GPIO HW MONITOR VG MINLINK UXL ML_VG_L0P ML_VG_L0N ML_VG_LP ML_VG_LN ML_VG_LP ML_VG_LN ML_VG_LP ML_VG_LN ML_VG_HP/GPIO 0/GPIO /GPIO /STI_/GPIO /STO_/GPIO /SLO_/GPIO /SLK_/GPIO0 /GE_STT/GPIO /GE_LE/GPIO N N N N N U T T T T R R0 P P N M L N P P M M G H0 G L TP TP TP TP TP TP TP TP TP TP 0 MEM_PV MEM_PV _VIO _VR R R R R0 0K_ 0K_ 0K_ 0K_ T T0 V R00 R R R R R _VIO R0 *K/F_ LVS@0K_ OR_I 0K_ OR_I 0K_ OR_I 0K_ OR_I *0K_ OR_I *0K_ OR_I _VR R0 R R0 R R R R *K/F_ EP@0K_ *0K_ *0K_ *0K_ *0K_ *0K_ V_S R R R *0K_ 0K_ 0K_ OR_I OR_I OR_I R R R 0K_ *0K_ *0K_ OR_I OR I SETTING L OR_I For TP R () OR_I () OR_I () OR_I0 () OR_I 0K_ OR_I0 OR_I OR_I OR_I0 OR_I R0 *0K_ 0 ep 0 ELN LVS Synaptics Quanta omputer Inc. PROJET : Size ocument Number Rev FH /(ST/VG//SPI) Wednesday, January, 0 ate: Sheet of

10 (LG) 0 V V V_S V_V_US.V_S L PY00T-Y-N//0ohm_ L PY00T-Y-N//0ohm_ V_S V.u/.V_ L U@PY00T-Y-N//0ohm_ U@.u/.V_ L PY00T-Y-N//0ohm_.u/.V_.u/.V_ TRE WITH >=mil TRE WITH >=mil FH_VPL SSUS_S FH_VPL SUS_S L R 0_ U@0.u/0V_ u/0v_ PY00T-Y-N//0ohm_ EMI.V_S.V_S *0.u/0V_ *0.u/0V_ FH_V SSUS_S L R 0_ U@PY00T-Y-N//0ohm_ R 0_ R *U@0_.V_FH_R VPL_.V FH_VPL SSUS_S FH_VPL SUS_S 0.u/0V_ VQ--.V I/O power u/.v_.vsus 0u/.V_ 0.u/0V_ 0.u/0V_ L FH_VN US_S PY00T-Y-N//0ohm_.u/.V_ 0 0.u/0V_ L PY00T-Y-N//0ohm_ 0.u/0V_ FH_VPL PIE FH_VPL ST R TRE WITH >=0mil 0u/.V_ 0 u/0v_ *0_ LO_P *.u/.v_ FH_VR US_S TRE WITH >=mil m 0.u/0V_ 0u/.V_ FH_VN SSUS_S_R FH_VR SSUS_S 0m 0.u/0V_ V_V_US m m m m 0m u/0v_ m m m TRE WITH >=0mil 0m E 0 G H V U T L H G M 0 0 G H J K K M M0 N N0 M N M P M N P P N N P M PLE LL THE EOUPLING PS ON THIS SHEET LOSE TO S S POSSILE. V Y V V V U U T T U HUSON-M Part of VIO PIGP_ VIO PIGP_ VIO PIGP_ VIO PIGP_ VIO PIGP_ VIO PIGP_ VIO PIGP_ VIO PIGP_ VIO PIGP_ VIO PIGP_0 VPL SYS VPL VPL ML VN VPL SSUS_S VPL US_S VPL PIE VPL ST LO_P VPL VN ML_ VN ML_ VN ML_ VN ML_ VIO GE_S VR GE_S_ VR GE_S_ VIO_GE_S_ VIO_GE_S_ VN US_S_ VN US_S_ VN US_S_ VN US_S_ VN US_S_ VN US_S_ VN US_S_ VN US_S_ VN US_S_ VN US_S_0 VN US_S_ VN US_S_ VN US_S_ VN US_S_ VR US_S_ VR US_S_ VN SSUS_S_ VN SSUS_S_ VN SSUS_S_ VN SSUS_S_ VN SSUS_S_ VR SSUS_S_ VR SSUS_S_ VR SSUS_S_ VR SSUS_S_ PI/GPIO I/O MIN GE LINK PI LN EXPRESS LKGEN I/O SERIL T US ORE S0.V_S I/O US SS VR VR VR VR VR VR VR VR VR VN LK_ VN LK_ VN LK_ VN LK_ VN LK_ VN LK_ VN LK_ VN LK_ VN PIE_ VN PIE_ VN PIE_ VN PIE_ VN PIE_ VN PIE_ VN PIE_ VN PIE_ VN ST_ VN ST_ VN ST_ VN ST_ VN ST_ VN ST_ VN ST_ VN ST_ VN ST_ VN ST_0 VIO S_ VIO S_ VIO S_ VIO S_ VIO S_ VIO S_ VIO S_ VIO S_ VXL S VR S_ VR S_ VPL SYS_S VN HWM_S VIO_Z_S T T T0 U U V V V0 Y H J K L M N N P Y E F G Y m 0m 0m m m N L M V V Y Y W G N0 M0 J M m S_.--.v standby power TRE WITH >=0mil VIO S VXL_.V m VR_.V TRE WITH >=mil 0m m m Trace width >=0 mil TRE WITH >=00mil 0.u/0V_ TRE WITH >=0mil u/0v_ TRE WITH >=00mil 0.u/0V_ TRE WITH >=00mil 0.u/0V_ VPL_.V VN_.V_HWM VIO_Z 0 0.u/0V_ 0 u/0v_ 0.u/0V_ 0.u/0V_ u/0v_ V-- S/ ORE power u/0v_.v_v_fh_r.v_kv 0.u/0V_.V_PIE_VR u/0v_.v_v_st u/0v_ u/0v_.u/.v_ S_.V--.V standby power u/0v_ 00 u/0v_ 0 u/0v_ 0.u/0V_ 0 u/0v_ u/0v_ R 0_ 0u/.V_ u/.v_ KV_.V-- Internal clock Generator I/O power.v L.V H0KF-T/./0ohm_ PIE_VR--PIE I/O power L.V H0KF-T/./0ohm_ 0 u/.v_ V_ST--ST phy power L.V H0KF-T/./0ohm_ u/.v_ R 0_ 0u/.V_.V_S S plus mode R 0_ *0.u/0V_.u/.V_ V_S L V_S PY00T-Y-N//0ohm_ E E E E F F F F F F F F F F G G G H H H J J J0 J J J K K K K L L L L L L M M M M N N N N N P P P0 P P P R R R R T T T U VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ HUSON-M Part of N VSSN_HWM VSSPL_ VSSN_ K VSSXL VSSNQ_ VSSIO_ H VSSPL_SYS EFUSE GROUN VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_00 VSS_0 VSS_0 VSS_0 VSS_0 VSS_0 VSS_0 VSS_0 VSS_0 VSS_0 VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ T T U U U U0 U U0 U V V V W W W W Y Y Y 0 E E E E F F F F G0 G H H H H H H H H J J J K K L M M N N N N T L K N R R0 *U@0_ U@u/0V_ U@0.u/0V_ 0 U@0.u/0V_ U@u/0V_ 0 R U@0u/.V_ U@0.u/0V_ *U@0_ U@u/0V_ U@0.u/0V_ POWER V_S R 0_ VIO_Z 0.u/.V_.V_S.V VPL_.V L *U@PY00T-Y-N//0ohm_ L U@PY00T-Y-N//0ohm_.u/.V_ *0.u/0V_ V_S VN_.V_HWM L PY00T-Y-N//0ohm_ 0.u/0V_.u/.V_ V 0.u/0V_ VPL_.V L PY00T-Y-N//0ohm_.u/.V_ 0.u/0V_ Quanta omputer Inc. PROJET : Size ocument Number Rev FH /(POWER) Tuesday, January 0, 0 ate: Sheet of 0

11 (LG) STRPS PINS V V V V_S V_S V_S V_S R 0K_ R *0K_ R0 *0K_ R *0K_ R 0K_ R *0K_ R 0K_ OVERLP OMMON PS WHERE POSSILE FOR UL-OP RESISTORS. () PI_LK PI_LK () PI_LK PI_LK () PI_LK PI_LK () LP_LK0 () LP_LK () E_PWM LP_LK0 LP_LK E_PWM System PWR_OK V_S () RT_LK RT_LK *0.u/0V_ R *0K_ R 0K_ R0 0K_ R 0K_ R *0K_ R.K_ R *.K_ E_PWM--> SPI ROM:.-KΩ % pull-down LP ROM: Pull-up to.v_s. External pull-up resistor is not required as FH has integrated 0-KΩ pull-up to.v_s. () FH_PWRG FH_PWRG U TSH0FU PWROK_E R0 00K_ PU_OREPG (,) PWROK_E (,0) Remove PI_LK function REQUIRE STRPS PULL HIGH PI_LK LLOW PIE Gen EFULT PI_LK PI_LK USE EUG STRP PI_LK non_fusion LOK MOE LP_LK0 E ENLE LP_LK LKGEN ENLE EFULT E_PWM LP ROM RT_LK S PLUS MOE ISLE EFULT FH PWRG KT PULL LOW FORE PIE Gen IGNORE EUG STRP EFULT FUSION LOK MOE EFULT E ISLE EFULT LKGEN ISLE SPI ROM EFULT S PLUS MOE ENLE EUG STRPS FH HS K INTERNL PU FOR PI_[:] () PI_ PI_ () () () () PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PULL HIGH PI_ USE PI PLL PI_ ISLE IL UTORUN PI_ USE F PLL PI_ USE EFULT PIE STRPS PI_ ISLE PI MEM OOT EFULT EFULT EFULT EFULT EFULT R *.K_ R0 *.K_ R *.K_ R *.K_ R *.K_ PULL LOW YPSS PI PLL ENLE IL UTORUN YPSS F PLL USE EEPROM PIE STRPS ENLE PI MEM OOT Quanta omputer Inc. PROJET : Size ocument Number Rev FH /(STRP & PWRG) Tuesday, January 0, 0 ate: Sheet of

12 HLL I (HSR) VPU R R 0_ *00K_ LV_ LV Maintenance L and POWER Service SWITH Guide,Service (LS) Manual,Motherboard Schematics MER for POWER Laptop/notebook () R 0_ Irush=. VG=0. <EMI> *p/0v_ R *00_ R0 0_ () () USP- USP L USP-_R USP_R V R 0 POWER 0. _POWER.u/0V_ *VPORT_ LI# *VPORT_ 0.u/0V_ *.u/.v_ 0.u/0V_ 0.0u/V_.u/0V_ *MM000GE/00m/0ohm R 0_ 000p/0V_ *0.u/0V_ V R 0K_ RT(RT) ISPON Q TEU u/.v_ V R 0K_ L# MR PXH I-TRG R00V-0 R Q N00W 00K_ LI# (0) INT_LVS_LON () E_FPK# (0) () INT_LVS_IGON u/.v_ R 00K_ V R 0_ U IN OUT IN ON/OFF I(P) GTU L MOULE (LS) () () () () () () () () TXLLKOUT_EPTX TXLLKOUT-_EPTX- TXLOUT_EPTX TXLOUT-_EPTX- TXLOUT0_EPTX TXLOUT0-_EPTX- TXLOUT_EPTX0 TXLOUT-_EPTX0- TXLOUT-_EPTX0- TXLOUT_EPTX0 0 R L0 EP@0.u/0V_ EP@0.u/0V_ LVS@0_ TXLOUT-_EPTX0-_ TXLOUT_EPTX0_ TXLLKOUT_EPTX_N TXLLKOUT-_EPTX-_N *LVS@MM000GE/00m/0ohm R LVS@0_ R TXLOUT0_EPTX_N TXLOUT0-_EPTX-_N *LVS@MM000GE/00m/0ohm R LVS@0_ R0 L L LVS@0_ LVS@0_ TXLOUT_EPTX_N TXLOUT-_EPTX-_N *LVS@MM000GE/00m/0ohm R LVS@0_ R L LVS@0_ TXLOUT_EPTX0_R TXLOUT-_EPTX0-_R *LVS@MM000GE/00m/0ohm R LVS@0_ R L EP@0_ (0) (0) 0m*pcs=0m R 0_ PNEL_OLOR PNEL_ENG TXLOUT-_EPTX0-_N TXLOUT_EPTX0_N *EP@MM000GE/00m/0ohm R EP@0_ 0.u/V_ R 0_ R 0_ V LV _POWER 0.u/0V_ L_LK_EPUX_R L_T_EPUX-_R I_HP L_VJ ISPON PNEL_OLOR_R PNEL_ENG_R V_LIGHT TXLLKOUT_EPTX_N TXLLKOUT-_EPTX-_N TXLOUT0_EPTX_N TXLOUT0-_EPTX-_N TXLOUT_EPTX_N TXLOUT-_EPTX-_N TXLOUT_EPTX0_R TXLOUT-_EPTX0-_R TXLOUT-_EPTX0-_N TXLOUT_EPTX0_N L_T_EPUX-_N L_LK_EPUX_N USP-_R USP_R N G_ G_0 G_ G_ G_ L ONN V F 0 RSX0M-0 SM0P0TFT <Layout note> PLE inductances 0 EGREE FROM EH OTHER 0.u/0V_ RTV L_T_EPUX- L_LK_EPUX EP@0.u/0V_ EP@0.u/0V_ L_T_EPUX-_ L_LK_EPUX_ R EP@0_ L L_T_EPUX-_N L_LK_EPUX_N *EP@MM000GE/00m/0ohm R EP@0_ R LVS@0_ () INT_RT_RE () INT_RT_GRE () INT_RT_LU R R R 0/F_ 0/F_ 0/F_ 0 *0p/0V_ L L L *0p/0V_ *0p/0V_ PY00T-0Y-N//ohm_ PY00T-0Y-N//ohm_ PY00T-0Y-N//ohm_.p/0V_.p/0V_ RT_R RT_G RT_.p/0V_ 0 N0 RT_ RT_S RTHSYN RTVSYN RT_SL RT ONN T () L_LK_EPUX () L_T_EPUX- ep (LS) L L_LK_EPUX_R L_T_EPUX-_R *LVS@MM000GE/00m/0ohm R LVS@0_ V V () INT_LVS_PWM (0) ONTRST R 0_ R *0_ *0.u/0V_ L_VJ R EP@00K_ R0 *LVS@00K_ V V 0.u/0V_ 0.u/V_ 0.u/0V_ RTV RT_YP RT_R RT_G RT_ U <Layout note> lose to ONN V_SYN V_ YP V_VIEO VIEO_ VIEO_ VIEO_ SYN_OUT SYN_OUT SYN_IN SYN_IN _IN _IN _OUT _OUT 0 RT_VSYN RT_HSYN RT_SL RT_S R0 R0 INT_RT_VSYN () INT_RT_HSYN () /F_ /F_ VSYN_R HSYN_R R R R R.K_.K_.K_.K_ L 0_ L 0_ V INT_LK () INT_T () RTV RTVSYN RTHSYN *0p/0V_ *00p/0V_ *00p/0V_ *00p/0V_ *00p/0V_ RTV RTVSYN RTHSYN RT_SL RT_S L_T_EPUX-_ L_LK_EPUX_ R EP@00K_ () INT_ePI_HP R EP@0_ I_HP R EP@00K_ IP_Rout=0ohm nd source: L0000W0 (M M00-0QR Rout=ohm) Quanta omputer Inc. PROJET : Size ocument Number Rev RT/LVS/EP Tuesday, January 0, 0 ate: Sheet of

13 HMI (HM) V Q N00K R *00K/F_ HMI_PL_MOS lose to HMI onnector EMI reserve for HMI TX_HMI R *00/F_ TX_HMI- TX_HMI R0 *00/F_ TX_HMI- TX0_HMI R *00/F_ TX0_HMI- TX_HMI R *00/F_ TX_HMI- V () () () () () () () () TX_HMI () HMI_LK F () HMI_T SM0P0TFT V_HMI_ 0 0.u/.V_ *0.u/0V_ RSX0M-0 TX_HMI HMI_LK HMI_T V_HMI HMI_HP R 00K_ TX_HMI- TX_HMI TX0_HMI- TX_HMI TX_HMI- TX0_HMI TX_HMI- R /F_ TX_HMI R0 R R /F_ /F_ /F_ TX_HMI- TX_HMI TX_HMI- R /F_ TX0_HMI R /F_ TX0_HMI- R /F_ TX_HMI R /F_ TX_HMI- TX_HMI- TX_HMI TX_HMI- TX0_HMI TX0_HMI- TX_HMI TX_HMI- N SHELL 0 Shield - Shield Shield 0-0 K K Shield K- E Remote N LK T V HP ET SHELL HMI connector 000/ EMI SVO I ontrol (HM) V V R 0K_ R 0K_ V V H0H-0PT H0H-0PT R HMI_LK K/F_ R HMI_T K/F_ () INT_HMI_HP HMI_HP Q N00W HMI_HP_E# (0) Quanta omputer Inc. PROJET : Size ocument Number Rev HMI ate: Tuesday, January 0, 0 Sheet of

14 LN (LN) V_S R0 0_ V_LN V0 R0 0_ EV0 lose to I 0 0.u/0V_ 0 0.u/0V_ 0 0.u/0V_ 0 *.u/0v/ lose To I 0 0 lose To I Pin. 0 0 u/0v_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ TRL <000> hange from P to P by vendor's measure report. lose To I Pin. p/0v_ () PIE_REQ_LN# Pull-Up at LK Gen side U HV MIP0 MIN0 MIP MIN N V LKREQPIN MLKX 0 RSET TRL KXTL KXTL LEPIN/SPIS V GPOUTPIN EESKPIN/LE/TLK/SPISK LN_TLE# GPO R0 LN_LINKLE# RTL0T-V-G EEIPIN/TI/SPISI/S EEOPIN/LE/SPISO EESPIN/TS/SL V LNWKEPIN 0 V ISOLTEPIN PERSTPIN V_LN EEI/S LE/EEO EES/SL V0 PIE_WKE# V_LN ISOLTE# LKREQ_LN#_R R PIE_WKE# EEI/S EES/SL PIE_WKE# (,) V Int. PU in S V_LN HSIP HSIN REFLK_P REFLK_N VTX HSOP HSON TX PIE_RST# (,) 0 0 R0 0_ 0 0.u/0V_ Y MHz-LN p/0v_ R 0_ R V_LN TX0P TX0N TXP TXN V0 LKREQ_LN#_R MLKX TRL.K/F_ RSET T K_ T T R0 R K_ K_ R00 R0 R0 *0K_ *0K_ 0K_ 0K_ 00 *.u/0v/ R 0_ () PIE_TXP0_LN () PIE_TXN0_LN () LK_PIE_LNP () LK_PIE_LNN () PIE_RXP0_LN () PIE_RXN0_LN 0.u/0V_ 0.u/0V_ EV0 PIE_RXP0_LN_ PIE_RXN0_LN_ TRNSFORMER (LN) For Rural RJ onnector (LN) TX0P TX0N TXP TXN R 0_ R 0_ R0 0_ R 0_ TX0P_R TX0N_R TXP_R TXN_R For Rural, use /F_ (S-00F) For Normal, use 0/J_ (S0000J) U *ULMPT.TT TXN_R TXP_R TX0N_R TX0P_R U X-TX0P X-TX0N X-TXP X-TXN For Rural, stuff 0/J_ (S0000J) For Normal, unstuff 0/J_ (S0000J) X-TXN X-TXP TERM0 X-TX0N X-TX0P R U0 *ULMPT.TT *0_ TERM X-TXN TERM X-TXP X-TX0N X-TX0P T- T T N N T R- R TX- 0 TX T N N T RX- RX N N/- N/ RX-/- N/- N/ RX/ TX-/0-0 TX/0 RJ-ONN *0p/0V_ *0p/0V_ 0 *0p/0V_ *0p/0V_ 0.0u/V_ The value should be 0.0uF-0.uF NS00 LF_othhand R0 /F_ R /F_ *P00SLRP_ Reserve for EMI request TERM 000p/KV_0 Quanta omputer Inc. PROJET : Size ocument Number Rev LN RTL0T-V-G ate: Tuesday, January 0, 0 Sheet of

15 Mini ard (MP) (0) T_POWERON# (,,,0) PLTRST# () PLK_EUG () () () () PIE_TXP PIE_TXN PIE_RXP PIE_RXN R 0_ R0 0_ R0 0_ V_Mini_V N0 Reserved Reserved Reserved Reserved.Vaux.Vaux PETp0 PETn0 PERp0 PERn0 UIM_ UIM_ UIM_VPP R 0_ LP_LFRME# (,,0) () LK_PIE_WLNP R0 0_ REFLK UIM_RESET LP_L (,,0) () LK_PIE_WLNN REFLK- UIM_LK R 0_ LP_L (,,0) LP_L (,,0) LKREQ_MP#_Q UIM_T 0 R 0_ LKREQ# UIM_PWR R 0_ LP_L0 (,,0) Reserved.V MINI_WKE# Reserved WKE#.V.V 0.V LE_WPN# LE_WLN# LE_WWN# 0 US_ US_- SM_T SM_LK 0.V.Vaux PERST# 0 W_ISLE# V_Mini_V.V_Mini_V WL_SMT WL_SMLK PIE_RST#_R RF_EN WLN_LE# WIMX_LE# R 0_ USP () USP- () V_Mini_V PIE_RST# (,) RF_EN (0) WLN ONN R 0_ R.K_ RF_LE_ON Q N00K Turn off WLN LE when G module is on R 0_ WLN_LE# () G_MINI_LE# (,,) (,,) PT_SM PLK_SM V_Mini_V V_Mini_V R 0_ R 0_ WL_SMT WL_SMLK (0) IO_LNPWR# R V R 0_ V_Mini_V 0. *0u/.V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_.V R *0_.V_Mini_V 0. *000p/0V_ *0.u/0V_ *0u/.V_ FH: V_S (,) PIE_WKE# E: VPU (0) WLN_WKE# FH: V () PIE_REQ_WLN# VPU R Q MINI_WKE# LKREQ_MP#_Q R 0_ Mini ard (MN) () () () () PIE_TXP PIE_TXN PIE_RXP PIE_RXN T V_Mini_V N Reserved Reserved Reserved Reserved.Vaux.Vaux PETp0 PETn0 PERp0 PERn0 UIM_ UIM_.V 0.V LE_WPN# LE_WLN# LE_WWN# 0 US_ US_- SM_T SM_LK 0.V.Vaux PERST# 0 W_ISLE# <0//(E)> hange from 0k to 00k to reduce leakage V_Mini_V.V_Mini_V WLN_LE# G_MINI_LE# USP_R USP-_R G_SMT G_SMLK PIE_RST#_R R G_EN (0) *G@0_ no matter have G function or not, need to stuff this PU. PIE_RST# V_Mini_V R 00K_ G_MINI_LE# () VSUS R R V R R.V R0 G@0_ G@0_ *G@0_ *G@0_ V_Mini_V *G@0_ 0 G@0u/.V_.V_Mini_V Peak:. Normal:. G@0.u/0V_ 0. *G@000p/0V_ 0 G@0.u/0V_ *G@0.u/0V_ G@0.u/0V_ G@0.u/0V_ nd source: HK0 G@0.u/.V_ 0 G@0p/0V_ V_Mini_V Q PT_SM PLK_SM *G@N00W R0 *G@0_ R00 *G@0_ RN *G@.K_PR G_SMT G_SMLK () () () LK_PIE_GP LK_PIE_GN PIE_REQ_G# T REFLK REFLK- LKREQ# Reserved Reserved WKE# UIM_VPP UIM_RESET UIM_LK UIM_T 0 UIM_PWR.V.V UIM_VPP UIM_RST UIM_LK UIM_T UIM_PWR G@G ONN R G@0_ USP_R USP-_R L0 USP () USP- () *G@MM000GE/00m/0ohm R G@0_ R0 0 *G@00_ *G@p/0V_ MultiMedia SIM (MN) <Layout Notes> Keep USIM signals max length within 000mils. UIM_PWR G@p/0V_ <0000()_Qualcomm design guide> Place 0.uF near connector's V pin () () USP- USP UIM_LK 0 JSIM LK() -() () T G@SIM-ONN () V() VPP() RST() T() Max:.m (Option) UIM_T G@0p/0V_ UIM_PWR UIM_VPP UIM_RST UIM_LK G@0p/0V_ UIM_T UIM_RST G@p/0V_ UIM_VPP *G@p/0V_ <000> Un-stuff since EM0W doesn't use Vpp UIM_RST UIM_LK U H H VN VP H H *G@M-0SO UIM_VPP UIM_T V UIM_PWR G@u/.V_ G@0.u/0V_ Quanta omputer Inc. PROJET : Size ocument Number Rev Mini-ard/WL/G/SIM Tuesday, January 0, 0 ate: Sheet of

16 odec LX (O) HPR Maintenance and HPR Service () Guide,Service Manual,Motherboard Schematics ERPHONE for Laptop/notebook (MP) HPL HPL () MI-VREFO O Place near codec MI-VREFO MI_R.u/.V_ R0.K_ 0 INT_MI-VREFO 0u/.V_ O MI_L.u/.V_ R K_ OMO_MI OMO_MI () V.u/.V_.u/.V_ O.u/.V_ 0.u/0V_ *0u/.V_ Place next to pin V <000> dd k P by FE suggestion for discharing MI-J# R K/F_ O O 0 *V/V/00P_ 0u/.V_ O Place next to pin 0 0.u/0V_ NLOG Spilt by O U VSS V P N PVEE HP-OUT-R HP-OUT-L MI-VREFO-L MI-VREFO-R 0 MI-VREFO LO-P VREF VSS V LINE-R LINE-L 0.u/0V_ O Place next to pin 0u/.V_ Q SK0 R *0u/.V_ K/F_ V V.u/.V_.u/.V_ R 0_ 0 0.u/0V_ R 0_ 0.u/0V_ VPV Place next to pin.u/.v_.u/.v_ VPV 0.u/0V_ 0.u/0V_ Place next to pin Spilt by P Spilt by L_SPK L_SPK- R_SPK- R_SPK EP# 0 PV SPK-L PVSS PVSS SPK-L- SPK-R- SPK-R PV V LX-V-GR GPIO0/MI-T SPIFO/EP SPIFO P GPIO/MI-LK P# ST-OUT IT-LK VSS ST-IN V-IO SYN 0 RESET# PEEP MI-R MI-L MONO-OUT JREF Sense- MI-R MI-L LINE-R LINE-L 0 Sense IGITL SENSE MI_R MI_L LIN_INT_R LIN_INT_L NLOG LX-V-GR Placement near udio odec SENSE R R R u/0v_ u/0v_ 0K/F_ 0K/F_.K/F_ O MI-J# MI_INT 0 HP_J# O 000p/0V_ HP_J# () PEEP dont coupling any signals if possible / separate PEEP to igital from Realtek suggestion <00> dd n P to for amic noise depressing by FE Vic suggestion <000> dd E PWM control for beep sound volumn control O V R 0_ Z_V PEEP_ 0.Vrms u/0v_ EEP_ R R K_ K_ PEEP_E (0) SPKR () 0.u/0V_.u/.V_ 00p/0V_ R.K_ If either H device io power use.v, all device IO power change to.v Place next to pin T T MI_T MI_LK Z_V_R R 0_ Z_V P# 0V Power down lass SPK amplifier V : Power up lass SPK amplifier Z_SIN_R R _ Z_RESET#_UIO () Z_SYN_UIO () Z_SIN0 () 0.u/0V_.u/.V_ Place next to pin Z_SOUT_UIO () *p/0v_ Z_ITLK_UIO () Power (O) Internal Speaker (MP) (O) Internal nalog MI (MP) emodulation Filter V Place close to odec V IGITL L 0_ NLOG <00> For analog mic ES protection using <00> hange to 0K by codec FE suggestion 0mil for each signal R *0_ R 0_ INT_MI-VREFO R0 0K_ Mute (O) V <00> hange to 0K by codec FE suggestion R_SPK R0 0_ R_SPK- R 0_ L_SPK- R 0_ L_SPK R 0_ *p/0v_ *p/0v_ N R_SPK_ R_SPK-_ L_SPK-_ R *0_ L_SPK_ R *0_ R *0_ R0 *0_ R-L-SPEKERS R *0_ R *0_ *p/0v_ *p/0v_ R *0_ R *0_ MI_INT R K_ *P-0V_ O MI_INT_R MI_INT_R () R R0 0_ R 0_ R 0_ P# *0K_ R00V-0 Z_RESET#_UIO 000p/0V_ 000p/0V_ R00V-0 EP# R00V-0 MP_MUTE# (0) O Quanta omputer Inc. PROJET : Size ocument Number Rev LX / MP / SPK Tuesday, January 0, 0 ate: Sheet of

17 ." ST H (H) Power Sequence onnector(pu) N RXP RXN TXN TXP H ONN.V.V.V 0 V V V RSV V 0 V V ST_RXN0_ ST_RXP0_.VST 0 *0u/.V_ 0.u/0V_ 0.u/0V_ V_H 0.0u/V_ 0.0u/V_ *0.u/0V_ 0u/.V_ *0u/.V_X. ST_TXP0 () ST_TXN0 () ST_RXN0 () ST_RXP0 () R R 0_ *0_ V V (0) NSWON# (,0) NSWON# (,0) SUS# (0,,,) MINON (0) HWPG (,0) PWROK_E (,) PU_PWRG (,) LT_RST# NSWON# S_ON RESERVE RESERVE RESERVE PH_RSMRST# NSWON# SUS# 0 SUS# 0 N *ON0_EUG SUSON MINON RESERVE RESERVE RESERVE RESERVE RESERVE RESERVE RESERVE HWPG 0 S_ON (0,,,) PH_RSMRST# (,0) SUS# (,0) SUSON (0,,) VRON (0,) PU_OREPG (,) _RST#_R () VRON RESERVE PU_OREPG PWROK_E RESERVE PU_PWRG RESERVE LT_RST# _RST#_R RESERVE LE (UIF) Stitching ap(em) N 0 V_S VPU V <00> In S and battery only mode, E will turn off PWRLE#/SUSLE# while E is idle. R0 _ PWRLE# (0) E *0.u/0V_ R 0/F_ SUSLE# (0) R _ TLE0# (0) R 0/F_ TLE# (0) R G@0/F_ G_MINI_LE# () R 0_ WLN_LE# () E *0.u/V_ E *0.u/V_ VORE E *0.u/0V_ VPU V E *0.u/0V_ VPU LE M/ VORE E *0.u/0V_ POWER LE(UIF) PWR indicator V LE LE_LUE_TOP R _ Quanta omputer Inc. PROJET : Size ocument Number Rev ST H/LE/SW ate: Tuesday, January 0, 0 Sheet of

18 US Left (US) VPU (0) 0 u/.v_ USON# U I(P)GEPU IN OUT IN OUT OUT EN O# VUS_ O_0# () <Layout note> lose to ONN 0u/.V_X. 0.u/0V_ US.0 onnector VPU R *0K_ GEPU: Enable: Low ctive /. Follow ZH () () *p/0v_ R () USP0- () USP0 US_RXP0 US_RXN0 *00_ R R 0_ L *MM000GE/00m/0ohm R 0_ RP U@0_ US_RXP0_R US_RXN0_R *V/0V/0.P_ *V/0V/0.P_ USP0-_N USP0_N US_RXN0_R US_RXP0_R US_TXN0_R US_TXP0_R N US.0 ONN VUS - SSRX- SSRX SSTX- SSTX 0 0 *U@HMI0FSF-00T0/0ohm/00m R U@0_ () () US_TXP0 US_TXN0 R U@0_ RP US_TXP0 U@0.u/0V_ US_TXP0_ US_TXP0_R US_TXN0 U@0.u/0V_ US_TXN0_ US_TXN0_R US.0 connector P/N:?? *U@HMI0FSF-00T0/0ohm/00m R U@0_ IO / (UIF) HOLE(OTH) V VPU 0.u/0V_ 0.u/0V_ N HOLE *HG-P HOLE *HG-P HOLE *HG-P HOLE *HG-P HOLE *HG-P HOLE *HG-P HOLE *HG-P / US Port / US Port ard Reader () 0_ET_R () /#_R () USP0- () USP0 () USP- () USP () USP- () USP () LK_M_R (,,,0) PLTRST# () O_# () OMO_MI () HP_J# () HPL () HPR () MI_INT_R VPU V R 0_ LK_M_R_R *0p/0V_ USON# O O O O O O O HOLE *H-IP HOLE *H-N HOLE0 *H-IP HOLE *H-IP HOLE *O-- HOLE *H-0P ONN P *SP-IR P *SP-IR P *SP-IR POWER M/ () _R N Power conn Quanta omputer Inc. PROJET : Size ocument Number Rev US Port/ Tuesday, January 0, 0 ate: Sheet of

19 KEYOR (K) VPU PU FN TRL(THM) N 0 0 MX MX MX MY0 MY MY MX MY MY MY MY MY MY MX MY MX MX MY0 MY MX0 MY MY MY MY MX (0) MX (0) MX (0) MY0 (0) MY (0) MY (0) MX (0) MY (0) MY (0) MY (0) MY (0) MY (0) MY (0) MX (0) MY (0) MX (0) MX (0) MY0 (0) MY (0) MX0 (0) MY (0) MY (0) MY (0) MY (0) RP 0 MX MX MX MX 0K_0PR <EMI> MX MX MX MY0 MY MY MX MY MY MY MY MY MY MX MY MX MX MY0 MY MX0 MY MY MY MY MX MX MX MX0 P *0P_PR P *0P_PR P *0P_PR P *0P_PR P *0P_PR P *0P_PR For EMI FN_PWM_N FNSIG *0p/0V_ *0p/0V_ R () THERM_LERT# PUFN# (0) PUFN# E PWM SIGNL *0_ V V V R 0K_ Q METR0-G R 0K_ R 0K_ V R 0_ FNSIG (0) V_FNV FNSIG FN_PWM_N 0.u/0V_ N FN ONN K ONN TOUH P (TP) TPM (TPM) (0) (0) TPLK TPT R 0K_ (,,) PT_SM (,,) PLK_SM () SMLERT# () OR_I TPLK_N TPT_N V_TP (,0) LKRUN# (,,,0) PLTRST# V_S V V 0mil R 0K_ R 0_ R 0_ *0p/0V_ *0p/0V_ V R 0_ 0.u/0V_ R 0_ R 0_ N 0 (,0) SERIRQ () LPP# (,,0) LP_L0 (,,0) LP_L (,,0) LP_LFRME# () PLK_TPM (,,0) LP_L (,,0) LP_L R0 R0 *0_ *0_ R 0_ *0p/0V_ R 0_ SERIRQ_R LPP#_R *0.u/0V_ PLK_TPM_ N 0 0 TPM_ON TP/ ONN Quanta omputer Inc. PROJET : Size ocument Number Rev K/T/TP/LE/Power onnector ate: Tuesday, January 0, 0 Sheet of

20 E(K) VPU R0._ LK_PI_E R0 *_ 0 *0p/0V_ L VPU_E.u/.V_ PY00T-0Y-N//ohm_ 0.0(0mils) 0.u/0V_ *0.u/0V_ (,,) LP_LFRME# (,,) LP_L0 (,,) LP_L (,,) LP_L (,,) LP_L () LK_PI_E (,) () 0.u/0V_ LKRUN# SIO_0GTE 0mil *0.u/0V_ E V E VPU SPI PU(K) 0.u/0V_ 0.u/0V_ U LFRME L0 L L L LLK 0u/.V_ V V V V V GPIO/LKRUN GPIO/G0 V 0 / / R 0_ V GPIO0/0 GPIO/ GPIO/ GPIO/ GPIO/0 GPI/ GPI/ u/.V_ 0 0.u/0V_ TP TP TP 0u/.V_ 0.0u/V_ R IM TEMP_MT () WLN_WKE# () IM () E_WLN_WKE# () _S SPI_S R R 0K_ 0K_ V_S (,,,) PLTRST# () E RST#_L R0 0_ () () () () () (,) () () () () () () () () () SIO_RIN# SIO_EXT_SI# E_FPK# MP_MUTE# RF_EN SERIRQ SIO_EXT_SMI# MX0 MX MX MX MX MX MX MX () MY0 () MY () MY () MY () MY () MY () MY () MY () MY () MY () MY0 () MY () MY () MY () MY () MY () PNEL_OLOR () PNEL_ENG PNEL_OLOR PNEL_ENG KRST/GPIO GPIO0/T ESI/GPIO LP GPIO0 GPIO0 GPIO/LRQ GPIO0 GPIO0 0 GPIO0/LPP GPIO0/IOX_OUT/RTS GPIO0 LREST GPIO 0 GPIO0 GPIO/PWUREQ GPIO/TS 0 GPIO SERIRQ GPIO/SL/TK 0 GPIO/S/TMS GPIO/SMI GPIO/TI GPIO GPO/SL GPIO0/PSLK/TO KSIN0 GPIO KSIN GPIO/PST/RY KSIN GPIO/S KSIN GPIO0 KSIN GPIO KSIN GPIO KSIN GPIO/SPI_SK KSIN GPO/SHM GPIO KSOUT0/JENK GPIO 0 KSOUT/TK GPO/IOX_LSH/TEST KSOUT/TMS GPO/IOX_SLK/XORTR 0 KSOUT/TI GPIO KSOUT/JEN0 K KSOUT/TO KSOUT/RY GPIO/T KSOUT GPIO0/T/IOX_IN_IO KSOUT GPIO/T KSOUT/SP_VIS KSOUT0/P0_LK TIMER GPIO/_PWM KSOUT/P0_T GPIO/_PWM KSOUT/GPIO GPIO/_PWM KSOUT/GPIO GPIO/_PWM KSOUT/GPIO GPIO/E_PWM KSOUT/GPIO/XOR_OUT GPIO0/F_PWM/RI GPIO0/KSOUT GPIO/G_PWM GPIO/KSOUT GPIO/H_PWM/SOUT _EN NSWON# HWPG L_LERT# PWROK_E o not use it RTRST#_E SUSLE# TP TP TP TP TP TP TP TP TP TP R 0_ IN () _S () NSWON# () LI# () MINON (,,,) _EN () VRON (,) SUS# (,) /# () S_ON (,,,) HMI_HP_E# () SUS# (,) PWROK_E (,) PH_RSMRST# (,) _SK () G_EN () _SI () NSWON# (,) USON# () SUSON (,,) FNSIG () ONTRST () PEEP_E () PWRLE# () TLE0# () PUFN# () SUSLE# () _SO () TLE# () SM US PU(K) PROHOT_E R 00K_ MLK MT PU_SI_E PU_SI_E Q N00K R R R R R0 0_ 0K_ 0K_ *0K_ *0K_ VPU V V_S H_PROHOT# (,) (,) MLK (,) MT () PU_SI_E () PU_SI_E TP TP MLK MT PU_SI_E PU_SI_E 0 0 GPIO/SL GPIO/S GPIO/SL GPIO/S GPIO/SL GPIO/S SM IR GPIO/IRRXM/SIN_R GPIO/SIN/IRRXL GPIO/IRRXM/TRST GPO/SOUT_R/TRIST PROHOT_E TP0 TP IO_LNPWR# () PH_RSMRST# R *.K_ () V_EN R0 *0_ () () () TPLK TPT T_POWERON# V_EN_R 0 GPIO/PSLK GPIO/PST GPIO/PSLK GPIOPST PS/ FIU F_SI/F_SIO F_SO/F_SIO0 F_S0 F_SK 0 SPI_SI_UR SPI_SO_UR_R SPI_S0#_UR SPI_SK_UR_R R 0_ R 00K/F_ R0 _ R _ R _ SPI_SI () SPI_SO () SPI_S () SPI_SK () TP0 TP O_EN GPIO00/KLKIN VTT PEI GPIO/LKOUT/IOX_IN_IO 0 VORF V_POR VREF 0 V_POR# VPU TP0 R K/F_ VPU HWPG(K) V R0 NPEL0X 0 L0 PY00T-0Y-N//ohm_ VORF_uR SM US RRNGEMENT TLE SM us attery / harger SM us PU () HWPG_.V () HWPG_.V () HWPG_.V () SYS_HWPG *S S *S *S 0K_ HWPG HWPG () pin V_GFX pin V_ for TI pin V for TI pin.v_gpu for TI pin GPU_RST# pin GFX_PWRG pin dgpu_vron pin VGPU_ORE pin.v_gpu pin dgpu_pwrok E u/.v_ SM us SM us N/ N/ () HWPG_.0V *S POWER-ON SWITH (UIF) SW S_ON R0 0K_ VPU Power Switch NSWON# *0.u/0V_ SW *.V/V/0P_ Power Switch Quanta omputer Inc. PROJET : Size ocument Number Rev E NPE0X Tuesday, January 0, 0 ate: Sheet of 0

21 () PR _R 0.0/F_0 PR0 0_ 0_N 0_P PR0 0_ P 0.u/0V_ P 0.u/0V_ PQ OL PR K/F_ () /#_R PR 0_ /# (0) PR 0K_ () 0_ET_R 0_P PQ N00K 0_N P 0.u/0V_ P0 0.u/0V_ P 0.u/0V_ PR.K/F_ VPU VPU PR 0K/F_ 0_ET ET P N REGN 0_REGN P u/0v_ EMI (0) IN PR 00K_ PR 00K_ PR 0_0 0_V 0 P 0.u/V_ V TST 0_ST PR 0_ P R00V-0 P n/0v_ P0 0.u/0V_ E *000p/0V_ P.u/V_ PJ 0 att_onn MT P 0.u/0V_ P *00p/0V_ PR 00_ P P *p/0v_ *p/0v_ PQ N00K PL FM T PL FM T TEMP_MT PR M_ MT MLK VPU PR 0K_ PR *0K_ T-V PR K/F_ TEMP_MT (0) VPU PR 0_ PR 0_ 0_IFULT# 0_MPOUT 0_ILIM 0 0_MPIN PR *00K_ OK# S SL IFULT# MPOUT ILIM MPIN IOUT PU Q0 HIRV PHSE LRV P SRP SRN 0_H 0_LX 0_L PR 0_ 0_SRP 0_SRN PR._ 0 P 0.u/V_ P 0.u/V_ P 0.u/V_ PQ MV PQ MV PR *._ P *0p/0V_ PL.uH_XX PR 0_ 0_SRP 0_SRN PR 0.0/F_0 PR0 0_ P 0.u/0V_ REGN MX voltage.v V_ILIM=0*(VSRP-VSRN)=0*Ichg*Rsr =0.V for. current limit T-V P 0u/V_0 P 0u/V_0 PR 0_ PR 00_ PR 00_ PR 00K/F_ P0 0.0u/V_ MLK (,0) (0) IM MT (,0) PU IP-Z H H MLK VN VP VPU TEMP_MT H H MT dd ES diode base on E FE suggestion (,,) SYS_SHN# () LM_PIN PR *0_ PR 0_ 0_MPOUT 0_MPIN P 00p/0V_ Size ocument Number Rev harger(bq0) Quanta omputer Inc. PROJET : ate: Tuesday, January 0, 0 Sheet of

22 () MIN MIN (,,) SYS_SHN# SYS_SHN# (,,) SUS SUS () Ven=.V JP 0.00/F_0 (0) SYS_HWPG VPU VL REF VL JP 0.00/F_0 EMI EMI VPU VPU Volt /- % T : PEK :. OP : Width : 00mil JP 0.00/F_0 P 0u/.V_X. P 0.u/0V_ P 00u/V_X. PR0.K/F_ PR0 0K/F_ P P.u/V_ 00p/0V_ PL0.uH_XX PR0 *._ P0 *0p/0V_ E *0.u/0V_ PQ ON0 PQ ON0 PR0 0_ P 0.u/0V_ PR *00K/F_ PR0 /F_ PR K/F EN SYS_SHN# V_PG V_H V_ V_LX V_L V_F PR 00K/F_ P 0.u/V_ PR 0K/F_ 0 PR 0_ PR 0_ EN P 0.u/0V PGOO UGTE OOT PHSE LGTE VOUT F EN _EN ENTRIP VREG P.u/.V_ PU RTP ENTRIP VREG P.u/.V_ REF TONSEL SKIPSEL UGTE OOT PHSE LGTE OUT F 0 P u/.v_ PR 0_ V_SKIP V_TON V_H V_L V_F PR *0_ PR00 *0_ V_ PR /F_ V_LX PR 0_ P 0.u/0V_ PQ ON0 E *0.u/0V_ P 00p/0V_ PQ0 ON0 PL.uH_XX PR *._ P *0p/0V_ P.u/V_ VPU_SR VPU.Volt /- % T :.0 PEK :. OP :. Width : 00mil PR0.K/F_ PR 0K/F_ VPU P 0.u/0V_ JP 0.00/F_0 P0 0u/.V_X. PR0 0K/F_ PR.K/F_ OP: L(ripple current) =(-)*/(.u*0.m*) =. Iocp=-(./)=. Vth=.*mOhm=.mV R(Ilim)=(.mV*0)/0u =.K V P0 0.u/0V_ P J0F0L P J0F0L V_LWP P 0.u/0V_ P 0.u/0V_ PR0 0_ V_L PR 0_ PR0 0_ OP:. L(ripple current) =(-.)*./(.u*0.m*) ~. Iocp=.-(./)=. Vth=.*mOhm=.mV R(Ilim)=(.mV*0)/0u ~K PR _ P 0.u/0V_ V_S V_S V VPU VPU VPU PR M_ PR0 _ PR _ PR M_ S VPU VPU SUS VSUS T :. PEK :. Width : 0mil S V_S T : 0. PEK : 0. Width : 0mil (,0,,) S_ON PQ MIN O0 PQ MVQ PQ TEU PR M_ PQ N00K PQ N00K PQ N00K V_S V_S T :. PEK :. Width : 0mil V MIN V T :.0 PEK :. Width : 0mil PQ MVQ V V T :. PEK :. Width : 00mil PQ0 O0 VSUS PQ O0 V_S Quanta omputer Inc. PROJET : Size ocument Number Rev SYSTEM V/V (RTP) ate: Tuesday, January 0, 0 Sheet of