CPU_CLK CLOCK GENERATOR NBGFX_CLK ICS9LPRS476AKLFT SLG8SP628VTR RTM880N-795 NBGPP_CLK SBLINK_CLK RJ45. AR8121(Giga) Mini Card (WLAN) MINI CARD (TV)

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1 RT LVS RII-SOIMM PG, RII-SOIMM PG, HMI MXM Module PG ST - H HMI PG 0 LVS PG RT PG R II MHZ ST0 ZK LOK IGRM HMI LVS(ch) PI-E X HT_LINK M Sg Griffin Processor ( Sg socket) PG,, RX0/RS0M/RS0M mm X mm, pin G _LINK (X) PG,0,, PU_LK NGFX_LK NGPP_LK SLINK_LK PI-E, X (port) PI-E, X (port0) US.0 (P) PI-E, X (port) PI-E, X (port) US.0 (P) SSR_LK R(Giga) Mini ard (WLN) MINI R (TV) NEW R LOK GENERTOR ISLPRSKLFT SLGSPVTR RTM0N- PG RJ PG PG PG PG PG HOST 00MHz PIE 00MHz US MHz REF MHz US.0 (P/) PU_ORE PU_ORE PU ORE PU VN_ORE N_ORE.V_VHTTX.V.V.V.V_N.V_S.VSUS.VSUS.V SMR SMR_VTERM VTERM VPU V_S VSUS V VPU V US.0 MINI R Ports X (M) PG N ORE (.0~.V).V.V.V V/V PG PG PG PG PG P STK UP LYER : TOP LYER : LYER : IN LYER : IN LYER : V LYER : OT aughter oard MM oard US oard Touch Pad board Touch Pad board (with Fingerprinter) 0 PG ST - H PG ST S00 US.0 (P) US.0 (P) Fingerprint PG PG US.0 (P0) US.0 (P) US.0 I/O Ports X (M) PG 0 US.0 I/O Ports X () PG 0 ST - O ST US.0 (P) ard Reader PG US.0 (P) US.0 I/O Ports X () PG 0 PG US.0 (P) luetooth PG US.0 (P) US.0 I/O Ports X () PG 0 E - ST PG 0 ST mm X mm, pin G.W(Ext).W(Int) zalia US.0 (P0) OKING PG zalia udio odec L PG PI ROUTING TLE evice ISEL# REQ#/GNT# Interrupt OZ REQ0# / GNT0# INTE# PG,,,, LP M ONN PG M oard RJ PORT- PORT- Speaker mplifier GRU PG E WPE H.P/ SPIF PG MI JK PG INT. MI PG INT. S.P. PG PG SPI VR FN Keyboard PG PG PG Flash Touch ROM Pad PG PG IR PG Kill SW PG Quanta omputer Inc. PROJET : ZK Size ocument Number Rev LOK IGRM Monday, ugust, 00 ate: Sheet of

2 0 G Power On Sequence OM naming rule From,attery VPU VPU From PWM SYS_HWPG(PU) From Power utton NSWON# From E S_ON V_S From E From E From S From S to E From E From PWM From E From PWM From E From PWM From E From S From S From S From S V_S.V_S >0ms RSMRST# >00ms NSWON# PIE_WKE# SUS#,SUS# SUSON SUSON VSUS.VSUS SMR_VREF SMR_VTERM HWPG_.V (SUS) MINON MINON V V.V.V.V N_ORE.V_N.V_VHTTX HWPG_.V,HWPG_.V,GFXPG(MIN) HWPG_._N VRON PU_ORE0, PU_ORE, PU VN_ORE,.V VRM_PWRG (PU) HWPG EPWROK S_PWRG N_PWRG PU_PWRG PLTRST# PIRST# PU_LT_RST# PU_LT_STOP# 0ns~0ns ms~0ms Items Function TO Name escription IR HMI port HMI transmitter HMI-E iscrete VG UM v v v v IR@ HM@ SI@ E@ EV@ IV@ Silicon image SiI / Renesas R/ External VG stuff Internal VG stuff New ard NEW@ RJ v M@ Modem RJ-0/00 0@ Marvell 00T(0/00) 0 Marvell 0(Giga) Option for RJ-0/00 and RJ-000 0@@ Option for 00/0 TV v TV@ FM transmitter v FM@ Mainstream I LE MI@ Low cost I LE LI@ INT MI v I_MI@ M Hyper Flash HF@ Only for M platform 0 North bridge(0m/rs0m) M@ Only for M platform North bridge(rx0) RX@ Only for M platform PowerXpress PX@ Only for M platform PowerXpress with UM SKU PX@IV@ Only for M platform PowerXpress with iscrete VG SKU PX@EV@ Only for M platform Power player/power Shift PP@ Only for M platform *Note: E will sampling SUS# & SUS# every ms. M S00 SMUS Table S00 ST0/SLK0(V) S00 ST/SLK(V_S) S00 ST/SLK(V_S) Power Reserve MOS ckt LK GEN RM Mini ard (H-ecoder) Mini-card(WL) New ard HMI V V V V V (theros) V V_S V V V V V V V V V V V E ST/SLK(VPU) E ST/SLK(VPU) E ST/SLK(VPU) E ST/SLK(VPU) Power Reserve MOS ckt attery PU thermal Sensor E EEPROM VG thermal Sensor Touch Sensor HMI E V E SMUS Table V VPU V VPU V VPU VPU X V X V X V V V V V Quanta omputer Inc. PROJET : ZK Size ocument Number Rev SYSTEM INFORMTION Monday, ugust, 00 ate: Sheet of

3 LK_GEN_SLGSP 0 V V_LK_V.V.V_LK_VIO L L K0HS00 U/.V_ 0.U/0V_ 0.U/0V_ 0 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ K0HS00 U/.V_ 0 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0 0.U/0V_ ISLPRS0 P/N : SLGSP P/N : LSP000 RTM0N- P/N : L U lock chip has internal serial terminations for differencial pairs, external resistors are reserved for debug purpose. Place within 0." of LKGEN R V V_LK_ L K0HS00.U/.V_ V_LK_V 0 VOT VSR VTIG VS_SR VST VPU VHTT VREF V 0 PUK_0T PUK_0 0 TIG0T TIG0 TIGT TIG PULKP_R PULKN_R NGFX_LKP_R NGFX_LKN_R MXM_REFLKP_R MXM_REFLKN_R RP RP RP 0X 0X EV@0X */F_ NGFX_LKP NGFX_LKN LK_MXM LK_MXM# PULKP PULKN LK_MXM () LK_MXM# () PULKP () PULKN () NGFX_LKP () NGFX_LKN () To MXM To PU RS0/RX0 for VG To N LKREQ# LKREQ# R *0K_ R *0K_ V Q *RHU00N0 V Q *RHU00N0 V_LK_V R LKREQ_TV# () LKREQ_WLN# ().V_LK_VIO *0_ G_XIN G_XOUT 0 0 VSR_IO0 VSR_IO VTIG_IO VS_SR_IO VPU_IO OT SR0 SR TIG S_SR ST PU HTT REF X X QFN S_SR0T S_SR0 S_SRT S_SR SR0T SR0 0 SRT SR SRT SR SRT SR SRT SR SRT/STT SR/ST SRT/M_SS SR/M_NS SLINK_LKP_R RP 0X SLINK_LKN_R SSR_LKP_R RP 0X SSR_LKN_R NGPP_LKP_R RP *0X NGPP_LKN_R LK_PIE_NEW_R RP 0X LK_PIE_NEW#_R LK_PIE_MINI_R RP 0X LK_PIE_MINI#_R LK_PIE_MINI_R RP 0X LK_PIE_MINI#_R LK_PIE_LN_R RP0 0X LK_PIE_LN#_R T0 T T T SLINK_LKP SLINK_LKP () SLINK_LKN To N SLINK_LKN () SSR_LKP SSR_LKP () SSR_LKN To S SSR_LKN () NGPP_LKP NGPP_LKP () NGPP_LKN NGPP_LKN () LK_PIE_NEW_ LK_PIE_NEW_ () LK_PIE_NEW_# To New ard LK_PIE_NEW_# () LK_PIE_MINI LK_PIE_MINI () LK_PIE_MINI# To Mini PIE Slot LK_PIE_MINI# () LK_PIE_TV LK_PIE_TV () LK_PIE_TV# To Mini PIE Slot LK_PIE_TV# () LK_PIE_LN LK_PIE_LN () LK_PIE_LN# To LN ontroller LK_PIE_LN# () RX0 only To N :(0/) dd WLN & LN LKREQ circuit (OI request) (,,0,,,) PLK_SM (,,0,,,) PT_SM SMLK SMT HTT0T/M HTT0/M NHT_REFLKP_R RP NHT_REFLKN_R 0X NHT_REFLKP NHT_REFLKN NHT_REFLKP () NHT_REFLKN () To N LK_P# P# MHz_0 LK_M_US_R R _ R _ LK_M_US LK_ard () LK_M_US () To S V_LK_V R R0.K_.K_ NEW_LKREQ# LK_P# (,) NEW_LKREQ# 0 T T p/0v_ p/0v_ NEW_LKREQ# LKREQ# LKREQ# G_XIN Y.MHZ G_XOUT LKREQ0# LKREQ# LKREQ# LKREQ# LKREQ# SLGSP T0 T T T T 0 T T T T T REF0/SEL_HTT REF/SEL_ST REF/SEL_ SEL_HTT SEL_ST Ra SEL_ R R Rb 00 *0p/0V_ *0p/0V_ Ra 0/ dd 0p for EMI issue (Suggestion by Seligo) Rb /F_ 0./F_ RX0.V.R 0R EXT_N_OS RS0.V R 0.R EXT_N_OS () To N N LOK INPUT TLE N LOKS RX0 HT_REFLKP 00M IFF HT_REFLKN 00M IFF REFLK_P M SE (.V) REFLK_N N GFX_REFLK 00M IFF RS0 00M IFF 00M IFF M SE (.V) vref 00M IFF(IN/OUT)* RES HIP 0 /W -%(00)L-F -->S0F RES HIP /W -%(00) -->SF00 RES HIP 0. /W -%(00) -->S00F RES HIP. /W -%(00) -->S0F GPP_REFLK GPPS_REFLK 00M IFF 00M IFF N or 00M IFF OUTPUT 00M IFF LOKS name NGFX_LKP NGFX_LKN MXM_REFLKP MXM_REFLKN NGPP_LKP NGPP_LKN RX0 RP00 STUFF RP STUFF RP00 STUFF RS0 RP00 STUFF RP N RP00 N SLINK_LKP SLINK_LKN RP00 STUFF RP00 STUFF lock pin function to N for VG reference clock to M-S external reference clock -RX0 only to N for RX0 for PIEX interface reference clock only RS0 is internal share with -LINK clock,rs0 not need to N for -LINK reference clock V_LK_V R.K_ R *.K_ R0.K_ SEL_ST SEL_HTT SEL_ R.K_ SEL_HTT SEL_HTT SEL_ST SEL_ R0 *0/F_ R */F_ (For S ) 0 0 * MHz.V single ended HTT clock 0 * 00 MHz differential HTT clock * * default 00 MHz non-spreading differential SR clock 00 MHz spreading differential SR clock MHz and M SS outputs 00 MHz SR clock LK_M_S () Quanta omputer Inc. PROJET : ZK Size ocument Number Rev LOK GENERTOR_SLGSP Monday, ugust, 00 ate: Sheet of

4 () () () () () () () () () () () ().V R 0_ R 0_ HT_N_PU H[..0] HT_N_PU L[..0] HT_N_PU_LK_H[..0] HT_N_PU_LK_L[..0] HT_N_PU_TL_H[..0] HT_N_PU_TL_L[..0] HT_PU_N H[..0] HT_PU_N L[..0] HT_PU_N_LK_H[..0] HT_PU_N_LK_L[..0] HT_PU_N_TL_H[..0] HT_PU_N_TL_L[..0].V_VLT R R.V_VLT *_ *_.V_VLT HT_N_PU H[..0] HT_N_PU L[..0] HT_N_PU_LK_H[..0] HT_N_PU_LK_L[..0] HT_N_PU_TL_H[..0] HT_N_PU_TL_L[..0] HT_PU_N H[..0] HT_PU_N L[..0] HT_PU_N_LK_H[..0] HT_PU_N_LK_L[..0] HT_PU_N_TL_H[..0] HT_PU_N_TL_L[..0] HT_N_PU_TL_H HT_N_PU_TL_L.U/.V_.U/.V_ 0.U/.V_ 0p/0V_.V.V_VLT.V_VLT.V_VLT.V_VLT HT_N_PU H0 HT_N_PU L0 HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H0 HT_N_PU L0 HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU_LK_H0 HT_N_PU_LK_L0 HT_N_PU_LK_H HT_N_PU_LK_L HT_N_PU_TL_H0 HT_N_PU_TL_L0 HT_N_PU_TL_H HT_N_PU_TL_L LMPGSN E E E F G G G H J K L L L M N N E F F F G H H H K K L M M M N P J J J K N P P P L0 0 0U/.V_ LS00-00M-N U VLT_0 VLT_ VLT_ VLT_ L0_IN_H0 L0_IN_L0 L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H0 L0_IN_L0 L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_LKIN_H0 L0_LKIN_L0 L0_LKIN_H L0_LKIN_L L0_TLIN_H0 L0_TLIN_L0 L0_TLIN_H L0_TLIN_L SOKET PIN HT LINK PUV 0.U/.V_ VLT_0 VLT_ VLT_ VLT_ L0_OUT_H0 L0_OUT_L0 L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H0 L0_OUT_L0 L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_LKOUT_H0 L0_LKOUT_L0 L0_LKOUT_H L0_LKOUT_L L0_TLOUT_H0 L0_TLOUT_L0 L0_TLOUT_H L0_TLOUT_L W/S= mil/0mil PU LK () PULKP 0.U/.V_ 00p/0V_ 00U/._ () PULKN M Suggestion / modify E E E E W W V U U U T R Y W V V V U T T Y W Y Y R R T R.V_VLT.V_VLT.V_VLT.V_VLT.U/.V_ 0.U/.V_ 0p/0V_ HT_PU_N H0 HT_PU_N L0 HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H0 HT_PU_N L0 HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N_LK_H0 HT_PU_N_LK_L0 HT_PU_N_LK_H HT_PU_N_LK_L HT_PU_N_TL_H0 HT_PU_N_TL_L0 HT_PU_N_TL_H HT_PU_N_TL_L 0.VSUS PULKIN PULKP PULKN Sideand Temp sense I PULKP PULKN Keep trace from resisor to PU within 0." keep trace from caps to PU within." () () () () PULKIN# () PU_LT_RST# () PU_PWRG (,) PU_LT_STOP#.V_VLT M Suggestion / modify R R.VSUS *00_ /F_ M Suggestion / modify 00p/V_ 00p/V_ R R PU_V0_F_H PU_V0_F_L PU_V_F_H PU_V_F_L T T0 T T T *00_ *00_ R0 R PU_RY PU_TMS PU_TK PU_TRST# PU_TI PUV W/S= mil/0mil PUV PUV PULKIN PULKIN# PU_LT_RST# PU_PWRG PU_LT_STOP# PU_LT_REQ#_PU PU_SI PU_SI PU_LERT./F_ PU_HTREF0./F_ PU_HTREF place them to PU within." T R R 0/F_ 0/F_ 00_ R *00_ R0 00_ R0 *00_ R0 *00_ R0 R0 0_ PUTEST PUTEST PUTEST PUTESTH PUTESTL PUTEST PUTEST0 PUTEST PUTEST PUTEST PUTEST F F F0 F F E R P F E Y G0 F H0 G E E F E E F U V V LKIN_H LKIN_L RESET_L PWROK LTSTOP_L LTREQ_L SI SI LERT_L HT_REF0 HT_REF V0_F_H V0_F_L V_F_H V_F_L RY TMS TK TRST_L TI TEST TEST TEST TEST_H TEST_L TEST TEST0 TEST TEST TEST TEST TEST TEST RSV RSV RSV RSV RSV KEY KEY SV SV THERMTRIP_L PROHOT_L MEMHOT_L THERM THERM VIO_F_H VIO_F_L VN_F_H VN_F_L REQ_L TO TEST_H TEST_L TEST TEST TEST TEST TEST TEST0 TEST TEST_H TEST_L RSV0 RSV RSV RSV RSV M W F W W W Y H G E0 E J H E F K H H PU_LT_RST# PU_LT_STOP# PU_LT_REQ#_PU PU_PWRG PU_SV_R PU_SV_R PU_THERMTRIP_L# PU_PROHOT_L# PU_MEMHOT_L# PU_THERM PU_THERM VIO_F_H VIO_F_L PU_REQ# PU_TO PUTESTH PUTESTL PUTEST PUTEST PUTEST PUTEST PUTESTH PUTESTL *0.U/0V_ T T T T *00_ *00_ T T 00_ R 00_ R 00_ R 00_ R R 0_ R0 0_ VIO_F_H VIO_F_L H_THERM H_THERM PU_VN_F_H () PU_VN_F_L () T0 T R0 R.V.V 0 /0 leakage issue, change.vsus to.v 0/ M suggest. pull up PU_PWRG to.sus. pop R pull up to.sus SOKET PIN V R 0K/F_ NTR_VREF 0.U/0V_ R.K/F_ NTR_VREF V 0/ M suggest remove MOS and connect directly NTR_VREF.VSUS.VSUS HT onnector / pull up R PU_REQ# to avoid noise cause system shut down NTR_VREF R K/F_ R 0_ R 0_ R K/F_ R 00_ Q PU_LT_REQ#_PU *SS_NL/SOT PU_LT_REQ# () PU_LT_RST# PU_LT_RST_HTP# Q SS_NL/SOT T0 () S_SLK S_SLK R *0_ PU_SI PU_REQ# *00p/0V_ R 0_ 0 *00p/0V_ G *SHORT_ P for debug only () S_ST S_ST THERM_LERT#_R R *0_ *SS_NL/SOT Q0 PU_SI PU_LERT.VSUS.VSUS.VSUS.VSUS R R 00_ PU_MEMHOT_L# R R 00_ / leakage issue,add R, no stuff R / double check 0K/F_ 0K/F_ Q0 Q MMT0 PU_MEMHOT# V R *0K_ () PU_MEMHOT# (,).VSUS HWPG.VSUS R 00_ Q FV0N R K_ R *0K_ *S R 00K_.VSUS PU_SV_R PU_SV_R PU_PWRG R0 K/F_ R K/F_ PU Thermal monitor Serial VI R0 0_ PU_SV PU_SV () R0 0_ PU_SV PU_SV () R 0_ PU_PWRG_SVI_REG PU_PWRG_SVI_REG () R *0_ R *0_ R *0_ V VFIX MOE VI Override ircuit SV SV Voltage Output V.V.0V 0.V PU_PROHOT_L# MMT0 R 0_ PU_THERMTRIP_L# E_PROHOT# () PU_PROHOT_S# () / double check R0 Q MMT0 *0_ PU_THERMTRIP# () SYS_SHN# (,) V Q RHU00N0 R0 0K_ R 0K_ / change G to GPU R0 00_ LMV () LK 0 () T V V Q RHU00N0 V U0 SLK S LERT# V XP XN 0.U/0V_ 0 00p/0V_ H_THERM / G reverse R 0 ohm for Griffin PU () THERM_LERT# R *.K_ R *0K_ THERM_LERT#_R OVERT# GPU RESS: H H_THERM R *0_ () PUFN#_ON V *N00E-LF R Q 0/0 change to G 0K_ MX,GP,WLG <check list> Layout Note:Routing 0:0 mils and away from noise source with ground gard Quanta omputer Inc. PROJET : ZK Size ocument Number Rev Sg HT, TL I/F / Monday, ugust, 00 ate: Sheet of

5 E E M_ZN M_ZP MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_0 MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_0 MEM_M_ MEM_M_T PU_VTT_SENSE MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_0 MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_0 MEM_M_ MEM_M_RESET# MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M0 MEM_M_M MEM_M_OT0 MEM_M_OT0 MEM_M_OT MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M0 MEM_M_RESET# MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T PU_M_S_L0 PU_M_S_L PU_M_LK_L PU_M_LK_H PU_M_LK_H PU_M_LK_L PU_M_LK_H PU_M_LK_HL PU_M_LK_L PU_M_LK_H MEMVREF_PU MEM_M_LK_P MEM_M_LK_P MEM_M_LK_N MEM_M_LK_P MEM_M_LK_N MEM_M_LK_P MEM_M_LK_N MEM_M_LK_N MEM_M_[0..] (,) MEM_M0_OT0 (,) MEM_M0_OT (,) MEM_M0_S#0 (,) MEM_M0_S# (,) MEM_M_KE0 (,) MEM_M_KE (,) MEM_M_LK_P () MEM_M_LK_N () MEM_M_LK_P () MEM_M_LK_N () MEM_M_NK0 (,) MEM_M_NK (,) MEM_M_NK (,) MEM_M_RS# (,) MEM_M_S# (,) MEM_M_WE# (,) MEM_M_NK0 (,) MEM_M_NK (,) MEM_M_NK (,) MEM_M_RS# (,) MEM_M_S# (,) MEM_M_WE# (,) MEM_M_LK_P () MEM_M_LK_N () MEM_M_LK_P () MEM_M_LK_N () MEM_M_KE0 (,) MEM_M_KE (,) MEM_M0_S#0 (,) MEM_M0_S# (,) MEM_M0_OT0 (,) MEM_M0_OT (,) MEM_M_[0..] (,) MEM_M_T[0..] () MEM_M_M[0..] () MEM_M_QS0_P () MEM_M_QS0_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS0_P () MEM_M_QS0_N () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_M[0..] () MEM_M_T[0..] () PU_VTT_SENSE () SMR_VTERM SMR_VTERM.VSUS SMR_VTERM SMR_VTERM.VSUS SMR_VREF Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : SG RII MEMORY I/F / Monday, ugust, 00 ZK Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : SG RII MEMORY I/F / Monday, ugust, 00 ZK Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : SG RII MEMORY I/F / Monday, ugust, 00 ZK PLE THEM LOSE TO PU WITHIN " Processor Memory Interface Place close to socket 0 lose to PU within 00 mils Reserved 0 m MEM:T U SOKET PIN MEM:T U SOKET PIN M_T M_T F M_T F M_T0 E M_T Y M_T M_T M_T F M_T F M_T F M_T M_T F M_T M_T0 M_T E M_T M_T 0 M_T 0 M_T F M_T F M_T F0 M_T E0 M_T M_T0 M_T E M_T M_T M_T M_T E M_T M_T M_T M_T G M_T0 G M_T M_T M_T G M_T G M_T E M_T E M_T M_T M_T 0 M_T0 0 M_T M_T M_T M_T 0 M_T M_T M_T M_T M_T 0 M_T0 M_T M_T M_T M_T M_T E M_T G M_T M_T M_T M_T0 M_T M_T M_T M_T0 M_T W M_T Y M_T M_T M_T M_T M_T M_T Y M_T Y M_T0 W M_T W M_T M_T Y M_T M_T M_T M_T M_T M_T 0 M_T0 Y0 M_T M_T Y M_T W M_T W M_T M_T M_T M_T Y M_T H M_T0 H0 M_T E M_T E M_T J M_T H M_T F M_T F0 M_T M_T M_T F M_T0 E M_T E0 M_T M_T M_T G M_T G M_T M_T F M_T E M_T H M_T0 E M_T E M_T H M_T E M_T M_T H M_T H M_T G M_T H M_T F M_T0 G M_M M_M M_M E M_M M_M E M_M M_M M_M0 M_QS_H F M_QS_L E M_QS_H E M_QS_L M_QS_H F M_QS_L F M_QS_H M_QS_L M_QS_H F M_QS_L E M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H0 M_QS_L0 M_M Y M_M M_M Y M_M M_M F M_M E M_M M_M0 E M_QS_H W M_QS_L W M_QS_H Y M_QS_L W M_QS_H M_QS_L 0 M_QS_H M_QS_L M_QS_H G M_QS_L G M_QS_H M_QS_L M_QS_H G M_QS_L G M_QS_H0 G M_QS_L0 H T T T T T T T T T T.p/0V_.p/0V_ T T R K/F_ R K/F_.U/.V_.U/.V_ R./F_ R./F_ 0p/0V_ 0p/0V_ 0.U/0V_ 0.U/0V_ R K/F_ R K/F_ 0p/0V_ 0p/0V_ 0p/0V_ 0p/0V_ MEM:M/TRL/LK U SOKET PIN MEM:M/TRL/LK U SOKET PIN VTT 0 VTT 0 VTT 0 VTT 0 VTT W0 VTT 0 VTT 0 VTT 0 VTT 0 M_OT V M_OT0 U M0_OT V M0_OT0 T M_OT0 Y M0_OT W M0_OT0 W RSV_M M_S_L0 U M0_S_L W M0_S_L0 V M0_S_L U M_S_L V0 M_S_L0 U0 M0_S_L0 T0 M_ K M_ K M_ V M_ K0 M_ L M_0 R M_ K M_ L M_ L M_ M M_ L0 M_ M M_ M M_ N M_ M0 M_0 N M_NK J M_NK R M_NK0 R0 M_RS_L R M_S_L T M_WE_L T MEMZP F0 MEMZN E0 VTT_SENSE Y0 MEMVREF W M_LK_H P M_LK_L P0 M_LK_H Y M_LK_L M_LK_H E M_LK_L F M_LK_H N M_LK_L N0 M_LK_H R M_LK_L R M_LK_H F M_LK_L F M_LK_H M_LK_L M_LK_H P M_LK_L R M_KE0 J M_KE J0 M_KE0 J M_KE H M_ J M_ J M_ W M_ L M_ L M_0 T M_ K M_ M M_ L M_ N M_ L M_ N M_ N M_ P M_ N M_0 P M_NK J M_NK U M_NK0 R M_RS_L U M_S_L U M_WE_L U RSV_M H 000p/0V_ 000p/0V_ 0 000p/0V_ 0 000p/0V_.p/0V_.p/0V_ T T 0.U/.V_ 0.U/.V_.U/.V_.U/.V_.p/0V_.p/0V_ 000p/0V_ 000p/0V_ 0p/0V_ 0p/0V_ 0 000p/0V_ 0 000p/0V_ T T T0 T0.U/.V_.U/.V_ R./F_ R./F_ 00 0.U/.V_ 00 0.U/.V_ 0 0.U/.V_ 0 0.U/.V_ 0.U/.V_ 0.U/.V_ 0 000p/0V_ 0 000p/0V_ T T T T.p/0V_.p/0V_ R *0_ R *0_ 0.U/.V_ 0.U/.V_ T T T T T T T T T T

6 PU_ORE0 PU VN_ORE.VSUS UE G V0_ V_ H V0_ V_ J V0_ V_ J V0_ V_ J V0_ V_ J V0_ V_ K V0_ V_ K0 V0_ V_ K V0_ V_ K V0_0 V_0 L V0_ V_ L V0_ V_ L V0_ V_ L V0_ V_ L V0_ V_ L V0_ V_ M V0_ V_ M V0_ V_ M V0_ V_ M0 V0_0 V_0 N V0_ V_ N V0_ V_ N V0_ V_ V_ K VN_ V_ M VN_ V_ P VN_ T VN_ VIO V VN_ VIO VIO H VIO VIO J VIO VIO K VIO VIO K VIO VIO K VIO VIO0 K VIO VIO L VIO VIO M VIO VIO M VIO VIO M VIO0 VIO M VIO VIO N VIO VIO SOKET PIN PU_ORE P P0 R R R R T T T T0 T T U U U U U V V V0 V V W Y.VSUS Y V V V V U T T T T R P P P P UF VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS E VSS VSS E VSS VSS E VSS VSS E VSS VSS E VSS VSS0 E VSS VSS E VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS00 VSS VSS0 VSS VSS0 VSS VSS0 VSS VSS0 VSS0 VSS0 VSS VSS0 VSS VSS0 VSS VSS0 VSS VSS0 VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS E VSS VSS F VSS VSS F VSS VSS F VSS VSS F VSS VSS0 F VSS VSS F VSS VSS F VSS VSS F VSS VSS F VSS0 VSS H VSS VSS H VSS VSS H VSS VSS H VSS VSS J VSS SOKET PIN J J J0 J J J J K K K K K K K L L L0 L L L L M M M N N N0 N N P P P P P R R0 R R T T T T T T U U U U0 U U U U V V V V V V V W Y Y N PU_ORE0 U/.V_ PU_ORE PU VN_ORE.VSUS.VSUS U/.V_ 0 U/.V_ OTTOM SIE EOUPLING U/.V_ U/.V_ U/.V_.VSUS U/.V_ 0.U/.V_ EOUPLING ETWEEN PROESSOR N IMMs PLE LOSE TO PROESSOR S POSSILE.U/.V_ U/.V_.U/.V_ 0 U/.V_ U/.V_ U/.V_.U/.V_ U/.V_.U/.V_ 0 0.U/.V_ 0.U/.V_ 0.0U/V_ 0.0U/V_ 0.U/.V_ U/.V_ 0p/0V_ 0.0U/V_ 0p/0V_ 0.U/.V_ 0.U/.V_ 0.U/.V_ 0.0U/V_ 0p/0V_ 0.U/.V_ 0.0U/V_ 0 0p/0V_ 0p/0V_ 0 PROESSOR POWER N GROUN Quanta omputer Inc. PROJET : ZK Size ocument Number Rev SG PWR & / ate: Monday, ugust, 00 Sheet of

7 MEM_M_N MEM_M_ MEM_M_ MEM_M_NK0 MEM_M_ MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_NK MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_NK PT_SM PLK_SM MEM_M_T MEM_M_M MEM_M_M MEM_M_M0 MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_0 MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_0 MEM_M_ MEM_M_ MEM_M_ MEMHOT_SOIMM#_ MEM_M_ MEM_M_RESET# MEM_M_NK0 MEM_M_ MEM_M_ MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_NK MEM_M_NK MEM_M_T MEM_M_N MEM_M_RESET# PT_SM MEM_M_T PLK_SM MEMHOT_SOIMM#_ MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M0 MEM_M_M MEM_M_M MEM_M_0 MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_0 MEM_M_ MEM_M_ MEM_M_ MEM_M_ IM_S0 IM_S IM_S0 IM_S IM_S0 IM_S IM_S0 IM_S 0.VSMVREF_IMM PT_SM (,,0,,,) PLK_SM (,,0,,,) MEM_M_T[0..] () MEM_M_M[0..] () MEM_M_M[0..] () MEM_M_QS0_P () MEM_M_QS_P () MEM_M_QS_P () MEM_M_QS_P () MEM_M_QS_P () MEM_M_QS_P () MEM_M_QS_P () MEM_M_QS_P () MEM_M_QS0_N () MEM_M_QS_N () MEM_M_QS_N () MEM_M_QS_N () MEM_M_QS_N () MEM_M_QS_N () MEM_M_QS_N () MEM_M_QS_N () MEM_M_LK_P () MEM_M_LK_N () MEM_M_LK_P () MEM_M_LK_N () MEM_M_KE0 (,) MEM_M_KE (,) MEM_M_RS# (,) MEM_M_S# (,) MEM_M_WE# (,) MEM_M0_S#0 (,) MEM_M0_OT0 (,) MEM_M0_OT (,) MEM_M0_S# (,) MEM_M_NK[0..] (,) MEM_M_[0..] (,) MEM_M_QS_N () MEM_M_QS_N () MEM_M_KE0 (,) MEM_M_KE (,) MEM_M_QS_N () MEM_M_QS_N () MEM_M_RS# (,) MEM_M_S# (,) MEM_M_WE# (,) MEM_M0_S#0 (,) MEM_M0_OT0 (,) MEM_M0_OT (,) MEM_M_QS_P () MEM_M_QS_P () MEM_M0_S# (,) MEM_M_QS_P () MEM_M_QS_P () MEM_M_QS_P () MEM_M_QS_P () MEM_M_LK_P () MEM_M_QS0_N () MEM_M_LK_N () MEM_M_QS0_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_N () MEM_M_LK_P () MEM_M_LK_N () MEM_M_NK[0..] (,) MEM_M_[0..] (,) MEM_M_T[0..] ().VSUS.VSUS V 0.VSMVREF_IMM 0.VSMVREF_IMM V.VSUS V 0.VSMVREF_IMM SMR_VREF Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R SOIMMS: / HNNEL Monday, ugust, 00 ZK Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R SOIMMS: / HNNEL Monday, ugust, 00 ZK Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R SOIMMS: / HNNEL Monday, ugust, 00 ZK o SMbus address SMbus address 0 H=. H=. 0 Only for reserved / hange N footprint from R--0-00P to R--0-00P- (SMT open issue) SO-IMM N R SO-IMM SOKET.V SO-IMM N R SO-IMM SOKET.V Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q 0 Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q 0 Q Q Q Q Q Q0 Q Q Q 0 Q Q Q Q Q Q Q0 0 Q Q Q N 0 N N N 0 N/TEST M0 0 M M M M 0 M M 0 M QS0 QS QS QS 0 QS QS QS QS K0 0 K0 K K KE0 KE 0 VREF RS 0 S WE 0 S0 0 S S0 S 00 S SL Vspd V0 V V V V V V 0 V V 0 V V0 V VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS QS0 QS QS QS QS QS QS QS OT0 OT VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 T T T T R 0K/F_ R 0K/F_ R K/F_ R K/F_ R 0K/F_ R 0K/F_ 0.U/0V_ 0.U/0V_ 0 0.U/0V_ 0 0.U/0V_ 0.U/0V_ 0.U/0V_ R0 0K/F_ R0 0K/F_ 000p/0V_ 000p/0V_ T T.U/.V_.U/.V_ T T 0 000p/0V_ 0 000p/0V_ R *0_ R *0_ R K/F_ R K/F_.U/.V_.U/.V_ 0.U/0V_ 0.U/0V_ T T R 0K/F_ R 0K/F_ T T SO-IMM N R SO-IMM SOKET.V SO-IMM N R SO-IMM SOKET.V Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q 0 Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q 0 Q Q Q Q Q Q0 Q Q Q 0 Q Q Q Q Q Q Q0 0 Q Q Q N 0 N N N 0 N/TEST M0 0 M M M M 0 M M 0 M QS0 QS QS QS 0 QS QS QS QS K0 0 K0 K K KE0 KE 0 VREF RS 0 S WE 0 S0 0 S S0 S 00 S SL Vspd V0 V V V V V V 0 V V 0 V V0 V VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS QS0 QS QS QS QS QS QS QS OT0 OT VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0

8 (,) MEM_M_[0..] (,) MEM_M_NK[0..] MEM_M_[0..] MEM_M_NK[0..] (,) MEM_M_[0..] (,) MEM_M_NK[0..] MEM_M_[0..] MEM_M_NK[0..] 0 SMR_VTERM SMR_VTERM (,) MEM_M_KE0 (,) MEM_M_WE# (,) MEM_M_S# (,) MEM_M0_OT (,) MEM_M0_S# (,) MEM_M_KE (,) MEM_M0_S#0 (,) MEM_M_RS# (,) MEM_M0_OT0 MEM_M_NK RP MEM_M_ MEM_M_KE0 RP0 MEM_M_ MEM_M_ RP MEM_M_ MEM_M_ RP MEM_M_ MEM_M_NK0 RP MEM_M_0 MEM_M_WE# RP MEM_M_S# MEM_M0_OT RP MEM_M0_S# MEM_M_ RP MEM_M_KE MEM_M_ RP MEM_M_ MEM_M_ RP MEM_M_ MEM_M_ MEM_M_ MEM_M_NK MEM_M_0 MEM_M0_S#0 MEM_M_RS# MEM_M_ MEM_M0_OT0 RP RP0 RP RP _PR PR PR PR PR PR PR PR PR PR PR PR PR PR_ U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_.VSUS.VSUS.VSUS.VSUS.VSUS.VSUS.VSUS.VSUS (,) MEM_M_KE0 (,) MEM_M_WE# (,) MEM_M_S# (,) MEM_M0_OT (,) MEM_M0_S# (,) MEM_M_KE (,) MEM_M0_S#0 (,) MEM_M_RS# (,) MEM_M0_OT0 MEM_M_KE0 MEM_M_NK MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_0 MEM_M_NK0 MEM_M_WE# MEM_M_S# MEM_M0_OT MEM_M0_S# MEM_M_KE MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_NK MEM_M_0 MEM_M0_S#0 MEM_M_RS# MEM_M0_OT0 MEM_M_ RP RP RP RP RP RP RP RP0 RP RP RP RP RP RP _PR PR PR PR PR PR PR PR PR PR PR PR PR PR_ U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_.VSUS.VSUS.VSUS.VSUS.VSUS.VSUS.VSUS.VSUS PLE LOSE TO PROESSOR WITHIN. INH PLE LOSE TO PROESSOR WITHIN. INH.VSUS.VSUS 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0 0.U/0V_ 0.U/0V_ PLE LOSE TO SOKET( PER EMI/EM) PLE LOSE TO SOKET( PER EMI/EM) Quanta omputer Inc. PROJET : ZK Size ocument Number Rev R SOIMMS TERMINTIONS ate: Monday, ugust, 00 Sheet of

9 R0 HT_PU_N H0 HT_PU_N L0 HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H0 HT_PU_N L0 HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N_LK_H0 HT_PU_N_LK_L0 HT_PU_N_LK_H HT_PU_N_LK_L HT_PU_N_TL_H0 HT_PU_N_TL_L0 HT_PU_N_TL_H HT_PU_N_TL_L R 0/F_ HT_RXLP HT_RXLN U Y HT_RX0P HT_TX0P Y HT_RX0N PRT OF HT_TX0N V HT_RXP HT_TXP V HT_RXN HT_TXN V HT_RXP HT_TXP V HT_RXN HT_TXN U HT_RXP HT_TXP U HT_RXN HT_TXN T HT_RXP HT_TXP T HT_RXN HT_TXN P HT_RXP HT_TXP P HT_RXN HT_TXN P HT_RXP HT_TXP P HT_RXN HT_TXN N HT_RXP HT_TXP N HT_RXN HT_TXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RX0P HT_RX0N Y HT_RXP Y HT_RXN W HT_RXP W0 HT_RXN V HT_RXP V0 HT_RXN U0 HT_RXP U HT_RXN U HT_RXP U HT_RXN T HT_RXLK0P T HT_RXLK0N HT_RXLKP HT_RXLKN M HT_RXTL0P M HT_RXTL0N R HT_RXTLP R0 HT_RXTLN HT_RXLP HT_RXLN RS0(RX0) HYPER TRNSPORT PU I/F HT_TXP HT_TXN HT_TXP HT_TXN HT_TX0P HT_TX0N HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXLK0P HT_TXLK0N HT_TXLKP HT_TXLKN HT_TXTL0P HT_TXTL0N HT_TXTLP HT_TXTLN HT_TXLP HT_TXLN E E F F F F H H J J K K K K F G G0 H J0 J J K L J M L M P P M H H L L0 M M P R HT_N_PU H0 HT_N_PU L0 HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H0 HT_N_PU L0 HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU_LK_H0 HT_N_PU_LK_L0 HT_N_PU_LK_H HT_N_PU_LK_L HT_N_PU_TL_H0 HT_N_PU_TL_L0 HT_N_PU_TL_H HT_N_PU_TL_L HT_TXLP HT_TXLN R R 0/F_ HT_PU_N H[..0] HT_PU_N L[..0] HT_PU_N_LK_H[..0] HT_PU_N_LK_L[..0] HT_PU_N_TL_H[..0] HT_PU_N_TL_L[..0] HT_N_PU H[..0] HT_N_PU L[..0] HT_N_PU_LK_H[..0] HT_N_PU_LK_L[..0] HT_N_PU_TL_H[..0] HT_N_PU_TL_L[..0] HT_TXLP HT_TXLN HT_RXLP HT_RXLN HT_PU_N H[..0] () HT_PU_N L[..0] () HT_PU_N_LK_H[..0] () HT_PU_N_LK_L[..0] () HT_PU_N_TL_H[..0] () HT_PU_N_TL_L[..0] () HT_N_PU H[..0] () HT_N_PU L[..0] () HT_N_PU_LK_H[..0] () HT_N_PU_LK_L[..0] () HT_N_PU_TL_H[..0] () HT_N_PU_TL_L[..0] () signals RS0 RX0 R 00 ohm % R 00 ohm % R.k ohm % R.k ohm % / modify RES HIP 00 /W -%(00) P/N : S00F00 0 RES HIP.K /W -%(00) P/N : SF version RS0M J000T0 00-K( ) RS0M J000T0 00-K( ) RX J000T0 00-K(-00) S00 JFG0T 00-K(SELFG) This block is for UM RS0 only, RX0 can remove all component version RS0M J000T 00-K(-00) RS0M J000T0 00-K0(-00) RX J000T 00-K0(-00) version S00 JFG0T U PR OF MEM_0(N) MEM_Q0/VO_VSYN(N) E MEM_(N) MEM_Q/VO_HSYN(N) V MEM_(N) MEM_Q/VO_E(N) E MEM_(N) MEM_Q/VO_0(N) MEM_(N) MEM_Q(N) MEM_(N) MEM_Q/VO_(N) MEM_(N) MEM_Q/VO_(N) MEM_(N) MEM_Q/VO_(N) MEM_(N) MEM_Q/VO_(N) MEM_(N) MEM_Q/VO_(N) MEM_0(N) MEM_Q0/VO_(N) E MEM_(N) MEM_Q/VO_(N) MEM_(N) MEM_Q(N) Y MEM_(N) MEM_Q/VO_(N) MEM_Q/VO_0(N) MEM_0(N) MEM_Q/VO_(N) E MEM_(N) MEM_(N) MEM_QS0P/VO_IKP(N) MEM_QS0N/VO_IKN(N) W MEM_RSb(N) MEM_QSP(N) Y MEM_Sb(N) MEM_QSN(N) MEM_WEb(N) MEM_Sb(N) MEM_M0(N) MEM_KE(N) MEM_M/VO_(N) V MEM_OT(N) IOPLLV(N) V MEM_KP(N) IOPLLV(N) W MEM_KN(N) IOPLLVSS(N) E MEM_OMPP(N) MEM_OMPN(N) MEM_VREF(N) RS0(RX0) S_MEM/VO_I/F 0 Y V Y 0 E 0 Y W 0 E W E E E E._IOPLLV_N.V_IOPLLV R R0 *0_ *0_ IOPLLV- memory PLL not applicable to RX0.V.V_N without Side-Port NU / / R0,R no stuff when RS0M without side port / RX Quanta omputer Inc. PROJET : ZK Size ocument Number Rev RS0/RS0-HT LINK I/F / ate: Monday, ugust, 00 Sheet of

10 PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP0 PEG_RXN0 PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP0 PEG_RXN0 U GFX_RX0P GFX_RX0N GFX_RXP GFX_RXN GFX_RXP GFX_RXN E GFX_RXP F GFX_RXN G GFX_RXP G GFX_RXN H GFX_RXP H GFX_RXN J GFX_RXP J GFX_RXN J GFX_RXP J GFX_RXN L GFX_RXP L GFX_RXN M GFX_RXP L GFX_RXN P GFX_RX0P M GFX_RX0N P GFX_RXP M GFX_RXN R GFX_RXP P GFX_RXN R GFX_RXP R GFX_RXN P GFX_RXP P GFX_RXN T GFX_RXP T GFX_RXN PRT OF PIE I/F GFX GFX_TX0P GFX_TX0N GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TX0P GFX_TX0N GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN E E F F F F H H H H J J K K K K M M M M N N P P _PEG_TXP _PEG_TXN _PEG_TXP _PEG_TXN _PEG_TXP _PEG_TXN 0 _PEG_TXP _PEG_TXN _PEG_TXP _PEG_TXN _PEG_TXP0 _PEG_TXN0 _PEG_TXP _PEG_TXN _PEG_TXP _PEG_TXN _PEG_TXP _PEG_TXN _PEG_TXP 0 _PEG_TXN 0 _PEG_TXP _PEG_TXN 0 _PEG_TXP _PEG_TXN _PEG_TXP 0 _PEG_TXN _PEG_TXP _PEG_TXN _PEG_TXP _PEG_TXN _PEG_TXP0 _PEG_TXN0 EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP0 PEG_TXN0 PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP0 PEG_TXN0 () PEG_RXN[:0] () PEG_RXP[:0] PEG_RXN[:0] PEG_RXP[:0] lose to North ridge _PEG_TXP _PEG_TXN _PEG_TXP _PEG_TXN _PEG_TXP _PEG_TXN _PEG_TXP _PEG_TXN PEG_TXN[:0] PEG_TXP[:0] TO lose to North ridge IV@0.U/0V_ IV@0.U/0V_ IV@0.U/0V_ IV@0.U/0V_ IV@0.U/0V_ IV@0.U/0V_ IV@0.U/0V_ IV@0.U/0V_ PEG_TXN[:0] () PEG_TXP[:0] () INT_HMITXP (0) INT_HMITXN (0) INT_HMITXP (0) INT_HMITXN (0) INT_HMITXP0 (0) INT_HMITXN0 (0) INT_HMITXP (0) INT_HMITXN (0) To HMI ONN T T0 () PIE_RXP () PIE_RXN () PIE_RXP () PIE_RXN () PIE_RXP () PIE_RXN () GLN_RXP () GLN_RXN () PIE_S_N_RX0P () PIE_S_N_RX0N () PIE_S_N_RXP () PIE_S_N_RXN () PIE_S_N_RXP () PIE_S_N_RXN () PIE_S_N_RXP () PIE_S_N_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN GLN_RXP GLN_RXN E GPP_RX0P GPP_TX0P GPP_RX0N GPP_TX0N E GPP_RXP GPP_TXP GPP_RXN GPP_TXN GPP_RXP GPP_TXP GPP_RXN PIE I/F GPP GPP_TXN V GPP_RXP GPP_TXP W GPP_RXN GPP_TXN U GPP_RXP GPP_TXP U GPP_RXN GPP_TXN U GPP_RXP GPP_TXP U GPP_RXN GPP_TXN S_RX0P S_TX0P Y S_RX0N S_TX0N S_RXP S_TXP Y S_RXN S_TXN S_RXP PIE I/F S S_TXP S_RXN S_TXN W S_RXP S_TXP Y S_RXN S_TXN PE_LRP(PE_LRP) PE_LRN(PE_LRN) RS0(RX0) PIE_TXP_ PIE_TXN_ PIE_TXP_ PIE_TXN_ 0 00 Y PIE_TXP_ 0 Y PIE_TXN_ 0 Y PIE_TXP_ Y PIE_TXN_ 0 V V E E E _TX0P TX0N TXP_ 0 _TXN TXP TXN TXP TXN_ N_PIELRP N_PIELRN R0 R00 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_.K/F_ K/F_ T T PIE_TXP () PIE_TXN () PIE_TXP () PIE_TXN () PIE_TXP () PIE_TXN () GLN_TXP () GLN_TXN () PIE_N_S_TX0P () PIE_N_S_TX0N () PIE_N_S_TXP () PIE_N_S_TXN () PIE_N_S_TXP () PIE_N_S_TXN () PIE_N_S_TXP () PIE_N_S_TXN ().V_N TO EPRESS R TO WLN TO MINI R TO PIE-LN NOTE: RS0M no support Graphic / HMI / modify RX0/RS0/RS0 difference table (PIE LINK) RS0 RX0/RS0 N_PIELRP R ().K () RS0 isplay Port Support (muxed on GFX) GFX_TX0,TX,TX and TX P0 UX0 and HP0 GPP GPP N N GPP GPP P GFX_TX,TX,TX and TX UX and HP Quanta omputer Inc. PROJET : ZK Size ocument Number Rev RS0/RS0-PIE I/F / ate: Monday, ugust, 00 Sheet 0 of

11 RX0: Powered from the.-v rail and driven by S00 LT_RST#, or S00 LT_RST# or _RST#. RS0: Powered from the.-v rail and driven by S00 LT_RST#, or S00 LT_RST# or _RST#. () RS0 N_PLTRST# North ridge RESET N_PLTRST# () () () INT_RT_RE INT_RT_GRN INT_RT_LU R R R IV@0/F_ IV@0/F_ IV@0/F_ V_V_N.V_VI_N.V_VQ_N INT_RT_RE INT_RT_GRN INT_RT_LU F E F G H H E F F G G E F E F U V(N) V(N) VI(N) VSSI(N) VQ(N) VSSQ(N) _Pr(FT_GPIO) Y(FT_GPIO) OMP_Pb(FT_GPIO) RE(FT_GPIO0) REb(N) GREEN(FT_GPIO) GREENb(N) LUE(FT_GPIO) LUEb(N) PRT OF RT/TVOUT TXOUT_L0P(N) TXOUT_L0N(N) TXOUT_LP(N) TXOUT_LN(N) TXOUT_LP(N) TXOUT_LN(G_GPIO0) TXOUT_LP(N) TXOUT_LN(G_GPIO) TXOUT_U0P(N) TXOUT_U0N(N) TXOUT_UP(PIE_RESET_GPIO) TXOUT_UN(PIE_RESET_GPIO) TXOUT_UP(N) TXOUT_UN(N) TXOUT_UP(PIE_RESET_GPIO) TXOUT_UN(N) INT_TXLOUT0 () INT_TXLOUT0- () INT_TXLOUT () INT_TXLOUT- () INT_TXLOUT () INT_TXLOUT- () T T0 INT_TXUOUT0 () INT_TXUOUT0- () INT_TXUOUT () INT_TXUOUT- () INT_TXUOUT () INT_TXUOUT- () T0 T0.V_N RX0 R R *.K_ *.K_ 0/ add K pull up to T /LK for RX0 / no stuff for RS0M/M/RX / stuff R.K for power play INT_RT_T INT_RT_LK () () () () () () INT_HSYN () INT_VSYN INT_RT_T INT_RT_LK () N_PWRG_IN NHT_REFLKP NHT_REFLKN () () () () () () EXT_N_OS.V_N NGFX_LKP NGFX_LKN NGPP_LKP NGPP_LKN SLINK_LKP SLINK_LKN.K_ R R IV@/F_.K_ R00 R0 0_ R 0_ INT_HSYN INT_VSYN INT_RT_T INT_RT_LK _RSET_N.V_PLLV.V_PLLV.V_VHTPLL.V_VPIEPLL N_PLTRST# N_PWRG_IN N_LT_STOP# N_LLOW_LTSTOP NHT_REFLKP NHT_REFLKN NGFX_LKP NGFX_LKN NGPP_LKP NGPP_LKN SLINK_LKP SLINK_LKN N_REFLK_P N_REFLK_N E F G H E 0 0 E F T T U U V V _HSYN(PWM_GPIO) _VSYN(PWM_GPIO) _S(PE_TLRN) _SL(PE_RLRN) _RSET(PWM_GPIO) PLLV(N) PLLV(N) PLLVSS(N) VHTPLL VPIEPLL VPIEPLL SYSRESETb POWERGOO LTSTOPb LLOW_LTSTOP HT_REFLKP HT_REFLKN REFLK_P/OSIN(OSIN) REFLK_N(PWM_GPIO) GFX_REFLKP GFX_REFLKN GPP_REFLKP GPP_REFLKN I I/O I/O GPPS_REFLKP(S_REFLKP) GPPS_REFLKN(S_REFLKN) I LOKs PM PLL PWR LVTM TXLK_LP(G_GPIO) TXLK_LN(G_GPIO) TXLK_UP(PIE_RESET_GPIO) TXLK_UN(PIE_RESET_GPIO) VLTP(N) VSSLTP(N) VLT_(N) VLT_(N) VLT_(N) VLT_(N) VSSLT(VSS) VSSLT(VSS) VSSLT(VSS) VSSLT(VSS) VSSLT(VSS) VSSLT(VSS) VSSLT(VSS) LVS_IGON(PE_TLRP) LVS_LON(PE_RLRP) LVS_EN_L(PWM_GPIO) 0 E0 E F G.V_VLTP_N.V_VLT N V_VLT_N INT_TXLLKOUT () INT_TXLLKOUT- () INT_TXULKOUT () INT_TXULKOUT- () /0 exchange LVS_PWM /LVS_LON INT_LVS_IGON () L_KLT_TRL () INT_LVS_LON () STRP_T R R *0K/F_.K_ selects Loading of straps from EPROM : use default vaule, default 0 : I Master can load strap values from EEPROM if connected, or use default values if not connected RX0 --RS0_UX_L RS0 -- SUS_TT V RS0_UX_L R RX0 *K_ () INT_LVS_EIT () INT_LVS_EILK (0) SVO_TRLT (0) SVO_TRLLK () V L LMPGSN N_ORE_ON INT_LVS_EIT INT_LVS_EILK IV_HMI_T IV_HMI_LK T0 T0 T0 V_V_N R0 0_ RS0_FT_GPIO STRP_T RS0_UX_L.V_N 0 G LMPGSN L I_T I_LK _T/UX0N(N) _LK/UX0P(N) UXP(N) UXN(N) STRP_T RSV UX_L(N) RS0(RX0).V_PLLV MIS. TMS_HP(N) HP(N) TVLKIN(PWM_GPIO) THERMLIOE_P THERMLIOE_N TESTMOE 0 E.V TMS_HP0 TMS_HP SUS_STT#_N R_N_THRM R_N_THRM TEST_EN R0.K/F_ T R 0_ T T0 R0 IV@0_ TMS_HP# (0) SUS_STT# () / RX connect to 0,0,,,,0, change to S0000J R *K_ Enables ebug us acess through memory T/O pads and GPIO. : Enable RX0, efault 0 : isable RX0 Enables ebug us acess through memory T/O pads and GPIO. : Enable RS0, efault 0 : isable RS0 (RS0 use VSYN#) Indicates if memory Side port is available or not 0: available RS0, efault : Not available RS0 ( RS0 use HSYN#) INT_VSYN INT_HSYN RX0 Reserved only R R R R RS0 K_ *K_ RS0 K_ *K_ 0/ RS0M atabook rev.0 define High disable V V V- nalog not applicable to RX0.V L LMPGSN 0U/.V_ PLLV - Graphics PLL not applicable to RX0.V VPIEPLL -PIE PLL L LMPGSN.V_PLLV 0mils width.v_vpiepll VHTPLL -HT LINK PLL L LMPGSN 0U/.V_ U/.V_ 0mils width.v_vhtpll.v / no stuff for RS0M/M 0.U/.V_.U/.V_ () () L (,) R 0_ LMPGSN PU_LT_STOP# PU_LT_REQ# LLOW_LTSTOP.V_VI_N.U/.V_.V_VQ_N.U/.V_.U/.V_ / voltage leakage issue remove Q,Q,R,R0,R stuff R,R Q *SS_NL/SOT PLLV - Graphics PLL not applicable to RX0 VI- igital not applicable to RX0 VQ- andgap Reference not applicable to RX0.V R 0_ RS0 Q *SS_NL/SOT R 0_.V R0 0_ RS0 VG_N VG_N R *.K_ R0 *.K_ N_LT_STOP# N_LLOW_LTSTOP L L LMPGSN.U/.V_ LMPGSN.U/.V_ RX0.V RS0 V 0 0.U/0V_ V.V_VLTP_N.V_VLT N R R VLTP - LVS or VI/HMI PLL not applicable to RX0 / RX no stuff them L,L,,L,R,L,L,L0, L *LMPGSN *0_ *0_ VLT - LVS or VI/HMI digital not applicable to RX0 V_VLT_N VLT - LVS or VI/HMI NLOG RS0 only 0 VG_N *.U/.V_ Quanta omputer Inc. PROJET : ZK Size ocument Number Rev RS0/RS0-SYSTEM I/F / Monday, ugust, 00 ate: Sheet of

12 UF E G G G H J R L L L L M N P R R R V U V V W W W W W Y E E E G E E J J K M L RX0/RS0 POWER IFFERENE TLE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE0 VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE0 VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE0 VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 PIN NME VHT VHTRX RX0.V.V RS0.V.V PIN NME IOPLLV V RX0 N N RS0.V.V PRT / GROUN VHTTX VPIE VG.V.V.V.V.V.V VI VQ PLLV N N N.V.V.V VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT0 VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT0 VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS V_MEM VPIE V N.V PLLV N.V.V VPIEPLL.V.V.V VHTPLL.V.V.V.V E G G G H J L L L L M0 N P0 R R R R H0 U V W W W Y L M N P P R R T U U U V W W Y E0 K V_MEM VG N N.V/.V.V VLTP VLT N N.V.V IOPLLV N.V VLT N N.V for - chip bug, - can remove.v L LMPGSN.V LMPGSN VPIE - PIE TX stage I/O for RX0/RS0 VHT - HT LINK digital I/O for RX0/RS0 VHTRX - HT LINK RX I/O for RX0/RS0.V_N 0..V for RS0MS00 0. VHTTX - HT LINK TX I/O for RX0/RS0.V for RS0MS00 00m L V - RS0 I/O transform.v for RS0M 0. L LMPGSN L LMPGSN.V.V 0U/._ 0U/._.U/.V_ 0.U/0V_ / del L stuff L for 0.U/.V_.U/.V_ 0.U/0V_ R0 0_ R 0_ V_MEM For UM RS0 only Not applicable to RX0 memory I/O transform 0 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.00 U/0V_ 0.00 *U/0V_.V_VHT 0.U/0V_.V_VHTRX 0.U/0V_.V_VHTTX 0.U/0V_ 0.U/0V_ 0.U/0V_.V_VPIE 0.U/0V_ 0.U/0V_ 0.U/0V_.V_VG_N.V_V_MEM / RX no stuff them R / RX connect to change to S0000J UE J VHT_ K VHT_ L VHT_ M VHT_ P VHT_ R VHT_ T VHT_ H VHTRX_ G VHTRX_ F0 VHTRX_ E VHTRX_ VHTRX_ VHTRX_ VHTRX_ E VHTTX_ VHTTX_ VHTTX_ VHTTX_ VHTTX_ Y0 VHTTX_ W VHTTX_ V VHTTX_ U VHTTX_ T VHTTX_0 R VHTTX_ P VHTTX_ M VHTTX_ J0 VPIE_ P0 VPIE_ K0 VPIE_ M0 VPIE_ L0 VPIE_ W VPIE_ H VPIE_ T0 VPIE_ R0 VPIE_ Y VPIE_0 VPIE_ VPIE_ VPIE_ E VPIE_ U0 VPIE_ RS0(RX0) PRT / POWER F VG_(V_) G VG_(V_) E V_MEM(N) V_MEM(N) VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_0 VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_MEM(N) V_MEM(N) V_MEM(N) V_MEM(N) V_MEM(N) V_MEM(N) VG_(N) VG_(N) E F G H J K M L P R T V U K J U J K M L L M M N N P P P R R T T U T J E0 Y H H.V_V_PIE 0 0.U/0V_ 0.U/0V_ 0 0.U/0V_.V_V_MEM V_VG 0.U/0V_ 0.U/0V_ 0.U/0V_ U/0V_ 0.U/0V_.V(0.) RS0 R 0_ 0. U/0V_ 0.U/0V_ 0U/.V_ 0/ follow M design guide.0 0.U/0V_ 0 0.U/0V_ 0.U/0V_ R0 R0 0_.V(0.0).V V V -.V I/O Not applicable to RX0 VPIE - PIE-E Main power R 0_.U/.V_.V_N / EMI stuff 0~0 for N_ORE *0_ V - ore Logic power 0U/.V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ N_ORE V_MEM For UM RS0 only Not applicable to RX0 memory I/O transform Quanta omputer Inc. PROJET : ZK Size ocument Number Rev RS0/RS0-POWER/ ate: Monday, ugust, 00 Sheet of

13 / reserve 00 PLTRST# () N_PLTRST# (,,,,,) PLTRST# R _ R _ PLTRST# PLE THESE PIE OUPLING PS LOSE TO U00 R *0M RST#_S R K_ R 0 p/0v_ *0.U/0V_ Y.V To RS0 RT_X RT_X (0) PIE_S_N_RX0P (0) PIE_S_N_RX0N (0) PIE_S_N_RXP (0) PIE_S_N_RXN (0) PIE_S_N_RXP (0) PIE_S_N_RXN (0) PIE_S_N_RXP (0) PIE_S_N_RXN (0) PIE_N_S_TX0P (0) PIE_N_S_TX0N (0) PIE_N_S_TXP (0) PIE_N_S_TXN (0) PIE_N_S_TXP (0) PIE_N_S_TXN (0) PIE_N_S_TXP (0) PIE_N_S_TXN.V_PIE_VR PIE_PV-- PIE PLL POWER.KHZ 0M_ test p/0v_ L () SSR_LKP () SSR_LKN () LK_M_S.V () LLOW_LTSTOP () PU_PROHOT_S# () PU_PWRG (,) PU_LT_STOP# () PU_LT_RST# T T T T T T R R R 0 LMPGSN T T T T T T T T T T T *K RST#_S 0.U/0V RX0P_ 0.U/0V RX0N_ 0.U/0V RXP_ 0.U/0V RXN_ 0.U/0V RXP_ 0.U/0V RXN_ 0.U/0V RXP_ 0.U/0V RXN_ PIE_N_S_TX0P PIE_N_S_TX0N PIE_N_S_TXP PIE_N_S_TXN PIE_N_S_TXP PIE_N_S_TXN PIE_N_S_TXP PIE_N_S_TXN /F_ PIE_LRP_S.0K/F_ PIE_LRN_S 0U/.V_ R (For S ).V_PIE_PV SSR_LKP SSR_LKN N_ISP_LKP N_ISP_LKN N_HT_LKP N_HT_LKN PU_HT_LKP PU_HT_LKN SLT_GFX_LKP SLT_GFX_LKN GPP_LK0P GPP_LK0N GPP_LKP GPP_LKN GPP_LKP GPP_LKN GPP_LKP GPP_LKN *0_ RT_X RT_X 0m U/0V_ T0 LLOW_LTSTOP PU_PROHOT_S# PU_PWRG PU_LT_STOP# PU_LT_RST# N U _RST# V PIE_TX0P V PIE_TX0N V PIE_TXP V PIE_TXN U PIE_TXP U PIE_TXN T PIE_TXP T PIE_TXN U PIE_RX0P U PIE_RX0N U PIE_RXP V PIE_RXN R0 PIE_RXP R PIE_RXN R PIE_RXP R PIE_RXN T PIE_LRP T PIE_LRN P P PIE_PV RT XTL PU Part of PI EXPRESS INTERFE N PIE_RLKP/N_LNK_LKP N PIE_RLKN/N_LNK_LKN P PU_HT_LKP M PU_HT_LKN M SLT_GFX_LKP M SLT_GFX_LKN J GPP_LK0P J GPP_LK0N L0 GPP_LKP L GPP_LKN M GPP_LKP M0 GPP_LKN PIE_PVSS K N_ISP_LKP K N_ISP_LKN M N_HT_LKP M N_HT_LKN 00MHZ N GPP_LKP P GPP_LKN L J J0 M_M_M_OS M_X M_X X X F LLOW_LTSTP F PROHOT# F LT_PG G LT_STP# G LT_RST# S00 LP RT LOK GENERTOR PI LKS PI INTERFE PILK0 PILK PILK PILK PILK PILK/GPIO PIRST# E0# E# E# E# FRME# EVSEL# IRY# TRY# PR STOP# PERR# SERR# REQ0# REQ# REQ# REQ#/GPIO0 REQ#/GPIO GNT0# GNT# GNT# GNT#/GPIO GNT#/GPIO LKRUN# LOK# INTE#/GPIO INTF#/GPIO INTG#/GPIO INTH#/GPIO LPLK0 LPLK L0 L L L LFRME# LRQ0# LRQ#/GNT#/GPIO MREQ#/REQ#/GPIO SERIRQ RTLK INTRUER_LERT# VT P P P P T T N PI_LK0_R PI_LK_R PI_LK_R PI_LK_R PI_LK_R PIRST#_L U P V T V U V V T W T R R R U U Y W V Y Y Y Y 0 W U Y W Y U W W V E PORT_# T E T T PE_GPIO E T LKRUN#_R V LOK# E E G E H H J J H H V INTE# INTF# INTG# INTH# LP_LK0 LP_LK L0 L L L LFRME# LRQ0#_S LRQ#_S S_GPIO SERIRQ T T RT_LK INTRUER_LERT# R0 _ R0 _ R _ R _ T T T T T T0 T R0 _ T T R 0_ () () () () () () R 0_ R _ R _ T PIRST# VPU T L0 (,) L (,) L (,) L (,) LFRME# (,) SERIRQ () RT_LK () VRT LKRUN# () PI_LK () PI_LK () PI_LK () PI_LK () PIRST# () ll the PI bus has build-in Pull-UP/own resistors RT T T PLK_EUG (,) PLK_ (,) VRT VRT H00H-0 VPU R K_ default PILK default GPIO H00H-0 N RT_T -00-P-L FH0MS PE_GPIO S_GPIO Maybe can remove RR = (V - 0.V-V)/0.m = k R.K/F_ R 0K/F_ R R R G R *SHORT_P R 0_ 0K_ 0 Q VRT_ MMT0 K/F_.K_ *.K_ V U/0V_ / R, change from k to 0. R change from K to K R,change from.k to.k R change form k to 0k 0 0.U/0V_ / voltage leakage remove R S00 I TRL(P) S00 (SELFG) P/N : JL0T00 0.U/0V_ Quanta omputer Inc. PROJET : ZK Size ocument Number Rev S00-PIE/PI/PU/LP / ate: Monday, ugust, 00 Sheet of

14 V_S V_S V_S V_S R R R V Z_SOUT Z_SYN Z_LK Z_RST# N only,an't be install R0 S_TEST0 S_TEST S_TEST *0K/F_ SWI# V SL0/ST0 is V tolerance M datasheet define it R R PLK_SM.K_ PT_SM SL/ST is V/S tolerance M datasheet define it R0 R0.K_.K_ S_SMLK S_SMT SL/ST is V/S tolerance M datasheet define it R R R.K_ S_SLK S_ST SUS_STT# SYS_RST# To zalia T T T () SUS# () SUS# () NSWON# () S_PWRG_IN () SUS_STT# 0/ add newcard ET# lock gen /R /MINI R/NEW R / Without Side-port NU Z_SYN_M () Z_SYN_UIO () (,) PU_MEMHOT# / NEW_ET# change from GEVEN# to GPM# R _ R _ R _ R _ R R R0 *.K_ *.K_ *.K_.K_.K_ G *.K_ *SHORT_ P K00HM-T_ K00HM-T_ 0 *0K_ R0 _ R _ Z_SOUT_M () Z_SOUT_UIO () /0 chagne VSUS to V_S IT_LK_M () IT_LK_UIO () Z_RST#_M () Z_RST#_UIO (,) () () () () () GTE0 RIN# E_SI# KSMI# (,,) PIE_WKE# () PU_THERMTRIP# () W_PWRG RSMRST# T00 T T T0 (,) NEW_LKREQ# T () PSPK (,,0,,,) PLK_SM (,,0,,,) PT_SM () PE_RESET_MXM# T T T T 0/ modify it /0 check it T T () USO# T () NEW_ET# (0) USO#0 / add, to avoid voltage leakage *0p/0V_ *0p/0V_ p/0v_ p/0v_ () Z_RST# H audio interface is.v voltage T T.V RI# SLP_S SUS# SUS# NSWON# S_PWRG_IN SUS_STT# S_TEST S_TEST S_TEST0 GTE0 RIN# E_SI# KSMI# RSMRST# PU_MEMHOT#_IN GPM# *S Z_LK Z_SOUT Z_SIN0_R Z_SIN_R Z_SIN_R Z_SYN Z_RST# SYS_RST# PIE_WKE# SWI# PU_THERMTRIP# W_PWRG G-sensor ST_IS ST_HOTPLUG R 0_ R 0_ R0 0_ H0H-0PT T T T R PLK_SM PT_SM S_SMLK S_SMT _SL_GPIO _S_GPIO LOW_ET *S R0 0_ *0K_ R R R0 *0K_ *0K_ M Suggestion / modify From 0K change to 0K *0K_ U E PI_PME#/GEVENT# E RI#/EXTEVNT0# H SLP_S/GPM# F SLP_S# G SLP_S# H PWR_TN# H PWR_GOO K SUS_STT# H TEST H TEST H TEST0 Y G0IN/GEVENT0# W KRST#/GEVENT# K LP_PME#/GEVENT# K LP_SMI#/EXTEVNT# F S_STTE/GEVENT# J SYS_RESET#/GPM# H WKE#/GEVENT# F LINK/GPM# J SMLERT#/THRMTRIP#/GEVENT# W N_PWRG RSMRST# US_O#/IR_TX/GEVENT# US_O#/IR_TX0/GPM# US_O#/IR_RX0/GPM# US_O#/IR_RX/GPM# E US_O#/GPM# F US_O#/GPM# E US_O0#/GPM0# H UIO US O INTEGRTE u S00 PI / WKE UP EVENTS E ST_IS0#/GPIO0 LK_REQ#/ST_IS#/GPIO SMRTVOLT/ST_IS#/GPIO W LK_REQ0#/ST_IS#/GPIO0 V LK_REQ#/ST_IS#/FNOUT/GPIO W0 LK_REQ#/ST_IS#/FNIN/GPIO0 W SPKR/GPIO SL0/GPO0# W S0/GPO# K SL/GPO# K S/GPO# 0 _SL/GPIO Y _S/GPIO LL#/GPIO Y SHUTOWN#/GPIO G R_RST#/GEVENT# M Z_ITLK M Z_SOUT J Z_SIN0/GPIO J Z_SIN/GPIO L Z_SIN/GPIO M Z_SIN/GPIO L Z_SYN M Z_RST# L Z_OK_RST#/GPM# H IM_GPIO0 H0 IM_GPIO H SPI_S#/IM_GPIO F IE_RST#/F_RST#/IM_GPO IM_GPIO E IM_GPIO E IM_GPIO IM_GPIO INTEGRTE u US MIS GPIO US. US.0 Part of USLK/M_M_M_OS US_ROMP US_FSP US_FSN US_FSP US_FSN US_HSP US_HSN US_HS0P US_HS0N US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HS0P US_HS0N IM_GPIO IM_GPIO IM_PWM0/IM_GPIO0 SL/IM_GPIO S/IM_GPIO SL_LV/IM_GPIO S_LV/IM_GPIO IM_PWM/IM_GPIO IM_PWM/IM_GPO IM_PWM/IM_GPO IM_GPIO IM_GPIO IM_GPIO0 IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO0 IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO0 IM_GPIO G E E F E H J0 E F 0 0 G H E E G G H H F F E0 E E E G0 G LK_M_US US_ROMP_S US_FSP US_FSN US_FSP US_FSN S_SLK S_ST S_SLK S_ST S_GPIO S_GPIO R0 LK_M_US () T T T T.K/F_ USP () USP- () USP0 () USP0- () USP () USP- () USP () USP- () USP () USP- () USP () USP- () USP (0) USP- (0) USP (0) USP- (0) USP (0) USP- (0) USP () USP- () USP () USP- () USP0 (0) USP0- (0) S_GPIO () S_GPIO () S_SLK () S_ST () SPI/LP define To TV To amera To WLN LK_M_US for EMI To Finger Printer To R REER To New ard OKING R *0_ *0p/0V_ To luetooth To M/ US To M/ US To M/ US/EST To M/ US 0/ US swap for layout route Z_SIN_R Z_SIN0_R V R _ R _ Z_SIN () Z_SIN0 () /EMI change Rfrom to K00HM-T stff 0 p V S00 R 0K_ R 0K_ LOW_ET LOW_ET ST_HOTPLUG R *K_ High : Main Strem Low : Low ost Quanta omputer Inc. PROJET : ZK Size ocument Number Rev S00-PI/GPIO/US / ate: Monday, ugust, 00 Sheet of

15 ST ST E-ST O () ST_TXP0 () ST_TXN0 () ST_TXP () ST_TXN (0) ST_TXP (0) ST_TXN () ST_TXP () ST_TXN ST PORT, are only support IE mode ST PORT 0,,, can support HI mode () ST_RXN0 () ST_RXP0 () ST_RXN () ST_RXP (0) ST_RXN (0) ST_RXP / change ST O from port to port (solve O post detect fail) () ST_RXN () ST_RXP 0.0U/V_ 0.0U/V_ 0.0U/V_ 0.0U/V_ 0.0U/V_ 0.0U/V_ 0.0U/V_ 0.0U/V_ PLE ST_L RES VERY LOSE TO LL OF S00 PLE ST OUPLING PS LOSE TO S00 ST_TXP0_R ST_TXN0_R 0 ST_TXP_R ST_TXN_R ST_TXP_R ST_TXN_R ST_TXP_R ST_TXN_R T0 T0 R R K/F_ () 0.0U/V_ 0.0U/V_ 0.0U/V_ 0.0U/V_ 0.0U/V_ 0.0U/V_ 0.0U/V_ 0.0U/V_ ST_LE# NOTE: PLV_ST-- R IS K % FOR MHz ST PLL XTL,.K % FOR 00MHz POWER INTERNL LOK T T ST_RXN0_ ST_RXP0_ ST_RXN_ ST_RXP_ ST_RXN_ ST_RXP_ ST_TXP_ ST_TXN_ ST_RXN_ ST_RXP_ ST_RIS_PN ST_LE# V_XTLV_ST ST_RXN_ ST_RXP_ ST_X ST_X.V_PLLV_ST XTLV_ST-- ST crystal power p/0v_ p/0v_ Y MHZ R 0M_ ST_X ST_X U ST_TX0P E ST_TX0N 0 ST_RX0N 0 ST_RX0P E0 ST_TXP 0 ST_TXN ST_RXN E ST_RXP ST_TXP ST_TXN E ST_RXN ST_RXP ST_TXP E ST_TXN ST_RXN ST_RXP E ST_TXP ST_TXN ST_RXN E ST_RXP ST_TXP ST_TXN E ST_RXN ST_RXP V Y W W ST_L ST_X ST_X ST_T#/GPIO PLLV_ST XTLV_ST S00 ST PWR SERIL T S00 Part of HW MONITOR ROM_RST# S_GPIO S_GPIO S_GPIO S_FNTH0 S_FNTH PORT_0_PWR_WN m 0 OR_I0 OR_I OR_I OR_I OR_I T T0 TEMPIN0 TEMPIN M_THRM_S TEMPIN_GPIO 0_ R T T0 T T0 T T T T V_V_HWM 0.U/0V_ T T T0 T T T T T M I Selection Table oard I NEW R R US FL Panel LE Panel W/ MXM W/O MXM W/ S-VIEO W/O S-VIEO W/ HMI W/O HMI R R R R R0 IV@K_ *K_ THERM_LERT# () V I H L OR_I0 I OR_I OR_I OR_I OR_I H L MXM_PRESENT# () V--H/W monitor nalog power M I I H L 0/ M suggest to connect to L H R R I 0K_ 0K_ I0 Mount R and Unmout R for non IR SKU L 0_ *K_ *K_ *K_ EMI FILTER HIP LMPGSN(0,.).U/.V_ R R R 0K_ 0K_ H L EV@0K_ V.V 0m) L0 LMPGSN.V_PLLV_ST IE_IORY IE_IRQ IE_0 IE_ IE_ IE_K# IE_RQ IE_IOR# IE_IOW# IE_S# IE_S# IE_0/GPIO IE_/GPIO IE_/GPIO IE_/GPIO IE_/GPIO IE_/GPIO0 IE_/GPIO IE_/GPIO IE_/GPIO IE_/GPIO IE_0/GPIO IE_/GPIO IE_/GPIO IE_/GPIO IE_/GPIO IE_/GPIO0 SPI_I/GPIO SPI_O/GPIO SPI_LK/GPIO SPI_HOL#/GPIO SPI_S#/GPIO LN_RST#/GPIO ROM_RST#/GPIO FNOUT0/GPIO FNOUT/GPIO FNOUT/GPIO FNIN0/GPIO0 FNIN/GPIO FNIN/GPIO TEMP_OMM TEMPIN0/GPIO TEMPIN/GPIO TEMPIN/GPIO TEMPIN/TLERT#/GPIO SPI ROM T /00/ 0/GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO0 V VSS Y Y Y Y E E0 0 E 0 0 E E G F F U J M M M P P R F G m / EMI stuff, for S HW MONITOR.U/.V_ 0.U/0V_ U/.V_ V m V_XTLV_ST L LMPGSN U/0V_ Place near ball Quanta omputer Inc. PROJET : ZK Size ocument Number Rev S00-ST/IE/HWM/SPI / ate: Monday, ugust, 00 Sheet of