SERVICE MANUAL HF/0MHz ALL MODE TRANSCEIVER ipro
INTRODUCTION This service manual describes the latest service information for the IC-PROII HF/0MHz ALL MODE TRANSCEIVER. VER. # # # # # #0 VERSION U.S.A. Europe France Italy Korea Spain SYMOL USA EUR FRA ITR KOR ESP DANGER NEVER connect the transceiver to an AC outlet or to a DC power supply that uses more than V. This will ruin the transceiver. DO NOT expose the transceiver to rain, snow or any liquids. DO NOT reverse the polarities of the power supply when connecting the transceiver. DO NOT apply an RF signal of more than 0 dm (00 mw) to the antenna connector. This could damage the transceiver s front end. To upgrade quality, any electrical or mechanical parts and internal circuits are subject to change without notice or obligation. ING PARTS e sure to include the following four points when ordering replacement parts:. 0-digit order numbers. Component part number and name. Equipment model name and unit name. Quantity required <SLE > 00000 S.IC NJMM IC-PROII MAIN-A UNIT pieces 0000 Screw ih M ZK IC-PROII Top cover 0 pieces Addresses are provided on the inside back cover for your convenience. REPAIR NOTES. Make sure a problem is internal before disassembling the transceiver.. DO NOT open the transceiver until the transceiver is disconnected from its power source.. DO NOT force any of the variable components. Turn them slowly and smoothly.. DO NOT short any circuits or electronic parts. An insulated tuning tool MUST be used for all adjustments.. DO NOT keep power ON for a long time when the transceiver is defective.. DO NOT transmit power into a signal generator or a sweep generator.. ALWAYS connect a 0 d to 0 d attenuator between the transceiver and a deviation meter or spectrum analyzer when using such test equipment.. READ the instructions of test equipment thoroughly before connecting equipment to the transceiver.
TALE OF CONTENTS SECTION SPECIFICATIONS SECTION INSIDE VIEWS SECTION CIRCUIT - RECEIVER CIRCUITS........................................................... - - TRANSMITTER CIRCUITS........................................................ - - PLL CIRCUITS................................................................. - - ANTENNA TUNER CIRCUITS..................................................... - - SCOPE CIRCUIT............................................................... - - POWER SUPPLY CIRCUITS...................................................... - - LOGIC CIRCUITS.............................................................. - 0 SECTION ADJUSTMENT PROCEDURES - PREPARATION EFORE SERVICING............................................... - - PLL ADJUSTMENT............................................................. - - TRANSMITTER ADJUSTMENT.................................................... - - RECEIVER ADJUSTMENT........................................................ - - TUNER ADJUSTMENT.......................................................... - - METER ADJUSTMENT.......................................................... - SECTION PARTS LIST SECTION MECHANICAL PARTS SECTION SEMI-CONDUCTOR INFORMATION SECTION OARD LAYOUTS - PT, RIT AND MIC OARDS...................................................... - - DISPLAY OARD............................................................... - - MODE, PHONE, KEY AND TEN-KEY OARDS........................................ - - RF-A UNIT.................................................................... - - PLL UNIT..................................................................... - - MAIN-A UNIT................................................................. - 0 - DSP-A, MEMORY AND PF OARDS.............................................. - - PA UNIT..................................................................... - - FILTER UNIT................................................................. - - 0 TUNER OARD............................................................... - - CTRL UNIT................................................................... - 0 SECTION LOCK DIAGRAM SECTION 0 VOLTAGE DIAGRAMS 0 - FRONT UNIT................................................................. 0-0 - DSP-A OARD................................................................ 0-0 - TUNER, MEMORY OARDS AND CTRL UNIT........................................ 0-0 - MAIN-A UNIT ().............................................................. 0-0 - MAIN-A UNIT ().............................................................. 0-0 - PLL UNIT.................................................................... 0-0 - PA AND FILTER UNITS......................................................... 0-0 - RF-A UNIT AND PF OARD..................................................... 0 -
SECTION SPECIFICATIONS GENERAL Frequency coverage: Receive 0.00 0.000 MHz*, * Transmit.00. MHz*.00. MHz*.000.00 MHz* 0.00 0.0 MHz*.000.0 MHz*.0. MHz*.000.0 MHz*.0.0 MHz*.000.00 MHz* 0.000.000 MHz* * Some frequency bands are not guaranteed. * Depending on version. Mode : US, LS, CW, RTTY, AM, FM Number of memory channels : 0 ( regular, scan edges) Antenna connector : SO- and phono [(RCA); 0 Ω] Usable temp. range: 0 C to +0 C ( F to F) Frequency stability : Less than ±0. ppm from min. after power ON. Freq. resolution : Hz Power supply :. V DC ± % (negative ground) requirement Current consumption: Transmit max. power A Receive stand-by.0 A (typical) max. audio. A (typical) Dimensions : 0 (W) (H) (D) mm (W) (H) (D) in Weight :. kg ( lb oz) ACC connector : -pin DIN connector ACC connector : -pin DIN connector CI-V connector : -conductor.(d) mm ( ") Display : -inch (diagonal) TFT color LCD TRANSMITTER Output power : SS/CW/RTTY/FM 00 W AM 0 W Modulation system : SS PSN modulation AM Low power modulation FM Phase modulation Spurious emission : Less than 0 d (HF bands) Less than 0 d (0 MHz band) Carrier suppression: More than 0 d Unwanted sideband suppression: More than d TX variable range : ±. khz Mic. connector : -pin connector (00 Ω) ELE-KEY connector: -conductor.(d) mm ( ") KEY connector : -conductor.(d) mm ( ") SEND connector : Phono (RCA) ALC connector : Phono (RCA) RECEIVER Receive system : Triple-conversion superheterodyne Intermediate frequencies: st IF frequency. MHz nd IF frequency khz rd IF frequency khz Sensitivity : SS, CW, RTTY (at. khz bandwidth).. MHz* 0. µv (0 d S/N) 0.0.0 MHz* 0. µv (0 d S/N) AM (at.0 khz bandwidth) 0.. MHz µv (0 d S/N).. MHz*.0 µv (0 d S/N) 0.0.0 MHz*.0 µv (0 d S/N) FM (at khz bandwidth).0. MHz* 0. µv ( d SINAD) 0.0.0 MHz* 0. µv ( d SINAD) * Pre-amp ON * Pre-amp ON Squelch sensitivity : (Pre-amp OFF) SS/CW/RTTY Less than. µv FM Less than.0 µv Selectivity : SS/RTTY (at. khz bandwidth) More than. khz/ d Less than. khz/ 0 d CW (at 00 Hz bandwidth) More than 00 Hz/ d Less than 00 Hz/ 0 d AM (at khz bandwidth) More than.0 khz/ d Less than.0 khz/ 0 d FM (at khz bandwidth) More than khz/ d Less than 0 khz/ 0 d Spurious and image: More than 0 d rejection ratio (except IF through in 0 MHz band) RIT variable range : ±. khz Audio output power : More than.0 W at 0 % distortion (at. V DC) with an Ω load PHONES connector: -conductor. (d) mm ( ") EXT SP connector : -conductor. (d) mm ( ") Ω ANTENNA TUNER Matching impedance range: HF bands. to 0 Ω unbalanced* 0 MHz band 0 to Ω unbalanced* * Less than VSWR :; * Less than VSWR.: Minimum operating input power: HF bands : W 0 MHz band : W Tuning accuracy : VSWR.: or less Insertion loss : Less than.0 d (after tuning) All stated specifications are subject to change without notice or obligation. -
SECTION INSIDE VIEWS TOP VIEW Fan control circuit FAN TUNER unit Antenna tuner CPU (IC: M0M-FP) PA unit Drive amplifier FILTER unit Common filter (L0, L0: LR-) CTRL unit Current transformer (L: LR-) C-MOS IC (IC: TCAC0F) -
OTTOM VIEW VCO- circuit VCO-A circuit PLL unit MEMORY board DSP-A board PF board YGR amplifier (IC: µpcg) Pre amplifier (IC: µpcg) FM IF IC (IC: TAFN) Ceramic filter (FI: CFJK) RF-A unit Optional unit UT-0 nd IF filter (FI: CFKE0) rd mixer (IC: TCWFU) MAIN-A unit -
SECTION CIRCUIT - RECEIVER CIRCUITS -- RF SWITCHING CIRCUIT (CTRL AND RF-A UNITS) The RF switching circuit leads receive signals to bandpass filters from an antenna connector while receiving. However, the circuit leads the signal from the RF power amplifier to the antenna connector while transmitting. RF signals from [ANT ] or [ANT ] pass through the antenna selector (RL), transmit/receive switching relays (RL, RL, RL), and low-pass filter (L, L, C C, C0), and are then applied to the RF-A unit via J. The signals from the CTRL unit either bypass or pass through the d (RF-A unit, RL, R) and/or d (RF-A unit, RL, R) attenuators via the antenna selector (RL0). y selecting the attenuators, 0 (bypass),, and d attenuations are obtained. The signals are then applied to the RF filters. When the [RX ANT] is selected, the RF signals are passed through the low-pass filter (RF-A unit, L, L, C C), then applied to the antenna selector (RF-A unit, RL0). -- RF ANDPASS FILTER CIRCUIT (RF-A UNIT AND PF OARD) RF bandpass filters pass only the desired band signals and suppress any undesired band signals. The RF circuit has bandpass filters and low-pass filter. () 0.0. MHz (PF OARD) The signals pass through the low-pass filter (L L, C C), attenuator (R R), and are then applied to the RF amplifiers (Q0, Q0). (). 0 MHz (RF-A UNIT AND PF OARD) The signals pass through the high-pass filter (L L, C C) to suppress excessively strong signals below. MHz. The filtered signals are applied to one of bandpass filters on the table at right above, and then applied to or bypassed the pre-amplifier circuit. Used RF filter Control and signal 0.0. MHz. MHz MHz MHz MHz MHz MHz 0 * : On the PF board Input diode N/A *D00 *D0 *D0 *D0 *D0 D and MHz MHz 0 MHz 0 0 MHz 0 MHz 0 MHz Control signal 0W 0 0W Input diode D D0 D D D D -- PRE-LIFIER CIRCUITS (RF-A UNIT) The IC-PRO has gain levels of pre-amplifier circuits. One has 0 d gain for the. MHz bands and the other one has d gain for the upper MHz bands. When the [P.] switch is set to [P. ] or [P. ], the signals are applied to the pre-amplifier (Q, Q) or pre-amplifier (IC) circuit, respectively. Pre-amplified or bypassed signals are applied to the RF amplifier circuits (Q0, Q0 and Q0, Q0). -- RF LIFIER AND ST MIXER CIRCUITS (RF-A UNIT) The st mixer circuit mixes the receive signals with the st LO signal to convert the receive signal frequencies into a. MHz st IF signal. The IC-PRO has two st mixer circuits for the dualwatch function. The signals from the pre-amplifier circuit, or signals which bypass the pre-amplifiers, are divided at L. Each signal is applied to a 0 MHz cut-off low-pass filter, RF amplifier (Q0, Q0 and Q0, Q0) and then to a st mixer (Q Q or Q Q). Each st LO signal (.0.0 MHz) enters the RF -A unit from the PLL unit via J or J. The LO signals are amplified at the LO amplifier (Q or Q), filtered by a low-pass filter, and then applied to each st mixer. Receiver construction LPF or PF 0.0 0.0 MHz st mixer Q Q st LO FIa/b Crystal filter. MHz st mixer A Q Q st LO A nd mixer Q Q nd LO.0 MHz RF-A UNIT FI, FI Ceramic filter khz MAIN-A UNIT rd mixer IC khz DSP-A board rd LO khz to squelch gate (IC0) -
-- ST IF CIRCUIT (RF-A UNIT) The st IF circuit filters and amplifies the st IF signal. The st IF signal combined at L is applied to a pair of MCF (Monolithic Crystal Filter; FIa/b) to suppress out-of-band signals. The level of converted st IF signal is adjusted at the PIN attenuators (D D, D or D D, D) controlled by the [AL] controller for the dualwatch function. The signal is applied to the st IF amplifier (Q or Q) and then combined at L. The combined signal passes through the d attenuator (R R) and MCFs (FIa/b). The signal is amplified at the st IF amplifier (Q). The amplified signal is then applied to the nd mixer circuit. -- ND MIXER CIRCUIT (RF-A UNIT) The nd mixer circuit mixes the amplified st IF signal and nd LO signal (.00 MHz) for conversion into the nd IF signal. The st IF signal from the st IF amplifier (Q) is converted into a khz nd IF signal at the nd mixer circuit (D). The nd IF signal is applied to the noise blanker gate (MAIN- A unit) via the J. -- NOISE LANKER CIRCUIT (MAIN-A UNIT) The noise blanker circuit detects pulse-type noise, and turns OFF the signal line when the noise appears. The nd IF signal from the RF-A unit is applied to the noise blanker gate (D, D). A portion of the nd IF signal from RF-A unit is amplified at the noise amplifiers (Q Q, Q), and is then detected at the noise detector (D) to convert the noise components to DC voltages. The signal is then applied to the noise blanker switch (Q, Q). At the moment the detected voltage exceeds Q s threshold level, Q outputs a blanking signal to close the noise blanker gate (D, D). The PLL unlock signal are also applied to Q, to control the noise blanker gate. Some DC voltage from the noise detector circuit is fed back to the noise amplifiers (Q Q) via the DC amplifiers (Q, Q). The DC amplifiers function as an AGC circuit to reduce average noise. Therefore, the noise blanker function shuts off pulse-type noise only. -- ND IF CIRCUIT (MAIN-A UNIT) The nd IF circuit amplifies and filters the nd IF signal, and applies the nd IF signal to the rd mixer circuit. The nd IF signal from the noise blanker gate (D, D) is amplified at the nd IF amplifier (Q) and passed through the ceramic filter (FI). The filtered signal is applied to the rd mixer circuit. -- RD MIXER AND RD IF CIRCUITS (MAIN-A UNIT) The rd mixer circuit mixes the nd IF signal and the rd LO signal to obtain the rd IF ( khz) signal. The nd IF signal from the ceramic filter (FI) is applied to the rd mixer circuit (IC, pin ). The rd LO signal from the PLL unit is applied to the rd mixer (IC, pin ). The mixed signal is output from pin. The rd IF signal is passed through the low-pass filter (IC0a) and amplified at the rd IF amplifier (IC0b). The filtered and amplified signal is then applied to the DSP-A board via DRIF line. --0 DSP RECEIVER CIRCUIT (DSP-A OARD) The DSP (Digital Signal Processor) circuit enables digital IF filter, digital noise reduction, digital PSN (Phase Shift Network)/Low Power/Phase demodulation, digital automatic notch, and etc. The khz rd IF signal from the rd IF amplifier (MAIN-A unit, IC0b) is amplified at the differential amplifiers (IC0a/b) after being passed through the T/R switch (IC), and is then applied to the A/D converter (IC). The coverted signal is level shifted V to. V at the level converter (IC0). DSP receiver circuit rd IF signal DRIF khz IC TXS signal IC0b/a Differential converter IC A/D converter IC0 Level converter IC00 DSP IC IC0 Level converter IC D/A converter T/R switch MAIN-A unit DSP-A board ICx ICz MAIN-A unit IC0 ICa ICy ICb IC Mixer DRAF LPF HPF AF amplifier signals TXS signal 0 TXS signal -
The level shifted signal is applied to the DSP IC (IC00) for khz digital IF filter, demodulation, automatic notch and noise reduction, etc. The output signal is level shifted. V to V at the level converter (IC0), and is applied to the D/A converter (IC) to convert into the analog audio signals. The converted audio signals are passed through the active filter (ICa), AF amplifier (ICb), analog switches (IC, pins, and pins, ) then applied to the lowpass filter (IC0). The filtered signals are passed through the analog switches (IC, pins, and IC, pins, ), high-pass filter (ICA) and mixer amplifier (ICA), and then applied to the MAIN-A unit via J00 (pin ) as the DRAF signal. -- TWIN PT CIRCUIT (DSP-A OARD) General PT (Passband Tuning) circuit shifts the center frequency of IF signal to electronically narrow the passband width. The IC-PRO uses the DSP circuit for the digital PT function and actually shifts the both lower and higher passbands of rd IF filter within ±. khz. The twin PT circuit in DSP IC (IC00) controlled by the [TWIN PT] controller adjusts the rd IF passband width and rejects interference. -- AGC CIRCUIT (DSP-A OARD) The AGC (Automatic Gain Control) circuit reduces IF amplifier gain and attenuates IF signal to keep the audio output at a constant level. The receiver gain is determined by the voltage on the AGC line (IC, pin ). The D/A converter for AGC (IC) supplies control voltage to the AGC line and sets the receiver gain with the [RF/SQL] control. The rd IF signal from the level converter (IC0) is detected at the AGC detector section in DSP IC (IC00), and is applied to the D/A converter for AGC via the level converter (IC0). The AGC voltage is amplified at the buffer amplifier (ICb) and is applied to the MAIN-A unit to control the AGC line. When receiving strong signals, the detected voltage increases and the AGC voltage decreases via the buffer amplifier (ICb). As the AGC voltage is used for the bias voltage of the IF amplifier (RF-A unit; Q), IF amplifier gain is decreased. -- S-METER CIRCUIT (MAIN-A UNIT) The S-meter circuit indicates the relative received signal strength while receiving by utilizing the AGC voltage which changes depending on the received signal strength. A portion of the AGC bias voltage from the DSP-A board is applied to the differential amplifier (IC0a, pin ) where the difference between the AGC and reference voltage is detected. The detected voltage is passed through the analog switch (IC, pins, ) as the SML signal and applied to the main CPU (IC0, pin 0) to activate the S/RF meter via the sub CPU (IC0) on the DISPLAY board. -- SQUELCH CIRCUIT (MAIN-A UNIT) The squelch circuit mutes audio output when the S-meter signal is lower than the [RF/SQL] setting level. The S-meter signal is applied to the main CPU (IC0, pin 0) and is compared with the threshold level set by the [RF/SQL] control. The [RF/SQL] setting signal is applied to the main CPU via the sub CPU (DISPLAY board; IC0, pin ). The main CPU analyzes the compared signal and outputs control signal to the squelch gate (IC0, pin ) via the interface IC (IC, pin ) to open or close the squelch as the SQLS signal. -- AF LIFIER CIRCUIT (MAIN-A UNIT) The AF amplifier amplifies the audio signals to a suitable driving level for the speaker. The AF signals (DRAF) from the DSP-A board are passed through the squelch gate (IC0) and amplified at the AF amplifier section of IC (pins, ), and volume is controlled by the AFGV signal at the VCA section (pins ). The volume controlled AF signals are passed through the AF mute gate (IC, pins, ), then applied to the AF power amplifier (IC, pin ) via the ripple filter (Q). The amplified audio signals are passed through the [PHONES] and [EXT SP] jacks then applied to the internal speaker when no plug is connected to the jacks. The AF mute gate is controlled by the [AF] control via the sub and main CPUs. AF amplifier circuit DRAF SQLS signal IC0 IC VCA Squelch gate AFGV signal IC Mute switch AFMS signal Q Ripple filter AF power amp. IC [PHONES] [EXT SP] DSP-A board MAIN-A unit Int. speaker -
- TRANSMITTER CIRCUITS -- MICROPHONE LIFIER CIRCUIT (MAIN-A UNIT) The microphone amplifier circuit amplifies microphone audio signals to a level needed for the DSP circuit. Audio signals from the [MIC] connector (MIC board; J, pin ) are amplified at the audio amplifier section in IC (pins, ) via the analog switch (IC00, pins, ), then applied to the buffer amplifier section (IC, pin ) and VCA section. The gain controlled signals are output from (IC, pin ) and passed through the analog switch (IC00, pins, ) and then applied to the DSP circuit as the DTAF signal. The VCA section in IC (pins ) controls microphone input gain according to the [MIC GAIN] control level using the MIGV signal coming from the main CPU via the I/O expander (IC, pin ). -- VOX CIRCUIT (MAIN-A UNIT) The VOX (Voice-Operated Transmission) circuit sets transmitting conditions according to voice input. A portion of the amplified audio signals from the AF amplifier section in IC are again amplified at the VOX amplifier section IC (pin ), also gain contolloed signals at the VCA section (pin ) are amplified at the AF amplifier (IC00b, pins, ), and then applied to the main CPU (IC0, pin 0) after passing through the analog switch (IC, pins, ) as the VOXL signal. The VOGV signal is applied to the VCA section in IC00 (pin ) from the main CPU via the I/O expander (IC, pin ) to adjust VOX actionable sensitivity. This is controlled by the VOX gain set in the VOX SET mode. -- DSP TRANSMITTER CIRCUIT (DSP-A OARD) The microphone audio signals from the MAIN-A unit via the DTAF line are applied to the analog switch (IC0, pin ) and output from pin or to the each modulation circuits. () When SS mode The audio signals from the analog switch (IC0, pin ) are amplified at the limitter amplifier (ICb) and applied to the low-pass filter (ICd/c) to limit the transmit passband width. The filtered signals are then applied to the differential amplifiers (IC0a/b) via the analog switch (IC0) and T/R switch (IC). () When FM/AM modes The audio signals from the analog switch (IC0, pin ) are applied to the modulation adjustment pots (R: FM mode, R: AM mode) via the limitter amplifier, preemphasis circuit (only FM mode) and splatter filter consist of IC. The level adjusted signals are applied to the differential amplifiers (IC0a/b) after being passed through the analog switch (IC0) and T/R switch (IC). The preemphasis circuit is cancelled by Q0, Q0, Q on AM mode. The amplified signals at the differential amplifiers (IC0a/b) are applied to the A/D converter (IC). The coverted signals are level shifted V to. V at the level converter (IC0). The level shifted signal is applied to the DSP IC (IC00) and modulated at the DSP IC to produce the khz transmitter IF signal. The modulated IF signal from the DSP IC is level shifted. V to V at the level converter (IC0), and is applied to the D/A converter (IC) to convert into the analog IF signal. The converted IF signal is passed through the active filter (ICa), buffer amplifier (ICb), analog switch (IC, pins, ) then applied to the low-pass filter (ICd/c). The filtered signal is applied to the MAIN unit via J00 (pin ) as the DTIF signal. When SS or RTTY mode, a portion of the filtered signal from the low-pass filter (ICd/c) is amplified at the IF and buffer amplifiers (ICb/c) and is applied to the transmit monitor circuit for the monitor function. -- SPEECH COMPRESSOR CIRCUIT (DSP OARD) The speech compressor compresses the transmitter audio input signals to increase the average output level (average talk power). When the speech compressor function is ON, the level shifted signal from the level converter (IC0) is applied to the DSP IC (IC00) and compressed at the DSP IC to obtain an average audio level. At the same time, the compressed signals are modulated at the DSP IC and applied to the level converter (IC0). Transmitter construction IC00x MIC VCA IC MOSL signal DTAF DSP-A board khz IF IC DTIF khz rd LO ( khz) FM/AM modes other modes FI Ceramic filter FI Ceramic filter MAIN-A UNIT D. khz nd LO (.00 MHz) FI Crystal filter andwidth khz D st LO LPF RF-A UNIT PFs -
-- IF LIFIER AND MIXER CIRCUITS (MAIN-A AND RF-A UNITS) The modulated rd IF signal from the DSP-A board (DTIF: khz) is applied to the rd mixer circuit (MAIN-A unit; IC, pin ). The applied rd IF signal is mixed with the rd LO signal from the DDS circuit (PLL unit; IC0) to produce a khz nd IF signal. The nd IF signal is output from pin and amplified at the IF amplifier (MAIN-A unit; Q). The amplified signal is passed through the ceramic bandpass filter (MAIN-A unit; FI: FM/AM modes, FI: other modes) for unwanted signals are suppressed. The filtered nd IF signal is ampllified at IF amplifier (MAIN-A unit; Q) and applied to the nd mixer circuit on the RF-A unit via J0. The nd IF signal is mixed with the MHz nd LO signal, coming from the PLL unit, at the nd mixer circuit (RF-A unit; D) to obtain a. MHz st IF signal. The st IF signal is passed through the MCFs (RF-A unit; FIa/b) to cutoff the undesired signals then amplified at the IF amplifier (RF-A unit; Q) via the T/R switch (RF-A unit; D). The amplified st IF signal is applied to the st IF mixer circuit (RF-A unit; D). The operating (transmitting) frequency is produced at the st IF mixer circuit (RF-A unit; D) by mixing the st IF and st LO signals. The mixed signal is then applied to the RF circuit. -- RF CIRCUIT (RF-A AND PA UNITS) The RF circuit amplifies operating (transmitting) frequency to obtain 00 W of RF output. The signal from the st IF mixer is passed through the lowpass filter (RF-A unit; L, L, C C) and amplified at the RF amplifier (RF-A unit; IC). The amplified signal is again amplified at the wide-band YGR amplifier (RF-A unit, IC) after passing through one of bandpass (Refer to page - for bandpass filters used) and high-pass filters, and is then applied to the PA unit via J. The signal applied from the RF-A unit is amplified at the predrive (Q), drive (Q, Q) and power amplifiers (Q, Q) in sequence to obtain a stable 00 W of RF output power. The amplified signal is applied to one of low-pass filters in the FILTER unit. -- LOW-PASS FILTER CIRCUIT (FILTER UNIT) The low-pass filter circuit contains Chebyschev low-pass filters to suppress the higher harmonic components. The signal from the power amplifiers on the PA unit is applied to one of low-pass filters, which is selected by the I/O expander (IC) in the CTRL unit via the buffer amplifier (CTRL unit; IC). The filtered signal is then applied to one of antenna connectors via the CTRL only/and TUNER unit/s. -- ALC CIRCUIT (MAIN-A UNIT) The ALC (Automatic Level Control) circuit controls the gain of IF amplifiers in order for the transceiver to output a constant RF power set by the [RF POWER] control even when the supplied voltage shifts, and etc. The RF power level is detected at one of the APC detector circuits (CTRL unit; D) to be converted into DC voltage and applied to the MAIN-A unit as the FORV signal. The FORV signal from the CTRL unit is applied to the comparator (ICb, pin ). The POCV signal, controlled by the [RF POWER] control via the I/O expander (IC, pin ), is also applied to the other input (pin ) for reference. The compared signal is output from pin and applied to the IF amplifiers in the MAIN-A (Q) and RF-A (Q) units to control amplifying gain. When the FORV signal exceeds the POCV voltage, ALC bias voltage from the comparator controls the IF amplifiers. This adjusts the output power to a specified level from the [RF POWER] control until the FORV and POCV voltages are equalized. In AM mode, the comparator operates as an averaging ALC amplifier. Q0 turns ON and the POCV voltage is shifted for 0 W AM output power (maximum) through R0. DSP Transmitter circuit AF signal IC0z DTAF Mode switch SS mode FM/AM mode MODS signal ICb Limitter ICa Limitter ICc/d LPF ICb LPF IC IC0x T/R switch Mode switch TXS signal IC0a/b Differential converter MAIN-A unit IC A/D converter DSP-A board IC0 Level converter IC00 DSP IC IC0 Level converter IC D/A converter TXS signal ICx ICd/c LPF DTIF khz IF MAIN-A unit -
The ALC bias voltage is also applied to the ALC meter amplifier (ICa, pin ) to obtain an ALC meter signal (ALCL). The amplified signal is passed through the analog switch (IC, pins, ) and applied to the main CPU (IC0, pin 0) to drive the S/RF meter via the sub CPU (IC0) on the DISPLAY board. An external ALC input from the [ALC] jack or [ACC] sockets is applied to the buffer amplifier (Q). External ALC operation is identical to that of the internal ALC. The FORV signal is also applied to the power meter amplifier (ICa, pin ). The amplified signal is passed through the analog switch (IC, pins, ) as an FORL signal and applied to the main CPU (IC0, pin 0) to drive the S/RF meter when the power meter is selected. -- APC CIRCUIT (MAIN-A UNIT) The APC (Automatic Power Control) circuit protects the power amplifiers on the PA unit from high SWR and excessive current. The reflected wave signal appears and increases when the connected antenna is mismatched to 0 Ω. The APC detector circuit (CTRL unit; D and L) detects the reflected signal, and applies it to the APC circuit (ICc, pin ) as a V signal. When the V signal level increases, the APC circuit decreases the ALC voltage to activate the APC. For the current APC, the power transistor current is obtained by detecting the voltages (ICH and ICL) which appear at both terminals of the current detector (PA unit; R). The detected voltages are applied to the differential amplifier (ICd, pins, ). When the current of transistors is increased, the amplifier controls the ALC line to prevent excessive current flow. A portion of the V signal is applied to the SWR meter amplifier (ICb, pin ). The amplified signal is passed through the analog switch (IC, pins, ) as an L signal and applied to the main CPU (IC0, pin 0) to drive the S/RF meter when the SWR meter is selected. --0 TEMPERATURE PROTECTION CIRCUIT (PA UNIT) The cooling fan (CHASSIS; MF) is activated while transmitting or when the temperature of the power amplifier exceeds the preset value. The temperature protection circuit consists of Q0 Q and R0. While transmitting, Q0 and Q are turned ON, and provide a voltage to the cooling fan to rotate at medium speed. The thermistor (R0) detects the temperature of the final amplifier (Q), and activates Q and Q to accelerate the cooling fan when the detected temperature exceeds 0 C ( F). The cooling fan rotates at high speed at 0 C ( F) or more. The thermistor keeps the cooling fan rotating even while receiving until the Q temperature drops to 0 C (0 F) or below. -- MONITOR CIRCUIT (DSP-A OARD AND MAIN-A UNIT) The microphone audio signals can be monitored to check voice characteristics. () When FM/AM modes (MAIN-A UNIT) A portion of the microphone audio signals from the VCA section in IC are applied to the analog switch (IC). The selected audio signals are applied to IC (pin ), and the output signals from pin are applied to the AF amplifier circuit (IC, pin ). () When SS/RTTY modes (DSP-A OARD) A portion of the transmit IF signal from the low-pass filter (ICd/c) is amplified at the IF (ICb) and buffer (ICa) amplifiers, and applied to the digital mixer circuit (IC0). The applied signal is mixed with a khz LO signal from the D/A converter (IC) to demodulate into the AF signals. The demodulated signals are passed through the buffer amplifier (ICa), low-pass filter (ICb/c) and AF amplifier (ICd), and then applied to the MAIN-A unit as the DMAF signal. The DMAF signal from the DSP-A board is amplified at the ALC amplifier (MAIN-A unit; IC, pins, ) and applied to the VCA section of IC (MAIN-A unit; pins, ). The volume controlled AF signals is applied to the AF amplifier circuit (MAIN-A unit; IC, pin ). - PLL CIRCUITS -- GENERAL The PLL unit generates a pair of st LO frequencies (.. MHz) for dualwatch and spectrum scope functions; a nd LO frequency ( MHz), rd LO frequency ( khz) and sweep LO frequency for the spectrum scope function. The st LO PLLs adopt a mixer-less dual loop PLL system and has VCO circuits. The LOs, except the nd, use DDSs while the nd LO uses the fixed frequency of the crystal oscillator. -- ST LO PLL CIRCUIT The st LO PLLs contain a main and reference loop as a dual loop system. oth PLLs have equivalent circuits this manual describes only the st LO PLL A circuit. The reference loop generates a 0. to 0. MHz frequency using a DDS circuit, and the main loop generates a. to. MHz frequency using the reference loop frequency. () EREE LOOP PLL The oscillated signal at the reference VCO (Q, D) is amplified at the buffer amplifiers (Q, Q0) and is then applied to the DDS IC (IC0, pin ). The signal is then divided and detected on phase with the DDS generated frequency. The detected signal output from the DDS IC (pin ) is converted into DC voltage (lock voltage) at the loop filter (R R, C, C) and then fed back to the reference VCO circuit (Q, D). -
() MAIN LOOP PLL The oscillated signal at one of the main loop VCOs (Q0, D0, D0), (Q, D, D), (Q, D D) and (Q, D D) is amplified at the buffer amplifiers (Q0, IC0) and is then applied to the PLL IC (IC, pin ) via the low-pass filter (L0, C0 C0). The signal is then divided and detected on phase with the reference loop output frequency. The detected signal output from the PLL IC (pin ) is converted into a DC voltage (lock voltage) at the loop filter and then fed back to one of the VCO circuits (Q0, D0, D0), (Q, D, D), (Q, D D) and (Q, D D). The oscillated signal is amplified at the buffer amplifiers (Q0, IC0) and then applied to the RF-A unit as a st LO A signal after being passed through the low-pass filters (L0, C0 C0 and L L, C C) and highpass filter (L, C C0) and mute circuit (D). -- ND LO AND EREE OSCILLATOR CIRCUITS The reference oscillator (X, Q) generates a.000 MHz frequency for the DDS circuits as a system clock and for the LO output. The oscillated signal is doubled at the doubler circuit (Q, Q) and the.0 MHz frequency is picked up at the double tuned filter (L, L). The.0 MHz signal is applied to the RF-A unit as a nd LO signal. -- RD LO CIRCUIT The DDS IC (IC0) generates a 0-bit digital signal using the MHz system clock. The digital signal is converted into an analog wave signal at the D/A converter (R0 R0). The converted analog wave is passed through the bandpass filter (L0, L0, C0 C) and then applied to the MAIN-A unit as the rd LO signal. -- MARKER CIRCUIT The divided signal at the DDS circuit (IC0) is used for the marker signals with the IC-PRO. The reference signal for the DDS circuit (.0 MHz) is divided to produce an acceptable frequency signal, MHz, with the programmable divider then divided again by 0 to obtain 00 khz cycle square-wave signals. The generated marker signals are output from pin of the DDS IC (IC0), and are then applied to the RF unit via the mute switch (IC) and J as the MKR signal. PLL CIRCUIT ANT st mixer A Q Q RF-A unit. MHz nd mixer D MAIN-A unit rd mixer IC Crystal filter to DSP-A board LOA Q0 Q Q Q.. MHz /N divider st LO PLL A circuit Main loop PLL st mixer LO.0 MHz.. MHz PLL unit LO khz LO to scope circuit (RF-A unit, IC) SLO. MHz to scope circuit (RF-A unit, D) SLO IC Ref. loop PLL Q Phase detector 0. 0. MHz / bit D/A st LO PLL circuit PF Q Q PF D/A LPF D/A LPF Loop filter Q0. MHz IC0 Phase detector DDS DDS IC0 DDS IC0 PLL IC IC0 Reference oscillator X:.0 MHz -
- ANTENNA TUNER CIRCUITS -- MATCHING CIRCUIT (TUNER UNIT) The matching circuit is a T-network. Using tuning motors, the matching circuit obtains rapid overall tuning speed. Using relays (RL RL), the relay control signals from the antenna tuner CPU (CTRL unit; IC) via the buffer amplifier (IC, IC) ground one of the taps of L L and add capacitors (C C). After selecting the coils and capacitors, motors (CTRL unit; MF, MF) adjust C and C using the antenna tuner CPU (CTRL unit; IC) and the motor controller (CTRL unit; Q Q, D, D, D, D) to obtain a low SWR (Standing Wave Ratio). -- DETECTOR CIRCUIT (CTRL UNIT) () SWR detector Forward and reflected power are picked up by a current transformer (L), detected by D and D, and then amplified at ICa and ICb, respectively. The amplified voltages are applied to the antenna tuner CPU (IC, pins, ). The tuner CPU detects the SWR. () Reactance components detector Reactance components are picked up by comparing the phases of the RF current and RF voltage. The RF current is detected by L and R and buffer-amplified at ICe and ICa and then applied to the phase comparator (ICa). RF voltages are detected by C C and then applied to the phase comparator (ICb) after being amplified at the buffer amplifiers (ICc, ICb). The output signal from the phase comparator (ICa, pin for RF current, ICb pin for RF voltage) is rectified at D and D for conversion into DC voltage. The rectified voltage signals are combined, then amplified at the inverter amplifier (ICb), then applied to the antenna tuner CPU (IC, pin ). A C-MOS IC is used for the buffer amplifier (IC) to improve functionable sensitivity; the inverter amplifier (IC) is very responsive even with a low signal level input. Together, these ensure quick and stable signal detection even at low RF signal level input. () Resistance components detector Resistance components are picked up by L, and detected by D, D and Q. The detected resistance components are amplified at the inverter amplifier (ICa), and then applied to the antenna tuner CPU (IC, pin ). -- MOTOR CONTROL CIRCUIT (CTRL AND TUNER UNITS) The control circuit of the internal antenna tuner consists of the CPU, EEPROM (Electronically-Erasable Programmable Read Only Memory), tuning motors and tuning relays. () Tuning relays (TUNER unit) According to the operating frequency band and antenna condition, tuning relays select the capacitors and coils. -- ANTENNA TUNER CPU PORT ALLOCATION (CTRL unit; IC) Pin Port number name Description R FOR PWRS Input port for the resistance components detection voltage. Input port for the reflected RF power voltage. Inpout port for the forward RF power voltage. Input port for the transceiver power OFF. Inputs low level signal when operating STDU the antenna tuner in 0 MHz band., SETI KEY START THRU SEND CL, CL Input port for reference voltage setting. Outputs tuner data signal. Input port for the serial signal. Input port for the [TUNER] ON/OFF signal. Input port for the TX/RX switching signal. Input port for the antenna tunner CPU system clock. Outputs the coil selection signal. DUAL High : While 0 MHz band is displayed. 0 LM, LM, LM, L0M, LM, L.M CO, CO, CO, CI, CI, CI PZ, PY, PX, PW, RZ, RY, RX, RW P Output the coil selection signal. Output the capacitor selection signal. Output pulse-type control signals for the tuning motors (MF, MF). Input port for the reactance components detection voltage. () CPU and EEPROM (CTRL unit) The antenna tuner CPU (IC) controls the tuning motors via the motor controller (Q Q, D, D, D, D) and tuning relays, and memorizes the best preset position in 00 khz steps. The memory contents are stored in the EEP- ROM (IC) without a backup battery. () Tuning motors (CTRL and TUNER units) A motor controller (Q Q, D, D, D, D) rotates the tuning motors (TUNER unit; MF, MF) to obtain a low SWR. -
- SCOPE CIRCUITS -- SCOPE RECEIVER CIRCUIT (RF-A UNIT) A portion of the. MHz st IF signal from the st mixer circuit (Q Q: while receiving) or IF amplifier (Q: while transmitting) is passed through the PIN attenuator (D0) and amplified at the IF amplifiers (Q, Q), and then mixed with the. MHz scope nd LO (SLO) signal at the mixer circuit (D) to produce the. MHz IF signal. The mixed IF signal is passed through the ceramic bandpass filters (FI, FI) to suppress unwanted signals. The filtered IF signal is applied to the FM IF IC (IC, pin ). The applied. MHz IF signal is mixed with the sweep LO (SLO) signals from the PLL unit at the FM IF IC (IC), which includes the RSSI terminal. The mixed IF signals are filtered at the ceramic bandpass filter (FI) then applied to the limiter amplifier section in the FM IF IC (IC, pin ). The applied IF signals are converted into DC voltages according to the applied IF signal strength at the RSSI section in the IC. The converted voltages are output from pin (IC) and amplified at ICb, then applied to the MAIN-A unit as the SCPL signal. Some of the DC voltages from the FM IF IC (IC) are amplified at ICa to produce AGC voltages for the IF amplifiers (Q, Q), producing wider dynamic range. y sweeping LO signals (SLO) are applied to the mixer section in the FM IF IC (IC), the spectrum scope function is activated. - POWER SUPPLY CIRCUITS -- PA UNIT LINE PHV HV V VA V V HV The voltage from an external power supply via the common filter circuit (FILTER unit; L0, L0). The same voltage as the PHV line passed through a fuse (F). The same voltage as the HV line passed through the switching relay (RL). The same voltage as the V line is applied to the AF power amplifier (MAIN-A unit; IC). Common V converted from the V line and regulated by the + regulator circuit (IC). Common V converted from the V line and regulated by the + regulator circuit (IC). Common V converted from the HV line and regulated by the HV regulator circuit (IC). -- FRONT UNIT LINE Common V converted from the V line and VF regulated by the + regulator circuit (IC). Common V converted from the V line and converted by the DC-DC converter circuit V (IC, Q, D). The voltage is applied to the V, V regulator circuits and etc. -- SWEEP LO CIRCUIT (PLL UNIT) The sweep LO signals (SLO) are generated by the DDS IC (IC0) using the MHz system clock. A 0-bit digital signal is converted into analog wave signals at the D/A converter (R0 R0). The converted analog wave is passed through the bandpass filter (L0, L0, C0 C) then applied to the RF-A unit after being amplified at the buffer amplifier (Q0). V V +V Common V converted from the V line and regulated by the regulator circuit (IC0). Common V converted from the V line and regulated by the V regulator circuit (IC). Common V converted from the V line and converted by the V DC-DC converter circuit (IC, Q, D). SCOPE CIRCUIT DIAGRAM st LO signal to nd mixer circuit SLO signal (.. MHz*) Q Q SLO signal (.0 MHz) IC Mixer RF signals IF amp. IF amp. Ceramic PF Ceramic PF FI st mixer A Q Q D FI FI ICa Limiter amp. Ceramic PF AGC RF-A unit to the MAIN-A unit SCPL signal amp. RSSI ICb *depending on sweeping passband width -
-- MAIN-A UNIT LINE RV TV Receive V converted from the V line and regulated by the RV regulator circuit (Q0, Q0, D0). Transmit V converted from the V line and regulated by the TV regulator circuit (Q, Q, D). -- CTRL AND PLL UNITS LINE Common V for the antenna tuner CPU (CTRL unit; IC) and the EEPROM (CTRL unit; IC), V converted from the V line and regulated by the + regulator circuit (CTRL unit; IC). Common V for each PLL-A and PLL- circuits regulated from the V line and regulated by the V + regulator circuit (PLL unit; IC: PLL-A, IC: PLL-). - LOGIC CIRCUITS -- AND SELECTION DATA (RF-A, CTRL AND PLL UNITS) To select the correct bandpass, low-pass filters and VCOs on the RF-A, FILTER and PLL units, the main CPU (MAIN- A unit, IC0) outputs the following band selection data via the I/O expander (RF-A unit, IC0, IC0, CTRL unit, IC) or DDS IC (PLL unit, IC0, IC0) depending on the displayed frequency. IC0, IC0 IC IC0 IC0 Frequency (RF-A unit) (CTRL) (PLL) (PLL) [MHz] PF LPF VCO-A VCO- 0.00. 0.. LS.0..0. LS VAS VS.0..0. LS.0 0. LS.0. VAS VS.0. 0.0..0. 0.0..0. 0W LS LS VAS VS 0.0.000000 0 L VAS VS.00000 0.000000 0W The D/A convertor (MAIN-A unit, IC) output signal from pin is amplified at IC0b (pins ) to obtain the band voltage for external equipment via the [ACC ] connector pin. -- SU-CPU PORT ALLOCATIONS (DISPLAY OARD; IC0) Pin number,,,,,, 00 Port name OSC, OSC DRES MS, MSA DOTK, DSHK MDM0 MDM TNRD, MOND ND, NRD LOCD, TXD RXD, PTD NOTD P, PA METV RSA, RS PA, P LMFD LFMD ALL NRL MIGL PWRL CMPL KYSL DELL NOTL PITL Description Input and output ports for the system clock oscillator (X0;.0 MHz). Input port for the reset signal. Input port for the [DIAL]; pulse-type signals are applied. Input ports for the [ELEC-KEY] jack. Output ports for the S/RF meter backlight and function switch activation indicator brightness control signal. acklight level Port MDM0 High Low High Low High Low High MDM Low High High Low Low High High MDM Low Low Low High High High High Control signal output ports for the activation indicator of function switches. High: When the function is activated. Input port for the [TWIN PT (inner)] control (PT board, S/inner). Outputs the S/RF meter (ME) drive signal. Input ports for the [RIT/ TX] control; pulse-type signals are applied. Input port for the [TWIN PT(outer)] control (PT board, S/outer). Input port for data signal from the main-cpu (MAIN unit; IC0). Outputs data signal for the main-cpu (MAIN unit; IC0). A/D input port for the [AL] control (R0/ inner). A/D input port for the [NR] control (R0/ outer). A/D input port for the [MIC GAIN] control (R). Input port for the [RF POWER] control (R). Input port for the [COMP] control (R). Input port for the [KEY SPEED] control (R). Input port for the [K-IN DELAY] control (R0). Input port for the [NOTCH] control (PT board, R/inner). Input port for the [CW PITCH] control (PT board, R/outer). - 0
-- MAIN-CPU PORT ALLOCATIONS (MAIN UNIT; IC0) Pin number,, 0 0 Port name A0 A, A A, A A SKYS RTKI Description Address signal output ports for the LCD controller (IC). Input port for the [KEY] jack. Low : During key down Input port for the RTTY keying. Pin number, Port name CON (PDAT) CON0 (PCK) XTAL, EXTAL Description Outputs data signal for the DDS circuits (PLL unit; IC0, IC0). Outputs clock signal for the DDS circuits (PLL unit, IC0, IC0). Input ports for the CPU system clock oscillator (X0;.0 MHz). 0,, 0 DPGI DSDR PWRK DSKY D0 D, D D, D D CTXD CRXD MCK MDAT TRVI IKEY RXS TXS ISTA DRES UNLC PST PSEL CON Power supply detection input port for the DSP-A board. Input port for data signal from DSP-A board. Input port for the [POWER] switch. Low : When the [POWER] is pushed. Outputs CW/RTTY keying. Data bus lines for the LCD controller (IC) and I/O expander (IC IC). Output port for the CI-V signal. Input port for the CI-V signal. Outputs clock signal. Outputs data signal. Input port for the [XVERT] detection signal. Input port for transmit control signal from the antenna tuner CPU (CTRL board; IC). Outputs RV regulator (Q0, Q0, D0) control signal. Low : While receiving Outputs TV regulator (Q, Q, D) control signal. Low : While transmitting Outputs antenna tuner start signal. Outputs reset/inhibit signal to the sub- CPU (DISPLAY board; IC0), DDS ICs (PLL unit; IC0, IC0), antenna tuner CPU (CTRL board; IC), and etc. Input port for unlock signal from the PLL unit. Outputs strobe signals for the I/O expander IC (PLL unit; IC). Outputs strobe selection signals for the I/O expander (PLL unit; IC). Outputs control signal for the DDS circuits (PLL unit; IC0, IC0). 0 0 0 0 0 0 0 LRES LTXD LRXD TMD SCPL VOXL AVXL ASO0 ASO ASO STON EEP SENI PWRS Outputs reset/inhibit signal for the LCD controller (IC), I/O expander (IC IC), and etc. Outputs data signal for the sub-cpu (DISPLAY board; IC0). Input port for data signal from the sub- CPU (DISPLAY board; IC0). Outputs [TIMER] indicator control signal. High: When the timer function is ON Input port for the scope signal. A/D input port for the VOX gain. A/D input port for the anti-vox level. A/D input port via the analog switch (IC) for the SML signal from the S-meter amplifier circuit (IC0a), and ALCL signal from the ALC meter amplifier circuit (ICa). A/D input port via the analog switch (IC) for the NSQO signal from the level conveter (DSP-A board; IC0), for noise squelch operation, and FORL signal from the power meter amplifier circuit (ICa). A/D input port from the analog switch (IC) for the FNTL signal from the low-pass filter (DSP-A board; ICa), for tone squelch operation, and L signal from the SWR meter amplifier circuit (ICb). Outputs CW side-tone signals. Outputs beep audio signals. Input port for connected microphone s PTT switch and SEND signal from the ACC jacks. High: While PTT switch is pushed or activated from an external unit. Outputs control signal for the power switching relay (PA unit; RL). High: During power ON -
-- INPUT EXPANDER ALLOCATIONS () DISPLAY board; IC Pin number, Port name KI MUDK KI KI0 KI, KI () MAIN-A unit; IC Pin number Port name CTFL RTDT EKEY TCON VINT VRAC SSY Description Input port for the [RIT], [ TX] and [CLEAR] switches. Input port for [UP] and [DN] switches of the connected microphone. Input port for the [D-WATCH], [CHANGE], [V/M] and [M/S] switches. Input port for the [TUNER], [MONI- TOR], [N] and [NR] switches. Input ports for the multi-function switches. Description Input port transmission status for CW Input port for RTTY decode data. Input port for the KEY signal from the connected AH-. Low : While tuning or tune NG Input port for AH- connection detection. High: When AH- is connected. Input port for interrupting signal from audio recoder. Input port for address clock signal from audio recoder. Input port for busy signal from the installed UT-0 SPEECH SYNTHE- SIZER. -- OUTPUT EXPANDER ALLOCATIONS () PLL unit; IC Pin number Port name PST PST PST PST PST PST PST Description Outputs strobe signals to DDS IC (IC0) for the st LO PLL A circuit. Outputs strobe signals to PLL IC (IC) for the st LO PLL A circuit. Outputs strobe signals to DDS IC (IC0) for the st LO PLL circuit. Outputs strobe signals to PLL IC (IC) for the st LO PLL circuit. Outputs strobe signals to DDS IC (IC0) for the rd LO PLL circuit. Outputs strobe signals to PLL IC (IC0) for the S LO PLL circuit. Outputs strobe signals to DDS IC (IC0) for the S LO PLL circuit. () PLL unit; IC0 Pin number 0 Port name MAKS PAMT PAFS VAS VAS VAS VAS () PLL unit; IC0 Pin number 0 Port name PMT PFS VS VS VS VS Description Outputs the marker mute switch (IC) control signal. High : When the [MARKER] is ON and receiving. Outputs LO mute switch (Q) control signal. Low : Muted Outputs bandpass filter select switch (Q) control signal. High : When less than MHz is displayed on the main band. Outputs the LO switch (Q) control signal. High : While.0 0.0 MHz band is displayed on the main band. Outputs the LO switch (Q) control signal. High : While 0.0. MHz band is displayed on the main band. Outputs the LO switch (Q) control signal. High : While.0. MHz band is displayed on the main band. Outputs the LO switch (Q) control signal. High : While 0.0. MHz band is displayed on the main band. Description Outputs LO mute switch (Q) control signal. Low : Muted Outputs bandpass filter select switch (Q) control signal. High : When less than MHz is displayed on the main band. Outputs the LO switch (Q) control signal. High : While.0 0.0 MHz band is displayed on the main band. Outputs the LO switch (Q) control signal. High : While 0.0. MHz band is displayed on the main band. Outputs the LO switch (Q) control signal. High : While.0. MHz band is displayed on the main band. Outputs the LO switch (Q) control signal. High : While 0.0. MHz band is displayed on the main band. -