Memory Systems Architecture and Performance Analysis Multi-bit Error Correction I Spring 2005 ENEE 759H Lecture12.fm Bruce Jacob David Wang University of Maryland ECE Dept. SLIDE 14 C α 2 C α = C 1 C 0 0 0 1 1 0 = 1 = α = α 2 = 0 1 0 1 1 1 1 α 2 α 111 α 2 α 0011111 1 1 0 0 0 0 0 0 0000 α 2 α 1 α 2 α 10001111 α 2 α 00111101000 α 2 α 1111000 0 0 0 1 1 1 α α 2 1 1 1 1 α 2 α 000111111000 α 2 α 1000 0 0 0 0 0 0 α 2 α 0 0 1 1 1 1 α 2 α 1 0 1 1 α 2 α 1 1 1 1 0 0 0 1 1 1 Parity check matrix in GF(2 2 ) Apply transform matrices Parity check matrix in binary field 0 0 1 0 1 1 T 0 = T 1 = 2 T α = T α = 0 0 0 1 1 0 0 1 1 1 C 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0 = 1010100111101010011100001010101010101000000000000000000000011110 0101011110000101111000000101010101010100000000000000000000111001 0111100000001010101001110000101010100010000000011110101010000000 1110010000000101010111100000010101010001000000111001010101000000 0000001010101101101010100111000000101010101010000000011110000000 0000000101011011010101011110000000010101010101000000111001000000 0000000000000111000010101010011110001010011110101010000000101010 0000000000001110000001010101111001000101111001010101000000010101 0 8 16 24 3132 40 48 56 63 UNIVERSITY OF MARYLAND

C 7 1 0 1 0 1 0 0 1 1 1 1 0 1 0 1 0 0 1 1 1 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 C 6 0 1 0 1 0 1 1 1 1 0 0 0 0 1 0 1 1 1 1 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 C 5 0 1 1 1 1 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 1 1 1 0 0 0 0 1 0 1 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 0 0 0 0 0 0 C 4 C 3 = 1 1 1 0 0 1 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 0 1 0 1 0 0 1 1 1 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 1 1 1 0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 C 2 0 0 0 0 0 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 0 C 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 0 1 0 1 0 1 0 0 1 1 1 1 0 0 0 1 0 1 0 0 1 1 1 1 0 1 0 1 0 1 0 0 0 0 0 0 0 1 0 1 0 1 0 C 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 0 1 0 1 0 1 1 1 1 0 0 1 0 0 0 1 0 1 1 1 1 0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 1 0 1 0 1 0 8 16 24 31 32 40 48 56 63 C 7 1 0 1 0 1 0 0 1 1 1 1 0 1 0 1 0 0 1 1 1 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 C 6 0 1 0 1 0 1 1 1 1 0 0 0 0 1 0 1 1 1 1 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 C 5 0 1 1 1 1 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 1 1 1 0 0 0 0 1 0 1 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 0 0 0 0 0 0 C 4 C 3 = 1 1 1 0 0 1 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 0 1 0 1 0 0 1 1 1 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 1 1 1 0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 C 2 0 0 0 0 0 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 0 C 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 0 1 0 1 0 1 0 0 1 1 1 1 0 0 0 1 0 1 0 0 1 1 1 1 0 1 0 1 0 1 0 0 0 0 0 0 0 1 0 1 0 1 0 C 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 0 1 0 1 0 1 1 1 1 0 0 1 0 0 0 1 0 1 1 1 1 0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 1 0 1 0 1 0 8 16 24 31 32 40 48 56 63 FIGURE 30.12: Locating a single bit and 2-adjacent bit errors in a 64-bit word. A two-bit error in positions 32,33 results in 11110011

TABLE 30.3 Error location table for the 2-adjacent error correction algorithm, taken from US Patent #5,490,155 (Compaq s Advanced ECC implementation) S7: 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 S6: 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 s s s s s5: 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 3 2 1 0 s4: 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 C4 C5 C6 5 3 1 C7 0 4 2 2,3 0.1 4,5 0 0 0 1 C0 51 49 47 63 33 61 28 59 30,31 0 0 1 0 C1 46 50 48 58 31 62 32 60 28,29 0 0 1 1 48,49 46,47 50,51 60,61 29 58,59 62,63 32,33 0 1 0 0 C2 57 52 54,55 11 35 9 19 7 17 0 1 0 1 45 39 23 21 37 0 1 1 0 43 24 12,13 0 1 1 1 41 14 26,27 1 0 0 0 C3 55 56 52,53 6 16 10 34 8 18 1 0 0 1 40 27 14,15 1 0 1 0 44 20 38 22 36 1 0 1 1 42 24,25 1 1 0 0 53 54 56,57 8,9 18,19 6,7 16,17 10,11 34,35 1 1 0 1 42,43 25 12 1 1 1 0 40,41 15 26 1 1 1 1 44,45 22,23 20,21 38,39 36,37 Syndrome of 11110011 points to bad bits 32,33

144b data bus 72b ECC word 72b ECC word x4 x4 x4 x4 4 bit wide DRAM Bit-Steering