SYLLABUS. osmania university UNIT - I UNIT - II UNIT - III UNIT - IV BASIC VERILOG HDL BEHAVIOURAL MODELING INTRODUCTION

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1 Contents i SYLLABUS osmania university UNIT - I BASIC VERILOG HDL Introduction to HDLs, Basic Concepts of Verilog, Data Types, System Tasks and Complier Directives. Gate Level Modeling : Gate Types and Gate Delays, Dataflow Modeling : Continuous Assignment and Delays, Design of Stimulus Block. UNIT - II BEHAVIOURAL MODELING Structured Procedures, Procedural Assignments, Timing Control, Conditional Statements, Sequential and Parallel Blocks, Generate Blocks. Switch Level Modeling, Tasks, Functions, Procedural Continuous Assignments, Design of Mealy and Moore State Models using Verilog, Logic Synthesis, Synthesis Design Flow, Gate Level Netlist. UNIT - III INTRODUCTION Introduction to MOS Technology, Basic MOS Transistor Action : Enhancement and Depletion Modes, Basic Electrical Properties of MOS, Threshold Voltage and Body Effect, Design of MOS Inverter with Different Loads, Basic Logic Gates with CMOS : Inverter, NAND, NOR, AOI, and OAI Gates, Transmission Gate Logic Circuits, BiCMOS Inverter. UNIT - IV MOS AND BICMOS CIRCUIT DESIGN PROCESSES MOS Layers, Stick Diagrams, Lambda Based Design Rules and Layout Diagrams, Basic Circuit Concepts : Sheet Resistance, Area Capacitance and Delay Calculation.

2 ii Contents UNIT - V COMBINATIONAL AND SEQUENTIAL LOGIC CIRCUITS Combinational Logic : Manchester, Carry Select and Carry Skip Adders, Crossbar and Barrel Shifters, Multiplexer. Sequential Logic : Design of Dynamic Register Element, 3T, 1T Dynamic RAM Cell, 6T Static RAM Cell, D Flip Flop using Transmission Gates, NOR and NAND based ROM Memory Design.

3 Contents iii vlsi design FOR b.e. (o.u) iv year i semester (ELECTRONICS AND COMMUNICATION ENGINEERING) CONTENTS UNIT - I [BASIC VERILOG HDL] OVERVIEW OF DIGITAL AL DESIGN WITH VERILOG HDL Evolution of Computer-Aided Digital Design Emergence of HDLs Typical Design Flow (VLSI Design Flow) Importance of HDLs Popularity of Verilog HDL Trends in HDLs Major Capabilities of Verilog Design Methodologies Bit Ripple Carry Counter (Example For Design Hierarchy) BASIC CONCEPTS OF VERILOG Laxical Conventions White Space Comments Operators Number Specification

4 iv Contents Strings Identifiers and Keywords Escaped Identifiers DATA A TYPES Value System Data Declaration Reg Declaration Net Declaration Syntax Port Types Delays on Nets Integer and Time Hierarchical Names Arrays Strings SYSTEM TASKS AND COMPLIER DIRECTIVES System Tasks Compiler Directives GATE TE-LEVEL MODELING Gate Types And/Or Gates BUF/NOT T Gates Array of Instances Examples Gate Delays Rise, Fall and Turnurn-off Delays Min/Typ/Max Values alues Delay Example

5 Contents v 1.6 DATAFL AFLOW MODELING Continuous Assignments Implicit Continuous Assignment Implicit Net Declaration Delays Regular Assignment Delay Implicit Continuous Assignment Delay Net Declaration Delay COMPONENTS OF A SIMULATION Example Design Block Stimulus Block Short Questions and Answers Expected University Questions with Answers UNIT - II [BEHAVIOURAL MODELING] BEHAVIOURAL MODELING STRUCTURED PROCEDURES Initial Statement Always Statement In One Module PROCEDURAL ASSIGNMENTS Blocking Assignment Nonblocking Assignment TIMING CONTROLS Delay-Based Timing Control Event-Based Timing Control Level-Sensitive Timing Control CONDITIONAL STATEMENTS TEMENTS

6 vi Contents 2.6 SEQUENTIAL AND PARALLEL BLOCKS OCKS Sequential Blocks Parallel Blocks GENERATE BLOCKS OCKS Generate Loop Generate Conditional Generate Case SWITCH LEVEL MODELING Switch-Modeling Elements MOS Switches CMOS Switches Bidirectional Switches Power and Ground Resistive Switches Delay Specification on Switches Examples CMOS NOR Gate to-1 Multiplexer Simple CMOS Latch TASKS Task Declaration and Invocation Task Examples Automatic (Re-Entrant) Tasks FUNCTIONS Function Declaration and Invocation Function Examples Automatic (Recursive) Functions

7 Contents vii Constant Functions Signed Functions Differences Between Tasks and Functions PROCEDURAL CONTINUOUS ASSIGNMENTS Assign and Deassign Force and Release DESIGN OF MEALY AND MOORE STATE TE MODELS USING VERILOG OG Defining Terms in State Machines Mealy Circuit Design of a Mealy Circuit Moore Circuit Design of a Moore Sequential Network Comparison Between Moore and Mealy Models LOGIC SYNTHESIS What is Logic Synthesis Impact of Logic Synthesis Verilog HDL Synthesis Verilog Constructs Verilog Operators Interpretation of a Few ew Verilog Constructs SYNTHESIS DESIGN FLOW RTL to Gates An Example of RTL-to-Gates GATE LEVEL NETLIST Functional Verification Short Questions and Answers Expected University Questions with Answers

8 viii Contents UNIT - III [INTRODUCTION INTRODUCTION] INTRODUCTION TO IC TECHNOLOG OGY Classification of ICs Evolution of IC Technology Advantages of ICs Moore s Law IC Manufacturing Process IC Design Challenges System Design Cycle Transistor Modeling Integration of Technologies Microelectornics Field IC Fabrication Steps MOS TECHNOLOGY Basic MOS Transistors ransistors Enhancement Mode Transistor Action Depletion Mode Transistor Action BASIC ELECTRICAL PROPERTIES OF MOS I DS DS Relationships The Non-Saturated Region The Saturated Region I DS DS Graph for Depletion Mode I DS DS Graph for Enhancement Mode THRESHOLD VOL OLTAGE AND BODY EFFECT Threshold Voltage oltage Body Effect MOS TRANSISTOR TRANSCONDUCTANCE ANCE (g m ) AND OUTPUT CONDUCTANCE ( ds ) FIGURE OF MERIT (ω O )

9 Contents ix 3.7 DESIGN OF MOS INVERTER WITH DIFFERENT LOADS nmos Inverter with Resistive Load nmos Inverter with Depletion Mode NMOS as a Load Z P.U /Z P.D Ratio for an nmos Inverter Driven by Another nmos Inverter Z P.U /Z P.D Ratio for an nmos Inverter Driven Through One (or) More Pass Transistors VARIOUS PULL-UPS nmos Enhancement Mode Transistor Pull-Up ull-up Complementary Transistor Pull-Up CMOS INVERTER ANALYSIS AND DESIGN CMOS LOGIC CIRCUIT BASIC LOGIC GATES WITH CMOS CMOS Inverter (Not Gate) CMOS NAND Gate CMOS NOR Gate Complex Gates in CMOS Logic AOI Logic Function OAI Logic Function SWITCH LOGIC Pass ass Tra ransistors nsistors Transmission Gates BICMOS INVERTER Short Questions and Answers Expected University Questions with Answers UNIT - IV [MOS AND BICMOS CIRCUIT DESIGN PROCESSES] INTRODUCTION TO VLSI CIRCUIT DESIGN FLOW Y-Chart Simplified View of VLSI Design Flow Top op-down and Bottom-Up Approach Semi-Custom and Full-Custom Design MOS LAYERS

10 x Contents 4.4 STICK DIAGRAMS nmos Design Style Guidelines to Draw Stick Diagram of nmos Logic Stick Diagrams for nmos Logic Gates PMOS Design Style Guidelines to Draw Stick Diagrams of PMOS Logic Stick Diagrams for PMOS Logic Gates CMOS Design Style Guidelines to Draw Stick Diagram of CMOS Logic Stick Diagrams for Basic Logic Gates Using CMOS Design Style DESIGN RULES Lambda-based Design Rules Lambda-based Design Rules for Conducting Paths Lambda-based Design Rules for Transistors Lamda-based Design Rules for Contact Cuts Double Metal MOS Process Rules CMOS Lambda-based Design Rules μm m CMOS Design Rules LAYOUT DIAGRAMS GRAMS BASIC CIRCUIT CONCEPTS Sheet Resistance Sheet Resistance Concept Applied to MOS Transistors and Inverters Sheet Resistance in MOS Transistors Inverter Resistance Calculation nmos Inverter CMOS Inverter

11 Contents xi Area Capacitance Standard Unit of Capacitance C g Some Area Capacitane Calculations DRIVING LARGE CAPACITIVE CITIVE LOADS Cascaded Inverters as Drivers Super Buffers BiCMOS Drivers WIRING CAPACIT CITANCE Fringing Fields Inter Layer Capacitances Peripheral Capacitance TIME DELAY Y UNIT (τ) Inverter Delays Estimation of CMOS Inverter Delay Propagation Delays Cascaded Pass ass Transistors Design of Long Polysilicon Wires ires Effects of Fan-in and Fan-out On Propagation Delay Choice of Layers Short Questions and Answers Expected University Questions with Answers UNIT - V [COMBINATIONAL AND SEQUENTIAL LOGIC CIRCUITS] COMBINATIONAL LOGIC CIRCUITS ADDERS Single Bit Addition Carry Propagate Addition (CPA) Carry Ripple Adder (CRA) Carry Look Ahead Adder (CLA) Manchester Carry Chain Adder Carry Skip Adder Carry Select Adder

12 xii Contents 5.3 SHIFTERS Crossbar Switch Barrel Shifter MULTIPLEXERS (DATA A SELECTORS) SEQUENTIAL LOGIC CIRCUITS DESIGN OF DYNAMIC REGISTER ELEMENT DYNAMIC SHIFT REGISTER DRAM (DYNAMIC RANDOM ACCESS MEMORY) One-Transistor DRAM Three-Transistor ransistor DRAM Four Transistor DRAM SRAM (STATIC TIC RANDOM ACCESS MEMORY) Y) Transistor SRAM D-FLIPFL -FLIPFLOP OP USING TRANSMISSION GATES TES READ ONLY MEMORY ROM Cell Organization Mask Programmed (ROM) Memory Circuits NOR-based ROM NAND-based ROM Flash Memory SERIAL ACCESS MEMORIES Shift Registers Queues (FIFO,, LIFO) CONTENT-ADDRESSABLE MEMORY Short Questions and Answers Expected University Questions with Answers