ΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2017

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1 ΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2017 ΔΙΑΛΕΞΗ 4: CMOS Αντιστροφέας (Inverter) ΧΑΡΗΣ ΘΕΟΧΑΡΙΔΗΣ [Προσαρμογή από Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al. ]

2 CMOS Inverter: A First Look V DD V in V out C L ΗΜΥ307 Δ4 CMOS Inverter.2 Θεοχαρίδης, ΗΜΥ, 2017

3 CMOS Inverter: Steady State Response V DD V DD V OL = 0 V OH = V DD V M = f(r n, R p ) R p V out = 1 V out = 0 R n V in = 0 V in = V DD ΗΜΥ307 Δ4 CMOS Inverter.3 Θεοχαρίδης, ΗΜΥ, 2017

4 CMOS Properties l Full rail-to-rail swing Þ high noise margins Logic levels not dependent upon the relative device sizes Þ transistors can be minimum size Þ ratioless l Always a path to V dd or GND in steady state Þ low output impedance (output resistance in kw range) Þ large fan-out (albeit with degraded performance) l Extremely high input resistance (gate of MOS transistor is near perfect insulator) Þ nearly zero steady-state input current l No direct path steady-state between power and ground Þ no static power dissipation l Propagation delay function of load capacitance and resistance of transistors ΗΜΥ307 Δ4 CMOS Inverter.4 Θεοχαρίδης, ΗΜΥ, 2017

5 Review: Short Channel I-V Plot (NMOS) X 10-4 V GS = 2.5V V GS = 2.0V V GS = 1.5V 0.5 V GS = 1.0V V DS (V) NMOS transistor, 0.25um, L d = 0.25um, W/L = 1.5, V DD = 2.5V, V T = 0.4V ΗΜΥ307 Δ4 CMOS Inverter.5 Θεοχαρίδης, ΗΜΥ, 2017

6 Review: Short Channel I-V Plot (PMOS) All polarities of all voltages and currents are reversed -2 V DS (V) V GS = -1.0V -0.2 V GS = -1.5V -0.4 V GS = -2.0V V GS = -2.5V -1 X 10-4 PMOS transistor, 0.25um, L d = 0.25um, W/L = 1.5, V DD = 2.5V, V T = -0.4V ΗΜΥ307 Δ4 CMOS Inverter.6 Θεοχαρίδης, ΗΜΥ, 2017

7 Transforming PMOS I-V Lines Want common coordinate set V in, V out, and I Dn I DSp = -I DSn V GSn = V in ; V GSp = V in - V DD V DSn = V out ; V DSp = V out - V DD I Dn Vout V in = 0 V in = 1.5 V in = 0 V in = 1.5 V GSp = -1 V GSp = -2.5 Mirror around x-axis V in = V DD + V GSp I Dn = -I Dp Horiz. shift over V DD V out = V DD + V DSp ΗΜΥ307 Δ4 CMOS Inverter.7 Θεοχαρίδης, ΗΜΥ, 2017

8 CMOS Inverter Load Lines PMOS V in = 0V X 10-4 NMOS V in = 2.5V V in = 0.5V 1.5 V in = 2.0V V in = 1.0V 1 V in = 2V 0.5 V in = 1.5V V in = 2.0V V in = 2.5V 0 V in = 1.5V V in = 1V V out (V) V in = 1.5V V in = 0.5V V in = 1.0V V in = 0.5V V in = 0V 0.25um, W/L n = 1.5, W/L p = 4.5, V DD = 2.5V, V Tn = 0.4V, V Tp = -0.4V ΗΜΥ307 Δ4 CMOS Inverter.8 Θεοχαρίδης, ΗΜΥ, 2017

9 CMOS Inverter VTC V out (V) V in (V) ΗΜΥ307 Δ4 CMOS Inverter.9 Θεοχαρίδης, ΗΜΥ, 2017

10 CMOS Inverter VTC NMOS off PMOS res NMOS sat PMOS res V out (V) V in (V) NMOS sat PMOS sat NMOS res PMOS sat NMOS res PMOS off ΗΜΥ307 Δ4 CMOS Inverter.10 Θεοχαρίδης, ΗΜΥ, 2017

11 CMOS Inverter: Switch Model of Dynamic Behavior V DD V DD R p V out V out C L R n C L V in = 0 V in = V DD ΗΜΥ307 Δ4 CMOS Inverter.11 Θεοχαρίδης, ΗΜΥ, 2017

12 CMOS Inverter: Switch Model of Dynamic Behavior V DD V DD R p V out V out C L R n C L V in = 0 V in = V DD Gate response time is determined by the time to charge C L through R p (discharge C L through R n ) ΗΜΥ307 Δ4 CMOS Inverter.12 Θεοχαρίδης, ΗΜΥ, 2017

13 Relative Transistor Sizing l When designing static CMOS circuits, balance the driving strengths of the transistors by making the PMOS section wider than the NMOS section to maximize the noise margins and obtain symmetrical characteristics ΗΜΥ307 Δ4 CMOS Inverter.13 Θεοχαρίδης, ΗΜΥ, 2017

14 Switching Threshold l V M where V in = V out (both PMOS and NMOS in saturation since V DS = V GS ) V M» rv DD /(1 + r) where r = k p V DSATp /k n V DSATn l Switching threshold set by the ratio r, which compares the relative driving strengths of the PMOS and NMOS transistors l Want V M = V DD /2 (to have comparable high and low noise margins), so want r» 1 (W/L) p k n V DSATn (V M -V Tn -V DSATn /2) (W/L) n k p V DSATp (V DD -V M +V Tp +V DSATp /2) = ΗΜΥ307 Δ4 CMOS Inverter.14 Θεοχαρίδης, ΗΜΥ, 2017

15 Switch Threshold Example l In our generic 0.25 micron CMOS process, using the process parameters from slide L03.25, a V DD = 2.5V, and a minimum size NMOS device ((W/L) n of 1.5) V T0 (V) g(v 0.5 ) V DSAT (V) k (A/V 2 ) l(v -1 ) NMOS x PMOS x (W/L) p (W/L) n = ΗΜΥ307 Δ4 CMOS Inverter.15 Θεοχαρίδης, ΗΜΥ, 2017

16 Switch Threshold Example l In our generic 0.25 micron CMOS process, using the process parameters from Lecture 3, a V DD = 2.5V, and a minimum size NMOS device ((W/L) n of 1.5) V T0 (V) g(v 0.5 ) V DSAT (V) k (A/V 2 ) l(v -1 ) NMOS x PMOS x (W/L) p 115 x ( /2) = x x = 3.5 (W/L) n -30 x ( /2) (W/L) p = 3.5 x 1.5 = 5.25 for a V M of 1.25V ΗΜΥ307 Δ4 CMOS Inverter.16 Θεοχαρίδης, ΗΜΥ, 2017

17 Simulated Inverter V M ~ (W/L) p /(W/L) n Note: x-axis is semilog q V M is relatively insensitive to variations in device ratio l setting the ratio to 3, 2.5 and 2 gives V M s of 1.22V, 1.18V, and 1.13V q Increasing the width of the PMOS moves V M towards V DD q Increasing the width of the NMOS moves V M toward GND ΗΜΥ307 Δ4 CMOS Inverter.17 Θεοχαρίδης, ΗΜΥ, 2017

18 Noise Margins Determining V IH and V IL 3 By definition, V IH and V IL are where dv out /dv in = -1 (= gain) V OH = V DD 2 1 V M NM H = V DD - V IH NM L = V IL - GND Approximating: V IH = V M - V M /g V IL = V M + (V DD - V M )/g V OL = GND0 VIL V in A piece-wise linear approximation of VTC VIH So high gain in the transition region is very desirable ΗΜΥ307 Δ4 CMOS Inverter.18 Θεοχαρίδης, ΗΜΥ, 2017

19 CMOS Inverter VTC from Simulation V out (V) V in (V) 0.25um, (W/L) p /(W/L) n = 3.4 (W/L) n = 1.5 (min size) V DD = 2.5V V M» 1.25V, g = V IL = 1.2V, V IH = 1.3V NM L = NM H = 1.2 (actual values are V IL = 1.03V, V IH = 1.45V NM L = 1.03V & NM H = 1.05V) Output resistance low-output = 2.4kW high-output = 3.3kW ΗΜΥ307 Δ4 CMOS Inverter.19 Θεοχαρίδης, ΗΜΥ, 2017

20 Gain Determinates V in Gain is a strong function of the slopes of the currents in the saturation region, for V in = V M (1+r) g» (V M -V Tn -V DSATn /2)(l n - l p ) Determined by technology parameters, especially channel length modulation (l). Only designer influence through supply voltage and V M (transistor sizing). ΗΜΥ307 Δ4 CMOS Inverter.20 Θεοχαρίδης, ΗΜΥ, 2017

21 Impact of Process Variation on VTC Curve Good PMOS Bad NMOS V out (V) Bad PMOS Good NMOS Nominal V in (V) Process variations (mostly) cause a shift in the switching threshold ΗΜΥ307 Δ4 CMOS Inverter.21 Θεοχαρίδης, ΗΜΥ, 2017

22 Scaling the Supply Voltage V out (V) V out (V) V in (V) Gain= V in (V) Device threshold voltages are kept (virtually) constant Device threshold voltages are kept (virtually) constant ΗΜΥ307 Δ4 CMOS Inverter.22 Θεοχαρίδης, ΗΜΥ, 2017

23 Next Time: CMOS Inverter Layout Out In metal1-poly via metal1 polysilicon metal2 V DD pdiff metal1-diff via GND PMOS (4/.24 = 16/1) NMOS (2/.24 = 8/1) ndiff metal2-metal1 via ΗΜΥ307 Δ4 CMOS Inverter.23 Θεοχαρίδης, ΗΜΥ, 2017

24 3D View ΗΜΥ307 Δ4 CMOS Inverter.24 Θεοχαρίδης, ΗΜΥ, 2017

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ΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2018

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