Z05 SYSTEM BLOCK DIAGRAM

Transcript

1 Z0 SYSTEM LOK IGRM PU ORE / VN (ISL) PGE N_ORE.V (RT0) PGE.V_N (RT0) PGE RII-SOIMM PGE RII-SOIMM PGE RII /00 MHz RII /00 MHz Lion Sabie SG Processor P (upg)/w PGE,,, M Griffin PU THERML SENSOR PGE PU Fan PGE R II SMR_VTERM.VSUS(TPSREGR) PGE HT LINK SYSTEM POWER (ISL) PGE SYSTEM HRGER (ISL) PGE LVS PGE RT PGE LVS RT NORTH RIGE & SOUTH RIGE PI-E Mini PI-E ard PGE PIE X (Wireless LN) PIE X PIE X Express LN ard ROOM MM (NEW R) (0/00/GagaLN) PGE PGE RJ PGE MPM US.0 X X US US ST - H PGE O(ST) PGE ST0 ST mm X mm, pin G US 0,, US US US 0 X X X X US.0 Ports luetooth P-cam Fingerprint PGE, PGE PGE PGE US X ard Reader Realtek RTSE ( in ) PGE.MHz PGE,,,0,,, zalia LP zalia udioontroller RealTek L PGE 0 M. PGE 0 RJ PGE P STK UP LYER : TOP LYER : Keyboard PGE K (WPE) PGE udio mplifier PGE 0 Int MI PGE 0 LYER : IN LYER : IN LYER : V LYER : OT Touch Pad SPI ROM PGE PGE Speaker SPIF/Phone Jack Line in MI Jack PGE 0 PGE PGE PGE Quanta omputer Inc. PROJET : Z0 Size ocument Number Rev lock iagram Friday, pril, 00 ate: Sheet of

2 <> HT_RX#[..0] HT_RX#[..0] <> HT_TX[..0] <> HT_RX[..0] HT_RX[..0] <> HT_TX#[..0] HT_TX[..0] HT_TX#[..0] PROESSOR HYPERTRNSPORT INTERFE VLT_x N VLT_x RE ONNETE TO THE LT_RUN POWER SUPPLY THROUGH THE PKGE OR ON THE IE. IT IS ONLY ONNETE ON THE OR TO EOUPLING NER THE PU PKGE VLT_RUN U HT_RX0 HT_RX#0 HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX0 HT_RX#0 HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# E E E F G G G H J K L L L M N N E F F F G H H H K K L M M M N P VLT_0 HT LINK VLT_0 VLT_ VLT_ VLT_ VLT_ VLT_ VLT_ L0_IN_H0 L0_OUT_H0 L0_IN_L0 L0_OUT_L0 L0_IN_H L0_OUT_H L0_IN_L L0_OUT_L L0_IN_H L0_OUT_H L0_IN_L L0_OUT_L L0_IN_H L0_OUT_H L0_IN_L L0_OUT_L L0_IN_H L0_OUT_H L0_IN_L L0_OUT_L L0_IN_H L0_OUT_H L0_IN_L L0_OUT_L L0_IN_H L0_OUT_H L0_IN_L L0_OUT_L L0_IN_H L0_OUT_H L0_IN_L L0_OUT_L L0_IN_H L0_OUT_H L0_IN_L L0_OUT_L L0_IN_H L0_OUT_H L0_IN_L L0_OUT_L L0_IN_H0 L0_OUT_H0 L0_IN_L0 L0_OUT_L0 L0_IN_H L0_OUT_H L0_IN_L L0_OUT_L L0_IN_H L0_OUT_H L0_IN_L L0_OUT_L L0_IN_H L0_OUT_H L0_IN_L L0_OUT_L L0_IN_H L0_OUT_H L0_IN_L L0_OUT_L L0_IN_H L0_OUT_H L0_IN_L L0_OUT_L E E E E W W V U U U T R Y W V V V U T T.U_ HT_TX0 HT_TX#0 HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX0 HT_TX#0 HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX#.V_HT Note:on MP,(HT=.V) and PU(HT=.V) and therefore cannot be connected to the same HT power rail. L FJHS00_0 L FJHS00_0 0 ohm() VLT_RUN 0.U_.U_.U_.U_ 0P_ LYOUT: Place bypass cap on topside of board NER HT POWER PINS THT RE NOT ONNETE IRETLY TO OWNSTREM HT EVIE, UT ONNETE INTERNLLY TO OTHER HT POWER PINS PLE LOSE TO VLT0 POWER PINS 0P_ <> HT_PU_UPLK0 <> HT_PU_UPLK#0 <> HT_PU_UPLK <> HT_PU_UPLK# J J J K L0_LKIN_H0 L0_LKIN_L0 L0_LKIN_H L0_LKIN_L L0_LKOUT_H0 L0_LKOUT_L0 L0_LKOUT_H L0_LKOUT_L Y W Y Y HT_PU_WNLK0 <> HT_PU_WNLK#0 <> HT_PU_WNLK <> HT_PU_WNLK# <> <> HT_PU_UPTL0 <> HT_PU_UPTL#0 <> HT_PU_UPTL <> HT_PU_UPTL# N P P P L0_TLIN_H0 L0_TLIN_L0 L0_TLIN_H L0_TLIN_L L0_TLOUT_H0 L0_TLOUT_L0 L0_TLOUT_H L0_TLOUT_L R R T R HT_PU_WNTL0 <> HT_PU_WNTL#0 <> HT_PU_WNTL <> HT_PU_WNTL# <> NO STU for HT R */F_ VLT_RUN R */F_ thlon Sg SOKET PIN thlon Sg Processor Socket SOKET PIN Quanta omputer Inc. PROJET : Z0 Size ocument Number Rev M Griffin HT I/F ate: Friday, pril, 00 Sheet of

3 E V_VTT_SUS_PU IS ONNETE TO THE V_VTT_SUS POWER SUPPLY THROUGH THE PKGE OR ON THE IE. IT IS ONLY ONNETE ON THE OR TO EOUPLING NER THE PU PKGE Processor R Memory Interface SMR_VTERM SMR_VTERM MEM:T <> M Q[0..] M Q[0..] <> M Q0 M Q0 M Q M_T0 M_T0 G PLE THEM LOSE TO U M Q.VSUS M Q M_T M_T F M Q PU WITHIN " M Q M_T M_T H 0 M Q VTT VTT W0 M Q M_T M_T G 0 MEM:M/TRL/LK M Q VTT VTT 0 G M Q M_T M_T H 0 M Q VTT VTT 0 E M Q M_T M_T H 0 M Q M Q M_T M_T R./F_ VTT VTT 0 R0 M Q M_ZP VTT 0 M Q M_T M_T E F0 K/F_ M Q M_ZN MEMZP PU_VTT_SUS_F M Q M_T M_T H.VSUS E0 M Q T M Q0 M_T M_T E R./F_ MEMZN VTT_SENSE Y0 M Q0 MEM_M_RESET# PU_M_VREF M Q M_T0 M_T0 E M Q T H RSV_M MEMVREF W 0 M Q M_T M_T H M Q MEM_M_RESET# M Q M_T M_T E M Q <> M OT0 T M0_OT0 RSV_M T 00 R0 M Q M_T M_T F M Q <> M OT V M OT0 M0_OT M Q M_T M_T M Q T U M OT M_OT0 M0_OT0 W M OT0 <>.U_ 000P_ K/F_ M Q M_T M_T G M Q T V M_OT M0_OT W M OT <> 0 M OT0 M Q M_T M_T G M Q M_OT0 Y T M Q M_T M_T M Q <> M S#0 T0 M0_S_L0 M Q M_T M_T M Q <> M S# U M S#0 <> M S#0 M0_S_L M0_S_L0 V M Q0 M_T M_T E0 M Q0 T0 U0 M S# <> M S# M_S_L0 M0_S_L W 0 M S#0 M Q M_T0 M_T0 E M Q T V0 M_S_L M_S_L0 U T 0 M Q M_T M_T F M Q M Q M_T M_T M Q <> M KE0 J M_KE0 M_KE0 J M KE0 <> M Q M_T M_T M Q <> M KE J0 M_KE M_KE H M KE <> E M Q M_T M_T F0 E M Q M Q M_T M_T F M Q T0 N M_LK_H M_LK_H P T G M Q M_T M_T H M Q T N0 M_LK_L M_LK_L R T G M Q M_T M_T J M Q <> M LKOUT E M_LK_H M_LK_H M LKOUT <> M Q M_T M_T E M Q <> M LKOUT# F M_LK_L M_LK_L M LKOUT# <> M Q0 M_T M_T E M Q0 <> M LKOUT Y M_LK_H M_LK_H F M LKOUT <> G M Q M_T0 M_T0 H0 M Q <> M LKOUT# M_LK_L M_LK_L F M LKOUT# <> G M Q M_T M_T H M Q T0 P M_LK_H M_LK_H R T M Q M_T M_T Y M Q T P0 M_LK_L M_LK_L R T M [0..] <> M Q M_T M_T M Q <> M [0..] M 0 M 0 M Q M_T M_T N E M Q M M_0 M_0 P M M Q M_T M_T M0 M Q M M_ M_ N M M Q M_T M_T W N M Q M M_ M_ P M M Q M_T M_T W M M Q M M_ M_ N M M Q M_T M_T Y M E M Q M M_ M_ N M M Q0 M_T M_T L0 M Q0 M M_ M_ L M M Q M_T0 M_T0 Y0 M M Q M M_ M_ N M M Q M_T M_T 0 L E0 M Q M M_ M_ L M M Q M_T M_T L F0 M Q M M_ M_ M M M Q M_T M_T K F M Q M 0 M_ M_ K M 0 M Q M_T M_T R F M Q M M_0 M_0 T M M Q M_T M_T L 0 M Q M M_ M_ L M M Q M_T M_T K0 0 M Q M M_ M_ L M M Q M_T M_T Y V M Q M M_ M_ W M M Q M_T M_T K E M Q M M_ M_ J M M Q0 M_T M_T W K M Q0 M_ M_ J M Q M_T0 M_T0 W M Q M S#0 <> M Q M_T M_T Y M Q <> M S#0 R0 M_NK0 M_NK0 R F M S# <> M Q M_T M_T Y M Q <> M S# R M_NK M_NK U M Q M_T M_T M Q <> M S# J M_NK M_NK J M S# <> F M Q M_T M_T F M Q M Q M_T M_T M Q <> M RS# R M_RS_L M_RS_L U M RS# <> F M Q M_T M_T M Q <> M S# T M_S_L M_S_L U M S# <> M Q M_T M_T M Q <> M WE# T M_WE_L M_WE_L U M WE# <> M Q M_T M_T Y Y M Q M Q0 M_T M_T W E M Q0 M Q M_T0 M_T0 F M Q M Q M_T M_T F M Q thlon Sg SOKET PIN M Q M_T M_T M Q M_T M_T thlon Sg Processor Socket SOKET PIN M QS0 M QS0 M QS#0 M_QS_H0 M_QS_H0 G M QS#0 <> M LKOUT <> M LKOUT M QS M_QS_L0 M_QS_L0 H M QS M QS# M_QS_H M_QS_H G M QS# M QS M_QS_L M_QS_L G M QS.pF_.pF_ M QS# M_QS_H M_QS_H M QS# M QS M_QS_L M_QS_L M QS <> M LKOUT# <> M LKOUT# F PLE LOSE TO PROESSOR PLE LOSE TO PROESSOR M QS# M_QS_H M_QS_H G E M QS# M QS M_QS_L M_QS_L G M QS <> M LKOUT WITHIN. INH <> M LKOUT WITHIN. INH M QS# M_QS_H M_QS_H M QS# M QS M_QS_L M_QS_L F M QS M QS# M_QS_H M_QS_H F M QS#.pF_ M QS M_QS_L M_QS_L 0.pF_ E M QS M QS# M_QS_H M_QS_H Y M QS# <> M LKOUT# <> M LKOUT# M QS M_QS_L M_QS_L W F M QS M QS# M_QS_H M_QS_H W E M QS# M_QS_L M_QS_L W To reverse SOIMM socket <> M M[0..] M M0 M M M M M M M M M M M M M M E E U M_M0 M_M M_M M_M M_M M_M M_M M_M M_M0 M_M M_M M_M M_M M_M M_M M_M E E F Y Y M M0 M M M M M M M M M M M M M M To normal SOIMM socket M M[0..] <>.U_.U_ SMR_VTERM.U_.U_.U_.U_.U_.U_ 000P_ 000P_ 0 000P_ 000P_ 0P_ 0P_ 0P_ 0 0P_ <> M QS[0..] M QS0 M QS M QS M QS M QS M QS M QS M QS thlon Sg SOKET PIN thlon Sg Processor Socket SOKET PIN M QS0 M QS M QS M QS M QS M QS M QS M QS M QS[0..] <> <> M QS#[0..] M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS#[0..] <> Quanta omputer Inc. PROJET : Z0 Size ocument Number Rev M Griffin RII MEMORY I/F Friday, pril, 00 ate: Sheet of E

4 THLON ontrol and ebug.v LYOUT: ROUTE V TRE PPROX. 0 mils WIE (USE x mil TRES TO EXIT LL FIEL) N 00 mils LONG. If M SI is not used, the SI pin can be left unconnected and SI should have a 0-Ω (±%) pulldown to VSS. R0 0_ PU_V_RUN.V L LMPG0SN_ 00U-.V_ 0.U_ PU_V_RUN 0.U_ 0 00P_ <> <> PU_LKP PU_LKN.VSUS PU_LKP PU_LKN R 0_ R 0_ R R place them to PU within." VLT_RUN *0_ *K/F_ 00P_ R /F_ 00P_ PU_SI PU_SI PU_LERT PU_V_RUN Keep trace from resisor to PU within 0." keep trace from caps to PU within." PU_LKIN_S_P PU_LKIN_S_N R R./F_./F_ PU_HT_RESET# PU_HT_PWRG PU_HT_LTSTOP# PU_LT_REQ#_PU PU_SI PU_SI PU_LERT PU_HTREF0 PU_HTREF PU_SI <> PU_SI <> F F F0 F F E R P U V V LKIN_H LKIN_L RESET_L PWROK LTSTOP_L LTREQ_L SI SI LERT_L HT_REF0 HT_REF KEY KEY SV SV THERMTRIP_L PROHOT_L MEMHOT_L THERM THERM M W F W W PU_SV_R PU_SV_R PU_THERMTRIP# PU_PROHOT# PU_MEMHOT# PU_THERM PU_THERM.VSUS R0 00_ PU_THERMTRIP# PU_PROHOT# R.VSUS.VSUS PWROK_E <,> THERM_SYS_PWR <,0> *Short_ MP_THERMIP# <>.V //0' hange to.v R *.K_ Q MMT0 R 00_ R R0 0_ R Q MMT0 *0_ *.K_ E_PROHOT# <> MP_PROHOT# <> <> //0' hange to <> HTPU_PWRG HTPU_STOP# R R *Short_ *Short_.VSUS R 00_.VSUS R 00_.VSUS PU_HT_PWRG PU_HT_LTSTOP# R 00_ lose PU Sockt.U_ /0/0' Implement on -test T T <> <> <> <> PU_V0_F_H PU_V0_F_L PU_V_F_H PU_V_F_L.VSUS R0 *0/F_ R0 *0/F_ T T T T T T T T T R 0_ PU_RY PU_TMS PU_TK PU_TRST# PU_TI PU_TEST_TSTUP PU_TEST_PLLTEST PU_TEST_PLLTEST0 PU_TEST_H_YPSSLK_H PU_TEST_L_YPSSLK_L PU_TEST_SNEN PU_TEST0_SNLK PU_TEST_SNLK PU_TEST_SNSHIFTEN PU_TEST_SNSHIFTEN PU_TEST_SINGLEHIN PU_TEST_NLOGIN F E Y G0 F H0 G E E F E E F V0_F_H V0_F_L V_F_H V_F_L RY TMS TK TRST_L TI TEST TEST TEST TEST_H TEST_L TEST TEST0 TEST TEST TEST TEST TEST TEST RSV RSV RSV RSV RSV VIO_F_H VIO_F_L VN_F_H VN_F_L REQ_L TO TEST_H TEST_L TEST TEST TEST TEST TEST TEST0 TEST TEST_H TEST_L RSV0 RSV RSV RSV RSV W Y H G E0 PU_REQ# E PU_TO J PU_TEST_H_PLLHRZ_P H PU_TEST_L_PLLHRZ_N PU_TEST_P E PU_TEST_P F PU_TEST_P PU_TEST_P0 K PU_TEST_H_FLKOUT_P PU_TEST_L_FLKOUT_N H H VIO_F_H <> T T T T T PU_VN_RUN_F_H <> PU_VN_RUN_F_L <> T T T T0 route as differential as short as possible testpoint under package PU_SV_R PU_SV_R PU_MEMHOT# //0' hange to R R0 *Short_ *Short_ R *00_ R *0_ Q *MMT0 VI Override ircuit R K_.VSUS R K_ PUMEMHOT# <> Serial VI lock PU SV <> Serial VI ata PU SV <> <> HTPU_RST#.VSUS R0 *Short_ PU_HT_RESET# thlon Sg SOKET PIN thlon Sg Processor Socket SOKET PIN HTPU_PWRG R *Short_ R *0_ R *0_ PU_PWRG_SVI <> R 00_ VFIX MOE PU_LT_REQ#_PU R *Short_ HTPU_REQ# HTPU_REQ# <>.VSUS SV SV Voltage Output(PU Power) 0 0.V 0.V 0.0V 0.V /0/0' Mount 00 ohm on -test PU H/W MONITOR /0/0' Reserve 0 ohm for PU thermal issue on -test V R0 R *0_ PU_THERM /F_ PU_THERM 0 mil trace / 0 mil space 00P_ MIL V_THM.U_ //0' hange from G to G on -test ddress H U G V -LT XN SMT XP SMLK -OVT R 0K_ KSMT KSMLK Q V V R 0K_ N00E To S GPIO To FN THERM_LERT# <> R.K_ PUFN#_ON <> V R.K_ Q N00E V Q N00E MT_PU <> MLK_PU <> PU_TEST_SINGLEHIN PU_TEST_SNSHIFTEN PU_TEST_P0 PU_TEST_P PU_TEST_PLLTEST PU_TEST_PLLTEST0 PU_TEST0_SNLK PU_TEST_SNEN PU_TEST_SNSHIFTEN PU_TEST_SNLK R R R R R R R *00_ *00_ R 00_ R00 *00_ *00_ *00_ *00_ *00_ *00_ R0 00_.VSUS /0/0' Mount 00 ohm on -test R *0_ PU_HT_RESET# R *0_ R0 *0_ R *0_ R 00_.VSUS V R 0K_ Q MMT0 HT ONNETOR PU_REQ# PU_RY PU_TK PU_TMS PU_TI PU_TRST# PU_TO R K/F_ H_HTPU_RST# T T T T T0 T T.VSUS T N *SP-00-0-P-LV HT RSV RSV0 REQ_L RY 0 TK TMS TI TRST_L TO 0 V_PRO_IO_ V_PRO_IO_RESET_L KEY Quanta omputer Inc. PROJET : Z0 Size ocument Number Rev M Griffin TRL & EUG Friday, pril, 00 ate: Sheet of 0 0

5 E PROESSOR POWER N GROUN UF VSS VSS J VSS VSS J PU_ORE0 PU_ORE VSS VSS J0 PU_ORE0 VSS VSS J UE VSS VSS0 J VSS VSS J VSS VSS J G V0_ V_ P VSS VSS K H V0_ V_ P0 VSS VSS K J V0_ V_ R 0 VSS0 VSS K J V0_ V_ R U-.V_ U-.V_.U_.0U_ 0P_ VSS VSS K J V0_ V_ R VSS VSS K J V0_ V_ R VSS VSS K K V0_ V_ T VSS VSS K K0 V0_ V_ T VSS VSS0 L K PU_ORE //0' el, 0, and V0_ V_ T VSS VSS L K V0_0 V_0 T0 VSS VSS L0 L V0_ V_ T VSS VSS L L V0_ V_ T VSS VSS L L V0_ V_ U VSS0 VSS L L V0_ V_ U E VSS VSS L L V0_ V_ U E 0 VSS VSS M L V0_ V_ U E U-.V_ U-.V_.U_.0U_ 0P_ VSS VSS M M V0_ V_ U E VSS VSS M V0_ V_ V E VSS VSS0 M M V0_ V_ V E VSS VSS N M0 V0_0 V_0 V0 E VSS VSS N N V0_ V_ V VSS VSS N0 N PU_VN_RUN V0_ V_ V VSS VSS N N V0_ V_ W VSS0 VSS N V_ Y VSS VSS P PU_VN_RUN K VN_ V_ VSS VSS P M VN_ V_ VSS VSS P P VN_ VSS VSS P T VN_ VIO Y.VSUS VSS VSS00 P V VN_ VIO V VSS VSS0 R VIO V U-.V_ VSS VSS0 R0 U-.V_ U-.V_.VSUS H VIO VIO V VSS VSS0 R J VIO VIO V VSS VSS0 R K VIO VIO U VSS0 VSS0 T K VIO VIO T VSS VSS0 T K VIO VIO0 T VSS VSS0 T K VIO VIO T VSS VSS0 T L VIO VIO T VSS VSS0 T M VIO VIO R VSS VSS0 T M VIO VIO P VSS VSS U M VIO0 VIO P VSS VSS U M EOUPLING ETWEEN PROESSOR N IMMs VIO VIO P VSS VSS U N VIO VIO P VSS VSS U0 VSS0 VSS U E PLE LOSE TO PROESSOR S POSSILE VSS VSS U F thlon Sg SOKET PIN VSS VSS U F VSS VSS U.VSUS thlon Sg F VSS VSS V F Processor Socket VSS VSS0 V F VSS VSS V SOKET PIN F VSS VSS V F VSS VSS V F VSS VSS V 0 F.U_.U_.U_.U_.U_.U_.U_.0U_.0U_ 0P_ VSS0 VSS V.U_.U_.U_ H VSS VSS W H VSS VSS Y H VSS VSS Y H VSS VSS N J VSS M Sg Griffin upg thlon Sg SOKET PIN thlon Sg Processor Socket SOKET PIN Top View F Quanta omputer Inc. PROJET : Z0 Size ocument Number Rev M Griffin PWR & ate: Friday, pril, 00 Sheet of E

6 E E MEM_SMLK MEM_SMT M Q0 M Q MEM_SMT M M 0 M M M M M M Q MEM_SMLK M M 0 M M M M M M Q M Q0 M Q M MVREF_IM M Q M Q M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# M Q M Q MVREF_IM MEM_SMLK M Q M Q M Q M Q M Q M Q M Q M Q M Q M M M0 M Q0 MVREF_IM M Q M M M M M M M M M M M QS0 M M M M M QS M QS M QS M QS M QS M QS M QS M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M 0 M Q M Q M M Q M M Q M M M Q M Q M M Q M M Q M Q M Q M Q M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M M M M M M0 M M M M M M M M M QS# M M QS M QS M QS M QS M QS M QS M QS0 M QS M Q M M M Q M Q0 M M M Q M Q M Q M M 0 M M Q M M Q M Q M Q M Q M M Q M Q0 MEM_SMT M Q M Q M Q M Q M Q M Q M OT M M M S#0 M M KE0 M S#0 M 0 M M WE# M KE0 M M KE M M S#0 M OT M M M M M M M M M 0 M M M M M M M S# M S# M WE# M RS# M M OT0 M S# M RS# M 0 M 0 M S#0 M S# M S# M S# M M M M OT0 M M KE M M M S# M M S# MSM_T <> MSM_LK <>.VSUS V V SMR_VTERM.VSUS SMR_VTERM V V.VSUS.VSUS.VSUS.VSUS.VSUS SMR_VREF V SMR_VTERM V V M [0..] <> M KE0 <> M KE <> M RS# <> M S# <> M WE# <> M S#0 <> M S# <> M OT0 <> M Q[0..] <> M LKOUT <> M LKOUT# <> M LKOUT <> M LKOUT# <> M OT <> M S# <> M S# <> M S#0 <> M QS#[0..] <> M QS[0..] <> M M[0..] <> M LKOUT <> M LKOUT# <> M LKOUT <> M LKOUT# <> M OT0 <> M KE0 <> M KE <> M OT <> M [0..] <> M S# <> M S#0 <> M S# <> M QS#[0..] <> M QS[0..] <> M M[0..] <> M RS# <> M S# <> M WE# <> M Q[0..] <> M S#0 <> M S# <> Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R-II SOIMM* Friday, pril, 00 Z0 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R-II SOIMM* Friday, pril, 00 Z0 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R-II SOIMM* Friday, pril, 00 Z0 REVERSE (H=.) REVERSE (H=.) //0' hange to T T.U_.U_.U_.U_ R *Short_ R *Short_ *0U-.V_ *0U-.V_ 0 U-.V_ 0 U-.V_.U_.U_ R _ R _ RP X_ RP X_ T T.U_.U_ R _ R _.U_.U_ R 0K_ R 0K_.U_.U_ RP X_ RP X_ *.U_ 0 *.U_ 0 U_ U_.U_.U_ RP X_ RP X_.U_.U_ T T Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q 0 Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q 0 Q Q Q Q Q Q0 Q Q Q 0 Q Q Q Q Q Q Q0 0 Q Q Q N 0 N N N 0 N/TEST M0 0 M M M M 0 M M 0 M QS0 QS QS QS 0 QS QS QS QS K0 0 K0 K K KE0 KE 0 VREF RS 0 S WE 0 S0 0 S S0 S 00 S SL Vspd V0 V V V V V V 0 V V 0 V V0 V VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS QS0 QS QS QS QS QS QS QS OT0 OT VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 SO-IMM J RII_SOIMM_R H. SO-IMM J RII_SOIMM_R H. Q0 *N00E Q0 *N00E.U_.U_.U_.U_ RP X_ RP X_.U_.U_.U_.U_ RP0 X_ RP0 X_ RP X_ RP X_.U_.U_.U_ 0.U_ 0.U_.U_.U_.U_.U_.U_.U_ 0.U_ 0.U_.U_ RP X_ RP X_ 0 *0U 0 *0U *.U_ *.U_ RP X_ RP X_ *0U-.V_ 0 *0U-.V_ 0 RP X_ RP X_ *.U_ 0 *.U_ 0.U_.U_.U_.U_ *0U-.V_ *0U-.V_ *.U_ *.U_.U_.U_ R0 *0_ R0 *0_ Q *N00E Q *N00E.U_ 0.U_ 0 *0U *0U RP X_ RP X_.U_.U_.U_.U_ RP X_ RP X_ *.U_ *.U_.U_.U_ RP X_ RP X_ Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q 0 Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q 0 Q Q Q Q Q Q0 Q Q Q 0 Q Q Q Q Q Q Q0 0 Q Q Q N 0 N N N 0 N/TEST M0 0 M M M M 0 M M 0 M QS0 QS QS QS 0 QS QS QS QS K0 0 K0 K K KE0 KE 0 VREF RS 0 S WE 0 S0 0 S S0 S 00 S SL Vspd V0 V V V V V V 0 V V 0 V V0 V VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS QS0 QS QS QS QS QS QS QS OT0 OT VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 SO-IMM J RII_SOIMM_R H. SO-IMM J RII_SOIMM_R H. *.U_ 0 *.U_ 0.U_.U_ R _ R _.U_.U_.U_.U_.U_.U_ RP *.KX_ RP *.KX_.U_.U_.U_.U_ RP X_ RP X_.U_.U_ U-.V_ U-.V_.U_.U_ R _ R _.U_.U_ RP X_ RP X_ *0U-.V_ 0 *0U-.V_ 0.U_.U_ RP X_ RP X_.U_.U_ RP X_ RP X_.U_.U_ *.U_ *.U_ RP X_ RP X_.U_.U_.U_.U_.U_ 0.U_ 0 R *Short_ R *Short_.U_.U_ RP X_ RP X_.U_.U_ RP X_ RP X_.U_ 0.U_ 0.U_.U_ R _ R _ RP X_ RP X_.U_.U_.U_.U_ R K/F_ R K/F_.U_.U_ T T.U_.U_.U_.U_.U_.U_.U_.U_ RP0 X_ RP0 X_ RP X_ RP X_.U_.U_ R K/F_ R K/F_ RP X_ RP X_ R0 _ R0 _.U_ 0.U_ 0 R 0_ R 0_.U_.U_ *.U_ *.U_.U_.U_.U_.U_.U_.U_.U_.U_ RP X_ RP X_.U_.U_.U_.U_ RP X_ RP X_

7 <> HT_TX[..0] <> HT_TX#[..0] HT_RX[..0] <> HT_RX#[..0] <> U FG-NVII-MP JMP0T0 HT_TX0 HT_TX#0 HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX0 HT_TX#0 HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# F G H J J K K L G F L K L K J K E F G H J L K E E HT_MP_RX0_P HT_MP_RX0_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX0_P HT_MP_RX0_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N SE OF HT HT_MP_TX0_P HT_MP_TX0_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX0_P HT_MP_TX0_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N K J K L K L L K K L K L H J L0 M0 G H F G H J E F E F G 0 0 E F HT_RX0 HT_RX#0 HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX0 HT_RX#0 HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# MP_PROHOT#.VSUS R 00_ <> HT_PU_WNLK0 <> HT_PU_WNLK#0 <> HT_PU_WNLK <> HT_PU_WNLK# J H L K HT_MP_RX_LK0_P HT_MP_RX_LK0_N HT_MP_RX_LK_P HT_MP_RX_LK_N HT_MP_TX_LK0_P HT_MP_TX_LK0_N HT_MP_TX_LK_P HT_MP_TX_LK_N K J G H HT_PU_UPLK0 <> HT_PU_UPLK#0 <> HT_PU_UPLK <> HT_PU_UPLK# <> <> HT_PU_WNTL0 <> HT_PU_WNTL#0 <> HT_PU_WNTL <> HT_PU_WNTL# H G MP_THERMIP# <> MP_THERMIP# MP_PROHOT# <> MP_PROHOT# L TI00U00_.V_PLL_HT 0m V.U_ R.U_ L TI00U00_ m.v_n.u_.v_ht_pll.u_,, : L TI00U00_ m.v_n.u_.v_pll_pu //0' hange from.uf to.uf.u_ /0/0' hange footprint from to 00.V_HT_PLL R 0/F_ HTMP_OMP_VM R0 0/F_ HTMP_OMP_ L HT_MP_RXTL0_P HT_MP_RXTL0_N HT_MP_RXTL_P HT_MP_RXTL_N THERMTRIP#/GPIO_ PROHOT#/GPIO_0.V_LL_HT.V_PLL_HT.V_PLL_PU HT_MP_OMP_V HT_MP_OMP_ HT_MP_TXTL0_P HT_MP_TXTL0_N HT_MP_TXTL_P HT_MP_TXTL_N HT_MP_REQ# HT_MP_STOP# HT_MP_RST# HT_MP_PWRG LKOUT_00MHZ_P LKOUT_00MHZ_N LKOUT_MHZ.V_HT_.V_HT_.V_HT_ K0 J0 0 L M K Y Y Y HTPU_REQ# LKOUT_MHz.V_HT_ 0 HT_PU_UPTL0 <> HT_PU_UPTL#0 <> HT_PU_UPTL <> HT_PU_UPTL# <> T0 HTPU_REQ# <> HTPU_STOP# <> HTPU_RST# <> HTPU_PWRG <> PU_LKP <> PU_LKN <> L TI00U00_.V_N 00m.V_N R 0_.U_ PU_SVREF G R.K/F_MP_TERM_J PU_SVREF LK00_TERM_.V_HT_.V_HT_.V_HT_.V_HT_ V V W W U_.V_HT_ U_.U_ U-.V_ L PY00T_.V_N 0m U_ U_.U_.U_ U-.V_ Quanta omputer Inc. PROJET : Z0 Size ocument Number Rev MP HyperTransport us ate: Friday, pril, 00 Sheet of

8 U FG-NVII-MP F G F F 0 0 F F F F H H H H H H K K K K K K J J0 K K0 PE0_RX0_P PE0_RX0_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE0_RX0_P PE0_RX0_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N SE OF PIE PE0_TX0_P PE0_TX0_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE0_TX0_P PE0_TX0_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N 0 0 E E0 F F0 G G0 H H0 H H [LN] [NEW R] [MINI R-] <,,> PIE_WKE# 0m <> PIE-LN_RXP <> PIE-LN_RXN <> LN_LKREQ# <> PIE-NEW_RXP <> PIE-NEW_RXN <> NEW_LKREQ# <> PPE# <> PIE-MINI_RXP <> PIE-MINI_RXN <> MINI_LKREQ#.V_N : //0' hange from.uf to.uf /0/0' hange footprint to 00 0m.V_N.V_PLL_HT L 0 L T0 T0 T0 T0 S PE0_PRSNTX PE0_PRSNTX PE0_PRSNTX PE0_PRSNTX LN_LKREQ# NEW_LKREQ# PPE#_R MINI_LKREQ# MLG00NJ_.V_PLLPE_SS.U_.U_.V_PLLPE_SS U MLG00NJ_.V_PLLPE R0.U_ R.U_.V_PLL_HT P0 PE_LK_OMP V.U_ R *.K/F_ <00mil H U U0 U U L L0 W W M M U U N N U U N0 N R U P P0 T V P P U V0 PE_WKE#/GPIO_ PE0_PRSNT_# PE0_PRSNT_# PE0_PRSNT_# PE0_PRSNT_# PE_RX_P PE_RX_N PE_LKREQ# PE_PRSNT# PE_RX_P PE_RX_N PE_LKREQ# PE_PRSNT# PE_RX_P PE_RX_N PE_LKREQ# PE_PRSNT# PE_RX_P PE_RX_N PEE_LKREQ#/GPIO_ PEE_PRSNT# PE_RX_P PE_RX_N PEF_LKREQ#/GPIO_ PEF_PRSNT# PE_RX_P PE_RX_N PEG_LKREQ#/GPIO_ PEG_PRSNT#.V_PLL_PE_SS.V_PLL_PE N/.V_PLL_PE N/.V_PLL_PE_SS PE_LK_OMP Remove R for Nvidia suggest. PE_REFLK_P PE_REFLK_N PE_TX_P PE_TX_N PE_REFLK_P PE_REFLK_N PE_TX_P PE_TX_N PE_REFLK_P PE_REFLK_N PE_TX_P PE_TX_N PE_REFLK_P PE_REFLK_N PE_TX_P PE_TX_N PEE_REFLK_P PEE_REFLK_N PE_TX_P PE_TX_N PEF_REFLK_P PEF_REFLK_N PE_TX_P PE_TX_N PEG_REFLK_P PEG_REFLK_N.V_PE_.V_PE_.V_PE_.V_PE_.V_PE_.V_PE_.V_PE_.V_PE_.V_PE_.V_PE_.V_PE_.V_PE_.V_PE_ PE_RST0# PE_RST# R R0 M M T T M M T T0 M M T T M0 M T T P P T T P P P R W W V V W Y Y Y Y W Y W Y W0 W PIE-LN_TXP_ PIE-LN_TXN_ LK_PIE-LN R LK_PIE-LN_#_R PIE-NEW_TXP_ PIE-NEW_TXN_ LK_PIE_NEW_R LK_PIE_NEW#_R PIE-MINI_TXP_ PIE-MINI_TXN_ LK_PIE_MINI_R LK_PIE_MINI#_R //0' dd and Empty R and R, dd R0 and R.V_PE R R0.V_PE R *0_ *0_ *Short_.U_ R R 0 0 *.U_ *.U_.U_.U_ R _ R _.U_.U_ R _ R _.U_.U_ R _ R0 _ //0' el U_ *0_ *Short_.U_ PIE-LN_TXP <> PIE-LN_TXN <> LK_PIE-LN <> LK_PIE-LN# <> PIE-NEW_TXP <> PIE-NEW_TXN <> LK_PIE_NEW <> LK_PIE_NEW# <> PIE-MINI_TXP <> PIE-MINI_TXN <> LK_PIE_MINI <> LK_PIE_MINI# <> //0' hange to short pad from 0 ohm L U-.V_ U_ *Short_.V_N [NEW R] [MINI R-] //0' hange the 0 and 0 from.v_pe_ to.v_pe_ and Empty it PIE_RST# <> dd 0R resistor, The resistor should only be stuffed for MP [R Reader] [LN] 00m00m m00m //0' Empty,.U_ L0 *U-.V_ *U-.V_ U-.V_ PY00T_.V_N PIE_RST# <> LK_PIE-LN *0P_ For EMI LK_PIE-LN# *0P_ LK_PIE_MINI LK_PIE_MINI# *0P_ *0P_ LK_PIE_NEW LK_PIE_NEW# *0P_ *0P_ Quanta omputer Inc. PROJET : Z0 Size ocument Number Rev MP PI-Express us ate: Friday, pril, 00 Sheet of

9 REQ0# REQ# REQ# REQ# REQ# E0 G0 J0 M E U FG-NVII-MP PI_REQ0# PI_REQ#/FNRPM PI_REQ#/GPIO_0/RS_SR# PI_REQ#/GPIO_/RS_TS# PI_REQ#/GPIO_/RS_SIN# MP SE OF PI_GNT0# PI_GNT#/FNTL PI_GNT#/GPIO_/RS_TR# PI_GNT#/GPIO_/RS_RTS# PI_GNT#/GPIO_/RS_SOUT# F0 H0 K0 L0 F GNT0# T V INT# INT# EVSEL# INT# PI/LP PULL-UP 0 RP.KX_0PR INT# TRY# PERR# REQ# V INT# INT# INT# INT# L K J J H G F E G E J K L G J E H F L J K PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_INTW# PI_INTX# PI_INTY# PI_INTZ# PI PI_E0# PI_E# PI_E# PI_E# PI_EVSEL# PI_FRME# PI_IRY# PI_PR PI_PERR#/GPIO_/RS_# PI_SERR# PI_STOP# PI_PME#/GPIO_0 PI_RESET0# PI_RESET# PI_RESET# PI_LK0 PI_LK PI_LK PI_LK PI_LK PI_LKIN K K F K L J H J J K K EVSEL# FRME# IRY# PERR# SERR# STOP# PI_PME# PIRST_R# R IERST_R# PIRST# PI_LK R PI_LK PI_LK PI_LK PI_LK PI_LKIN T T *_ T T T T R _ PIRST# <> L:match to within 000 = Length of PI feedback and onboard devices = V STOP# SERR# IRY# FRME# PI_PME# LKRUN# 0 R0 LOK YPSS LP_LK_E RP.KX_0PR R *.K_.K_ REQ# REQ# REQ0# REQ# V *P_ V TRY# K PI_TRY# <> LKRUN# <> SERIRQ R0 T00 T0 0K_ LRQ# LRQ#0 SERIRQ P F0 L K K K J L L J K L J J L K G0 PI_LKRUN#/GPIO_ LP_RQ#/GPIO/FNRPM LP_RQ0#/GPIO_0 LP_SERIRQ IE_T_P0/WUS_T0 IE_T_P/WUS_T IE_T_P/WUS_T IE_T_P/WUS_T IE_T_P/WUS_T IE_T_P/WUS_T IE_T_P/WUS_T IE_T_P/WUS_T IE_T_P IE_T_P IE_T_P0 IE_T_P IE_T_P IE_T_P IE_T_P IE_T_P IE LP LP_FRME# LP_PWRWN#/GPIO_/EXT_NMI# LP_RESET0# LP_RESET# LP_0 LP_ LP_ LP_ LP_LK0 LP_LK IE_R_P0/WUS_STOP IE_R_P/WUS_RX_EN IE_R_P/WUS_TX_EN IE_S_P#/WUS_PHY_RESET# IE_S_P# IE_K_P# L G E H J K J LFRME#_R LP_P# LP_RST# LP_RST# L0_R L_R L_R L_R LP_LK_E_R PI_LK_EUG R R _ T R0 _ T R0 _ R _ R _ R0 _ R0 _ R0 _ LFRME# <,,> PLTRST# <,> L0 <,> L <,> L <,> L <,> LP_LK_E <> PI_LK_EUG <> PI_LK_EUG R PI_LKIN *P_ *P_ V R R R.K_ 0K_.K_ PREQ K IE_INTR H0 PIORY K0 L0 LE_ET_P F IE_REQ_P/WUS_PLK IE_INTR_P/WUS_PHY_TIVE IE_RY_P/WUS_T_EN IE_IOR_P#/WUS_SERIL_T LE_ET_P/GPIO_ IE_IOW_P#/WUS STTUS IE_OMP_PV IE_OMP_ J0 M K IE_OMP_V R0 IE_OMP_V_ /F_ V R0 K_ R /F_ Quanta omputer Inc. PROJET : Z0 Size ocument Number Rev MP PI/LP/IE ate: Friday, pril, 00 Sheet of

10 U FG-NVII-MP R R0 0K_ 0K_ 0 0 E F G J0 J RGMII_RX0/MII_RX0 RGMII_RX/MII_RX RGMII_RX/MII_RX RGMII_RX/MII_RX RGMII_RX/MII_RXLK RGMII_RXTL/MII_RXV MII_RXER/GPIO_ MII_OL/MSM_T MII_RS/MSM_LK SE OF LN.V_UL_RMGT.V_UL_RMGT RGMII_TX0/MII_TX0 RGMII_TX/MII_TX RGMII_TX/MII_TX RGMII_TX/MII_TX RGMII_TXLK/MII_TXLK RGMII_TXTL/MII_TXEN L V_UL N.V_UL J K L L H R0 K V_UL.V_UL 0K_ R 0K_ LN_INT RGMII/MII_INTR/GPIO RGMII/MII_M RGMII/MII_MIO K0 L0 MIO R 0K_.V_UL.V_UL N.V_PLL_M_UL RGMII/MII_PWRWN#/GPIO_ MII_OMP_PV MII_OMP_ UF_MHZ MII_RESET# MII_VREF G H0 RGMII_VREF R 0K_ R /F_.0U_ RG RSET K RG VREF RG RSET RG VREF RG RE RG GREEN RG LUE INT_RT_R <> INT_RT_G <> INT_RT_ <> INT_RT_R INT_RT_G INT_RT_ R R R 0/F_ 0/F_ 0/F_ m.v_n L TI00U00_.U_ 0.U_ //0' hange from.uf to.uf /0/0' hange footprint to 00 <> L_KLT_TRL <> INT_LVS_LON <> INT_LVS_IGON.V_PLL_ISP N E F MP_GPIO MP_GPIO HMI_TXP_ HMI_TXN_ HMI_TX0P_ K HMI_TX0N_ J HMI_TXP_ M0 HMI_TXN_ L0 HMI_TXP_ K0 HMI_TXN_ J0 HP_ROM_SLK HP_ROM_ST R 0K_ HPLUG_ET E R0 0K_ HPLUG_ET //0' hange to L L *Short_ 0m.V.U_ 0 *U_.V_IFP.U_ L TI00U00_ mm V 0 *.U_.V_PLL_IFPP //0' Empty *.U_ //0' hange from 0.UF to.uf 0.U_ m.v_pllpe_ss U0 00m.V_N L TI00U00_.V_P_V H HMI_RSET K HMI_VPROE K.U_.U_.U_ V R0 R T T T0 T T T0 T T T T *.K_ *.K_ R *K/F_ *.0U_ E H U T E E L M TV RSET TV VREF.V_PLL_ISP TV_XTLIN TV_XTLOUT GPIO_/FERR/SYS_SERR/IGPU_GPIO_* GPIO_/NFERR/SYS_PERR/IGPU_GPIO_* L_KL_TL L_KL_ON L_PNEL_PWR HMI_TX_P/ML0_LNE_P HMI_TX_N/ML0_LNE_N HMI_TX0_P/ML0_LNE_P HMI_TX0_N/ML0_LNE_N HMI_TX_P/ML0_LNE_P HMI_TX_N/ML0_LNE_N HMI_TX_P/ML0_LNE0_P HMI_TX_N/ML0_LNE0_N UX_H0_P UX_H0_N HPLUG_ET HPLUG_ET.V_IFP.V_IFP.V_IFP_HV.V_HMI_PLL_HV.V_PLL_P.V_P_V HMI_RSET HMI_VPROE S FLT PNEL RG HSYN RG VSYN _LK0 _T0.V_RG_.V_TV_ TV RE TV GREEN TV LUE IFP_TX_P IFP_TX_N IFP_TX0_P IFP_TX0_N IFP_TX_P IFP_TX_N IFP_TX_P IFP_TX_N IFP_TX_P IFP_TX_N IFP_TX_P IFP_TX_N IFP_TX_P IFP_TX_N IFP_TX_P IFP_TX_N IFP_TX_P IFP_TX_N IFP_TX_P IFP_TX_N _LK _T _LK _T IFP_RSET IFP_VPROE G H G H E F E0 E 0 0 J J E E F0 F G0 G H H0 L J L K 0 V.U_.U_ INT_TXLOUT INT_TXLOUT- UM_HMI_LK UM_HMI_T IFP_RST IFP_VPROE L HSYN <> VSYN <> RTLK <> RTT <> TI00U00_ R 0_ V R 00//-Edison add, follow NV recommend. *0_ T0 T0 *.U_.U_ R R TXLLKOUT <> TXLLKOUT- <> TXLOUT0 <> TXLOUT0- <> TXLOUT <> TXLOUT- <> TXLOUT <> TXLOUT- <> L_EILK <> L_EIT <> 0K_ V 0K_ V [LVS] m //0' Mount.UF(HM0) //0' hange footprint from 00 to 00 R *K/F_ Quanta omputer Inc. PROJET : Z0 Size ocument Number Rev MP LN and Graphics ate: Friday, pril, 00 Sheet 0 of

11 UE FG-NVII-MP [ST H] [ST O].VSUS <> ST_TXP0 <> ST_TXN0 <> ST_RXN0 <> ST_RXP0 <> ST_TXP <> ST_TXN <> ST_RXN <> ST_RXP.0U_.0U_.0U_.0U_ ST_TXP0_ E ST_TXN0_ E ST_TXP_ ST_TXN_ G G E E G G H H ST_0_TX_P ST_0_TX_N ST_0_RX_N ST_0_RX_P ST TX_P ST TX_N ST RX_N ST RX_P ST_0_TX_P ST_0_TX_N ST_0_RX_N ST_0_RX_P ST SE OF US US0_P US0_N US_P US_N US_P US_N US_P US_N US_P US_N US_P US_N US_P US_N US_P US_N US_P US_N US_P US_N U U U U U U V V W W W W W W Y Y USP USP- USP USP- USP0 <> USP0- <> USP <> USP- <> USP <> USP- <> USP <> USP- <> USP <> USP- <> USP <> USP- <> USP <> USP- <> USP <> USP- <> INT LEFT US- INT LEFT US- ard Reader NEW R LUETOOTH EXT US(PJ) MINI R- US PULL-OWN USP RN USP- USP0 RN USP0- USP RN USP- USP RN USP- KX_ KX_ KX_ KX_ 0.U_ 0.U_ 0.U_.U_.U_ 0.U_.U_.V- coupling capacitor for ST Placement put near ST trace that cross through.v and.u_ T T T T ST_TXP ST_TXN G G ST_RXN F ST_RXP F L L K L ST TX_P ST TX_N ST RX_N ST RX_P ST_0_TX_P ST_0_TX_N ST_0_RX_N ST_0_RX_P US0_P US0_N US_P US_N US_P US_N US_P US_N US_P US_N RSV RSV USP USP- USP USP- USP USP- USP USP- USP0 <> USP0- <> Fingerprint USP RN USP- USP- USP RN USP RN USP- USP RN USP- USP RN USP- KX_ KX_ KX_ KX_ KX_ 0,, : //0' hange to.uf /0/0' hange footprint to 00 0m.V_N 0m 0m 0m R //0' hange to <> ST_LE# L0.V_N 0 L.V_N L.V_N *Short_ 0U-.V_.V_SP_ 0U-.V_ MLG00NJ_.V_PLL_SP_V.U_.U_ MLG00NJ_.U_.V_PLL_SP_SS.U_ TI00U00_.U_.V_PLL_LEG.U_.U_.U_.U_ J J K K W V P E E E E 0.U_ 0 ST TX_P ST TX_N ST RX_N ST RX_P ST_LE#/GPIO_.V_PLL_SP_V.V_PLL_SP_SS.V_PLL_LEG.V_SP_.V_SP_.V_SP_.V_SP_.V_SP_.V_SP_ RSV RSV RSV RSV US_O0#/GPIO_ US_O#/GPIO_ US_O#/GPIO_ US_O#/GPIO_/MGPIO_ US_O#/GPIO_/MGPIO_.V_PLL_US.V_US_UL.V_US_UL T T T T T P Y Y USO#0 USO# USO# USO# USO#.V_US_PLL 0.U_.V_US_UL L USO# USO#0 USO# USO# V *.U_ //0' Empty.U_ TI00U00_ L0.U_ RN0 R TI00U00_ V_S 0KX_PR 0K_ m VSUS 0m USP- RN USP USP RN USP- USP RN USP- USP0- RN USP0 USP RN USP- USP RN USP- KX_ KX_ KX_ KX_ KX_ KX_ m.v_n L PY00T_ 0.U_ 0.U_ 0.U_ 0.U_.V_SP_ ST_THRM.U_ R.K/F_ 0 0 E0 J.V_SP_.V_SP_.V_SP_ ST_TERMP US_RIS_ T US_RIS_ R /F_ 00//: Page the resistor R from 0ohm change to ohm(follow NV suggest) Quanta omputer Inc. PROJET : Z0 Size ocument Number Rev MP ST and US ate: Friday, pril, 00 Sheet of

12 E_SI# KSMI# R *0K_ R *.K_ <> ST-O_PRESENT# <> GTE0 <> RIN# <> E_SI# <> KSMI# <> SM_INTRUER# <> MP_LI# <0> H_SIN0 <0> H_SIN V T T T T T T0 R 0_ T T H_SIN MP_GPIO P MXM_PRESENT# MP_GPIO N R MXM_RUNPWROK M PE_RST_MXM# M0 SIO_PME# RI# M K K M P P L P PM_T# N0 UF FG-NVII-MP H_ST_IN0/GPIO_ H_ST_IN/GPIO_/MGPIO_0 H_ST_IN/GPIO_/MGPIO_ GPIO_/PWRN_OK/SPI_S GPIO_/NMI/PS_LK0 GPIO_/SMI#/PS_T0 GPIO_/SI/PS_LK GPIO_/INIT#/PS_T GPIO_/SUS_STT/LMTR_EXT_TRIG# 0GTE/GPIO_/FNTL KRRSTIN#/GPIO_/FNRPM SIO_PME#/GPIO_/SPI_S EXT_SMI#/GPIO_ RI#/GPIO INTRUER# LI# LL# SE OF H MIS H_OK_EN#/GPIO_ H_OK_RST#/GPIO H_ST_OUT/GPIO_ H_ITLK H_RESET# H_SYN/GPIO_ SLP_S# SLP_RMGT# SLP_S# MP_VI0/GPIO_ MP_VI/GPIO_ MP_VI/GPIO_ SPKR R P R H H H K MP_GPIO MP_GPIO H_SOUT H_ITLK H_RESET# H_SYN R H_SOUT H_SYN H_ITLK H_RESET# SUSR# R 0_ SLP_RMGT# SUSR# R T *Short_ VORE.I0_R R_PPE# R_WKE# T T H R _ R _ R _ R _ R _ R _ R _ R _ R *K_ //0' hange R to T T T *K_ EMI Solution H_SOUT H_SYN H_RESET# H_ITLK R00 0_ SUS# <> SUS# <> MP_SPKR <0> H_SOUT_O <0> H_SOUT_M <0> H_SYN_O <0> H_SYN_M <0> H_ITLK_O <0> H_ITLK_M <0> H_RESET#_O <0> H_RESET#_M <0> 0P_ 0P_ 0P_ 0P_ MP STRPPING H_RESET# (LN) 0 MII RGMII (EFULT) H_SOUT_R, LFRM# (IOS) 00 LP (EFULT) 0 PI IOS 0 SPI IOS RESERVE (SPI) MP_SPKR (oot MOE) 0 USER TLE (EFULT) SFE TLE H_SYN_R (SIO LOK) 0.MHz (EFULT) MHz SPI_O, SPI_LK (SPI LOK) 00 MHz 0 MHz 0 MHz MHz V_S R0 0K_ H_RESET# R *0K_ V V R R *.K_ *.K_ R R.K_.K_ H_SOUT LFRME# <,,> V R *0K_ MP_SPKR R 0K_ V R *0K_ R 0K_ H_SYN U_ V W W0 Y0 0 W Y FI_RSV0 FI_RSV FI_RSV FI_RSV FI_RSV FI_RSV FI_RSV FI_RSV FI_RSV SM_LK0 SM_T0 SM_LK/MSM_LK SM_T/MSM_T SM_LERT#/GPIO_ THERM#/GPIO_ E G E F F K SM_LERT# PLK_SM <,> PT_SM <,> MSM_LK <> MSM_T <> THERM_LERT# <> V_S V_S R R0 R R 0K_ *0K_ *0K_ 0K_ MP_SPI_O MP_SPI_LK <> NSWON# <> RTRST# elay 0ms after S powerok <> RSMRST# <,> PWROK_E <,> HWPG_.V R <,0> HWPG_.V <,> PU_OREPG //0' hange R to R _ T R R0 P_ P_ P_ R *Short_ PWRTN# RSTTN# HT_VL T MP_TI U T MP_TO T T MP_TMS T *0K_ MP_TRST# U K_ MP_TK T *0M_ P_ Y MHZ XTL XTL LK_KX LK_KX Y.KHz R0 P M L T0 M P M H H H H PWRTN# RSTTN# RT_RST# PWRG_S PWRG MEM_VL MP_VL/HT_VL PU_VL JTG_TI JTG_TO JTG_TMS JTG_TRST# JTG_TK XTLIN XTLOUT XTLIN_RT XTLOUT_RT SM/I PULL-UP PLK_SM R.K_ PT_SM R.K_ SM_LERT# R.K_ THERM_SI/GPIO_/MSM_LK THERM_SI/GPIO_/MSM_T THERM_LERT#/GPIO_/PWR_LE# FNRPM0/GPIO_0 FNTL0/GPIO_ FNTL/GPIO_ MPV_EN/HTV_EN PUV_EN SPI_S0/GPIO_0 SPI_LK/GPIO_ SPI_I/GPIO_ SPI_O/GPIO_ SUS_LK/GPIO_ UF_SIO_LK TEST_MOE_EN PKG_TEST V_S MP_GPIO F F F N M K K M J P J ORI0 ORI ORI HTV_EN MP_GPIO0 MP_SPI_LK EMIL_LE# MP_SPI_O SUS_LK_R SIO_LK P TESTMOE_EN P0 R T T T T R K_ K_ PU_SI <> PU_SI <>.VSUS HTV_EN <,0> PU_VRON <> cer Suggest Reserve HP EEPROM 00//0 NO PN HP EEPROM R *.K_ R *.K_ V_S HP_WP PLK_SM PT_SM *.u/v_ U V 0 WP SL N S *T N 00//-Edison: Removethese part R, R, R, R,, Q, Q MSM_LK MSM_T R R.K_.K_ V V_S 0 R00 0K_ R0 *0K_ R 0K_ R *0K_ R 0K_ ORI0 ORI ORI R0 *0K_ M/ I for "/" I0 I I M/ " 0 0 X 0 0 " 0 0 " U 0 " ual ore PU & MXM 0 " ual ore PU & UM " Single ore PU & UM *MP JTG HEER Quanta omputer Inc. PROJET : Z0 Size ocument Number Rev MP H/SM/PMU/GPIO ate: Friday, pril, 00 Sheet of

13 .V_UL V_UL VRT RT_HG RT_HG RT_HG VRT_ VRT_ RTRST# SM_INTRUER# <> RTRST# <>.V_S V_S V N_ORE VRT VPU VPU VRT V_UL.V_UL Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : MP POWER//RT Friday, pril, 00 Z0 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : MP POWER//RT Friday, pril, 00 Z0 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : MP POWER//RT Friday, pril, 00 Z0 MP POWER PLNE/ & YPSS 0m RT 0MIL 0MIL 0MIL 0m 0m 0m //0' hange to //0' hange to.u_.u_ R *Short_ R *Short_.U_.U_ R 0K/F_ R 0K/F_ *U_ *U_ H00H H00H U_ U_ R0 *Short_ R0 *Short_ 0.U_ 0.U_ R0 K_ R0 K_ R 0K/F_ R 0K/F_.U_.U_ N RT-T_ONN N RT-T_ONN R.K/F_ R.K/F_ U-.V_0 U-.V_0 H00H H00H.U_.U_ R K/F_ R K/F_.U_.U_.U_.U_.U_.U_ L G M M N U0 U M L H P L J V M M N N0 G R M E G F F E G J F M T0 U J J E T P G G N 0 J T H E N Y E Y J J J U N M R R U H M P T N R E J P Y T Y J T F J V E 0 F0 F V G0 G J E0 J J L E E N J V0 E E P H F R R N H G L N F M N V R M W J T T SE OF FG-NVII-MP UH SE OF FG-NVII-MP UH 0.U_ 0.U_.U_.U_ R.K/F_ R.K/F_.U_.U_.U_.U_.U_.U_.U_.U_.U_.U_.U_.U_.U_.U_.U_.U_ U-.V_ U-.V_.U_.U_.U_.U_.U_.U_ U-.V_ U-.V_ G *SHORT_ P G *SHORT_ P.U_.U_ N.V_UL N.V_UL V0.0V.0V 0.0V W.0V.0V.0V.0V.0V W.0V.0V.0V.0V V.0V.0V U.0V Y.0V W.0V0 Y.0V U.0V U.0V Y0.0V.0V.0V V.0V Y.0V Y0.0V W0.0V V.0V0.0V N.V_VT L.V_UL L.V_UL H.V F.V G.V J.V R J G G R H R M K N H V L P L V F F M E H F M M V F Y G N R V E U E M Y E H PWR/ SE OF UG FG-NVII-MP PWR/ SE OF UG FG-NVII-MP.U_.U_.U_.U_.U_.U_ R M_ R M_.U_.U_ U_ U_.U_.U_.U_.U_.U_.U_ Q MMT0 Q MMT0 U_ U_

14 LVS SINGLE_H N TXLLKOUT- _L L_V TXLLKOUT RIGHTNESS.U_ TXLOUT0- V TXLOUT0 _PWR TXLLKOUT 0 0 TXLLKOUT- TXLOUT- TXLOUT L_ON TXLOUT0 <> L_ON RIGHTNESS TXLOUT0- TXLOUT- R 0_ L_EILK TXLOUT L_EIT 0 0 TXLOUT L TXLOUT- V <> USP- USP-_R R.K_ <> USP USP_R TXLOUT R0.K_ TXLOUT- *RFM00M 0 0 L_EILK R 0_ ON0X_0 L_EILK L_EIT L_EIT <0> TXLLKOUT- <0> TXLLKOUT <0> TXLOUT0- <0> TXLOUT0 <0> TXLOUT- <0> TXLOUT <0> TXLOUT- <0> TXLOUT <0> L_EILK <0> L_EIT //0' hange R and R0 to R0 R R.U-V_ *0_ *Short_ *Short L 000P_ L_KLT_TRL <0> E_L_KLT_TRL <> *000P_ EMI Solution *000P_ L POWER V U //0' hange to lose to LVS ONN. MER MOULE POWER V R 0 PWR <0> INT_LVS_IGON R.U_ *Short_ //0' hange to ISP_ON R 0K_ IN IN ON/OFF T0 OUT LV_.U_ R *Short_ 0U-.V_.U_.0U_ L_V 0U-.V_ Q *O 0U-.V_ 000P_ V R EUSE UR'S SUGGESTION, *.K_ TIE HNGE FROM TO HIGH. onfirm by Joms Q *TEU _POWERON <> RT V NHW RTV N <0> INT_RT_R <0> INT_RT_G <0> INT_RT_ <0> HSYN <0> VSYN <0> RTLK INT_RT_R INT_RT_G INT_RT_ HSYN VSYN RTLK INT_RT_R INT_RT_G INT_RT_ R R R 0/F_ 0/F_ 0/F_ 0 0P_ 0P_ L L L 0P_ K0LL0_ K0LL0_ K0LL0_ 0P_ 0P_ RT_R RT_G RT_ 0P_ 0 RT_ONN T_ RTHSYN RTVSYN LK_ RTV.U_ RTVSYN *0P_ RTHSYN *0P_ <0> RTT RTT LK_ 0P_ V U R *0_ R 0_ RT_SENSE# <> T_ 0P_ 0 V.U_.U_ RTV.U_ INT_RT_R INT_RT_G INT_RT_ V_SYN V_ YP V_VIEO VIEO_ VIEO_ VIEO_ M00 SYN_OUT SYN_OUT SYN_IN SYN_IN _IN _IN _OUT _OUT 0 VSYN HSYN VSYN HSYN RTLK RTT L L R R LK_ T_ M00: L0000W0 IP: L00000 LM0SN_ LM0SN_.K_.K_ RTVSYN RTHSYN V R.K_ RTV R.K_ TV Out (SVHS) MiniIN -pin elete TVOUT MiniIN Quanta omputer Inc. PROJET : Z0 Size ocument Number Rev LVS/RT/P-amera Friday, pril, 00 ate: Sheet of

15 Giga LN MM/M V_LN.V_LN V_LN.V_LN R R.V_LN.V_LN.U_ L 00-00m L 00-00m L 00-00m L 00-00m <> <> <> <> <> <>.U_ 0mil 0mil 0mil R R 0mil PIE-LN_RXP PIE-LN_RXN PIE-LN_TXP PIE-LN_TXN LK_PIE-LN LK_PIE-LN#.U_ M : 0.uF apacitor M : 0 ohm Resistor 0.U_.U_.U_.U_.U_ R R V/V_IO VL PIE_SS_V.U_.U_ TXP_E TXN_E PIE_WKE_R# LN_PERST# U V V V V V V VL VL GPHY_PLLV PIE_PLLV PIE_V PIE_V PIE_ VIO VIO VIO VIO VIO VP MM/M 0mm X 0mm -Pin QFN ISV XTLV V V V VL VL PIE_TXP PIE_TXN PIE_RXP PIE_RXN WKE# PERST# REFLK REFLK- TR- TR TR- TR TR- TR TR0- TR0 LINKLE# SP00LE# SP000LE# TRFFILE# GPIO 0 0 URT_MOE GPIO_SERILI GPIO0_SERILO 0mil ISV XTLV V LINKLE# R0 LN_TLE#.U_.U_ TXP_ TXP_ TXN TXP LN_TXN LN_TXP LN_TXN LN_TXP TX0N TX0P L L L R 0_ M_WP.U_.U_ 00-00m 00-00m 00-00m TXP_ TXP_ LN_TXN LN_TXP LN_TXN LN_TXP V R R R R R R R R R R0 R R @0_ TXP VL TXP VL VH TXN TXN TXP VH TXN TXN TXP VL VH elete LN within OK Selector P_ V_LN V Y MHZ R R0 R LN_XTL LN_XTL K/F_ K/F_.K_ R 0_ R UX_PRES VM_PRES _PWR PLK_SM_LN PT_SM_LN.K/F_ XTLO R VUXPRSNT VMINPRSNT _PWR SM_LK SM_T XTLO XTLI R SLK SI SO S# N/(ENERGY_ET) VP M_SL R SI R M_S S# R R ENERGY_ET_R R @0_ *.K_ *.K_.K_ *.K_ R 0_ V_LN ENERGY_ET <>.V_LN VIO_.V_LN LN_V TX0P TX0N Transformer elta- LFE-R:GIGIT U TT T T- MT MX MX- LN_MT0 LN_MX0 LN_MX0- /0/0' hange PN form 0Z0LN0 to 0Z0LN0 on -test P_ <> LN_LKREQ# V_S Q *TEU LN_LKREQ# V_S R K_ R 0_ N(LK_REQ#) MMKMLG/M REGTL REGTL REG_ R R LN REGTL LN_V TXP TXN LN_V TXP TXN TT T T- TT T MX- T- MT MX MT MX MX- 0 LN_MT LN_MX LN_MX- LN_MT LN_MX LN_MX- <,,> PIE_WKE# PIE_WKE_R# LN_V 0 TT MT LN_MT <> <> PIRST# PIE_RST# R0 0_ R V_LN *0_ R 0_ LN_PERST# LN POWER EEPROM V_LN.U_.U_ 0.U_.U_ TXP TXN T LFE-R MX T- MX- LN_MX LN_MX- R _ R _ LNMT_G R _ R _ <,> <,> PT_SM PLK_SM FOR SF R //0' hange to R LN_LKREQ# Q *N00E *Short_ Q *N00E *Short_ V_LN RP *.KX_ PT_SM_LN PLK_SM_LN V_LN.V_LN V_LN R0 R0.V_LN 0mil._0 0 L.U_ *@K0HS 0. *_0.U_ 0 mil LN REGTL U-.V_ 0mil LN_REG_V VIO_ mil V_LN 0mil LN REGTL 00.U_ L 0mil V_S 0mil.V_LN 0U-.V_.U_.U_.U_.U_.U_ R.K_ R *.K_ R *.K_ EEPROM Strapping c R0 *.K_ M_WP M_SL M_S.U_ U V 0 WP SL N S SO SI S# SLK 0 T V_LN V_LN R 0_ R 0_ *0P-KV_0 *0P-KV_0 EMI solution TIPL RINGL 0P_ N 0P_ FI_SP_HF_JE RJ- N RINGL RING TIPL TIP LN_LINKLE# LE_GREEN LN_V 0 LE_P_ LE_ORNGE LN_V LE_YEL LN_TLE# LE_P_ LN_MX0 TX/0 LN_MX0- TX-/0- LN_MX RX/ LN_MX N/ LN_MX- N/- LN_MX- RX-/- LN_MX N/ LN_MX- N/- RJ-&RJ- 000P-KV_0 EMI Solution LN_LINKLE# LN_TLE# 0 0P_ 0P_ Quanta omputer Inc. PROJET : Z0 Size ocument Number Rev GigaLN M/RJ & RJ Friday, pril, 00 ate: Sheet of

16 *0u/0V_ VPU 0 <,> USON#.U_ U IN OUT IN OUT OUT EN# - O# TPS0GNR R0 *.K/F_ USPWR 00U-.V_ 000P_ LI SWITH //0' hange from 00K to 0K V R0 0K_ R.K_ <> USP0- <> USP0 <> USP- <> USP L WM-0-00T USP0-_R USP0_R Z0-0H_ES /0/0' Implement ES diode on -test L WM-0-00T 0 USP-_R USP_R Z0-0H_ES /0/0' Implement ES diode on -test USPWR 00U-.V_ N SYUIN_US Z0-0H_ES 0 000P_ N SYUIN_US Z0-0H_ES LEFT US LEFT US elete IR Function 00/0/ VPU nda GPIO list have internal PU R0 *0K_ SS *SS R0 0_ 0.U_ R0 0_ VSUS R *0K_ SS LI# Q TEU L_ON <> MP_LI# <> LI# <> MR ME-00 INT_LVS_LON <0> E_FPK# <> R0 0_ U_ VPU H h-tcbcdp PU H h-tcbcdp H h-tcbcdp H h-tcbcdp M H h-tcbcdp H h-tcbcdp LUETOOTH H h-tcbcdp H h-tcbcdp LUETOOTH MOULE ONNETOR Q0 O VSUS T_POWER Power oard FN <> T_POWERON# H h-cdp 00// add H h-cd0p- H h-cdp- P *EMIP <> USP <> USP- <> T_LE EMI solution H h-cdn 00// add P P P *ME-P *ME-P *ME-P H H-P- P *EMIP P *EMIP T_POWER T_LE.P_ N0 T_ONN *EMIP *EMIP P *EMIP H0 h-cdp- P *EMIP P P *ME-P *ME-P 000P_ 0U-.V_ H h-cdp H0 h-cdp H h-cdp P *EMIP P *EMIP P *EMIP H H-scdp- H h-tpbpsdp- H h-tcbexdp- H H-P- P *EMIP P *ME-P P *ME-P H H-P- P0 *EMIP H H-P-.P_ H h-cdp H H-P P P H0 h-cdp- H H-P- H H-P- H h-cdp- H h-cdp- H h-cdp- P0 P P P P P 0/ *ME-P *ME-P *ME-P *ME-P *ME-P *ME-P Quanta omputer Inc. PROJET : Z0 Size ocument Number Rev US/T/LI/HOLE ate: Friday, pril, 00 Sheet of

17 MINI-ard MINI-ard Port- <,> PLTRST# <> PI_LK_EUG <> <> <> <> PIE-MINI_TXP PIE-MINI_TXN PIE-MINI_RXP PIE-MINI_RXN WS_LKR *0P_ If M.P must N all debug R R R *0_ *0_.V WS_TR WS_LKR.U_ 0.U_ N PETp0 PETn0 PERp0 PERn0 V.V 0.V LE_WPN# LE_WLN# LE_WWN# 0 US_ US_- SM_T L K0LM-T_ L K0LM-T_ SM_LK 0.V.Vaux PERST# 0.V V_MINI V_MINI 0 *00U-.V_.U_ RF_LE# R VSUS_MINI T *0_ R *0_ R 0_ S V.U_ VSUS VSUS_MINI *.U_ RF_LE# <> USP <> USP- <> PT_SM <,> PLK_SM <,> PIE_RST# <> RF_EN <>.U_ 0.U_ elete MINI-ard Port- <> <> <> <,,> LK_PIE_MINI LK_PIE_MINI# MINI_LKREQ# PIE_WKE# R 0_ MINI_REQ_LK REFLK REFLK- LKREQ# WKE# 0.V.V RP 0X_ RP0 0X_ R 0_ LFRME# <,,> L <,> L <,> L <,> L0 <,> Q MINIPI_E_ONN_WL *TEU VSUS New card //0' hange to NEW R'S POWER SWITH PIE_WKE# V_S <> R 0_ PPE#_E <> <> <> <> Q *TEU <> <> <> PIE-NEW_TXP PIE-NEW_TXN PIE-NEW_RXP PIE-NEW_RXN LK_PIE_NEW LK_PIE_NEW# <> PPE# NEW_LKREQ# <> <> R USP USP- *Short_ PPE# NEW_V PERST# NEW_VUX NEW_.V NEW_SMT NEW_SMLK PUS# N PETp0 0 PETn0 PERp0 PERn0 0 REFLK REFLK- PPE# LKREQ#.V.V PERST#.VUX WKE# 0.V.V SM_T SM_LK RESERVE RESERVE PUS# US_ US_- 0 U TPSPWG NEW_V V..VOUT..VOUT V_S NEW_VUX UXIN UXOUT.V NEW_.V..VOUT..VOUT PIE_RST# SYSRST# STY# PPE# SHN# PPE# PUS# PUS# RLKEN PERST# N PERST# 0 O# 0 PPE# : ( Internal Pull Up, active low when card support PIE ) PUS# : ( Internal Pull Up, active low when card support US ) SHN# : ( Internal Pull Up ) NEW_V /0/0' el R and for reset issue on -test EXPR-FOXONN V_S V.V Q N00E RP.KX_ PT_SM NEW_SMT.U_.U_.U_.U_.U_ NEW_V Q NEW_VUX NEW_V NEW_.V N00E 0 0 PLK_SM NEW_SMLK.U_.U_.U_.U_.U_.U_ Quanta omputer Inc. PROJET : Z0 Size ocument Number Rev MINI PI-E card & NEW R Friday, pril, 00 ate: Sheet of

18 TP SWITH E-KEY ST H LEFT# SW MISKI_SWITH_. SW <,> MX0 MY0 <,> MISKI_SWITH_. N RXP RXN TXN TXP ST_RXN0_ ST_RXP0_.0U_.0U_ ST_TXP0 <> ST_TXN0 <> ST_RXN0 <> ST_RXP0 <> RIGHT# SW MISKI_SWITH_. MX0 MY0:E-Key.V.V.V 0 V V V RSV V 0 V V ST-H HV.0U_.0U_.U_.U_ //0' hange to R *Short_.U_ 00U-.V_ V <> TPT <> TPLK TPT TPLK TP ONN R.K_ V R.K_ L L P_ P_ V L KP0HST. LZ0-0MT 0. LZ0-0MT 0..U_ TPT_R TPLK_R RIGHT# LEFT# TP_V mil N 0 0 TOUH_P_TP_P EMI solution near connector O (ST) N RXP RXN TXN TXP ST_RXN_ ST_RXP_.0U_.0U_ ST_TXP <> ST_TXN <> ST_RXN <> ST_RXP <> P ST-O_PRESENT# <> V V 0 V_O R.K_ M ST-O V_O 00mil //0' hange to L0 *Short_ V 000P_.U_.U_.U_ 00U-.V_ Quanta omputer Inc. PROJET : Z0 Size ocument Number Rev ST-H & ST-O&TP ate: Friday, pril, 00 Sheet of

19 E V_R VSUS IN R REER 0 X_/MS_0/S_0 ()S-V *0U-.V_.U_ *.U_.U_.U_ S_ ()S-T0 X_RE#/S_ ()S-T 0 X_WE#/S_ ()S-T ()X-V S_LK ()S-T X_# S_M ()S-LK ()X- X_R/# S_# ()S-M ()X-R/ X_RE#/S_ S_WP# S- ()X-RE X_E# S-WP ()X-E X_LE ()X-LE X_LE ()X-LE X_WE#/S_ ()X-WE X_WP# ()X-WP V_R R0 00K/F_ R 0_ R_RST# R *Short_ //0' hange to U P_ R0 *0M_ Y MHz LK_MX XTLI LK_MX0 P_ MOE_SEL R_RST# X_LE X_E# X_LE X_RE#/S_ X_WE#/S_ X_R/# X_WP# EMI Solution X_/MS_0/S_0 X_/MS_ X_/MS_ X_/MS_ MS_SLK MS_# X_/MS_S X_0 X_ X_/MS_ X_/MS_ X_ X_/MS_S X_/MS_0/S_0 X_/MS_ U_ X_/MS_0/S_0 S-V S_ S-T0 X_RE#/S_ S-T U_.U_ X_WE#/S_ S-T X-V VREG S_M S_LK X_# S_M S-T V_PLL S_M S-LK X- X_R/# R0.K/F_ X_0 S_# S-M X-R/ X_RE#/S_ RREF S_T/X_0/MS_ S_WP# S-/ X-RE X_E# V_R X_ MS_SLK X_LE S_LK/X_/MS_LK R 0_ S-WP X-E N R 0_ S_LK X-LE X_LE S-VSS X-LE X_WE#/S_ <> USP- M V V_R S-VSS X-WE 0 X_WP# <> USP P S- X-WP.U_ X_0 X_/MS_ X_/MS_0/S_0 MS-V X-0 X_ S_T/X_/MS_ X_/MS_ MS-T0 X- X_/MS_ V_R X_/MS_ X_/MS_ N N 0 MS-T X- 0 0 X_/MS_ MS-T X- X_ RTSE-GR V_R MS_# MS_SLK MS-T X- X_/MS_S V_IN MS_INS# MS_# MS-SLK X- X_/MS_0/S_0 V_X X_/MS_ X_/MS_S MS-INS X- X_/MS_ R_V S_T/X_/MS_ MS-S X- 0 VREG 0 X_/MS_0/S_0 VREG S_T0/X_/MS_0 0 MS-VSS V_R X_/MS_ MS-VSS XG-.U_.U_ V X_/MS_ X- X_/MS_S X_/MS_S PROONN-MXP N.U_ MS_SLK S_LK V_X V_X V_X V_X XTL_TR GPIO0 EEO EES EESK EEI X_# 0 S_WP XTLO S_# MS_ X_ MS_ G_PLL MOE_SEL RST# X_LE X_E# X_LE 0 S_T/X_RE# S_T/X_WE# X_RY S_T/X_WP#/MS_ *P_ *P_ 0 N ()MS-V ()MS-T0 ()MS-T ()MS-T ()MS-T ()MS-SLK ()MS-INS ()MS-S ()S/()MS/()X- ()S/(0)MS/()X- *R_REER_TTN N (0)X-0 ()X- ()X- ()X- ()X- ()X- ()X- ()X- 0 SIO- SIO- V_R R0 *0_ X_# S_WP# S_# MS_ X_ MS_ X_/MS_ X_ R0 *0_ R 0_ S_ RREER POWER T T T0 T T MOE_SEL 0mil V_X R *0K_ *p/0v_.u_.0u_.0u_.0u_ R/ = 0K/pF => R0 Reside R/ = N / N => R Reside Quanta omputer Inc. PROJET : Z0 Size ocument Number Rev RTSE -ard Reader Friday, pril, 00 ate: Sheet of E

20 OE(L/LS-V) L L R *Short_ O //0' hange to SPK OUT FRONT-L FRONT-R EP /0/0' Empty on -test R *L@0_ MUTE_L MI-VREFO-R R.K_ MI-VREFO MI-VREFO-L R0.K_ L_VREF 0U-.V_ V_O MI_R MI_L O OE(L) Power V L TI00G.U_ 0 0.U_ 0U-.V_.U_.U_ 0U-.V_ O U *G-JTEU R *0_ V VEN VEN VOUT J V_O R *K_ INT MI array N MI_INTL INT_MI *P_ O 00.U_ O R.K_ MI-VREFO HP Jack O V_O R SURR-L 0K/F_ L_JREF 0 U FRONT-R MONO-OUT V SURR-L JREF FRONT-L Sense N MI-VREFO-R GPIO MI-VREFO 0 LINE-VREFO MI-VREFO-L VREF VSS V LINE-R LINE-L MI-R MI-L LINE-R LINE-L MI-R MI-L 0.U_.U_ U-V_ U-V_ LINE-R_ <> LINE-L_ <> MI_R <> MI_L <> EMI suggest / Vo=.*(RR)/R=.V R *K_ //0' hange to R R *Short_ *Short_ V_V O SURR-R SURR-R VSS N N N L/LS_V -R 0 - -L MI-R MI-L MI_INT_R MI_INT_L 0 0 U-V_ U-V_ MI_INTL O *.U_ P_ *.U_ R *Short_.U_.U_.U_ 000P_ R *0K_ R 0K_ R *0K_ R *0K_ R *0K_ R *0K_ G_Lv G_Lv G_ttack G_ON/OFF G_Recovery G_Recovery <> SPIF_OUT EP R 0_ MUTE_L L SPIF_OUT_ K00LL 0. MI-LK EP SPIFO V MI-//GPIO0 MI-//GPIO VSS ST-OUT IT-LK VSS ST-IN V SYN RESET# PEEP N N Sense SENSE SENSE <> O O P_ *.U_ P_ 000P_ 000P_ O R 0K_ O R *0K_ R 0K_ R 0K_ R 0K_ R 0K_ 0 V.V R 0_ R *0_ Z_V 0U-.V_.U_ V 0 0U-.V_ 0.U_ Z_SIN PEEP Z_V R _ H_RESET#_O <> H_SYN_O <> H_SIN0 <> G-attack-time selection G_ttack ( pin) ttack time ms ms G ON/OFF selection G_ON/OFF ( pin) G ON/OFF ON OFF G-recovery-time selection G_Recovery (0 pin) G_Recovery ( pin) Recovery Time.0 s.0 s.0 s.0 s G-on-level selection G_Lv ( pin) G_Lv ( pin) G ON Level Output Po (RL= ohm). dv. W.0 dv.0 W. dv 0. W.0 dv 0. W R 0_ 0P_ 0P_ EMI Solution H_ITLK_O <> V_V O V_O H_SOUT_O <> M N R *0_ V_S M R 0_ RSV VSUS <> H_SOUT_M _SO RSV.V <> H_SYN_M R _ H_SIN_M _SYN <> H_SIN _SI 0 <> H_RESET#_M _RST# _LK H_ITLK_M <> SP_STY ON/OFF & HP_STY ON/OFF SP_STY ( pin) SP_STY ( pin) SP_STY ON/OFF ON OFF OFF OFF HP_STY ( pin) HP_STY ( pin) HP_STY ON/OFF ON OFF OFF OFF G_Lv G_Lv G_ttack G_ON/OFF G_Recovery 0 U G_Lv G_Lv V G_ttack G_ON/OFF V_P G_Recovery V_HP Test Test Test Test V_SPR V_SPL VSS_P SP_OUTL VSS U-V_ U-V_ INSPKL O 0 0P_ EMI Solution R0 0_ 0 0P_.U_ EMI Solution SPK FRONT-L FRONT-R 0 U-V_ U-V_ FRONT-L- FRONT-R- V R0 R 0K/F_ 0K/F_ O R R0 0 0 G_Recovery FRONT-L- 0K/F_ 0P_ PREOUT-L FRONT-R- 0K/F_ 0P_ PREOUT-R U-V_ G_Recovery SP_INL PREOUT_L SP_INR PREOUT_R VREFSP Panasonic N SP_OUTL SP_OUTL SP_OUTL SP_OUTR SP_OUTR SP_OUTR 0 INSPKR- INSPKL- INSPKR SPK INSPKR- INSPKR INSPKL- INSPKL L L L L K0LL 0. K0LL 0. K0LL 0. K0LL 0. INSPKR-N INSPKRN INSPKL-N INSPKLN 0 *P_ *P_ 0 *P_ N SPEKER_H. *P_.U_ <> <> MP_MUTE# MUTE FUNTION EP HP_MUTE# R V U TSH0FU *0_ U0 TSH0FU MUTE_SPK MUTE_HP SP_STY SP_STY HP_STY HP_STY N N 0 _P 0 _SPL _SPR EP EP EP SP_OUTR HP_OUTL EP EP EP EP EP EP 0 HP_INL HP_INR HP_OUTR EP 0 EP EP N HPINL HPINR R0 R R R P_ 0K/F_ 0K/F_ 0K/F_ 0K/F_ HPL SURR-L SURR-R HPR HPL <>.U_.U_ HPR <> SURR-L SURR-R HP eep PEEP U-V_ EEP_ R O 0K_ MP_SPKR <> O V //0' hange to R *0_ V_V V_O O P_ P_ P -- ISOLTE Modify P to P_~ 00P_ R K_ R *0U-.V_ *Short_ 0U-.V_.U_ O 0 U-V_ 00 U-V_ 0 U-V_ O 0 U-V_ U-V_ U-V_ Quanta omputer Inc. PROJET : Z0 Size ocument Number Rev L & M/MP/SPK/MI Friday, pril, 00 ate: Sheet of 0

21 MI 0U V <0> MI_L <0> MI_R <0> LINE-L_ <0> LINE-R_ MI_L MI_R LINE-L_ LINE-R_ L L L L0 K0HS_ K0HS_ K0HS_ K0HS_ O MI_L MI_R MI_J# 0 0p/0V_NPO_ 0p/0V_NPO_ LINE IN LINEINL_SYS LINEINR_SYS LINEIN_J# 0 0p/0V_NPO_ 0p/0V_NPO_ O N MI Normal OPEN Jack N LUE Normal OPEN Jack LINEIN MI_J# O 0U LINEIN_J# *0U HPPLG# V O V O HeadPhone OUT/SPIF <0> HPL <0> HPR R R /F_ /F_ HPL_SYS HPR_SYS L L0 K0HS_ K0HS_ 0p/0V_NPO_ 0p/0V_NPO_ O V_SP LK N HPPLG# HPL_SYS HPR_SYS LE SPIF_OUT 0 rive I O SPIF Normal OPEN Jack Q TYU V_SP V 0K K HPPLG# <0> SPIF_OUT VR <0> SENSE SENSE R R R 0K/F_ 0K/F_.K/F_ MI_J# LINEIN_J# LINEOUT_J# <> IGVOL_UP <> IGVOL_N IGVOL_UP IGVOL_N VR VR_XRE0_NOLE V LINEOUT_J# V R 0K_ R HP_ON 0K_ Q N00E HPPLG# Q N00E O O Quanta omputer Inc. PROJET : Z0 Size ocument Number Rev udio Jack ate: Friday, pril, 00 Sheet of

22 WPE I/O RESS SETTING VPU V R-0 Index I/O ddress ata L LMG0SN_ VPU 0 0 XOR TREE TEST MOE.U_ 0.U_.U_.U_.U_.U_ U V V V V V V 0.U_ E 0.U_ V.U_.U_ R0 R 0 0 _POWERON Eh SHM=0: Enable shared memory with host IOS E_SOUT_R_EUG ORE EFINE Eh R R Fh Fh 0K_ *0K_ <,,> LFRME# <,> L0 <,> L <,> L <,> L For PILK <> LP_LK_E LP_LK_E <> LKRUN# <> GTE0 R <> RIN# _ <> E_SI# <> E_FPK# <> RE_KEY 0P_ For PIRESET <,> PLTRST# <,> USON# <> SERIRQ <> KSMI# <,> MX0 <> MX <> MX <> MX <> MX <> MX <> MX <> MX <,> MY0 <> MY <> MY <> MY <> MY <> MY <> MY <> MY <> MY <> MY <> MY0 <> MY <> MY <> MY <> MY <> MY <> MY <> MY <> MLK <> MT <> MLK_PU <> MT_PU <> TPLK <> TPT <> HG-EN S LP_LK_E SI#_R MLK MT MLK_PU MT_PU LFRME L0 L L L LLK GPIO/LKRUN G0 KRST ESI/GPIO GPIO/LRQ GPIO0/LPP LREST GPIO/PWUREQ SERIRQ GPIO/SMI KSIN0 KSIN KSIN KSIN KSIN KSIN KSIN KSIN KSOUT0/JENK KSOUT/TK KSOUT/TMS KSOUT/TI KSOUT/JEN0 K KSOUT/TO KSOUT/RY KSOUT KSOUT KSOUT KSOUT0 KSOUT KSOUT/GPIO KSOUT/GPIO KSOUT/GPIO KSOUT/GPIO/XOR_OUT GPIO0/KSOUT GPIO/KSOUT GPIO/SL GPIO/S GPIO/SL GPIO/S GPIO/PSLK GPIO/PST GPIO/PSLK GPIOPST GPIO/PSLK GPIO/PST LP SM PS/ / / GPIO0/T GPIO0/ GPIO0 GPIO0/ GPIO/SL GPIO0/IRTX 0 GPIO/S 0 GPIO/_PWM GPIO/H_PWM GPIO/T GPIO0/F_PWM GPIO/TK GPIO GPIO/TMS 0 GPIO/TI GPIO/E_PWM GPIO/IRRXM/TRST GPO/SL GPIO0/TO GPIO/T GPIO/IRTX/RY GPIO/S GPIO GPO/TRIS 0 GPO/R0 GPIO 0 TIMER SPI IR FIU GPI0/0 GPI/ GPI/ GPI/ GPIO0/ GPIO0/ GPI/0 GPI/ GPI/ GPI/ GPIO/T GPIO0/T GPIO/T GPIO/IRRX/SIN GPIO0/IRRX_IRSL0 GPIO/IRTX/SOUT GPIO/IRRXM/SIN_R GPIO/IRRXL GPIO/IRTX GPO/SOUT_R/R GPIO/_PWM GPIO/_PWM GPIO/_PWM GPIO/G_PWM GPIO/SPI_I GPO/SPI_O/SHM GPIO/SPI_SK F_SI F_SO F_S0 0 F_SK HWPG NSWON#_R RT_SENSE# RF_EN IRRX T T0 T T T E_SOUT_R_EUG R _ R _.U_.U_ S SPI_SI_uR SPI_SO_uR SPI_S0#_uR SPI_SK_uR MTEMP <> PIE_WKE# <,,> SYS_I <> IGVOL_UP <> IGVOL_N <> -SET <> PUFN# <> PPE#_E <> V-SET <> IN <> NSWON# <> LI# <> SUS# <> SUSLE# <> TLE0# <> TLE# <> VRON <> MINON <,,0> MP_MUTE# <0> E_PROHOT# <> SUSON <,0> ENERGY_ET <> HP_MUTE# <0> /# <> S_ON <,0> PUMEMHOT# <> NSWON# <> T_POWERON# <> _POWERON <> FNSIG <> E_L_KLT_TRL <> NUMLE# <> PWRLE# <> PSLE# <> RT_SENSE# <> RF_EN <> ELL-SET <> RSMRST# <> SUS# <> PWROK_E <,> N_TEMP <0> SMUS PULL-UP ER I SPI FLSH SHM VPU RF_EN isabled ('') if using FWH device on LP. Enabled ('0') if using SPI flash for both system IOS and E firmware R0 0K_ MLK_PU MT_PU MLK MT MLK_PU MT_PU SPI_SI_uR SPI_SO_uR SPI_SK_uR SPI_S0#_uR U0 SO SI SK E R0 U SL S WP R R R R L0 V HOL WP VSS WX0VSSIG 0 0K_.K_.K_.K_.K_ V VPU VPU.U_ VPU 0.U_ E_KX KX/KLKIN GPIO/LKOUT 0 E_LOK T R00 Y 0M_ R K/F_ E_KX KX WPE 0 VORF V_POR VREF 0 V_POR# VREF_uR R0.K_ VPU R 0_ VPU INTERNL KEYOR STRIP SET VPU P_ P_ VORF_uR 0 V VPU MY0 RT_SENSE# R0 R0 0K_ *.K_ Internal pull-up V.KHZ L HZ000R_ U-V_ R R E E <> HWPG_NORE S 0K_ *0K_ <> HWPG_.V_N *S <> HWPG_SYS S HWPG <,0> HWPG_.V 0 *S <,> HWPG_.V S <0> <0> <,> HWPG_.V HWPG_.V_S PU_OREPG S *S *S Quanta omputer Inc. PROJET : Z0 Size ocument Number Rev E WPE_0G & SPI Friday, pril, 00 ate: Sheet of