HOST 133/166MHz PCIE 100MHz VGA 96MHz USB 48MHz REF 14MHz PCI-E, 1X PCI-E, 1X. PCIE3 & PCI Express Mini Card PG 19 PCI-E, 1X USB2.

Transcript

1 P P/N N ESRIPTI P E M(L,0X, REV) P/N: 0EM P E M(L,0X,REV) P/N: 0EM P E US/(L,.X., REV) P/N: 0ES P E US/(L,.X.,REV) P/N: 0ES E ST E ST SSY P/N E M S/S SSY P/N: ESS00 E M /S SSY P/N: ES00 E M SSY P/N: EM00 W/O NT E US/ S/S SSY P/N: NESS00 E US/ SSY P/N: NEU00 PT E SSY P/N E M S/S SSY P/N: ESS0000 E M /S SSY P/N: ES000 E M SSY P/N: EM000 NT E US/ S/S SSY P/N: NESS000 E US/ SSY P/N: NEU000 V_ORE.V VP PU VR PG 0.V VP PG RII-SOIMM PG, RII-SOIMM PG, Panel onnector PG 0 S-Video PG 0 VG PG 0 ST - H PG PT - H PG Internal O -ROM PG / MHZ R II LVS TVOUT VG ST0 PT 00 zalia _LINK M S Turion Rev.F ual-ore/ Sempron Rev.F Single-ore ual-ore W / Single-ore W ( Sg socket) PG,,, HT_LINK RS FG S0 G PG,0,, PG HOST /MHz PIE 00MHz VG MHz US MHz REF MHz PI-E, X PI-E, X PI-E, X PI-E, X US.0 (P0~P) PI us MHz LOK GENERTOR IS luetooth PG Express ard PIE & US NEW R LN RTL-GR PG PG US.0 I/O Ports PG PG Mini PI-E ard (WLN) PIE PI Express Mini ard PG Mini PI-E ard (TV) PIE & PI Express Mini ard PG US PIE0 US US0 & US S US I/F US PG Magnetics / N. US & US PG.VSUS.V SMR_VTERM WIRE RJ VPU V_S VSUS VSUS V V US.0 I/O.VSUS SMR VTERM V/V HRGER NTENN JK PG PG PG US UGHTEROR zalia udio PG mplifier zalia M MX PG PG PG,,, LP K NS PG X-us SWITH LE PG TI PI0 REQ#, GNT# INTE#, INTG#, INTH# ard Reader PG PG, IEEE N. PG MINI PI N. 0 REQ#, GNT# INTF#, INTG# EUG PURPOSE LY PG MI. PG INT. S.P. H.P PG PG MOEM RJ PG K/ N. PG Touch Pad PG Flash ROM PG Size ocument Number Rev LOK IGRM ate: Monday, pril 0, 00 Sheet of PROJET : E Quanta omputer Inc.

2 TLE OF TENTS Page 0 : LOK IGRM Page 0 : TLE OF TENTS Page 0 : THL HT I/F Page 0 : THL RII MEMORY Page I/F 0 : THL TRL & EUG Page 0 : THL PWR & Page 0 : RII SOIMMX Page 0 : RII TERMINTI Page 0 : RS-HT LINK0 I/F Page 0 : RS-PIE LINK I/ F Page : RS-SYSTEM I/F & LKGEN Page : RS-POWER Page : LOK GENERTOR Page : S0M-PIE/ PI/PU/LP Page : S0M PI/GPIO/US/ Page : S0M H/POWER/EOUP LI Page : S0M STRPS Page : MINI P I Page : MINI R TV & WLN Page 0 : RT&LVS&S-VIE0&S Page : H & ROM, HOLES Page : US, LUETOOTH Page : LN PI-E RJ & RJ Page : PI0_ & NEW R Page : PI0_ (/IN) Page : UIO(L) & M Page : UIO(MP&POWER&HP ) Page : P & FLSH Page : LE & SW & K & TP & FN Page 0 : PU ORE MX Page :.V/.V/.V Page :.V/RII Page : SYSTEM V/V Page : TTERY HRGER SYSTEM PU R N S0 S POWER VOLTGE TIVE SOPE V -V V.V VLW.VLW V_UL.V_UL V_N V_PU V_MEM V VQ PLV LPV.V_S -V V.V V.V V.V.V/.0V.0V.V.V.V.V.V IN S-S IN S-S IN S-S IN S-S S0-S S0-S S0-S S0-S IN S-S IN S-S IN S-S IN S-S IN S-S TRE 0 MIL PLNE/ 00 MIL PLNE/ 0 MIL PLNEOPER V.V IN S-S OPPER V.V IN S-S PLNEOPPER TRE 0 MIL TRE 0 MIL TRE 0 MIL VR.V IN S-S TRE 0 MIL VTT_R 0.V IN S-S OPPER 0 V_LK.V IN S-S OPPER IN S-S ROUTING PLNE TRE 0 MIL PLNE PLNE PLNE/ 0 MIL.VLW.V S0-S TRE 0 MIL VORE VP V VI[0..].0V.V IN S-S IN S-S V.V IN S-S TRE 0 MIL PLNEOPER PLNE PGE.V_S.V IN S-S PLNE.VLW_S.V S0-S PLNE.VLW_S.V S0-S PLNE.V_SU_PHY.V S0-S TRE 0 MIL V_K.V IN S-S TRE 0 MIL V_REF V IN S-S TRE 0 MIL PU-PWR.0V IN S-S TRE 0 MIL PIE_PV.V IN S-S TRE 0 MIL IN S-S PLNEOPER S0-S PLNEOPER PLNEOPER V.V IN S-S TRE 0 MIL 0 TRE 0 MIL LVR.V IN S-S TRE 0 MIL PIE_VR.V IN S-S PLNEOPER.V_T.V IN S-S PLNE 0 PLLV_T.V IN S-S TRE 0 MIL 0 XTLV_T.V IN S-S TRE 0 MIL 0 V_US_TX.V S0-S PLNEOPER V_US_RX.V S0-S PLNEOPER.V_V.V S0-S TRE 0 MIL V_T.0V -- TRE 0 MIL VLW RSMRST# PS_, SLP_S#, SLP_S# V,V,.V VRM_PWRG V_N_PWRG VRM_PWRG N_PWRG S_PWRG PU_PWRG PI_RST# PU_RST# EFISH POWER UP SEQUENE T T T T>= 0 ms ms < T < 0ms ms < T < ms PROJET : E Quanta omputer Inc. Size ocument Number Rev LOK IGRM ate: Monday, pril 0, 00 Sheet of

3 PROESSOR HYPERTRNSPORT INTERFE VLT_x N VLT_x RE NETE TO THE LT_RUN POWER SUPPLY THROUGH THE PKGE OR THE IE. IT IS LY NETE THE OR TO EOUPLING NER THE PU PKGE VLT_RUN U VLT_ VLT_ VLT_ VLT_0 VLT_ VLT_ VLT_ VLT_0 E E E E.U/.V_ VLT_RUN () HT_IN_P () HT_IN_N () HT_IN_P () HT_IN_N () HT_IN_P () HT_IN_N () HT_IN_P () HT_IN_N () HT_IN_P () HT_IN_N () HT_IN0_P () HT_IN0_N () HT_IN_P () HT_IN_N () HT_IN_P () HT_IN_N () HT_IN_P () HT_IN_N () HT_IN_P () HT_IN_N () HT_IN_P () HT_IN_N () HT_IN_P () HT_IN_N () HT_IN_P () HT_IN_N () HT_IN_P () HT_IN_N () HT_IN_P () HT_IN_N () HT_IN0_P () HT_IN0_N () HT_LKIN_P () HT_LKIN_N () HT_LKIN0_P () HT_LKIN0_N N P M M L M K K H H G H F F E F N N L M L L J K G H G G E F E E J K J J L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H0 L0_IN_L0 L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H0 L0_IN_L0 L0_LKIN_H L0_LKIN_L L0_LKIN_H0 L0_LKIN_L0 L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H0 L0_OUT_L0 L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H0 L0_OUT_L0 L0_LKOUT_H L0_LKOUT_L L0_LKOUT_H0 L0_LKOUT_L0 T T V U V V Y W T R U U V U W W Y Y Y W HT_OUT_P () HT_OUT_N () HT_OUT_P () HT_OUT_N () HT_OUT_P () HT_OUT_N () HT_OUT_P () HT_OUT_N () HT_OUT_P () HT_OUT_N () HT_OUT0_P () HT_OUT0_N () HT_OUT_P () HT_OUT_N () HT_OUT_P () HT_OUT_N () HT_OUT_P () HT_OUT_N () HT_OUT_P () HT_OUT_N () HT_OUT_P () HT_OUT_N () HT_OUT_P () HT_OUT_N () HT_OUT_P () HT_OUT_N () HT_OUT_P () HT_OUT_N () HT_OUT_P () HT_OUT_N () HT_OUT0_P () HT_OUT0_N () HT_LKOUT_P () HT_LKOUT_N () HT_LKOUT0_P () HT_LKOUT0_N ().V L L FJHS00 FJHS00 0 ohm() VLT_RUN 0.U/.V_ 0.U/.V_ 0.U/V_.U/V_ 0 0P_ 0P_ LYOUT: Place bypass cap on topside of board NER HT POWER PINS THT RE NOT NETE IRETLY TO OWNSTREM HT EVIE, UT NETE INTERNLLY TO OTHER HT POWER PINS PLE LOSE TO VLT0 POWER PINS R R0./F HT_TLIN_P P HT_PU_TLOUT_P HT_TLIN_N L0_TLIN_H L0_TLOUT_H T T P HT_PU_TLOUT_N./F L0_TLIN_L L0_TLOUT_L R T0 N L0_TLIN_H0 L0_TLOUT_H0 R () HT_TLIN0_P HT_TLOUT0_P () P L0_TLIN_L0 L0_TLOUT_L0 R () HT_TLIN0_N HT_TLOUT0_N () thlon S Processor Socket PROJET : E Quanta omputer Inc. Size ocument Number Rev THL HT I/F ate: Monday, pril 0, 00 Sheet of

4 E V_VTT_SUS_PU IS NETE TO THE V_VTT_SUS POWER SUPPLY THROUGH THE PKGE OR THE IE. IT IS LY NETE THE OR TO EOUPLING NER THE PU PKGE.VSUS Processor R Memory Interface R0 K/F U M Q M Q () M Q[0..] PU_M_VREF M Q M_T M_T M Q[0..] () F M Q M Q M_T M_T F M Q M Q0 M_T M_T E M Q0 M Q M_T0 M_T0 Y W M Q 0 R M Q M_T M_T Y M Q.U_ 000p/0V_ K/F M Q M_T M_T M Q M Q M_T M_T F M Q M Q M_T M_T F M Q M Q M_T M_T F M Q.VSUS M Q M_T M_T M Q 0.V_VTER M Q M_T M_T F M Q M Q M_T M_T Y M Q U M Q0 M_T M_T Y M Q0 R M Q M_T0 M_T0 W E M Q M Q M_T M_T W.F W M Q MEMVREF VTT 0 M Q M_T M_T M Q VTT_SENSE VTT 0 0 M Q M_T M_T Y M Q T Y0 VTT_SENSE VTT 0 0 M Q M_T M_T M Q VTT 0 F M Q M_T M_T M Q M_ZN VTT W0 F M Q M_T M_T E0 M Q M_ZP MEMZN VTT 0 F0 M Q M_T M_T F0 M Q MEMZP VTT 0 E0 M Q M_T M_T M Q VTT 0 M Q0 M_T M_T 0 M Q0 VTT 0 M Q M_T0 M_T0 Y0 E M Q R M Q M_T M_T M Q (,) M S# V M0_S_L M0_LK_H Y M_LKOUT () M Q M_T M_T Y.F M Q (,) M S# J M0_S_L M0_LK_L M_LKOUT# () M Q M_T M_T W M Q (,) M S# V M0_S_L M0_LK_H E M_LKOUT0 () M Q M_T M_T W M Q (,) M S#0 T M0_S_L0 M0_LK_L F M_LKOUT0# () E M Q M_T M_T M Q M Q M_T M_T M Q (,) M S# Y M0_S_L M0_LK_H F M_LKOUT () M Q M_T M_T M Q (,) M S# J M0_S_L M0_LK_L F M_LKOUT# () M Q M_T M_T Y M Q (,) M S# W M0_S_L M0_LK_H M_LKOUT () G M Q0 M_T M_T H M Q0 (,) M S#0 U M0_S_L0 M0_LK_L M_LKOUT# () G M Q M_T0 M_T0 H0 M Q PLE THEM LOSE TO M Q M_T M_T E M Q (,) M_KE H M_KE M0_OT W M_OT (,) M Q M_T M_T E M Q PU WITHIN " (,) M_KE J M_KE0 M0_OT0 W M_OT (,) G M Q M_T M_T J M Q (,) M_KE J0 M_KE M0_OT V0 M_OT (,) G M Q M_T M_T H M Q (,) M_KE0 J M_KE0 M0_OT0 U M_OT0 (,) E M Q M_T M_T F M Q (,) M [0..] E M K J M M Q M_T M_T F0 M Q M [0..] (,) M M_ M_ K0 J M M Q M_T M_T M Q M M_ M_ V W M M Q M_T M_T M Q M M_ M_ 0 K L M M Q0 M_T M_T F M Q0 M M_ M_ 0 E L0 L M M Q M_T0 M_T0 M Q M 0 M_ M_ E0 R U M 0 M Q M_T M_T M Q M M_0 M_0 L L M M Q M_T M_T M Q M M_ M_ L M M M Q M_T M_T M Q M M_ M_ 0 G L L M M Q M_T M_T M Q M M_ M_ G M N M M Q M_T M_T M Q M M_ M_ M0 N M M Q M_T M_T M Q M M_ M_ F M N M M Q M_T M_T M Q M M_ M_ E M N M M Q M_T M_T M Q M M_ M_ 0 H N P M M Q0 M_T M_T M Q0 M M_ M_ E N P M M Q M_T0 M_T0 M Q M 0 M_ M_ E R T M 0 M Q M_T M_T M Q M_0 M_0 H M Q M_T M_T E M Q M Q M_T M_T M Q (,) M S# K M_NK M_NK K M S# (,) M Q M_T M_T M Q (,) M S# R0 M_NK M_NK T M S# (,) E H M Q M_T M_T M Q (,) M S#0 T M_NK0 M_NK0 U M S#0 (,) G H M Q M_T M_T G M Q M Q M_T M_T M Q (,) M RS# T0 M_RS_L M_RS_L U M RS# (,) H M Q M_T M_T M Q (,) M S# U0 M_S_L M_S_L V M S# (,) F M Q0 M_T M_T M Q0 (,) M WE# U M_WE_L M_WE_L U M WE# (,) M_T0 M_T0 G M M M M R II: M/TRL/LK M M M_M M_M Y M M M M M_M M_M E M M thlon S M M M_M M_M Y M M Processor Socket M M M_M M_M E M M M M M_M M_M F M M M M M_M M_M E M M M M0 M_M M_M M M0 () M M[0..] M_M0 M_M0 E M M[0..] () M QS0 M QS0 R: T M QS M QS thlon S M QS 0.V_VTER M QS Processor Socket M QS M QS M QS M QS M QS M QS M QS 0 M QS M QS () M QS[0..] M QS () M QS[0..].U/.V_.U/.V_.U/.V_.U/.V_.U/V_.U/V_.U/V_.U/V_ 000p/0V_ 000p/0V_ 000p/0V_ 000p/0V_ 0P_ 0P_ 0P_ 0P_ M QS#0 M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS# () M QS#[0..] M QS# () M QS#[0..] To SOIMM socket (Far) M QS M QS# M QS M QS# M QS M QS# M QS M QS# M QS M QS# M QS M QS# M QS M QS# M QS0 M QS#0 F E E F F F E M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H0 M_QS_L0 M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H0 M_QS_L0 W W Y W 0 G G G G G H M QS M QS# M QS M QS# M QS M QS# M QS M QS# M QS M QS# M QS M QS# M QS M QS# M QS0 M QS#0 To SOIMM socket (near) PROJET : E Quanta omputer Inc. Size ocument Number Rev THL RII MEMORY I/F Monday, pril 0, 00 ate: Sheet of E

5 LYOUT: ROUTE V TRE PPROX. 0 mils WIE (USE x mil TRES TO EXIT LL FIEL) N 00 mils LG. THL ontrol and ebug.vsus PU_V_RUN L LMPG0SN PU_V_RUN.V If M SI is not used, the SI pin can be left unconnected and SI should have a 00-Ω (±%) pulldown to VSS..V R *00 R *00 R 00_ PU_SI_R PU_SI_R PU_V_RUN F F U V V THERMTRIP_L PROHOT_L F H_THERMTRIP# H_PROHOT# R 00_ () ().U/.V_.U/V_ 00p/V 00p/V PULK R F PULK# 00p/V 0 00U/.V_ PU_LKIN_S_P PU_LKIN_S_N place them to PU within " VLT_RUN PU_HT_RESET# PU_LL_PWROK PU_LTSTOP# T0 (0) OREFV To Power (0) OREF- T PU_VIO_SUS_F_H T PU_VIO_SUS_F_L T :dd LEVEL-SHIFT circuit on PSI# that between PU_LKIN_S_P PU_LKIN_S_N PU and POWER.V V R.F R.F T0 T T PU_SI_R PU_SI_R PU_HTREF PU_HTREF0 F0 F F P R F E W Y RESET_L PWROK LTSTOP_L SI SI HT_REF HT_REF0 V_F_H V_F_L VIO_F_H VIO_F_L LKIN_H LKIN_L VI VI VI VI VI VI0 PU_PRESENT_L PSI_L VI (0) VI (0) VI (0) VI (0) VI (0) VI0 (0) PU_PRESENT# PSI# PSI_L is a Power Status Indicator signal. This signal is asserted T when the processor is in a low powerstate. PSI_L should be connected to the power supply controller, if the controller supports skipmode, or diode emulation mode. PSI_L is asserted by the processor during the and S states..v V.VSUS EN Remove R for Power sequence R R0 *.K/F_.U_ R 0K_ R K/F_ PWR_PSI# (0) PU_RY PU_TMS PU_TK PU_TRST# PU_TI G0 F RY TMS TK TRST_L TI REQ_L TO E0 E PU_REQ# PU_TO (,) PU_PWRG (,,) LT_STOP# 00_.V R 00_ PU_LL_PWROK U0 NSZ0PX_NL.VSUS.U_ PU_LTSTOP# PSI# Q MMT0 T T T T0 T T PU_TEST_H_YPSSLK_H PU_TEST_L_YPSSLK_L PU_TEST_PLLTEST0 PU_TEST_PLLTEST PU_TEST_P PU_TEST_P PU_TEST_P PU_TEST_P0 PU_TEST_SNSHIFTEN PU_TEST0_NLOG_T PU_TEST_IERKM PU_TEST_THERM PU_TEST_THERM PU_TEST_GTE0 PU_TEST_RIN0 E E G H0 E F W W Y TEST_H TEST_L TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST_H TEST_L TEST TEST TEST TEST TEST0 TEST_H TEST_L TEST TEST TEST0 TEST E E F J H F E K PU_TEST_H_FLKOUT_P R 0.F PU_TEST_L_FLKOUT_N ROUTE S 0 Ohm IFFERENTIL PIR PLE IT LOSE TO PU WITHIN " PU_TEST_SNLK PU_TEST_TSTUP PU_TEST_SNSHIFTEN PU_TEST_SNEN PU_TEST0_SNLK PU_TEST_H_PLLHRZ_P PU_TEST_L_PLLHRZ_N PU_TEST_SINGLEHIN PU_TEST_URNIN# PU_TEST0_NLOGOUT PU_TEST0_IG_T T T T T T.V U NSZ0PX_NL T0 T T T PU_RSV_M0_LK_P PU_RSV_M0_LK_N PU_RSV_M0_LK0_P PU_RSV_M0_LK0_N P0 P N0 N RSV0 RSV RSV RSV RSV RSV RSV0 RSV H PU_M_RESET# PU_M_RESET# PU_RSV_VISTR PU_RSV_VISTR0 T T T T () LT_RST# (,,) E_PWRG (,) N_PWRG R 00_ R *0_ R 0_.VSUS.U_ PU_HT_RESET# U NSZ0PX_NL T T T T PU_RSV_M0_LK_P PU_RSV_M0_LK_N PU_RSV_M0_LK0_P PU_RSV_M0_LK0_N R R P R RSV RSV RSV RSV MIS RSV RSV RSV RSV RSV RSV RSV RSV RSV0 H G R W R H H PU_RSV_VN_F_P PU_RSV_VN_F_N PU_RSV_ORE_TYPE T T0 T M NPT S SOKET Processor Socket.VSUS.V.VSUS R0 0_ Q0 MMT0 R 00_ R *0_ H_PROHOT# PU_E_PROHOT# () PU_PROHOT# ().VSUS 00_.V R *0_ R H_THERMTRIP# S_THERMTRIP# () separated input voltage 00 R0 E_PWRG Q *MMT0 R.K/F_.K/F_ Q MMT0 THERM_SYS_PWR () PU_TEST_SINGLEHIN PU_TEST_URNIN# PU_PRESENT# PU_TEST_H_YPSSLK_H PU_TEST_SNEN PU_TEST0_SNLK PU_TEST_SNLK PU_TEST_SNSHIFTEN PU_TEST_SNSHIFTEN PU_TEST_P PU_TEST_P0 PU_TEST_L_YPSSLK_L PU_TEST_PLLTEST0 PU_TEST_PLLTEST R 00_ R 00_ R K/F_ R 0/F_ R 00_ R 00_ R 00_ R 00_ R 00_ R 00_ R 00_ R 0/F_ R 00_ R 00_ IF no use which Net need pull-up or down.vsus R 0_ R 0_ R0 0_ R 0_ R0 0_ PU_REQ# PU_RY PU_TK PU_TMS PU_TI PU_TRST# PU_TO LT_RST# HT NETOR T T T T T T T T PU H/W MITOR V NOTE: HT TERMINTI IS REQUIRE FOR REV. x SILI LY. PUT LOSE LYOUT V R 0K_ Q N00E-LF V R PU_TEST_THERM /F_ PU_TEST_THERM 0 mil trace / 0 mil space MIL V_THM.U_ 00P/0V_ ddress H U G V -LT XN SMT XP SMLK -OVT R0 0K_ KSMT KSMLK Q V R 0K_ N00E-LF To S GPIO To FN MX_L# () MX_OV# () V R 0K_ Q N00E-LF MT_PU () MLK_PU () PROJET : E Quanta omputer Inc. Size ocument Number Rev THL TRL & EUG Monday, pril 0, 00 ate: Sheet of

6 upg Top View OTTOMSIE EOUPLING F thlon Sg PROESSOR POWER N GROUN thlon S Processor Socket thlon S Processor Socket EOUPLING ETWEEN PROESSOR N IMMs PLE LOSE TO PROESSOR S POSSILE THL PWR & Monday, pril 0, 00 Size ocument Number Rev ate: Sheet of V_ORE V_ORE V_ORE V_ORE.VSUS.VSUS.VSUS U/0V_.0U_ 0 U/0V_.U/V_.U/V_ 0.U/.V_ 0 U/0V_ 0P_ 0 U/0V_ U/0V_ UE POWER G H J J J K K0 K K L L L L L M M M M0 N N N P P0 R R R R T T T T0 T T U U U U V V V0 V V W Y J K L M P T U V H J K K K K L M M M M N P P P P R T T T T U V V V V Y V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO0 VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO0 VIO VIO VIO VIO VIO VIO VIO 0 U/0V_ UF GROUN E E E E E E E E F F F F F F F F F H H H H J J J J0 J J J J K K K K K K K L L L0 L L L L M M M M N N N0 N N P P P P R R0 R R T T T T V V V W Y Y N T T U U U U0 U U U U V V V V P VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS VSS VSS VSS VSS VSS VSS VSS0 VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS00 0.U/V_.U/V_ 0.U/.V_.0U_ 00 U/0V_.U/V_.U/V_ Quanta omputer Inc. PROJET : E 0P_ 00 0P_.U/V_ 0.0U_ 0 U/0V_ 0.U/.V_ U/0V_.U/V_ U/0V_ 0.U/.V_ 0 0P_ 0 U/0V_

7 E E (H=.) (H=.) REVERSE REVERSE R-II SOIMM* Monday, pril 0, 00 Size ocument Number Rev ate: Sheet of M_LKOUT# M M M M 0 M QS M M M M Q M Q M Q M Q M Q M QS#0 M_LKOUT M M Q M Q M Q M Q M Q M M0 M Q M Q M Q M QS# M_LKOUT# M Q M Q M M M M M M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M QS M M Q M Q M Q M Q M_LKOUT0# M QS# M M_LKOUT M QS M M Q M_LKOUT M QS# M_LKOUT# M Q M Q M Q M Q M Q0 M_LKOUT M QS M QS M Q M Q0 M Q M Q0 M M Q0 M Q M_LKOUT# M QS# M QS M M M Q M Q M Q M Q M Q M QS0 M Q M Q M Q M Q M Q MVREF_IM M QS M M M M M M M QS# M QS# SMK SMT M Q M Q M QS# M M M Q M Q M Q M Q M Q M 0 M Q M Q M Q0 M M M M M M Q M Q M Q M Q M QS# M QS0 M M M M Q M Q0 M QS M M M Q M Q M QS# M QS M M M M Q M Q M Q0 M Q M Q M M0 M 0 M Q M Q M Q M Q M M M Q M Q M Q M Q M QS M Q M QS# M M Q M Q M Q M Q M M M M M M Q M Q M Q M Q0 M Q M QS# M M M Q M Q M Q0 M Q M_LKOUT M QS# M M Q M Q M Q M M QS M QS M M Q M Q M Q M QS M Q M Q M Q M Q M Q M_LKOUT# M QS# M QS#0 M M Q0 M Q0 M Q M QS# M M M Q M_LKOUT0 M 0 M Q M Q0 M QS M M Q M Q M Q M Q M Q MVREF_IM MVREF_IM M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M [0..] (,) M_KE0 (,) M_KE (,) M RS# (,) M S# (,) M WE# (,) M S#0 (,) M S# (,) M_OT0 (,) M Q[0..] () M_LKOUT0 () M_LKOUT0# () M_LKOUT () M_LKOUT# () M_OT (,) M S# (,) M S# (,) M S#0 (,) M QS#[0..] () M QS[0..] () M M[0..] () M_LKOUT () M_LKOUT# () M_LKOUT () M_LKOUT# () M_OT (,) M_KE (,) M_KE (,) M_OT (,) M [0..] (,) M S# (,) M S#0 (,) M S# (,) M QS#[0..] () M QS[0..] () M M[0..] () M RS# (,) M S# (,) M WE# (,) M Q[0..] () M S# (,) M S# (,) M S# (,) M S# (,) M S#0 (,) M S# (,) V V V.VSUS.VSUS.VSUS.VSUS.VSUS.VSUS 0.V_REF.P_ 0.U_ R K/F_.U_ *0U/.V/XR 0 U/0V_.U_ 0.U_.U_ 0 R *0_.U_.U_.U_.U_.U_.U_.U_.U_.P_.U_ *0U/.V/XR 0.U_ SO-IMM N RII_SOIMM_R Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q N N N N N/TEST M0 M M M M M M M QS0 QS QS QS QS QS QS QS K0 K0 K K KE0 KE VREF RS S WE S0 S S0 S S SL Vspd V0 V V V V V V V V V V0 V VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS QS0 QS QS QS QS QS QS QS OT0 OT VSS VSS VSS VSS VSS VSS VSS VSS VSS0.U_.U_.U_ SO-IMM N RII_SOIMM_R Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q N N N N N/TEST M0 M M M M M M M QS0 QS QS QS QS QS QS QS K0 K0 K K KE0 KE VREF RS S WE S0 S S0 S S SL Vspd V0 V V V V V V V V V V0 V VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS QS0 QS QS QS QS QS QS QS OT0 OT VSS VSS VSS VSS VSS VSS VSS VSS VSS0.U_ R 0_.P_ 0U/0V/XR_ Quanta omputer Inc. PROJET : E.U_.U_ 0U/0V/XR_.U_ 0.U_ R 0K_.U_ R K/F_.U/0V/XR.U/0V/XR.U_.U_.P_ SMT () SMK ()

8 0.V_VTER (,) (,) (,) (,) (,) (,) (,) (,) (,) (,) (,) (,) (,) (,) (,) (,) (,) (,) (,) (,) (,) (,) (,) (,) (,) (,) (,) (,) M_KE0 M_KE M_KE M_KE M_OT0 M_OT M_OT M_OT M S#0 M S# M S# M WE# M S# M RS# M S#0 M S# M S# M WE# M S# M RS# M S#0 M S# M S# M S# M S#0 M S# M S# M S# M S#0 M S# M S# M WE# M S# M RS# M S#0 M S# M S# M WE# M S# M RS# R0 _ R _ R _ R0 _ R0 _ R _ R _ R _ R0 _ R _ R0 _ R00 _ R _ R _ R _ R _ R0 _ R _ R _ R _ R _ R _ R0 _ R _ R _ R _ R _ R _ 0.V_VTER *0U/.V/XR *0U/.V/XR.U_.U_.U_.U_.U_.U_.U_.U_.U_ *0.U_ *0.U_.U_.U_.U_.U_.U_ *0.U_.U_.U_.U_ *0.U_.U_.U_.U_ *0.U_.U_ (,) M [0..] (,) M [0..] M M 0 M 0 M M M M M M M M M M M M M M 0 M M M M M M M M M M M M 0 M M M R _ R _ RP 00-X RP0 00-X RP 00-X RP 00-X RP 00-X RP 00-X RP 00-X RP 00-X RP 00-X RP 00-X RP 00-X RP 00-X RP 00-X R _ R _ RP 00-X PROJET : E Quanta omputer Inc. Size ocument Number Rev R-II TERMINTI ate: Monday, pril 0, 00 Sheet of

9 U VHT_PKG () HT_OUT_P () HT_OUT_N () HT_OUT_P () HT_OUT_N () HT_OUT_P () HT_OUT_N () HT_OUT_P () HT_OUT_N () HT_OUT_P () HT_OUT_N () HT_OUT0_P () HT_OUT0_N () HT_OUT_P () HT_OUT_N () HT_OUT_P () HT_OUT_N () HT_OUT_P () HT_OUT_N () HT_OUT_P () HT_OUT_N () HT_OUT_P () HT_OUT_N () HT_OUT_P () HT_OUT_N () HT_OUT_P () HT_OUT_N () HT_OUT_P () HT_OUT_N () HT_OUT_P () HT_OUT_N () HT_OUT0_P () HT_OUT0_N () HT_LKOUT_P () HT_LKOUT_N () HT_LKOUT0_P () HT_LKOUT0_N () HT_TLOUT0_P () HT_TLOUT0_N R R R R U U U U W W0 0 0 Y T R U U V U V V W W Y W P P HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RX0P HT_RX0N HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RX0P HT_RX0N HT_RXLKP HT_RXLKN HT_RXLK0P HT_RXLK0N HT_RXTLP HT_RXTLN PRT OF HYPER TRNSPORT PU I/F HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TX0P HT_TX0N HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TX0P HT_TX0N HT_TXLKP HT_TXLKN HT_TXLK0P HT_TXLK0N HT_TXTLP HT_TXTLN R./F HT_RXLP HT_TXLP R 00/F_ HT_RXLP HT_TXLP HT_RXLN HT_TXLN R./F HT_RXLN HT_TXLN P P P P M M M M L L G G J0 J F F N N L M K K J K G H F F E F E E L L J J N P HT_IN_P () HT_IN_N () HT_IN_P () HT_IN_N () HT_IN_P () HT_IN_N () HT_IN_P () HT_IN_N () HT_IN_P () HT_IN_N () HT_IN0_P () HT_IN0_N () HT_IN_P () HT_IN_N () HT_IN_P () HT_IN_N () HT_IN_P () HT_IN_N () HT_IN_P () HT_IN_N () HT_IN_P () HT_IN_N () HT_IN_P () HT_IN_N () HT_IN_P () HT_IN_N () HT_IN_P () HT_IN_N () HT_IN_P () HT_IN_N () HT_IN0_P () HT_IN0_N () HT_LKIN_P () HT_LKIN_N () HT_LKIN0_P () HT_LKIN0_N () HT_TLIN0_P () HT_TLIN0_N () RSM HT PROJET : E Quanta omputer Inc. Size ocument Number Rev RS-HT LINK0 I/F ate: Monday, pril 0, 00 Sheet of

10 V V V VSUS V.V VLT_RUN.U_ 0.U_.U_.U_.U_.U_.U_.U_.U_ 0.U_ V.V.V V V.V.V.V U VLT_RUN.U_ V_ORE.U_ V_ORE.VSUS.U_ V_ORE.VSUS.U_ V V.U_ V.U_.VSUS.U_ 0.V_VTER () LN_PIE_RXP0 () LN_PIE_RXN0 R: 0KOhm FOR RS.KOhm FOR R:.KOhm RS0 FOR RS NI FOR RS0 GPP_TX0P_ GPP_TX0N_ GPP_TXP_ GPP_TXN_ R: R: Place these caps close to connector GPP_TXP_.U_ () PIE_RXP GPP_RXP GPP_TXP PIE_TXP () GPP_TXN_.U_ () PIE_RXN E GPP_RXN GPP_TXN PIE_TXN () PIE I/F GPP Y GPP_TXP_.U_ () MINI_PIE_RXP GPP_RXP GPP_TXP MINI_PIE_TXP () E GPP_TXN_.U_ () MINI_PIE_RXN GPP_RXN GPP_TXN MINI_PIE_TXN () () MINI_PIE_RXP () MINI_PIE_RXN _TX0P_.U_ () _RX0P W E S_RX0P S_TX0P _TX0P () W PIE I/F S 0 _TX0N_.U_ () _RX0N S_RX0N S_TX0N _TX0N () () () _RXP _RXN R R G G J J J J L L L L M M M M P P P P R R R R U U W W Y Y V W W W 0K_.K/F_ GFX_RX0P GFX_RX0N GFX_RXP GFX_RXN GFX_RXP GFX_RXN GFX_RXP GFX_RXN GFX_RXP GFX_RXN GFX_RXP GFX_RXN GFX_RXP GFX_RXN GFX_RXP GFX_RXN GFX_RXP GFX_RXN GFX_RXP GFX_RXN GFX_RX0P GFX_RX0N GFX_RXP GFX_RXN GFX_RXP GFX_RXN GFX_RXP GFX_RXN GFX_RXP GFX_RXN GFX_RXP GFX_RXN GPP_RX0P GPP_RX0N GPP_RXP GPP_RXN S_RXP S_RXN RSM HT PRT OF PIE I/F GFX GFX_TX0P GFX_TX0N GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TX0P GFX_TX0N GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GPP_TX0P GPP_TX0N GPP_TXP GPP_TXN S_TXP S_TXN PE_ISET(PE_LI) PE_PL(PE_LRP) PE_TXISET(N) PE_NL(PE_LRN) J H K K K L L L N N P P P R R R T U V V V W W W Y E E E R E R _TXP TXN_.U_.U_.U_ 0 0/F_ V_PKG 00/F_.U_.U_.U_ 0 Ohm FOR RS Ohm FOR RS0 LN_PIE_TXP0 () LN_PIE_TXN0 () MINI_PIE_TXP () MINI_PIE_TXN () _TXP () _TXN () Ward update to 00 Ohm FOR RS KOhm FOR RS0 PROJET : E Quanta omputer Inc. Size ocument Number Rev RS-PIE LINK I/F ate: Monday, pril 0, 00 Sheet 0 of

11 .V L HTPV.V L0 VQ K0HS00 0U/0V/XR_.U/.V_ K0HS00 0U/0V/XR_.U/0V/XR R 0_ V L V_N K0HS00.U/.V_.U_.V R 0_ V.U/0V/XR.V L (,,) LT_STOP# V K0HS00 R R K/F PLLV 0 0U/0V/XR_.V V R 0K_ Q MMT0 STRP_T 0K_ TV_SWITH (0) TV_/R_SYS (0) TV_Y/G_SYS (0) TV_OMP_SYS.U/.V_ R K/F_ (0) (0) (0) LT_STOP#_N VG_RE VG_GRN VG_LU R LO_ROM#: LO ROM STRP ENLE High, LO ROM STRP ISLE Low, LO ROM STRP ENLE _VSSQ close to N R R 0/F_ 0/F_ 0/F_ R K VQ R 0_ T R LO_ROM# R0 R R R R (0) PHL_LK (0) PHL_T T T0 V V_N R0 0_ T T R TV_SWITH N_RST# LT_STOP#_N 0K_ PLLV *.K_ FT_GPIO0 *.K_ FT_GPIO *.K_ FT_GPIO *.K_ FT_GPIO *.K_ FT_GPIO G H 0 0 U RT/TVOUT PRT OF PM PLL PWR LOKs MIS. RSM HT VO LVS L_P LVS_L R 0_ T TXLOUT0 (0) TXLOUT0- (0) TXLOUT (0) TXLOUT- (0) TXLOUT (0) TXLOUT- (0) T T close to N TV_/R_SYS TXOUT_U0P T _VSSQ TV_Y/G_SYS _R TXOUT_U0N T00.U_ 0 R 0_ TV_OMP_SYS Y_G TXOUT_UP T OMP_ TXOUT_UN T TXOUT_UP T E RE TXOUT_UN T F T0 _LPVSS GREEN TXOUT_UP G LUE TXOUT_UN T0 (0) VSYN VSYN (0) HSYN E RS: LVR=.V R R HSYN TXLK_LP TXLLKOUT (0) R TXLK_LN TXLLKOUT- (0) R /F H T HEK 0/F_ 0/F_ 0/F_ RSET TXLK_UP G L K0HS00.V R 0_ TXLK_UN T (0) LK TO R 0_ SL (0) T S LPV E 0OHM.V LPVSS PLLV 0.U/.V_ L PLLV(PLLV).U_ 0 L PLLVSS LVR LPVSS LVR_ HTPV K0HS00 HTPV LVR_ HTPVSS LVR_ (,,,,) LINK_RST# (,) N_PWRG () NSR_LKP () NSR_LKN () SLINK_LKP () SLINK_LKN () MREQ# () N_OS () LLOW_LTSTOP () HTREFLK 0 F E G G V V VSSN VSSN VI VSSI VQ VSSQ SYSRESET# POWERGOO LTSTOP# LLOW_LTSTOP HTTSTLK HTREFLK TVLKIN OSIN OSOUT(PLLV) GFX_LKP GFX_LKN S_LKP S_LKN FT_GPIO0 FT_GPIO FT_GPIO FT_GPIO FT_GPIO FT_GPIO MREQb I_LK I_T THERMLIOE_P THERMLIOE_N TMS_HP _T STRP_T TESTMOE STRP_T TXOUT_L0P TXOUT_L0N TXOUT_LP TXOUT_LN H TXOUT_LP G TXOUT_LN TXOUT_LP E TXOUT_LN LVSSR LVSSR LVSSR LVSSR LVSSR LVSSR LVSSR LVSSR LVS_IG LVS_L LVS_LEN VO_0(GPP_TXP) VO_(GPP_TXN) VO_(N) VO_(GPP_RXP) VO_(GPP_RXN) VO_(N) VO_(N) VO_(GPP_TXN) VO_(GPP_TXP) VO_(GPP_RXN) VO_0(GPP_RXP) VO_(N) VO_VSYN(N) VO_E(N) VO_HSYN(N) VO_IKP(N) VO_IKN(N) F F E G F E E E E0 0 E E E.U_ T T T T T0 T T T T0 T T0 T0 T T0 T T T0.U/.V_ L_P R0 R LVS_L R 0_ L_POWER_ (0) K/F K/F.U_ K0HS00.U/.V LVSSR R.K/F_ OSOUT() VO_0() VO_() RS OSOUT VO_0 VO_ RS0 PLLV GPP_TXP GPP_TXN LVS_L N_PWRG NSZ0PX_NL V U EN : OM Lose and stuff R R 0_ L (0) VO_() VO_ GPP_RXP VO_(E) VO_(E) VO_() VO_(E0) VO_0(0) VO_ VO_ VO_ VO_ VO_0 GPP_RXN GPP_TXN GPP_TXP GPP_RXN GPP_RXP PROJET : E Quanta omputer Inc. Size ocument Number Rev RS-SYSTEM I/F & LKGEN ate: Monday, pril 0, 00 Sheet of

12 S G S0 V V VR VHT N RS POWER STTES V V Power Signal V HTPV PLLV S VI VR LVR LPV LVR S/S RS: V=.V RS: 0 Ohm RESISTOR 0 ohm() 0 ohm() ohm (000m) SUGGEST REMOVE L E SME S PU. PLN FS UNER THIS PLN :Remove Jump RS-POWER Monday, pril 0, 00 Size ocument Number Rev ate: Sheet of V V_PKG VHT_PKG V_PKG V_PKG.V V.V V V VR.V VVO VPLL VLT_RUN.V V V_N.V V U/0V_ 0U/0V/XR_ 00U/.V_ 0U/0V/XR_ U/0V_ 0U/0V/XR_ 0 0 U/0V_ U/0V_ U/0V_ Quanta omputer Inc. PROJET : E 0 U/0V_ L TI00G 0U/0V/XR_ 0 U/0V_ GROUN PR OF UE RSM HT F E G Y P R E M J G J L L L0 L M M0 M M N N L P P0 P R R R0 W Y U0 H W Y G V V V F V H G J H J F L M M J P T N R U T U U Y W Y Y Y R 0 G Y P E E0 M Y Y R E T T E H F M H M R VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS R 0_ POWER PRT OF U RSM HT E E Y W 0 E J J E G E E M F L E W L L L M R M N N N J H P P R E U F R E F G E U U P L J 0 G0 M E U U V_HT V_HT V_HT V_HT V_HT V_HT V_HT V_HT V_HT V_HT0 V_HT V_HT V_HT V_HT V_HT V_ V_ V_(VPLL_) V_ V_ V_ V_ V_ V_ V_ V_ V_ V_(V_0) V_(V_) V_(V_) V_(V_) V_(V_) V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_(V_) V_(V_) V_(V_) V_(VPLL_) V_ VR_ VR_ VSS(VSSPLL_) VSS0(VSSPLL_) V_VO(VR_) V_VO(VR_) V_VO(VR_) V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_0 V_ VHT_PKG V_PKG V_PKG V_ V_ V_ U/0V_ SW00 U/0V_ U/0V_ SW00 0 U/0V_ U/0V_ 0U/0V/XR_.U/.V_ 0U/0V/XR_ L FJHS00.U/0V/XR 0U/0V/XR_ 0 L LMPG0SN 00U/.V_ U/0V_ 0 U/0V_ 0U/0V/XR_ U/0V_.U/0V/XR SW00 U/0V_ U/0V_.U/.V_ U/0V_ U/0V_ L TI00G U/0V_ U/0V_ U/0V_ U/0V_ L TI00G U/0V_ 0U/0V/XR_

13 V L0 K0HS00 LK_V LK_V L K0HS00 V ohm/ U/0V_.U_.U_.U_.U_.U_.U_.U_.U_.U_ 0 U/0V_ - PLE LL SERIL TERMINTI RESISTORS LOSE TO U00 - PUT EOUPLING PS LOSE TO lock Gen.POWER PIN (,,) PT_SM (,,) PLK_SM V R 0_ V R 0_ V Q *N00E-LF 00ohm/00m 00ohm/00m EXT LK FREQUENY SELET TLE(MHZ) FS FS FS L Q R0 *N00E-LF*0K_ PU Hi-Z X PI Parallel Resonance rystal US V SMT SMK L K0HS00 R0 *0K_ SRLK HTT [:] LK_V R 0K_ Hi-Z X/ X/ K0HS00 U/0V_ Hi-Z..U_ 0 U/0V_ LK_V_REF LK_V_US.U_ P_ Ioh = * Iref (.m) Voh = 0 ohm OMMENT R0 *M_ LK_V Normal THL operation heck M clock LK_XIN 0 U0 VPU V_SR V_SR V_SR V_SR V_ V_TIG V_REF 0 VHTT _PU _SR _SR _SR _SR TIG _REF HTT XIN P_ LK_XOUT_R0 0_ LK_XOUT Y XOUT.MHZ () () SMK SMT R /F_ RESET_IN# N SMLK SMT IREF IS V PULKT0 PULK0 PULKT PULK SRLKT0 SRLK0 TIGLKT0 TIGLK0 TIGLKT TIGLK TIGLKT TIGLK TIGLKT TIGLK SRLKT SRLK SRLKT SRLK SRLKT SRLK SRLKT SRLK SRLKT SRLK SRLKT SRLK SRLKT SRLK LKREQ# TROL SR,, LKREQ# TROL SR,, LKREQ# TROL SR0, LKREQ# LKREQ# LKREQ# MHz_ MHz_0 FS/REF FS0/REF0 FS/REF HTTLK0 LK_V PULK_EXT_R PULK#_EXT_R SLINK_LKP_R SLINK_LKN_R NSR_LKP_R NSR_LKN_R SSR_LKP_R SSR_LKN_R GPP_LK0P_R GPP_LK0N_R GPP_LKP_R GPP_LKN_R GPP_LKP_R GPP_LKN_R GPP_LKP_R GPP_LKN_R R0.K_ R LK_M R LK_M R.K_ R R R 0_ R 0_ T R R R R R R R R R R R R R0 R R0 R LK_V S_OSIN_R N_OSIN_R HTREFLK_R /F_ /F_ /F_ /F_ R /F /F_ /F_ /F_ /F_ /F_ /F_ /F_ /F_ /F_ /F_ /F_ /F_ /F_ /F_ MINI_LKREQ# () NEW_LKREQ# () R./F LK_PM () USLK () LK_V R0 R0 R R0 R R0 R./F R./F R./F.K_.K_.K_ /F_ /F_ /F_ PULK () PULK# () R./F R./F R./F R.K_ R./F R./F R.K_ R./F R./F R0.K_ R00 R R0 S_OSIN () N_OS () HTREFLK () R./F R./F R./F R./F *0_ *0_ *0_ SLINK_LKP () SLINK_LKN () NSR_LKP () NSR_LKN () SSRLK () SSRLK# () LK_PIE_MINI_ () LK_PIE_MINI_# () LK_PIE_LN () LK_PIE_LN# () LK_PIE_NEW () LK_PIE_NEW# () LK_PIE_MINI_ () LK_PIE_MINI_# () PROJET : E Quanta omputer Inc. Size ocument Number Rev EXTERNL LOK GENERTOR ate: Monday, pril 0, 00 Sheet of

14 R R R PIE Power.V RT E_PWRG L TI00G MMT0 VRT RT_N0 R.U_ RT_N0 VSUS N EN S_-000 Per ME's request, Swap Pin and Pin FOR S00, NET TO PU_PG/LT_PG FOR S0, NET TO R0 SSMUXSEL/GPIO0 00/F_ (,) PU_PWRG T0 T T T (,,) LT_STOP# VSUS T T R.K/F_ R K/F_ T () LLOW_LTSTOP T () H_PSLP# T () LT_RST# PU_PWR_S R0 *0K_ K_X R0 *0_ H_INTR H_NMI H_INIT# H_IGNNE# H_0M# H_FERR# STP_PU# R 0_ PRSLPVR FOR S0, THIS LL IS LT_RST# LY 000p/0V_ U.U_ R.K_ NSZ0PX_NL E_PWRG U For EMI (,,,,) LINK_RST# m S0 S xmm G0 U PI_MINI R _ PLK_MINI PLK_MINI *P RST# PILK0 PLK_MINI (,) Part of PI_ R _ PLK_ PLK_ *P_ PILK T PLK_ (,) J U PI_PM R _ PLK_PM PLK_PM *P_ () SSRLK PIE_RLKP PILK PLK_PM (,) J V PI_SIO R _ PLK_SIO PLK_SIO *P_ () SSRLK# PIE_RLKN PILK PLK_SIO () W PI_LK R _ PILK PILK *P RX0P_ PILK PILK () R *0_.0U_ P U PI_LN R _ PLK_LN PLK_LN *P_ (0) _RX0P _RX0N_ PIE_TX0P PILK PLK_LN ().0U_ P V PI_LK R _ PILK PILK 0 *P_ (0) _RX0N S LIRTI RESISITOR VLUE _RXP_ PIE_TX0N PILK PILK ().0U_ M T SPIF_RR R 0_ (0) _RXP.0U RXN_ PIE_TXP SPIF_OUT/PILK/GPIO S_SPIF_OUT () (0) _RXN M PIE_TXN S00 S0 PIRST#_ T K PIE_TXP PIRST# J T K PIE_TXN OHM % 0 OHM % [0..] T H PIE_TXP [0..] (,,) 0 T H PIE_TXN W 0/ROM.0K % 0 OHM % /ROM Y V (0) _TX0P T PIE_RX0P /ROM W 0 ohm.k %.U_ (0) _TX0N T PIE_RX0N /ROM W (0) _TXP T PIE_RXP /ROM (0) _TXN T PIE_RXN /ROM Y U T M PIE_RXP /ROM (,,) E_PWRG NSZ0PX_NL T M PIE_RXN /ROM PIRST#_ T0 M PIE_RXP /ROM PIRST# T M PIE_RXN /ROM PIRST# (,,,) 0 R 0/F_ PIE_LRP 0/ROM E J R 0/F_ PIE_LRN PIE_LRP /ROM PIE_VR E R PIE_LRN /ROM *P_.K_ P_.V L R.K/F_ PIE_LI /ROM E E SK00T-0Y-S PIE_LI /ROM PIE_PV /ROM U PIE_PV /ROM0 J R *0_ /ROM U EN PIE_PVSS /ROM H OM HNGE N UNMOUNTE R V 0U/0V/XR_ U/0V_.U_ /ROM F 0 PIE_VR_ 0/ROM F J PI_LOK# R.K_ PIE_VR_ /ROM F INTE# R.K_ PIE_VR_ /ROM G H INTF# R.K_ PIE_VR_ /ROM G INTG# R.K_ 0 PIE_VR_ G H INTH# R.K_ PIE_VR_.U_ G PIE_VR PIE_VR_ J H PIE_VR_ J PIE_VR_ L G PIE_VR_0 L 0 PIE_VR_ 0 L G PIE_VR_ N V.U_.U_.U_ PIE_VR_ E0#/ROM0 E0# (,).U_.U_.U_.U_.U_.U_ E#/ROM F E# (,) E#/ROMWE# J R 0K_ E# (,) U/0V_ G SERIRQ E# E# (,) FRME# FRME# FRME# (,) H EVSEL# RN.KX_ EVSEL#/ROM0 EVSEL# (,) G IRY# PERR# IRY# 0 IRY# (,) Ti Recommend TRY# FRME# TRY#/ROMOE# TRY# (,).U_ PR TRY# Vendor: NSK PR/ROM F PR (,) Y STOP# STOP# Part Number: NXG.KEFU PPM. STOP# STOP# (,) G PERR# K_X PERR# PERR# (,) SERR# RN.KX_ SERR# SERR# (,) J REQ0# REQ# Y.KHZ REQ0# E REQ# EVSEL# K_X REQ# G REQ# REQ0# REQ# REQ# () H REQ# REQ# REQ#/GPIO0 REQ# () H REQ# REQ#/GPIO GNT0# RN *.KX_ R R 0M_ GNT0# F GNT# GNT0# GNT# 0M_ H GNT# GNT# GNT# GNT# () R GNT# GNT# VPU VRT P_ GNT#/GPIO GNT# () P_ G GNT# GNT# GNT#/GPIO G LKRUN# R0 LKRUN# LKRUN# (,,) F PI_LOK# RN.KX_ K/F_ R LOK# REQ# RT_N0 TI recommand have internal pull-up INTE# SERR# PU_PWR_S INTE#/GPIO INTE# () F INTF# REQ# INTF#/GPIO INTF# () F INTG# IRY# K_X INTG#/GPIO INTG# (,) F INTH# X INTH#/GPIO INTH# () Q U/0V_.K/F_ RT_N0 R.U_.K/F_ JP *lear P X S0 XTL PI EXPRESS INTERFE PU_PG/LT_PG W INTR/LINT0 W NMI/LINT W INIT# SMI# SLP#/LT_STP# IGNNE#/SI 0M#/SI Y FERR# STPLK#/LLOW_LTSTP H PU_STP#/PSLP_V# PSLP_O#/GPIO W PRSLPVR LT_RST#/PRSTP#/PROHOT# PU LP PI INTERFE RT PI LKS L0 L0 G L L G L L H L L H F LFRME#/FWH LFRME# J LRQ#0 LRQ0# H LRQ# LRQ#/GNT#/GPIO W MREQ# MREQ#/REQ#/GPIO F SERIRQ SERIRQ RTLK RT_IRQ#/GPIO F VT E RT_ U/0V_ VRT dd for debug. L0/FWH0 () L/FWH () L/FWH () L/FWH () LFRME#/FWH (,) MREQ# () SERIRQ (,,) RT_LK () UTO_# () P_ GNT# PR L L L L0 MREQ# LKRUN# LRQ# LRQ#0 R R R R0 R R R RN *.K_ *.K_ 00K/F_ 00K/F_ 00K/F_ 00K/F_ 0K_ 0KX_.U_ R 0K_ S- H_PSLP# PROJET : E Quanta omputer Inc. Size ocument Number Rev ustom S0M PIE/PI/PU/LP I/F ate: Monday, pril 0, 00 Sheet of

15 PU/P Edison-- /0 Modify SUS_STT# SUS# SUS# NSW# PME# SWI# EMIL_LE# RI# GPM# GEVENT# PIE_WKE# MX_L# S_THERMTRIP# EXTEVNT# GPIO PLK_SM PT_SM S_LL# GPIO RIN# GPIO0 GPIO GPIO GPIO RST_H# GPIO GPIO GPIO0 PSPK PU_PROHOT# If throttling from SM remore R _SIN Z_SIN _SIN0 _ITLK_R Z_RST# Z_SYN Z_SOUT Z_ITLK () _ITLK_M () Z_ITLK S- R R R R R R0 R R R R R0 R R R R0 R R R R0 R R0 R R R0 R0 R R0 R R R R R R0 R R R R R *0K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ *0K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ *P_.K/F_.K/F_ 0K_.K/F_ 0K_ 0K_ 0K_ 0K_ 0K_.K/F_ 0K_ 0K_ 0K_.K/F_.K_.K_ R _ R0 _ *P_ V_S V.U_.U_ Z_ITLK S_OSIN R *_ (,,) PME# () RI# () SUS# () SUS# () NSW# (,,) E_PWRG () () () GTE0 RIN# SWI# (,) PIE_WKE# () S_THERMTRIP# SUS_STT# elay 0ms after S powerok () RSMRST# () S_OSIN () PU_PROHOT# () RST_H# () PSPK (,,) PLK_SM (,,) PT_SM (,) PU_PWRG () H_PSLP# () MX_L# (,,) LT_STOP# () _SOUT_M PME# RI# SUS# SUS# NSW# OR_I OR_I0 R 0_ S_LL# 0K_ 0K_ GTE0 RIN# SWI# EXTEVNT# GEVENT# GPM# PIE_WKE# EMIL_LE# S_THERMTRIP# RSMRST# S_M_X GPIO0 GPIO PU_PROHOT# GPIO RST_H# GPIO PSPK PLK_SM PT_SM US_OP# US_OP# US_OP# US_OP# Z_RST# R 0_ () US_OP# US_OP# () US_OP# US_OP# US_OP# T () SI# SI# () KSMI# KSMI# T () _SOUT () _SIN0 () Z_SIN T T0 T V_S R R R0 0_ Z_ITLK Z_SOUT Z_SYN GPIO0 _ITLK_R _SOUT _SIN0 Z_SIN _SIN _SYN_R _RST# GPIO T GPIO GPIO H_PSLP# GPIO MX_L# R0 0_ *P_ E OM HGE N STUFF R0. For PU speed issue. F E G F G F E G E L L L J J M L T U PI_PME#/GEVENT# RI#/EXTEVNT0# F SLP_S# SLP_S# E PWR_TN# PWR_GOO SUS_STT# TEST TEST TEST0 G0IN KRST# N Z_ITLK M Z_SOUT K Z_SIN/GPIO L Z_SYN K Z_RST# S0 S0 S xmm LP_PME#/GEVENT# LP_SMI#/EXTEVNT# S_STTE/GEVENT# SYS_RESET#/GPM# WKE#/GEVENT# LINK/GPM# SMLERT#/THRMTRIP#/GEVENT# RSMRST# M_OS OS / RST ST_IS0#/GPIO0 ROM_S#/GPIO GHI#/ST_IS#/GPIO W_PWRG/GPIO SMRTVOLT/ST_IS#/GPIO SHUTOWN#/GPIO SPKR/GPIO SL0/GPO0# S0/GPO# SL/GPO# F S/GPO# _SL/GPIO _S/GPIO SSMUXSEL/ST_IS#/GPIO0 LL#/GPIO _ITLK/GPIO _SOUT/GPIO Z_SIN0/GPIO Z_SIN/GPIO Z_SIN/GPIO _SYN/GPIO0 _RST#/GPIO R _ Z_SOUT R _ Z_SYN () Z_SOUT () Z_SYN () Z_RESET# 00 *0P_ *P_ T T T R _ R 0K_ ZLI US O GPIO US_O#/SLP_S/GPM# US_O#/Z_OK_RST#/GPM# US_O#/GEVENT# US_O#/GEVENT# US_O#/R_RST#/GPM# US_O#/GPM# US_O#/GPM# US_O#/GPM# US_O#/GPM# US_O0#/GPM0# E N N N E N N N N N () _SYN_M *P_ Part of PI / WKE UP EVENTS R _ *P_ US INTERFE US PWR S_M_X USLK US_ROMP US_ROMP US_TEST US_TEST0 US_HSP US_HSM- US_HSP US_HSM- US_HSP US_HSM- US_HSP US_HSM- US_HSP US_HSM- US_HSP US_HSM- US_HSP US_HSM- US_HSP US_HSM- US_HSP US_HSM- US_HSP0 US_HSM0- VSS 0 H G E E G H E E G H G H E G H VTX_0 VTX_ VTX_ VTX_ VTX_ VRX_0 VRX_ 0 VRX_ VRX_ VRX_ V VSS_US_ VSS_US_ VSS_US_ 0 VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_0 VSS_US_ VSS_US_ 0 VSS_US_ VSS_US_ VSS_US_ E VSS_US_ E VSS_US_ F VSS_US_ VSS_US_ VSS_US_0 VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_0 VSS_US_ VSS_US_ VSS_US_ F F F F F F G G H H J J J J J J () _RESET#_M R *_ 0 *0P_ R0 0_ R R T T0 T T T T EN HNGE R'S FOOTPRINT TO 00 V_US *0_.K/F_ USP () USP- () USP (0) USP- (0) USP () USP- () USP () USP- () USP () USP- () USP () USP- () USP () USP- () USP0 () USP0- () R0 _ *P_ R _ *P_ USLK () US0: M/ IO US: M/ IO US: / IO US: / IO US: NEW R US: MINI R US: S US: LUETOOTH US power V_US.V_V LN???? Z_RST# U/0V_.U_.U/0V/XR U/0V_ V U/0V_.U_ oard I I I Z_RST# KSMI# US power use S power,ut Over current signal datasheet is S only,ut TI FE say use S is ok US_OP# SI# US_OP# US_OP# US_OP# US_OP# US_OP# US_OP#.U_ For ST mount R, For PT mount R *0K_@ST R R.U_ OR_I0 *0K_OR_I R R0 RP0 RP RN.U_ 0K_@PT R -Test Size ocument Number Rev ustom S0M PI/GPIO/US/ ate: Monday, pril 0, 00 Sheet of V_S *0K_.K/F_ 0KX_ V_S 0KX_ 0KX_ L TI00G.U_ L SK00T-0Y-S R 0K_.U_ VSUS PROJET : E Quanta omputer Inc.

16 ST clock Option EMI--/0 ST Power 0ohm/ 0ohm/ /-rec S- PU_PWR=.V WHEN S00 PU_PWR=.V WHEN S0 For First build,if next build no use remove from OM. For First build,if next build no use remove from OM. Modify Resistor :R When PT mount S0000J ST nd Osc mount S0F S0M H/POWER/EOUPLING ustom Monday, pril 0, 00 Size ocument Number Rev ate: Sheet of S_S_V S_S_.V P0 P P P P P P P0 P P P P P P P P ST_TX0_ ST_TX0-_ ST_L ST_X ST_X ST_T# ST_X R_OM_ML ST_X V_.V VQ_V V_Y V_VREF V_VREF V_S V_K_.V.VUS_PHY.VSUS V.V.V_S.VUS_PHY.V_T PLLV_T XTLV_T XTLV_T.V.V PLLV_T XTLV_T PLLV_T.V_T.V.V_T V.V V V.VUS_PHY V V.V.V PU_PWR_S.U_ Y *MHZ@ST 0.U_ Q *MMT0@ST.U_ R0 *0M_@ST 0.0U_ U/0V_ 0U/0V/XR_.U_.U_.U_ R0.K/F_ 0 SW00 L SK00T-0Y-S U/0V_.U_ 0 *.U_ 0.U_.U_ T0.U_.U_ U/0V_ 00U/.V_.U_ 0.U_ L FJHS00.U_.U_ L SK00T-0Y-S L SK00T-0Y-S R.K/F_ T.U_ R *K/F_@ST.U_.U_ Part of S00 S xmm POWER U S0 W V V V V V U T R R P P P N N M M L L L L M P P T V W W W W E H N M N R U R M N U J J G F G H H G J J J U V V E E E H J U F J J K 0 Y E 0 F E M M J J G G G H J J K L L L L L M M M N N P P P P P P T T T T T U V V V V V V V R T V W E F J V VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VQ_ VQ_ VQ_ VQ_ VQ_ VQ_ VQ_ VQ_ VQ_ VQ_0 VQ_ VQ_ VQ_ VQ_ VQ_ VQ_ VQ_ VQ_ VQ_ VQ_0 PU_PWR V_VREF S_.V_ US_PHY_.V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ VSS_ VSS_ VSS_ VSS_ S_.V_ S_.V_ S_.V_ VK_.V VSSK VSS_ VSS_ VSS_ VSS_ V_0 V_ V_ S_.V_ VQ_ VQ_ VQ_ VQ_ VQ_ VSS_ S_.V_ S_.V_ S_.V_ S_.V_ S_.V_ US_PHY_.V_ US_PHY_.V_ US_PHY_.V_ VSS_ VSS_ VQ_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ US_PHY_.V_ VK_.V VQ_ VQ_ PIE_VSS_ PIE_VSS_ PIE_VSS_ PIE_VSS_ PIE_VSS_ PIE_VSS_ PIE_VSS_ PIE_VSS_ PIE_VSS_ PIE_VSS_ PIE_VSS_ PIE_VSS_ PIE_VSS_ PIE_VSS_ PIE_VSS_ PIE_VSS_ PIE_VSS_ PIE_VSS_0 PIE_VSS_ PIE_VSS_ PIE_VSS_ PIE_VSS_ PIE_VSS_ PIE_VSS_ PIE_VSS_ PIE_VSS_ PIE_VSS_ PIE_VSS_0 PIE_VSS_ PIE_VSS_ PIE_VSS_ PIE_VSS_ PIE_VSS_ PIE_VSS_ PIE_VSS_ PIE_VSS_ PIE_VSS_ PIE_VSS_0 PIE_VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ PIE_VSS_ PIE_VSS_0 PIE_VSS_.U_ U/0V_ U/0V_ T Y *MHZ_OS V VSS OE OUT 0.0U_.U_ L0 *TI00G_@ST T /00 Part of S0 S xmm SERIL T POWER SERIL T SPI ROM HW MITOR U S0 Y W W E F G H J J H G G F F E E E J0 E F F E F F G G G G G G E H H J H J H J H H J H0 J0 H J H J F F F G G E J J G G G T V N P W G V L M V M P M V P P T T M N M P H H J J G G G0 J G H0 J H J IE_IORY IE_IRQ IE_0 IE_ IE_ IE_K# IE_RQ IE_IOR# IE_IOW# IE_S# IE_S# IE_0/GPIO IE_/GPIO IE_/GPIO IE_/GPIO IE_/GPIO IE_/GPIO0 IE_/GPIO IE_/GPIO IE_/GPIO IE_/GPIO IE_0/GPIO IE_/GPIO IE_/GPIO IE_/GPIO IE_/GPIO IE_/GPIO0 V_ST_ XTLV_ST V_ST_ PLLV_ST_ VSS_ST_0 VSS_ST_ VSS_ST_ V_ST_ PLLV_ST_ VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_0 VSS_ST_ VSS_ST_ V_ST_ ST_TX ST_TX- ST_RX ST_RX- ST_TX ST_TX- ST_RX ST_RX- ST_TX0 ST_TX0- ST_RX0- ST_RX0 ST_TX ST_TX- ST_RX- ST_RX ST_L ST_X ST_X ST_T#/GPIO V_ST_ V_ST_ V_ST_ V_ST_ VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_ SPI_I/GPIO SPI_O/GPIO SPI_LK/GPIO SPI_HOL#/GPIO SPI_S#/GPIO FNOUT/GPIO FNOUT/GPIO FNIN0/GPIO0 FNIN/GPIO FNIN/GPIO LN_RST#/GPIO ROM_RST#/GPIO 0/GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO0 TEMPIN0/GPIO TEMPIN/GPIO TEMPIN/GPIO TEMPIN/TLERT#/GPIO FNOUT0/GPIO V VSS TEMP_OMM V_ST_ V_ST_0 V_ST_ V_ST_ VSS_ST_ VSS_ST_ VSS_ST_ V_ST_ VSS_ST_ VSS_ST_ V_ST_ VSS_ST_ V_ST_ 00U/.V_ 0.U_ R 0_@PT.U_.U_ R0 0_@PT T T.U_ L *SK00T-0Y-S@ST T 0.U_ R 0_ 0.U_ Quanta omputer Inc. PROJET : E T U/0V_.U_.U_.U_.U_ U/0V_.U_.U_ R 0_@PT R */F_ U/0V_ T L *LMS_.U_ 0.U/0V/XR U/0V_ T L FJHS00 U/0V_.U_.U_ *.U_.U_ T L SK00T-0Y-S 0 U/0V_.U_.U_ 0.U_ T 0.U_ R *0_ T R 0_@PT.U_ L *SK00T-0Y-S@ST.U_ *P_@ST R0 K/F_ 00 U/0V_ U/0V_.U_.U_.U_ 0 U/0V_ *P_@ST PK# (,) PREQ () PIOR# () PIOW# () PS# () PS# () P0 () P () P () PHRY () IRQ () ST_TXP0 () ST_TXN0 () ST_RXP0 () ST_RXN0 () P[0..] () ST_LE# ()

17 Edison-/0--hange to S0 V V_S V V V V :OM change. R: Stuff, R: Un-stuff. isable US PHY POWEROWN. V_S V V V V V () _SOUT () RT_LK () PILK () PILK (,) PLK_MINI (,) PLK_ R *0K_ R 0K_ R *0K_ R 0K_ R0 0K_ R *0K_ () UTO_# () S_SPIF_OUT (,) PLK_PM () PLK_SIO () PLK_LN (,) LFRME#/FWH R 0K_ R *0K_ R *0K_ R 0K_ R 0K_ R *0K_ R 0K_ R0 *0K_ R 0K_ R0 *0K_ R0 *0K_ R 0K_ R *0K_ R 0K_ R 0K_ R *0K_ R *0K_ R00 0K_ REQUIRE STRPS PULL HIGH PULL LOW _SOUT USE EUG STRPS IGNORE EUG STRPS EFULT RT_LK INTERNL RT EFULT EXTERNL RT PI_LK PI_LK PI_LK0 PI_LK USE INT. PLL USE EXT. MHZ EFULT PU IF=K PU IF=P EFULT PLK_MINI ROM TYPE: H, H = PI ROM PLK_ H, L = LP TYPE I ROM L, H = LP TYPE II ROM EFULT L, L = FWH ROM NOTE:FOR S0,PILK[:] RE NETE TO SUSTRTE LLS PILK[:0] PULL HIGH PULL LOW UTO_# S_SPIF_OUT PLK_PM PLK_SIO PLK_LN PWR MNUL PWR EFULT UTO PWR SPIF_OUT SIO MHz SIO MHz EFULT PI_LK XTL MOE NOT SUPPORTE MHZ OS MOE EFULT PI_LK US PHY POWEROWN ISLE EFULT US PHY POWEROWN ENLE PI_LK PIE_M_SET LOW EFULT PIE_M_SET HIGH LFRME# LFRME# ENLE THERMTRIP# EFULT ISLE THERMTRIP# IOS ENLE FTER STRTUP V V V V V V V R 0K_ R *0K_ R *0K_ R *0K_ R *0K_ R *0K_ R *0K_ (,) PK# (,,) (,,) (,,) (,,) (,,) (,,) R *0K_ R *0K_ R 0K_ R 0K_ R 0K_ R 0K_ R0 *0K_ EUG STRPS PK# PI_ PI_ PI_ PI_ PI_ PI_ PULL HIGH USE LG RESET EFULT YPSS PI PLL YPSS PI LK YPSS IE PLL USE EEPROM PIE STRPS S- PULL LOW USE SHORT RESET USE PI PLL EFULT USE PI LK EFULT USE IE PLL EFULT USE EFULT PIE STRPS EFULT PROJET : E Quanta omputer Inc. Size ocument Number Rev ustom S0M STRPS ate: Monday, pril 0, 00 Sheet of

18 I Select : 0 Interrupt Pin : INTG#, INTF# Request Indicate : REQ# Grant Indicate : GNT# (,) INTG# (,) PLK_MINI () REQ# (,) (,) (,,) (,,) (,) E# (,,) (,) (,) (,) (,) E# (,) IRY# (,,) LKRUN# (,) SERR# (,) PERR# (,) E# (,) (,) (,) 0 (,) (,) (,) (,) (,) PLK_MINI EUG PURPOSE LY V V V N *MINIPI TIP RING LN LN LN LN LN LN LN LN 0 LE_GP LE_YP LE_GN LE_YN N N -INT V V -INT 0 R(IRQ) R(IRQ) VUX PILK -RST V -REQ -GNT 0 V -PME (V) 0 V 0 (V) -E ISEL 0 0 PR -E 0 -IRY V -FRME -LKRUN -TRY -SERR -STOP V 0 -PERR -EVSEL -E 0 0 -E0 V V 0 (V) 0 V (V) SERIRQ SYN MEN 0 0 SIN0 SOUT 0 0 ITLK SIN 0 0 -_PRIMRY -RESET 0 EEP -MPIK MI SPK -MI -SPK 0 -RI N V VUX V V VSUS PIRST# R 0/F_0 0 VSUS INTF# () GNT# ().U_ PIRST# (,,,) 0 (,) (,,) (,,) (,,) (,) 0 (,) PR (,) (,) (,) FRME# (,) TRY# (,) STOP# (,) V EVSEL# (,) (,) (,) (,) (,) E0# (,) (,) (,) (,) 0 (,) SERIRQ (,,) 0.U_.U_.U_ PROJET : E Quanta omputer Inc. Size ocument Number Rev MP MINI PI NETOR (EUG LY) ate: Monday, pril 0, 00 Sheet of

19 TV MINI R PROUT NME: MINI VT MFR NME: 00 N MINIPI EXP_0P_H V_TV.V VSUS (,) PIE_WKE# (,,) PME# R *0_ R 0_ VSUS Q TEU (0) MINI_PIE_TXP (0) MINI_PIE_TXN (0) MINI_PIE_RXP (0) MINI_PIE_RXN () LK_PIE_MINI_ () LK_PIE_MINI_# () MINI_LKREQ# R 0_ EN REMOVE P. TV_REQ_LK PETp0 PETn0 PERp0 PERn0 REFLK REFLK- LKREQ# WKE#.V.V LE_WPN# LE_WLN# LE_WWN# US_ US_- SM_T SM_LK.V.Vaux PERST#.V.V GP_IR T TV_SENSE# () R0 0_ R 0_ R 0_ R 0_ USP () USP- () PT_SM (,,) PLK_SM (,,) LINK_RST# (,,,,) EN FOR THREML ISSUE SWP TV N WLN LOTI V VSUS.V 0U/0V/XR_.U_.U_.U_.U_.U_.U_ WLN MINI R N MINIPI EXP_0P_H.V V VSUS PIE_WKE# R PME# R *0_ *0_ VSUS Q *TEU (0) MINI_PIE_TXP (0) MINI_PIE_TXN (0) MINI_PIE_RXP (0) MINI_PIE_RXN () LK_PIE_MINI_ () LK_PIE_MINI_# EN REMOVE P. PETp0 PETn0 PERp0 PERn0 REFLK REFLK- LKREQ# WKE#.V.V LE_WPN# LE_WLN# LE_WWN# US_ US_- SM_T SM_LK.V.Vaux PERST#.V.V WLN_LE NO SUPPORT US LINK_RST# R 0_ WIRELESS_LE R 0_ R 0_ R 0_ RF_EN PT_SM PLK_SM WIRELESS_LE () RF_EN () V.V VSUS.U_ 0.U_.U_.U_ V V_TV V_TV_S L KHS0_ MINI R () TV_POWER# O0 Q0 0U/0V/XR_.U_ PROJET : E Quanta omputer Inc. Size ocument Number Rev MINI R (WLN N TV) ate: Monday, pril 0, 00 Sheet of

20 RT () VG_RE () VG_GRN () VG_LU VG_RE VG_GRN VG_LU.U/V V R 0/F_ V_RT RT_R RT_G RT_ 0P_ U M00 V_SYN V_ YP V_VIEO VIEO_ VIEO_ R 0/F_ VIEO_ 0P_ V SYN_OUT SYN_OUT SYN_IN SYN_IN _IN _IN _OUT _OUT R 0/F_ 0 SSM L 0_ L 0_ L 0_ 0P_ VSYN HSYN VSYN HSYN LK T RTLK_R RTT_R 0P_ R _ R0 _.U_ V_RT RT_R RT_G RT_ 0 0P_ VSYN () HSYN () R R V.K/F_.K/F_ MIL L L0 0P_ V_RT 0 hange Value to.k RT PORT LM0SN_ LM0SN_ () MITOR_PLUG# LK () R0 R.K/F_.K/F_ T () hange FootPrint 00 N RT_FSFR 0P_ R _ R _ RTT RTHSYN RTVSYN RTLK 0P_ 0P_ MTW 0P_ LVS & S N L_0 INV TXLOUT0 TXLOUT0- TXLOUT TXLOUT- ISP VJ PHL_LK PHL_T L NETOR TXLLKOUT TXLLKOUT- TXLOUT TXLOUT- LV S_V 0_ V LV 0U/0V/XR_U/0V_ V R R TXLLKOUT () TXLLKOUT- () TXLOUT () TXLOUT- () TXLOUT () TXLOUT- () TXLOUT0 () TXLOUT0- () PHL_LK () PHL_T () R L KHS0_ USP- USP.K_.K_ L V 0 PHL_T PHL_LK V K0LL_.U_ 0_ 0_ L *LWHN00SQL INV R U/0V_ R0 TRST () 0U/V_ USP- () USP () 000p/0V_.U_ TV () TV_/R_SYS L TV_/R_SYS.UH R 0/F_ P_ TV-HROM 0 P_ N TV-LUM L.UH P_ TV_Y/G_SYS R 0/F_ P_ TV_Y/G_SYS () () L_POWER_ V.U_ U IN IN / T0_ OUT W:0 mil LV L POWER SUPPLY V 0.U_ R 0_.U_.0U_ LV W:0 mil 0U/0V/XR_ V TV_/R_SYS TV_Y/G_SYS TV_OMP_SYS FM0FR0 TV-OMP L.UH P_ P_ TV_OMP_SYS R 0/F_ TV_OMP_SYS () R () L () E_FPK# 0K_ VPU MTW MTW R 0K_.U_ V 0U 0U V V 0 0U LI SWITH N. SW LI# R 0K_ R MTW K/F_ ISP LI# () RT, LVS, TV, S MPU-0- change to Lid switch 0.U_ PROJET : E Quanta omputer Inc. Size ocument Number Rev VG Ports, LI, S-VIEO, S ate: Monday, pril 0, 00 Sheet 0 of

21 PT H PT O () P[0..] P P P0 P P P P P P0 P P P P P P P () IELE# RST_H# () RST_H# (,,,,) LINK_RST# LINK_RST# () PREQ () PIOW# () PIOR# () PHRY (,) PK# () IRQ () P () P0 () PS# *00P_ V H_V R R *_ *_.U_ -RST_H0 P P P P P P P P0 PHRY IRQ IELE# 000p/0V_ -RST_H0 H_@PT N V V P P P0 P P P P P PSEL -PIG R H_V LOSE IE SIE R P.U_ R 0_ *0K_ R *0K_ P () PS# () R 0_ *00U/.V_ IRQ *0K_ V V V O_V 0K_@PT R When ST,Un-stuff R and stuff R Reserve Slave for PT Reserve Master for ST -RST_H0 P P P P P P P P0 PIOW# PHRY IRQ P P0 PS# IELE# RSEL_R R *0_@ST N P P P0 P P P P P PREQ PIOR# PK# -PIG P PS# 000p/0V_.U_ FH0MR0V.U_.U_ O_V R 0_ *00U/.V_ V Q TEU R *0K_ PREQ R *.K_ LINK_RST# H h-cdp H h-c0dp H H-P H h-cdp H h-c0dp H0 h-c0dp H h-c0dp H h-c0dp H h-cdp H h-cdp H h-c0dp ST H N *ST_H@ST HS H-S0P HS HS H-S0PLU-V h-cd0p HS H-S0P HS H-S0P N HS H-S0P HS H-S0P HS H-S0P MINI R H h-c0dp ST_RXN0_ ST_RXP0_ 0 0.0U_.0U_ RST HS0 H-0P HS H-S0P HS H-S0P HS H-S0P P *EMI_P H H-SP RXP RXN TXN TXP ST_TXP0 () ST_TXN0 () ST_RXN0 () ST_RXP0 () HS H-S0P HS H-S0P hole for new card.v.v.v V V V RSV V V V 0 0.VST H_V SPURE N P. OME FROM PT H For First build,if next build no use remove from OM..VST R *0_@ST.U/0V/XR_ V.U/0V/XR_.U_ 0 X H H-P H H-P Hole for luetooth H H H-0P-V H-T0P-V Hole for M EN PER ME REQUEST, FOUR PS. P *EMI_P P *EMI_P P *EMI_P P *EMI_P ISK N HOLE PROJET : E Quanta omputer Inc. Size ocument Number Rev H & ROM, HOLES ate: Monday, pril 0, 00 Sheet of

22 US POWER SUPPLY LUETOOTH hage US Power to S plane VSUS.U_ () US# 0 MILS R 0_ VSUS U GPU USPWR_M IN OUT IN OUT OUT EN# US_O_M R 0_ - O# 0 MILS 0U/0V/XR_.U_ FOR M/ () T_POWER# V 0U/0V/XR_ VSUS.U_ 0 MILS VSUSU GPU USPWR_ IN OUT IN OUT OUT EN# R US_O_ R 0_ *0_ - O# 0 MILS 0U/0V/XR_.U_ US_OP# () FOR US/ () () () USP USP- T_LE R 0_ L *LWHN00SQL R 0_ USP USP- Q L O0 KHS0_ T_PWR_R T_POWER T_LE.0U_ N FHS0FR US_OP# () US I/O NETORS US OR WIRE NETOR USPWR_M L LMPG0SN USP_PWR_M R 0_ 0 00U/.V_ () () () () L *LWHN00SQL R 0_ R 0_ L *.U_ *.U_ USP_PWR_M USP- USP N 00MR00SX0ZX 0 USP0- USP0 USP0- USP0 USP- USP () USP- () USP () USP- () USP USPWR_ N *LWHN00SQL R 0_ *.U_ *.U_ : change P/N US, T, US/ OETOR Size ocument Number Rev MINI PI & US PORT & T ate: Monday, pril 0, 00 Sheet of PROJET : E Quanta omputer Inc.

23 RTL-GR Y MHZ_LN P_ P_ THERE IS E E PLNE UNER I V_S U/0V_.U_ 0 LN_XTL LN_XTL R0.K_ U TRL GV VTRL V MIP0 MIN0 V MIP MIN V MIP MIN V MIP MIN V V V V V LE0_T# LE_LINK# LE_T# V V RTL-GR V 0 0 RSET VTRL GV KTL KTL V V LE0 LE LE LE V V N N V N N LNWKE PERST V EV HSIP HSIN E REFLK_P REFLK_N EV HSOP HS E V EESK EEI V EEO EES V N V N N V V ISOLTE N N V 0 EESK EEI V EEO EES V V V V ISOLTE V MTW MTW MTW LE_T# LE_LINK# V off during S and S V R K/F_ R K_ TRNSFORMER RJ NETOR.U_ V L *K0HS0.0U_ V LN.0U_.0U_ V R MI0 MI MI MI LE_T# 00/F_ LE_LINK#.0U_ V R 00/F_ N0 LE_Y_ LE_Y_ TR TRT TR- TR TRT 0 TR- TR TRT TR- TR TRT TR- TRL V MI0 MI0- V MI MI- V MI MI- V MI MI- V V V MI0- MI- MI- MI- LE_O_ LE_G_ LE_O/G_ SHIEL SHIEL RJ onnector FHSFR0 0 0 R *0K_ LYOUT SUGGESTI (,,) PME# () LN_PME# (,,,,) LINK_RST# (,,,) PIRST# R *0_ R 0_ R0 0_ LN_PME# R 0_ LN_PME_WKE# LN_PERST# V EV E EV E V SYSTEM E-P (0) LN_PIE_TXP0 (0) LN_PIE_TXN0 () LK_PIE_LN () LK_PIE_LN# (0) LN_PIE_RXP0 (0) LN_PIE_RXN0.U_.U_ LN_RXP0 LN_RXN0 E E E POWER SUPPLY V_S POWER SUPPLY.W L0 K0HS0 0MILS V U/0V_ V U/0V_.U_ L.U_ K0HS0.U_.U_.U_ LOSE RTL V pins (,, and ) V EEPROM R.K_ V TRL E Q S 0MILS.U_.U_ LOSE RTL VH pins ( and ) V EES EESK EEI EEO U S SK I O T V N ORG.U_ TRE <" WITH > MILS TRL V E U/0V_ Q S 0MILS R 0_ ISOLTE E N L L K0HS0 K0HS0.U_.U/.V_.U_.U_.U_ EV.U_ E LOSE RTL VL pins (,, and ) LOSE for RTL V pins ( and ) V RJ N S_-000 TIP RING 0 000P/KV_0 000P/KV_0 G G N RJ- LN TRE <" WITH > MILS U/0V_.U_.U_.U_.U_.U_ 0.U_.U_.U_ LOSE RTL V pins (,,,,,,,, and ) PROJET : E Quanta omputer Inc. Size ocument Number Rev LN RTL-GR PI-E & RJ ate: Monday, pril 0, 00 Sheet of

24 PI0 PI I/F NEW R NEW R HEER: FHMR0 (0-) NEW R EJETER: FZF00 (0-) I Select : Interrupt Pin : INTE#, INTG#, INTH# Request Indicate : REQ# Grant Indicate : GNT# R0 (,,) [0..] (,) (,) (,) (,) 0/F_ (,) PR (,) EVSEL# (,) FRME# () GNT# (,) (,) () (,) (,) (,) E0# E# E# E# IRY# PERR# REQ# SERR# STOP# TRY# [0..] PM_ISEL PLK_PM PR EVSEL# FRME# GNT# PM_ISEL IRY# PERR# REQ# SERR# STOP# TRY# R LK_PM R R P U V W R0 U0 V0 R U V W V U R W W T T R P R R P N N N M M M M M W0 V U P U U R L N V R L W V W U /E0 /E /E /E PR EVSEL FRME GNT ISEL IRY PERR REQ SERR PIXX_0 *_ PLK_PM_R LK_PM_R GRST PLK PRST TEST0 STOPRSV // V0 // V# TRY N *_ LK SUSPEN MFUN0 MFUN MFUN MFUN MFUN MFUN MFUN SPKROUT RI_OUT/PME S SL LTH T LOK 0 F K J G H H H J J J L K H L G G EN OM HNGE REMOVE Y N 0 STUFF R0 LKM GRST#_ 0_SUS# INTE# R 0_ INTH# SERIRQ VSP R0.K/F_ FM_LE LKRUN# PLK_PM PIRST# PMSPK PM_PME# S_R SL_R P TEST_M PHY_TEST_M P PSMOE E *0p_ *0p_ R0 0_ Y OUT V *MHz R E0 US_EN# R US_EN R R R OE *0_ R 0_ 0K_ *0K_.K/F_ 0K_ V LK_PM () 0 *.U_ V INTE# () INTG# (,) INTH# () SERIRQ (,,) V FM_LE () LKRUN# (,,) PLK_PM (,) PIRST# (,,,) PMSPK () RI# () Q TEU V _V V V PME# (,,) U PMI PORT PIXX_0 V V // 0 0 // // // // 0 // 0 // // // // // 0 // // // // // // IOWR# // // IOR# // // OE# 0 // E# // 0 // // // // // // // // 0 // /E# // REG# /E# // /E# // /E0# // E# J 0 0 F E E E F H J J J K K K L L L M M N M N N P E E H L PR // H EVSEL# // F FRME# // E GNT# // WE# G INT# // REY(IREQ#) E IRY# // F PERR# // G REQ# // INPK# SERR# // WIT# STOP# // 0 G TRY# // G LK // F LKRUN# // WP(IOIS#) STSHG // V(STSHG#/RI#) LOK# // H RST# // RESET UIO // V(SPKR#) # // # # // # N VS // VS# VS // VS# RSV // RSV // RSV // H 0 M (0) PIE_TXP (0) PIE_TXN (0) PIE_RXP (0) PIE_RXN () LK_PIE_NEW () LK_PIE_NEW# () NEW_LKREQ# (,,) PT_SM (,,) PLK_SM () () (,) PIE_WKE# PETp0 PETn0 PERp0 PERn0 0 REFLK REFLK- PPE# LKREQ#.V.V PERST#.VUX WKE# 0.V.V SM_T SM_LK RESERVE RESERVE PUS# US_ US_- 0 USP USP- PPE# NEW_V NEW_PERST# NEW_VUX NEWR_PIE_WKE# NEW_.V PUS# R 0_ R 0_ PERP PERN USP USP- NEWR_PIE_WKE# NEW R'S POWER SWITH (,,,,) LINK_RST# V V_S.V Q TEU.U_.U_ V_S U TPSPWG.. UXIN.. SYSRST# SHN# RLKEN N 0.VOUT.VOUT UXOUT.VOUT.VOUT STY# PPE# PUS# PERST# O# 0 NEW_V NEW_VUX NEW_.V PPE# PUS# NEW_PERST# N FOXN_NEW_R IEEE EEPROM V PPE# : ( Internal Pull Up, active low when card support PIE ) PUS# : ( Internal Pull Up, active low when card support US ) SHN# : ( Internal Pull Up ) R R V.K_.K_ S_R SL_R U S SL WP L0 0 V 0.U_ V R K/F_ GRST#_.U/V_ V GRST# > ms > 0 ns V V_S.V.U_.U_.U_ NEW_VUX.U_ NEW_V 0 0U/0V/XR_.U_.U_ NEW_.V 0U/0V/XR_.U_ IEEE & NEW R PRST# PLK > 00 us PROJET : E Quanta omputer Inc. Size ocument Number Rev PI0- & NEW R ate: Monday, pril 0, 00 Sheet of