BENQ(EL3) LCDPC Block Diagram

Transcript

1 P STK UP ENQ(EL) LP lock iagram LYER : TOP LYER : GN LYER : IN LYER : IN LYER : V LYER : OT RJ-." panel UO/MO RII M//G/G/G 0/00 Ethernet RTL0EL H LVS PI-E PI-E M VORE:+0.V ~ +.V 0 VLT:+.V V:+.V 0. -PIN G HT-LINK RS0E HOST LVS, MI, R LK POWER GN mmxmm FG PIN _LINK VI[0:] +/- PU_LK +/- HLK PI-E US ST PU VORE lock Gengerator H MX IS MINI R WLN Module EM0 SPK in ard Reader JME H OE L WX H_UIO S00 RT,, ST, IE, LP, PU PI-E, US, MI, PI SM, GPIO, LK mmxmm FG PIN IE US US SS module/zif Webam onn. US PORT X amera Module Headohone Out US X US LP US Int. Mic TPM E ITE SPI Flash Size ocument Number Rev lock iagram Quanta omputer Inc. PROJET : ENQ Tuesday, January 0, 00 ate: Sheet of

2 VPU SW VSUS SUSON ontrol y E SW V PU V.SUS MINON SW V. SUSON VPU() lways ON PWM VPU() VPU SUSON SW VSUS ontrol y E MINON SW V. RV_ON SW RV ontrol y E MINON MINON SW LO V PU_V(.V) SUSON PWM.VSUS MINON SW V. VTERM (0.V) Power On Sequence IN VPU/VPU NSWON# PWRTN# RV_ON IN LWYS ON S OFF VRON PWM S OFF +VORE RSMRST# SUS#,SUS# SUSON MINON VSUS,V VR_ON VORE_PU N_PWRG PWROK PIRST# S00 Quanta omputer Inc. PROJET : EL Size ocument Number Rev lock iagram Tuesday, January 0, 00 ate: Sheet of

3 V L K0HS00_ LK_V LK_V L K0HS00_ V U/.V_ 0.U_ 0.U_ 0.U_ *0.U_ 0.U_ 0.U_ 0.U_ 0.U_ 0 0.U_ 0U_00 Put ecoupling aps close to lock Gen. power pin V L K0HS00_ LK_V_US LK_V U V L LK_V R 0K_ K0HS00_ 0u/.V_ 0u/.V_ 0.U_ 0.U_ P_ Y.MHZ LK_V_REF P_ R *M_ Parallel Resonance rystal LK_XIN LK_XOUT 0 VPU V_SR V_SR V_SR V_SR V_ V_TIG V_REF VHTT GN_PU GN_SR GN_SR GN_SR GN_SR GN_ GN_TIG GN_REF GNHTT XIN XOUT RESET_IN# N V 0 GN PULKT0 PULK0 PULKT PULK SRLKT SRLK TIGLKT0 TIGLK0 0 TIGLKT TIGLK TIGLKT TIGLK TIGLKT 0 TIGLK SRLKT SRLK SRLKT 0 SRLK SRLKT SRLK SRLKT SRLK SRLKT0 SRLK0 SRLKT SRLK SRLKT SRLK LK_V PULK_EXT_R PULK#_EXT_R SLINK_LKP_R SLINK_LKN_R NSR_LKP_R NSR_LKN_R SSR_LKP_R SSR_LKN_R GPP_LK0P_R GPP_LK0N_R GPP_LKP_R GPP_LKN_R GPP_LKP_R GPP_LKN_R RP RP RP RP RP RP R R./F_./F_ X X X X X X R /F_ PULKP PULKN SLINK_LKP 0 SLINK_LKN 0 NSR_LKP 0 NSR_LKN 0 LK_PIE_WLN LK_PIE_WLN# LK_PIE_LN LK_PIE_LN# SSRLKP SSRLKN PE0LK+ PE0LK- 00MHZ 00MHZ 00MHZ, SLK0, ST0 *0.U_ *0.U_ Ioh = * Iref (.m) Voh = 0 ohm R /F_ 0 SMLK SMT IREF LKREQ# LKREQ# LKREQ# MHz_ MHz_0 FS/REF FS0/REF0 FS/REF HTTLK0 LK_M R R //F_ USLK MHZ R./F_ R./F_ R0./F_ R./F_ R./F_ R./F_ R./F_ R./F_ R./F_ R0./F_ R./F_ R./F_ IS LKREQ# ONTROL SR,, LKREQ# ONTROL SR,, TIG LKREQ# ONTROL SR0, TIG0,, LK_V R R 0K_ 0K_ R 0K_ EXT LK FREQUENY SELET TLE(MHZ) FS FS FS0 PU SRLK [:] HTT PI US OMMENT Hi-Z Hi-Z Hi-Z.00 Reserved 0 0 X X/ X/.00 Reserved Reserved Reserved Reserved Reserved Normal operation S_OSIN_R R _ N_OSIN_R R _ HTREFLK_R R0 _ R./F- R *0_ R *0_ R *0_ S_OSIN N_OS 0 HTREFLK 0 MHZ MHZ Quanta omputer Inc. Size ocument Number Rev lock Generator PROJET : enq ate: Tuesday, January 0, 00 Sheet of

4 LYOUT NOTE: VLT must be routed as a pour or a trace at least 00 mils wide. VLT may be routed from the source to either Lx balls or Fx balls. hoose whichever makes routing simpler. V. VLT_RUN L VLT_RUN *FJHS00_0 L L L L U VLT_ VLT_ VLT_ VLT_ VLT_ VLT_ VLT_ VLT_ F F F F 0.U_ L *FJHS00_0 VLT_RUN HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN0_P HT_IN0_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN0_P HT_IN0_N HT_LKIN_P HT_LKIN_N HT_LKIN0_P HT_LKIN0_N R _ R _ HT_TLIN_P HT_TLIN_N Y Y W W U U R R M M L L J J H H T T T T P P P P M M K K K K H H P P M M P P L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H0 L0_IN_L0 L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H0 L0_IN_L0 HT LINK L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H0 L0_OUT_L0 L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H0 L0_OUT_L0 L0_LKIN_H L0_LKOUT_H L0_LKIN_L L0_LKOUT_L L0_LKIN_H0 L0_LKOUT_H0 L0_LKIN_L0 L0_LKOUT_L0 L0_TLIN_H L0_TLOUT_H L0_TLIN_L L0_TLOUT_L Y Y E E E E H H K K K K Y Y Y Y F F F F H H F F HT_PU_TLOUT_P HT_PU_TLOUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT0_P HT_OUT0_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT0_P HT_OUT0_N HT_LKOUT_P HT_LKOUT_N HT_LKOUT0_P HT_LKOUT0_N T T VLT_ON PQ TEU--F VPU VLT_RUN PR 00K_ VLTONG PQ MEN00E VLT_RUN.u/.V_ PR R.u/.V_ PR *K PQ MEN00E VPU PR M VLT.u/.V_ V..u/.V_ P *00p/0V/XR PQ 0P_NPO_ O 0P_NPO_ VLT_RUN VLT HT_TLIN0_P HT_TLIN0_N V V L0_TLIN_H0 L0_TLIN_L0 L0_TLOUT_H0 L0_TLOUT_L0 V V HT_TLOUT0_P HT_TLOUT0_N PU_EG alls Size ocument Number Rev HT LINK Quanta omputer Inc. PROJET : ENQ ate: Tuesday, January 0, 00 Sheet of

5 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M0 MEM_M_M MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_0 MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_0 M_ZP M_ZN PU_M_VREF PU_M_VREF.VSUS.VSUS SMR_VTERM SMR_VTERM MEM_M_QS_P MEM_M_QS_N MEM_M_QS_P MEM_M_QS_N MEM_M_QS_N MEM_M_QS_P MEM_M_QS_N MEM_M_QS_P MEM_M_QS_N MEM_M_QS_P MEM_M_QS_N MEM_M_QS_P MEM_M_QS_N MEM_M_QS0_P MEM_M_QS0_N MEM_M_T[..0] MEM_M_M[..0] M_OT0 M S# M S# M S#0 M RS# M S# M WE# M_KE0 M S#0 M S# MEM_M_[..0] MEM_M_QS_P M_OT M_KE PU_VTT_SUS_SENSE M_LKOUT M_LKOUT# M_LKOUT0 M_LKOUT0# Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R Tuesday, January 0, 00 ENQ Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R Tuesday, January 0, 00 ENQ Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R Tuesday, January 0, 00 ENQ PLE THEM LOSE TO PU WITHIN " Processor R Memory Interface to power block LYOUT NOTE: ecoupling between PU and IMM. Place close to PU as possible..u_.u_.u_.u_ 0.0U_ 0.0U_ 0P_ 0P_ 0P_ 0P_ 0P_ 0P_ 0.U_ 0.U_ R.F_ R.F_ R.F_ R.F_ 0.U_ 0.U_ 0.U_ 0.U_ 0P_ 0P_ 0.U_ 0.U_ 0.U_ 0.U_ 000P_ 000P_.U_.U_ R: M/TRL/LK U PU_EG alls R: M/TRL/LK U PU_EG alls VTT VTT VTT VTT VTT K0 VTT N0 VTT L0 VTT M0 VTT M0_LK_L0 Y M0_LK_L F M0_LK_L J M0_LK_H0 Y M0_LK_H M0_LK_H K M_LK_H H M_LK_L G M_LK_H E0 M_LK_L E M_LK_H0 M_LK_L0 M_0 M_ W M_ M_ Y0 M_ U M_ V0 M_ U M_ R M_ R M_ P M_0 M_ T0 M_ P M_ G M_ M M_ P0 M_NK R M_NK M_NK0 E M_RS_L M_S_L F0 M_WE_L E RSV0 N RSV0 M RSV0 RSV0 RSV0 RSV RSV N RSV M RSV RSV RSV RSV RSV H RSV H RSV0 P RSV P RSV J RSV T RSV T RSV RSV T RSV V RSV U RSV0 V RSV V RSV W RSV Y RSV Y RSV Y RSV RSV R RSV RSV E RSV0 F RSV H M_OT0 F M0_OT0 G RSV G MEMVREF VTT_SENSE 0 MEMZN G MEMZP H M_S_L H M_S_L0 E M0_S_L H0 M0_S_L0 F RSV00 K RSV0 F RSV0 J RSV0 F RSV0 N RSV0 P M_KE M0 M_KE0 M 0.0U_ 0.0U_ 0.0U_ 0.0U_ R: T U PU_EG alls R: T U PU_EG alls M_T0 F M_T E M_T E M_T E M_T H M_T G M_T H M_T H M_T E M_T M_T0 F M_T 0 M_T F M_T G M_T G0 M_T G M_T G M_T M_T G M_T F M_T0 E M_T H M_T M_T H M_T H M_T F M_T E M_T F0 M_T E M_T M_T0 G M_T M_T J M_T J M_T G M_T J M_T K0 M_T H M_T F M_T F M_T0 G M_T J M_T F0 M_T F M_T K M_T F M_T J0 M_T G0 M_T G M_T F M_T0 G M_T F M_T K0 M_T H M_T F M_T K M_T H M_T G M_T F M_T F M_T0 J M_T J M_T H M_T G M_HEK0 H M_HEK H M_HEK L M_HEK L M_HEK F M_HEK G M_HEK J M_HEK K0 M_M0 G M_M H M_M E M_M E M_M J M_M K M_M K M_M L M_M H0 M_QS_L0 F M_QS_L H M_QS_L F M_QS_L F M_QS_L H M_QS_L G M_QS_L H M_QS_L K M_QS_H0 E M_QS_H G M_QS_H E M_QS_H E M_QS_H G M_QS_H H M_QS_H G M_QS_H J RSV N RSV L RSV L RSV N RSV N RSV M RSV M RSV N RSV L RSV0 N RSV M RSV N RSV M RSV N RSV L RSV N RSV M RSV L RSV N RSV0 L RSV L RSV N RSV N RSV M RSV M RSV L0 RSV L RSV L RSV K RSV0 N RSV M RSV M RSV E RSV RSV RSV RSV F RSV F RSV RSV0 RSV 0 RSV RSV RSV RSV 0 RSV 0 RSV RSV RSV RSV0 RSV RSV RSV RSV RSV 0 RSV RSV RSV RSV RSV0 RSV RSV RSV RSV RSV K RSV K RSV G RSV F RSV L RSV0 K RSV H RSV G RSV H RSV N RSV N0 RSV K RSV N RSV RSV RSV0 0 RSV RSV J RSV H RSV M RSV N RSV L0 RSV M0 RSV N RSV M RSV0 N0 RSV M0 RSV RSV RSV RSV RSV RSV 0 RSV RSV M_QS_H J M_QS_L J 0 0.U_ 0 0.U_ R 00/F_ R 00/F_ R 00/F_ R 00/F_ 0.0U_ 0.0U_

6 HT onnector.vsus R 0_ R 0_ R 0_ LT_RST#.VSUS R 0_ PU_SI PU_SI R 00_ PU_REQ# PU_RY PU_TK PU_TMS PU_TI PU_TRST# PU_TO.VSUS.VSUS R 0K_ Q *MMT0 V H_HTPU_RST# If M SI is not used, the SI pin can be left unconnected and SI should have a 00-Ω (±%) pulldown to VSS. R 00_ R *00_ N *SP-00-0-P-LV GN GN RSV GN RSV0 GN REQ_L GN RY GN0 0 TK GN TMS GN TI GN TRST_L GN TO GN0 0 V_PRO_IO_ GN V_PRO_IO_ RESET_L KEY GN R K/F_ 00_ R PU_SI_R PU_SI_R PU_V L 0ohm_00m V_RUN LT_RST# PU_PWRG 0, PU_LTSTOP# To power lock PU_ORE OREEF+V OREEF- PU_VIO_SUS_F_H PULKP PULKN.U_00 0.U close to PU *0/F_ *0/F_ 00p_ 00p_ 00pF PR PR R _ VLT_RUN.VSUS R R0 PU_SI_R PU_SI_R._ PU_HTREF._ PU_HTREF0 PU_VIO_SUS_F_H PU_VIO_SUS_F_L PU_LKIN_S_P PU_LKIN_S_N PU_RY PU_TMS PU_TK PU_TRST# PU_TI PU_TEST_H_YPSSLK_P PU_TEST_L_YPSSLK_N PU_TEST_PLLTEST0 PU_TEST_PLLTEST T T0 T T T T R 00_ PU_TEST_P PU_TEST_P PU_TEST_P PU_TEST_P0 PU_TEST_SNSHIFTEN H_THERM H_THERM K M M N N V0 V E E M K H N K L M J H J H N H L M J J U V V RESET_L PWROK LTSTOP_L SI SI HT_REF HT_REF0 V_F_H V_F_L VIO_F_H VIO_F_L LKIN_H LKIN_L RY TMS TK TRST_L TI TEST_H TEST_L TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST THERM THERM TEST TEST THERMTRIP_L PROHOT_L VI VI VI VI VI VI0 PU_PRESENT_L PSI_L REQ_L TO TEST_H TEST_L TEST TEST TEST TEST TEST0 TEST_H TEST_L TEST TEST TEST0 TEST J PU_THERMTRIP# N PU_PROHOT#_PV M PU_PRESENT# R E N N E 0 H G N F M G H J M PU_REQ# T PU_TO PU_TEST_H_FLKOUT_P PU_TEST_L_FLKOUT_N PU_TEST_SNLK PU_TEST_TSTUP PU_TEST_SNSHIFTEN PU_TEST_SNEN PU_TEST0_SNLK PU_TEST.VSUS R00 K_ R K_ R K_ R K_ R K_ R K_ K_ PSI#.VSUS.VSUS R 0K_ MMT0 Q V VI VI VI VI VI VI0 To power lock R T T T T R0 *00_ R 00_ R 00_ 0./F_ R.K PU_TEST PU_TEST_PLLTEST PU_TEST_PLLTEST0 PU_TEST_SNEN THERMTRIP#, To power lock R 00_.VSUS R 00_ R R0 00_ 00_ 0, SYS_SHN# V 0 0.U_ 00P_ THERM_V H_THERM H_THERM SYS_SHN# GN Vout =.(+R/R) =. (+00K/00K) =.V U V XP XN -OVT PU SHN VO SET G-0TUF P u/.v_ G- MSOP-_- PR 00K/F_ R SMUS dd. : h SMLK PR 00K/F_ *0.U SMT -LT GN + 0R_ 0 00U/0V V TLERT# Thermal Senser PU_V P u/.v_ TLERT# 0, SMUS SLVE RESS G G- THMLK 0 THMT 0 (N) (PU) V.VSUS R.K R 0K_ PU_PROHOT#_PV MMT0 Q V R.K TLERT_# M L M M W W J P M J0 RSV RSV RSV PU_EG alls RSV RSV RSV RSV RSV0 RSV RSV MIS RSV L RSV RSV G RSV 0 RSV E RSV G RSV RSV0 V V V G RSV 0 RSV RSV K RSV 0 RSV K RSV R R PU_TEST_H_YPSSLK_P PU_TEST_L_YPSSLK_N *0K_ THMT *0K_ THMLK R0 0_ Q *N00E-LF MT MLK *N00E-LF Q R 0_.VSUS MT MLK Quanta omputer Inc. Size ocument Number Rev MIS R R 0/F_ 0/F_ PROJET : ENQ ate: Tuesday, January 0, 00 Sheet of

7 PU_ORE PU_ORE.VSUS PU_ORE PU_ORE.VSUS.VSUS Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : PU Power and GN Tuesday, January 0, 00 ENQ Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : PU Power and GN Tuesday, January 0, 00 ENQ Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : PU Power and GN Tuesday, January 0, 00 ENQ LYOUT NOTE: ottom side decoupling. 0.U_ 0.U_ 0.U_ 0.U_ 0 0.0U_ 0 0.0U_ GN UG PU_EG alls GN UG PU_EG alls VSS J VSS J VSS J VSS J VSS J VSS J VSS K VSS K VSS K VSS0 K VSS K VSS K VSS K VSS K VSS K VSS K VSS K VSS K VSS L VSS0 M VSS M VSS M VSS M VSS M VSS M VSS M VSS M VSS M VSS N VSS0 N VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS00 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS VSS 0 VSS E0 VSS E VSS F VSS F0 VSS F VSS G VSS G VSS0 G VSS VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS 0 VSS VSS VSS 0 VSS0 VSS VSS VSS E VSS E VSS E VSS E VSS E0 VSS E VSS E VSS0 E VSS E0 VSS E VSS E VSS E VSS F VSS F VSS F VSS F VSS G VSS0 G VSS G VSS G VSS G VSS G VSS H VSS H VSS H0 VSS H VSS H VSS0 H 0 0.U_ 0 0.U_ 0 U/.V_ 0 U/.V_ U/.V_ U/.V_ 0P_ 0P_ 0.0U_ 0.0U_ U/.V_ U/.V_ U/.V_ U/.V_.U_.U_ U/.V_ U/.V_ 0P_ 0P_ 0 0P_ 0 0P_ 0.0U_ 0.0U_ GN UH PU_EG alls GN UH PU_EG alls VSS R VSS R VSS R VSS R VSS R VSS R VSS0 R0 VSS T VSS T VSS T VSS T VSS T VSS T VSS V VSS V VSS V0 VSS00 U VSS0 U VSS0 U VSS0 U VSS0 U VSS0 W VSS0 W VSS0 W VSS0 W VSS0 W VSS0 W VSS W VSS Y VSS Y0 VSS Y VSS Y VSS Y0 VSS Y VSS Y VSS F VSS0 VSS G VSS VSS VSS G VSS G VSS G VSS G0 VSS H VSS H VSS H0 VSS H VSS0 H VSS J VSS J VSS J VSS J VSS J VSS J VSS J VSS J VSS J VSS0 J VSS J VSS J0 VSS J VSS K VSS K VSS K VSS VSS K VSS K VSS0 K VSS L VSS L VSS L VSS L VSS L0 VSS L VSS L VSS L VSS L VSS0 L VSS L VSS L VSS L0 VSS M VSS M VSS M VSS M VSS M VSS M VSS0 M VSS M VSS N VSS N VSS N VSS N0 VSS N VSS N VSS N VSS P VSS0 P0 VSS P VSS P VSS P 0P_ 0P_ POWER UE PU_EG alls POWER UE PU_EG alls V# V# V# V# V# V# V# V# V# V#E E V#E E V#E E V#F F V#F F V#F F V#F F V#G G V#G G V#H H V#J J V#J0 J0 V#J J V#J J V#J J V#J0 J0 V#J J V#J J V#K0 K0 V#K K V#K K V#K K V#K0 K0 V#K K V#K K V#K K V#L L V#L L V#L L V#L L V#M M V#M0 M0 V#M M V#M M V#N N V#N N V#N N V#N N V#P P V#P P V#P0 P0 V#P P V#P P V#0 0 V# V# V# V# V# V# V#0 0 V# V# V# V# V# V# V# V# V# V# V#E E V#E E V#E E V#E E V#E E V#V V V#V V V#Y Y V#Y Y V#Y Y V#W0 W0 V#W W V#W W V#W W V#V V V#V V V#V V V#T0 T0 V#T T V#T T V#T0 T0 V#R R V#R R V#R R V#R R 0.U_ 0.U_ U/.V_ U/.V_ U/.V_ U/.V_ 0 0.U_ 0 0.U_ U/.V_ U/.V_.U_.U_.U_.U_ 0.U_ 0.U_ 0.U_ 0.U_ U/.V_ U/.V_ U/.V_ U/.V_ 0.U_ 0.U_ POWER UF PU_EG alls POWER UF PU_EG alls VIO#Y Y VIO#U U VIO#R R VIO#P P VIO#W W VIO#W0 W0 VIO#W W VIO#U0 U0 VIO#N0 N0 VIO#U U VIO#R R VIO#R0 R0 VIO#N N VIO#U U VIO#Y Y VIO#M M VIO#G G VIO#G0 G0 VIO#F F VIO#E0 E0 VIO#E E VIO# VIO#0 0 VIO#E E VIO# VIO#0 0.U_.U_ U/.V_ U/.V_

8 HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT0_P HT_OUT0_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N R R R R U U U U W W0 0 0 Y U HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RX0P HT_RX0N HT_RXP HT_RXN HT_RXP HT_RXN PRT OF HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TX0P HT_TX0N HT_TXP HT_TXN HT_TXP HT_TXN P P P P M M M M L L G G J0 J F F HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN0_P HT_IN0_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N RS0 HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT0_P HT_OUT0_N HT_LKOUT_P HT_LKOUT_N HT_LKOUT0_P HT_LKOUT0_N HT_TLOUT0_P HT_TLOUT0_N T R U U V U V V W W Y W P P HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RX0P HT_RX0N HT_RXLKP HT_RXLKN HT_RXLK0P HT_RXLK0N HT_RXTLP HT_RXTLN HYPER TRNSPORT PU I/F HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TX0P HT_TX0N HT_TXLKP HT_TXLKN HT_TXLK0P HT_TXLK0N HT_TXTLP HT_TXTLN HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN0_P HT_IN0_N HT_LKIN_P HT_LKIN_N HT_LKIN0_P HT_LKIN0_N HT_TLIN0_P HT_TLIN0_N R./F_ HT_RXLP HT_TXLP HT_RXLN HT_RXLP HT_TXLP R 00F_ R./F_ HT_TXLN HT_RXLN HT_TXLN N N L M K K J K G H F F E F E E L L J J N P RS0E Quanta omputer Inc. Size ocument Number Rev RS0E HT PROJET : ENQ ate: Tuesday, January 0, 00 Sheet of

9 LINK SOUTH RIGE LINK _PETX+ _PETX- _RXP _RXN _RXP _RXN PERX+ PERX- GPP_RXP_LN GPP_RXN_LN GPP_RX0P_LN GPP_RX0N_LN GPP_RXP_R GPP_RXN_R SOUTH RIGE LINK _RX0P _RX0N _RXP _RXN LINK G G J J J J L L L L M M M M P P Y Y W W P P R R R R U U V W U GFX_RX0P GFX_RX0N GFX_RXP GFX_RXN GFX_RXP GFX_RXN GFX_RXP GFX_RXN GFX_RXP GFX_RXN GFX_RXP GFX_RXN GFX_RXP GFX_RXN GFX_RXP GFX_RXN S_RXP(GPP_RX0P) S_RXN(GPP_RX0N) S_RXP(GPP_RXP) S_RXN(GPP_RXN) GPP_RXP GPP_RXN GPP_RXP GPP_RXN PRT OF PIE I/F GFX PIE I/F GPP PIE I/F S GFX_TX0P GFX_TX0N GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN S_TXP(GPP_TX0P) S_TXN(GPP_TX0N) S_TXP(GPP_TXP) S_TXN(GPP_TXN) GPP_TXP GPP_TXN GPP_TXP GPP_TXN GPP_RX0P(N) GPP_TX0P(N) GPP_RX0N(N) GPP_TX0N(N) GPP_RXP(N) GPP_RXN(N) S_RX0P S_RX0N S_RXP S_RXN GPP_TXP(N) GPP_TXN(N) S_TX0P S_TX0N S_TXP S_TXN J H K K K L L L N N P P P R R R Y Y U U V V V W W W close to connector. _TXP TXN TXP TXN_ GPP_TXP GPP_TXN GPP_TX0P GPP_TX0N GPP_TXP 0 GPP_TXN _TX0P TX0N TXP TXN_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ *0.u/0V_ *0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ PIE 0 Ethernet PIE ard Reader PIE MINI ard _TXP _TXN _TXP _TXN PETX+ PETX- GPP_TX0P_LN GPP_TX0N_LN GPP_TXP_R GPP_TXN_R _TX0P _TX0N _TXP _TXN LINK SOUTH RIGE LINK MINI-ard Wireless lan Ethernet RTL0EL ard Reader JM LINK SOUTH RIGE LINK R0 R *0K/F_ *.K/F_ N(PE_ISET) N(PE_TXISET) PE_LRP(PE_PL) PE_LRN(PE_NL) E E R R /F_.0K/F_ V_PKG RS0E Quanta omputer Inc. Size ocument Number Rev RS0E PIE PROJET : ENQ ate: Tuesday, January 0, 00 Sheet of

10 V. V. V L FMH0HM-T_ L FMH0HM-T_ L FMH0HM-T_, PU_LTSTOP# V. VQ.uF/0V_ PLLV.uF/0V_ HTPV 00 u/0v_ L FMH0HM-T_ V. R R 0K_ Q MMT0 *0_ PLLVP V R 0K_ RT_RE RT_GRN RT_LU RT_VSYN RT_HSYN N LTSTOP V. L V L0 FMH0HM-T_ FMH0HM-T 0 RTLK RTT,0,,, N_RST#, N_PWRG LLOW_LTSTOP L FMH0HM-T_ 0 HTREFLK SUS_STT# N_OS NSR_LKP NSR_LKN.uF/0V_ u/0v_.u/0v_.uf/0v_ R VQ V_N R R -SLR _ T_SR _ PLLV 0 0 PLLVP HTPV N LTSTOP R0 R /F_ 0K_ *.K_ U G H E F G E F F G 0 F E V V VSSN VSSN VI VSSI VQ VSSQ _R Y_G OMP_ RE GREEN LUE VSYN HSYN RSET SL S PLLV PLLVSS HTPV HTPVSS PRT OF RT/TVOUT SYSRESET# POWERGOO LTSTOP# LLOW_LTSTOP HTTSTLK HTREFLK TVLKIN PLL PWR VPLL_(V) VPLL_(V) VSSPLL_(VSS) VSSPLL_(VSS) PM OSIN PLLV(OSOUT) GFX_LKP GFX_LKN LOKs LVS TXOUT_L0P TXOUT_L0N TXOUT_LP TXOUT_LN TXOUT_LP TXOUT_LN TXOUT_LP TXOUT_LN TXOUT_U0P TXOUT_U0N TXOUT_UP TXOUT_UN TXOUT_UP TXOUT_UN TXOUT_UP TXOUT_UN TXLK_LP TXLK_LN TXLK_UP TXLK_UN LPV LPVSS LVR_ LVR_ LVR_(LVR_) LVR_(LVR_) LVSSR LVSSR LVSSR LVSSR LVSSR LVSSR LVSSR LVSSR LVS_IGON LVS_LON LVS_LEN H G E E H G E F F E G F LPV L FMH0HM-T_ LVRP LVRP LVS_TX0+ LVS_TX0- LVS_TX+ LVS_TX- LVS_TX+ LVS_TX- LVS_TX+ LVS_TX- LVS_TX+ LVS_TX- LVS_TX+ LVS_TX- LVS_TX+ LVS_TX- LVS_TX+ LVS_TX- LVS_LK_L+ LVS_LK_L- LVS_LK_U+ LVS_LK_U- L LVS IGON LVS LON LVS LEN V. V FMH0HM-T_ L FMH0HM-T_ 0 0.u/0V_ 0.uF/0V_ 0 0.u/0V_ 0 LVRP 0.uF/0V_ LPV 0.u/0V_ ESIGN NOTE:THE FOLLOWING EUG POINTS SHOUL E PROVIE. STRP T T V R R R R00.K_.K_ K_ 0K_ 0.uF/0V LK _T N T STRP T SLINK_LKP SLINK_LKN MREQ# _LK _T T T N_THERM N_THERM R TMS_HP N T.K_ TESTMOE STRP T G G E S_LKP S_LKN MREQb I_LK I_T THERMLIOE_P THERMLIOE_N TMS_HP _T TESTMOE STRP_T MIS FT_GPIO0 FT_GPIO FT_GPIO FT_GPIO FT_GPIO FT_GPIO EF GPIO0 LO ROM# EF GPIO EF GPIO EF GPIO EF GPIO N_OS N_PWRG EF GPIO0 LO ROM# EF GPIO EF GPIO EF GPIO EF GPIO T T0 T T T T T T RS0E Thermal Senser R0 0R_ V 0 0.U 0 *0.U U SMUS dd. : h THERM_N_V V SMLK 00P_00 N_THERM XP SMT N_THERM XN -LT, SYS_SHN# -OVT GN G MSOP-_- TLERT#, THMLK THMT SMUS SLVE RESS G (N) G- (PU) Size ocument Number Rev RS0E MSI Quanta omputer Inc. PROJET : ENQ ate: Tuesday, January 0, 00 Sheet 0 of

11 ESIGN NOTE:THE FOLLOWING EUG POINTS SHOUL E PROVIE. T T T T0 T T T T0 T T T T T T T T V. R0 K/F_ MEM_VREF R0 K/F_ MEM_0 MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ MEM_0 MEM_ MEM_ MEM_ MEM_0 MEM_ 0.u/0V_ W 0 W E E0 Y E Y V Y W V E 0 UF PR OF MEM_0(N) MEM_(N) MEM_(N) MEM_(N) MEM_(N) MEM_(N) MEM_(N) MEM_(N) MEM_(N) MEM_(N) MEM_0(N) MEM_(N) MEM_(N) MEM_(N) MEM_0(N) MEM_(N) MEM_(N) MEM_RSb(N) MEM_Sb(N) MEM_WEb(N) MEM_Sb(N) MEM_KE(N) MEM_OT(N) MEM_KP(N) MEM_KN(N) S_MEM/VO_I/F MEM_M0(N) MEM_M/VO_(VO_) MEM_QS0P/VO_IKP(VO_IKP) MEM_QS0N/VO_IKN(VO_IKN) MEM_QSP(N) MEM_QSN(N) MEM_Q0/VO_VSYN(VO_VSYN) MEM_Q/VO_HSYN(VO_HSYN) MEM_Q/VO_E(VO_E) MEM_Q/VO_0(VO_0) MEM_Q(N) MEM_Q/VO_(VO_) MEM_Q/VO_(VO_) MEM_Q/VO_(VO_) MEM_Q/VO_(VO_) MEM_Q/VO_(VO_) MEM_Q0/VO_(VO_) MEM_Q/VO_(VO_) MEM_Q(N) MEM_Q/VO_(VO_) MEM_Q/VO_0(VO_0) MEM_Q/VO_(VO_) MEM_OMPP(N) MEM_OMPN(N) MEM_VREF(N) IOPLLV(N) IOPLLVSS(N) IOPLLV(N) E E E E E0 0 E Y W E Y.uF/0V_.uF/0V_ R0 0R/F_ R0 0R/F_ MEM_VREF IOPLLV IOPLLV L IOPLLV IOPLLV V. L FMH0HM-T FMH0HM-T V. RS0E Quanta omputer Inc. Size ocument Number Rev RS0E PIE PROJET : ENQ ate: Tuesday, January 0, 00 Sheet of

12 V. V. V. V. 0 u/0v_ u/0v_ L FMH0HM-T_ 0 u/0v_ u/0v_ V. u/0v_ u/0v_ L0 FMH0HM-T V. 0 u/0v_ u/0v_ L FMH0HM-T_ u/0v_ u/0v_ 0 u/0v_ u/0v_ u/0v_ UE PR OF VSS F VSS VSS E VSS G VSS Y VSS P VSS R VSS VSS M VSS0 J VSS G VSS J VSS L VSS L VSS L0 VSS L VSS M VSS M0 VSS M VSS0 M VSS N VSS N VSS VSS L VSS P VSS P0 VSS P VSS R VSS R VSS0 R0 VSS W VSS Y VSS VSS U0 VSS H VSS W VSS Y VSS VSS VSS0 G VSS VSS H VSS VSS R VSS VSS Y VSS T VSS T VSS V VSS0 R VSS H VSS GROUN u/0v_ u/0v_ 0u/0V_ 0u/0V_ RS0 V. V. V. u/0v_ 0u/0V_ 0u/0V_ VVO u/0v_ 0u/0V_ 0u/0V_ VSS M VSS P VSS G VSS E VSS F VSS VSS VSS H VSS G VSS0 J VSS H VSS VSS J VSS Y VSS F VSS L VSS M VSS M VSS J VSS0 P VSS T VSS N VSS R VSS R VSS T VSS T VSS U VSS U VSS W VSS0 Y VSS VSS 0 VSS V VSS W VSS VSS E VSS0 E VSS M VSS VSS VSS VSS F VSS VSS VSS VSS M U E V_HT PRT OF V_ V_HT V_ E V_HT V_ E V_HT V_ V_HT V_ E V_HT V_ V_HT V_ V_ V_ VHT_PKG V_0 V_ J V_ V_ J V_ V_PKG V_PKG E VR_ VR_ V_ V_ V_ V_(V_) V_ V_(V_) V_ U V_(V_) V_ W V_(V_) V_ V_(V_) V_ V_(V_) V_ V_(V_) V_0 E V_0(V_) V_ V_ V_MEM(V_VO) V_ V_MEM(V_VO) V_ V_MEM(V_VO) V_ V_MEM(V_VO) V_ V_MEM(V_VO) V_ V_MEM(V_VO) V_ E V_MEM(V_VO) V_ E V_MEM(V_VO) V_0 E V_MEM(V_VO) V_ V_MEM0(V_VO0) V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ RS0E FN,0 SYS_SHN# POWER VFN V, THERMTRIP#.u/.V_ U VO GN FON# GN GN VSET GN G 0, N_PWRG V. G E E M F L E M L L L M R M N N N J H P P R R U U P L J 0 G0 U U R0 0u/0V_ FNSIG 0 MIL TH_FN_POWER u/0v_ V. *_ Q R_THERMTRIP_PWR# R _ MMT0 V L FMH0HM-T_ V. Q V_PKG V N00E R0 0K_ u/0v_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_.u/.V_ u/0v_ 0u/0V_ 0u/0V_ 000p/0V_ R0 K_ u/0v_ N 0.0u/V_ FN V. SYS_SHN# u/0v_ 0u/0V_ 0u/0V_.uF/0V_ V. 0.u/0V_ 0.u/0V_ egree Protection RS0E Quanta omputer Inc. PROJET : ENQ Size ocument Number Rev RS0E Power F&G / FN ate: Tuesday, January 0, 00 Sheet of

13 .VSUS V.VSUS MEM_M_[..0] MEM_M_T[..0] S_ : 00 MEM_M_M[..0] M S#0 M S# M S# MEM_M_QS0_P MEM_M_QS_P MEM_M_QS_P MEM_M_QS_P MEM_M_QS_P MEM_M_QS_P MEM_M_QS_P MEM_M_QS_P MEM_M_QS0_N MEM_M_QS_N MEM_M_QS_N MEM_M_QS_N MEM_M_QS_N MEM_M_QS_N MEM_M_QS_N MEM_M_QS_N M_LKOUT0 M_LKOUT0# M_LKOUT M_LKOUT# M_KE0 M_KE M RS# M S# M WE# M S#0 M S# M_OT0 M_OT, ST0, SLK0.U_00 0.U_ M_LKOUT0.P_ M_LKOUT0# M_LKOUT.P_ M_LKOUT# MEM_M_M0 MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_0 0 MEM_M_ 0 0 MEM_M_ 00 MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_0 0 MEM_M_ 0 0 MEM_M_ MEM_M_ MEM_M_ MEM_M_ S0_ S_ 0.U_ MVREF_IM M0 M M M 0 M M 0 M M MEM_M_QS0_P MEM_M_QS_P QS0 MEM_M_QS_P QS MEM_M_QS_P QS 0 MEM_M_QS_P QS MEM_M_QS_P QS MEM_M_QS_P QS MEM_M_QS_P QS QS MEM_M_QS0_N MEM_M_QS_N QS0 MEM_M_QS_N QS MEM_M_QS_N QS MEM_M_QS_N QS MEM_M_QS_N QS MEM_M_QS_N QS MEM_M_QS_N QS QS M_LKOUT0 0 M_LKOUT0# K0 M_LKOUT K0 M_LKOUT# K K 0.U_ KE0 0 KE 0 RS S 0 WE 0 S0 S OT0 OT S0 00 S S SL Vspd VREF VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS 0 VSS VSS VSS VSS VSS VSS VSS0 0 0 V0 V V V V V V V V V V0 V N SO-IMM (H=) ST VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS 0 Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q 0 Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q 0 Q Q Q Q Q Q0 Q Q Q 0 Q Q Q Q Q Q Q0 0 Q Q Q N 0 N N N 0 N/TEST VSS VSS VSS 0 VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 0 VSS VSS VSS VSS VSS VSS RII_SOIMM_R MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T SMR_VREF SMR_VTERM R *0_ MVREF_IM U_.VSUS.VSUS R K/F_ R K/F_ 0 0.U_ 0.U_ 0.U_ 0.U_ 0.U_ 0.U_ 0.U_ 0.U_ 0.U_ *0.U_ *0.U_ 0.U_ 0.U_ 0.U_ 0.U_ 0.U_ *0.U_ 0.U_ 0.U_ V SMR_VTERM 0.U_ 0.U_ 0.U_ 0.U_ 0.U_ 0.U_ 0.U_ 0.U_ 0.U_ *0U_00 *0U_00 R R M_KE0 M_KE M_OT0 M_OT M S#0 M S# M S# M WE# M S# M RS# M S#0 M S# MEM_M_[..0], ST0, SLK0 *.K_S0_ *.K_S_ MEM_M_0 MEM_M_ MEM_M_ MEM_M_ MEM_M_0 MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_.This part should not contain any substances which are specified in SS-00-.Purchase ink, paint, wire rods and molding resins only from the business partners that Sony approves as Green Partners. 0_ R 0_ R V R 0_ V R0 0_ Q0 *N00E R _ R _ R _ R _ R _ R _ R _ R _ R0 _ R _ R _ R _ R _ R _ RP 00-X RP 00-X RP 00-X RP0 00-X RP 00-X RP 00-X RP 00-X Q *N00E RP *.K_PR MEM_SMT MEM_SMLK SMR_VTERM.VSUS.VSUS MEM_SMT MEM_SMLK 0 For EMI VSUS VSUS Quanta omputer Inc. Size ocument Number Rev RII SOIMM x *0U 0U_00 0U_00 0.U_ 0.U_ 0.U_ 0.U_ 0.U_ 0.U_ 0.U_ 0.U_ 0.U_ PROJET : ENQ ate: Tuesday, January 0, 00 Sheet of *0U *0.U_ *0.U_ *0.U_ *0.U_

14 , LP_RST# LINK_RST# R _ PILK0_R PLK_R 0,0,,, N_RST# G0 R RST# PILK0 U PILK_R PLK_ PLK_R 0,0,,, PIE_RST# Part of R0 _ PILK T PILK_R PLK_E PLK_, 0,0,,, IERST# SSRLKP J R _ PIE_RLKP PILK U PILK_R PLK_TPM PLK_E SSRLKN J R _ PIE_RLKN PILK V PILK_R R _ PILK PLK_TPM PLK_R 00MHZ 0 0.U RX0P_ PILK W PILK_R PILK PLK RX0P P R _ 0.U RX0N_ PIE_TX0P PILK U PILK_R PLK_E _RX0N P 0.U RXP_ PIE_TX0N PILK V R _ S_SPIF_R PILK _RXP M _RXN_ PIE_TXP SPIF_OUT/PILK/GPIO T T 0.U_ PILK _RXN M 0.U RXP_ PIE_TXN PIRST# RXP K 0.U RXN_ PIE_TXP PIRST# J _RXN K 0.U RXP_ PIE_TXN _RXP H [..] 0 0.U RXN_ PIE_TXP _RXN H PIE_TXN 0/ROM W /ROM Y _TX0P T PIE_RX0P /ROM W PIRST# TX0N T PIE_RX0N /ROM W _TXP T PIE_RXP /ROM _TXN T PIE_RXN /ROM Y _TXP M PIE_RXP /ROM Stuff L in -test _TXN M PIE_RXN /ROM R _TXP M PIE_RXP /ROM.K TXN M PIE_RXN /ROM PIE_PV R PIE_LRP 0/ROM E V_S PIE_LRN PIE_LRP /ROM J R.0K PIE_VR E L *LMPGSN_ PIE_LRN /ROM PIE_LI /ROM E PIE_LI /ROM E PIE_PWR /ROM L 0ohm_ U PIE_PV /ROM0 RT /ROM J U PIE Power PIE_PVSS /ROM 0U_00 U_ 0.U_ /ROM H F PIE_VR_ 0/ROM VRT V_S Stuff L0 in -test F PIE_VR_ /ROM J F L PIE_VR_ /ROM G *FM0- PIE_VR_ /ROM H G PIE_VR PIE_VR_ PIE_PWR G G PIE_VR_ H G R PIE_VR_ L J 0_ PIE_VR_ H J SHORT_P 0ohm_ PIE_VR_ L 0 G PIE_VR_0 L 0U_00 0U_00 0.U_ U_ U_ U_ U_ U_ 0 0.U_ 0.U_ PIE_VR_ L PIE_VR_ G N PIE_VR_ E0#/ROM0 0mil E#/ROM F T E#/ROMWE# J R VPU VPU V_S PIE_PWR PIE_PWR E# G PQ O0 *0_ FRME# EVSEL#/ROM0 H -00 PIEPWR_ON R R R IRY# G P-L TRY#/ROMOE# 00K_ M PR/ROM F STOP# Y PERR# G PIE_PWR_ SERR# REQ0# J VPU REQ# E *SS REQ# G REQ# T PIE_PWR_ REQ#/GPIO0 H REQ# R.K_ VRT_ R REQ#/GPIO H T Q GNT0#,,, MINON N00E-LF GNT# F GNT# H GNT# R 0K_ GNT#/GPIO T Q Q GNT#.K_ GNT#/GPIO G T0 N00E-LF N00E-LF LKRUN# G T 0.U_ PI_LOK# LOK# F T R *0M_ R Y.KHZ P_ R0 R0 R0 0M_ 0K_ R0 0_ K_X K_X P_ LT_RST# 0K_ PU_PWRG 0K_ PU_LTSTOP#,0 PU_LTSTOP# PU_SI PU_SI 0 LLOW_LTSTOP PU_PWRG LPP# LT_RST# R.K_ PU_PWR_S R K_ T T T T T T R T K_X K_X *0_ U X X S00 S00 S xmm XTL PI EXPRESS INTERFE PU_PG/LT_PG W INTR/LINT0 W NMI/LINT W INIT# SMI# SLP#/LT_STP# IGNNE#/SI 0M#/SI Y FERR# STPLK#/LLOW_LTSTP H PU_STP#/PSLP_V# PSLP_O#/GPIO W PRSLPVR LT_RST#/PRSTP#/PROHOT# PU LP PI INTERFE RT PI LKS INTE#/GPIO INTF#/GPIO F INTG#/GPIO F INTH#/GPIO F L0 G L G L H L H LFRME# F LRQ0# J LRQ#/GNT#/GPIO H MREQ#/REQ#/GPIO W SERIRQ F RTLK RT_IRQ#/GPIO F VT E RT_GN LP_RQ# R RT_LK SSM 0 U_ L0,, L,, L,, L,, LFRME#,, LP_RQ0# *0_ T0 MREQ# 0 SERIRQ,, T T0 VRT R0 K_ RT_LK SERIRQ MREQ# R R R *P_ ate: Tuesday, January 0, 00 Sheet of 0K_ *0K_ +.VLW V V PIRST# LER_MOS Quanta omputer Inc. PROJET : ENQ Size ocument Number Rev S00 PIE/PI/PU/LP Reserved For EMI *0K_ *U_ R *0_ Q MMT0 *0.U_ 0P_ 0P_ 0P_ 0P_

15 S_OSIN SLK ST THERMTRIP# GPM# S_STTE SWI# SUS_STT# NSWON# SUS# SUS# SI# SLK0 ST0 L_ON GPIO_S0 KSMI# RIN# GTE0 GPIO_S0 Z_ITLK_UIO Z_SOUT_UIO MHZ Z_SIN0 Z_SYN_UIO Z_RESET#_UIO R R R R0 R R R R R R0 R R R R R R R R R R *_.K_.K_.K_ *0K_ *0K_ *0K_ *0K_ *0K_ *.K_ *.K_ *0K_ *.K_ *0K_ *0K_ *0K_ *0K_ +.VLW V R0 _ Z_ITLK R _Z_SOUT R _ Z_SIN R.K_.K_ 0K_ *_Z_SIN0 R _ Z_SYN 0K_ *P_ R _ *0P_ Z_RST# R 0.U_ 0 GTE0 RIN# SWI# KSMI# PIE_WKE# T, THERMTRIP# PI_PME# SI# SUS# SUS# NSWON# SPWROK SUS_STT# RSMRST# S_OSIN T0 T T T L_ON 0.U_, SPKR, SLK0, ST0 SLK ST, LE SELET_, LE SELET_, LE SELET_ T T T T0 T US_OP# US_OP# US_OP# US_OP# US_OP# US_OP0# T _SOUT T T T T SI# SUS# SUS# NSWON# SUS_STT# S_TEST S_TEST S_TEST0 GTE0 RIN# SWI# KSMI# S_STTE GPM# GPM#_S GPIO0_S0 GPIO_S0 GPIO_S0 GPIO_S0 L_ON GPIO_S0 SLK0 ST0 SLK ST GPIO_S0 GPIO_S0 GPIO0_S0 GPIO_S US_OP# US_OP# US_OP# US_OP# US_OP# US_OP# US_OP# US_OP# US_OP# US_OP0# Z_ITLK Z_SOUT Z_SIN Z_SYN Z_RST# Z_SIN0 U S00 S xmm PI_PME#/GEVENT# Part of RI#/EXTEVNT0# F SLP_S# SLP_S# E PWR_TN# PWR_GOO SUS_STT# F TEST E TEST G TEST0 F G0IN G KRST# LP_PME#/GEVENT# LP_SMI#/EXTEVNT# S_STTE/GEVENT# F SYS_RESET#/GPM# E WKE#/GEVENT# LINK/GPM# G SMLERT#/THRMTRIP#/GEVENT# E RSMRST# OS / RST M_OS ST_IS0#/GPIO0 ROM_S#/GPIO GHI#/ST_IS#/GPIO W_PWRG/GPIO SMRTVOLT/ST_IS#/GPIO SHUTOWN#/GPIO SPKR/GPIO SL0/GPO0# S0/GPO# SL/GPO# F S/GPO# _SL/GPIO _S/GPIO SSMUXSEL/ST_IS#/GPIO0 LL#/GPIO ZLI US O GPIO US_O#/SLP_S/GPM# US_O#/Z_OK_RST#/GPM# US_O#/GEVENT# US_O#/GEVENT# US_O#/R_RST#/GPM# US_O#/GPM# US_O#/GPM# US_O#/GPM# US_O#/GPM# US_O0#/GPM0# N Z_ITLK M Z_SOUT K Z_SIN/GPIO L Z_SYN K Z_RST# L _ITLK/GPIO L _SOUT/GPIO L Z_SIN0/GPIO J Z_SIN/GPIO J Z_SIN/GPIO M _SYN/GPIO0 L _RST#/GPIO E N N N E N N T N N N PI / WKE UP EVENTS US INTERFE US PWR USLK US_ROMP US_TEST US_TEST0 US_HSP+ US_HSM- US_HSP+ US_HSM- US_HSP+ US_HSM- US_HSP+ US_HSM- US_HSP+ US_HSM- US_HSP+ US_HSM- US_HSP+ US_HSM- US_HSP+ US_HSM- US_HSP+ US_HSM- US_HSP0+ US_HSM0- VTX_0 VTX_ VTX_ VTX_ VTX_ VRX_0 VRX_ VRX_ VRX_ VRX_ V VSS VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_0 VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_0 VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_0 VSS_US_ VSS_US_ VSS_US_ 0 H G E E G H E E G H G H E G H E E F F F F F F F G G H H J J J J J J US_ROMP R R *_ MHZ USLK T T T T USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP0+ USP0- V_US.K/F_ *0P_ V_US 0U_00 +.V_V 0U_00 US0 US US US US US US US US RESERVE.U_00 S_TEST0 S_TEST S_TEST US power 0.U_ 0 0.U_ U_ R R R0 RER SIE US PORT RER SIE US PORT RER SIE US PORT RER SIE US PORT LEFT SIE US PORT LEFT SIE US PORT MINI R US PORT WEM US PORT touch panel module 0.U_ 0.U_ L RESERVE 0.U_ 0.U_ L FM0-0.U_ *.K_ R *0K_ *.K_ R00 *0K_ *.K_ R0 *0K_ LMPGSN_ +.VLW +.VLW S00 Quanta omputer Inc. PROJET : ENQ Size ocument Number Rev S00 PI/GPIO/US/ ate: Tuesday, January 0, 00 Sheet of

16 U From page P_ 0 P_ ST Power V L0 LMPGSN_ U V_S L LMPGSN_ ST_X Y R0 0M MHZ_ST ST_X XTLV_T U U V_S U PLLV_T 0 ST_TXP0 0 ST_TXN0 0 ST_RXN0 0 ST_RXP0 ST_LE# PLLV_T XTLV_T V_ST 0.0U 0.0U T0 T T T T T T T R0 K/F ST_TXP0_ ST_TXN0_ ST_L ST_X ST_X H J H0 J0 H J H J H H H J J H H J F J0 E E E E F F G G H H J J J J J E E F F F F G G G G G G G G G0 G H0 H ST_RX- ST_RX+ ST_TX0+ ST_TX0- ST_RX0- ST_RX0+ ST_TX+ ST_TX- ST_RX- ST_RX+ ST_TX+ ST_TX- ST_RX- ST_RX+ ST_TX+ ST_TX- ST_L ST_X ST_X ST_T#/GPIO PLLV_ST_ PLLV_ST_ XTLV_ST V_ST_ V_ST_ V_ST_ V_ST_ V_ST_ V_ST_ V_ST_ V_ST_ V_ST_ V_ST_0 V_ST_ V_ST_ V_ST_ V_ST_ V_ST_ VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_0 VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_0 VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_ S00 S xmm SERIL T Part of SERIL T POWER SPI ROM HW MONITOR T /00 IE_IORY IE_IRQ IE_0 IE_ IE_ IE_K# IE_RQ IE_IOR# IE_IOW# IE_S# IE_S# IE_0/GPIO IE_/GPIO IE_/GPIO IE_/GPIO IE_/GPIO IE_/GPIO0 IE_/GPIO IE_/GPIO IE_/GPIO IE_/GPIO IE_0/GPIO IE_/GPIO IE_/GPIO IE_/GPIO IE_/GPIO IE_/GPIO0 SPI_I/GPIO SPI_O/GPIO SPI_LK/GPIO SPI_HOL#/GPIO SPI_S#/GPIO LN_RST#/GPIO ROM_RST#/GPIO FNOUT0/GPIO FNOUT/GPIO FNOUT/GPIO FNIN0/GPIO0 FNIN/GPIO FNIN/GPIO TEMP_OMM TEMPIN0/GPIO TEMPIN/GPIO TEMPIN/GPIO TEMPIN/TLERT#/GPIO 0/GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO0 V VSS Y W W P0 P E P F P G P H P J P J P H P G P G P0 F P F P E P P P J J G G G G M T V N P W P P P T T V L M V M P M V N M S00_FOUT0 TEMP_OMM R_PPE#R V_HWM HWM_GN T T T T T T00 T0 T0 T0 T0 T0 T0 PIORY 0 IRQ 0 P0 0 P 0 P 0 PK# 0 PREQ 0 PIOR# 0 PIOW# 0 PS# 0 PS# 0 P[0..] 0 -LN_RST R0 *0K R_WKE# T0 T0 T0 T T T 0.U L L TLERT_# TLERT#,0.uF_.V *0R_00m 0R_00m R_PPE#R R0 *0K_ VPU R_PPE#R VPU V N00E Q R0 *0_ VPU R_PPE# L FM0- V_ST S00 0U_00 0U_00 0.U 00 0.U 0 0.U 0 0.U 0 0.U Size ocument Number Rev S00 H Quanta omputer Inc. PROJET : ENQ ate: Tuesday, January 0, 00 Sheet of

17 +.VLW ST_ON P 0U/.V_ VPU ST_ON RV R Q TEU PR K_ 0K PR *0_ P *0.U R *0 VEN 0.U_ PU G Q O J GN VO P 0U/.V_ U +.VLW R P 0U/.V_ 0U 00 PR 0_ R +.VLW R PR Q N00E-LF K/F_.V R= 0 R=K Vo=.*(+R/R) V U/.V U U U U U U V. V_S R0 short V_S R short R short R short 0 0U 0U U U U U 0.u/0V_ V_S +.VLW V_VREF V V 0U 00 +.VLW 0.u/0V_ R K/F 0U 00.VSUS V. V V_S 0 0U 0.u/0V_ 00 0.u/0V_ 0.u/0V_ 0 0U 00 PU_PWR_S R *0 R 0_ 0.u/0V_ L LMPGSN_ L LMPGSN_ V_VREF U *0.U SW u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_.U V_VREF VK_.V VK_.V.U U S00 S xmm VQ_ VSS_ VQ_ VSS_ VQ_ Part of VSS_ VQ_ VSS_ L VQ_ VSS_ L VQ_ VSS_ M VQ_ VSS_ P VQ_ VSS_ P VQ_ VSS_ T VQ_0 VSS_0 V VQ_ VSS_ W VQ_ VSS_ W VQ_ VSS_ W VQ_ VSS_ W VQ_ VSS_ VQ_ VSS_ VQ_ VSS_ VQ_ VSS_ VQ_ VSS_ VQ_0 VSS_0 VQ_ VSS_ E VQ_ VSS_ E VQ_ VSS_ E VQ_ VSS_ H VQ_ VSS_ J VQ_ VSS_ J VQ_ VSS_ J VQ_ VSS_ VSS_ M V_ VSS_0 M V_ VSS_ N V_ VSS_ N V_ VSS_ N V_ VSS_ R V_ VSS_ R V_ VSS_ U V_ VSS_ U V_ VSS_ U V_0 VSS_ V V_ VSS_0 V V_ VSS_ VSS_ S_.V_ VSS_ S_.V_ VSS_ F S_.V_ VSS_ J S_.V_ VSS_ J S_.V_ VSS_ K S_.V_ VSS_ VSS_ G S_.V_ VSS_0 H S_.V_ VSS_ H S_.V_ VSS_ H S_.V_ VSS_ VSS_ US_PHY_.V_ VSS_ US_PHY_.V_ VSS_ US_PHY_.V_ VSS_ 0 US_PHY_.V_ US_PHY_.V_ PIE_VSS_ PIE_VSS_ PU_PWR PIE_VSS_ PIE_VSS_ E V_VREF PIE_VSS_ PIE_VSS_ VK_.V PIE_VSS_ PIE_VSS_ VK_.V PIE_VSS_ PIE_VSS_0 VSSK PIE_VSS_ PIE_VSS_ V PIE_VSS_ PIE_VSS_ V PIE_VSS_ PIE_VSS_ V PIE_VSS_0 PIE_VSS_ V PIE_VSS_ PIE_VSS_ V PIE_VSS_ PIE_VSS_ V PIE_VSS_ PIE_VSS_ V PIE_VSS_ PIE_VSS_ V PIE_VSS_ PIE_VSS_0 U PIE_VSS_ PIE_VSS_ T PIE_VSS_ PIE_VSS_ T PIE_VSS_ PIE_VSS_ T PIE_VSS_ PIE_VSS_ T PIE_VSS_0 PIE_VSS_ T PIE_VSS_ PIE_VSS_ P PIE_VSS_ PIE_VSS_ S00 POWER 0 E F F G J J L L M M M M N N P P P R R R T T U U V V V V V V W W Y E E G J J J F G G G H J J J K L L L L L M M M N N P P P P P Quanta omputer Inc. PROJET : ENQ Size ocument Number Rev S00 POWER/EOUPLING ate: Tuesday, January 0, 00 Sheet of

18 REQUIRE STRPS V R *.K_ V V V V R R0 R R *0K_ 0K_ *0K_ 0K SOUT PILK PILK PLK_R, PLK_ S00 Internal P 0K R *0K_ R 0K_ R *0K_ R 0K_ R *0K_ PLK_R PLK SOUT PILK PILK PI_LK0 PI_LK PULL HIGH USE EUG STRPS USE INT. PLL PU IF=K EFULT ROM TYPE: H, H = PI ROM H, L = SPI ROM PULL LOW IGNORE EUG STRPS EFULT USE EXT. MHZ EFULT PU IF=P L, H = LP ROM EFULT L, L = FWH ROM EUG STRPS V V V V V V R R R0 R R R 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ R *.K_ R *.K_ R *.K_ R *.K_ R *.K_ R *.K_ PI_ PI_ PI_ PI_ PI_ PI_ PULL HIGH USE LONG RESET EFULT USE PI PLL EFULT USE PI LK EFULT USE IE PLL EFULT USE EFULT PIE STRPS EFULT OOTFILTIMER ISLE EFULT PULL LOW USE SHORT RESET YPSS PI PLL YPSS PI LK YPSS IE PLL USE EEPROM PIE STRPS OOTFILTIMER ENLE Size ocument Number Rev S00 STRPS Quanta omputer Inc. PROJET : ENQ ate: Tuesday, January 0, 00 Sheet of

19 WE M MOULE FOR EMI 0 *P_ 0.u/V_ MI_LK _PWR TO INVERTER POWER F R0 KLIGHT ON/OFF ONTROL V 0.U V _PWR Panel. UO. MO. UO. MO, LE SELET_, LE SELET_ WM LVS_TX+ LVS_TX- LVS_TX+ LVS_TX- US F USP+ L_ON US F# LON USP- For EMI L SS LVS LEN 0 R 0_ MI+_ LON 000p/0V_ MI_LK R 0_ MI_T_ U MI_T VJ TSH0FU(F) R *0_ R *0_ MI+ 0 LVS LON N R N 0K_ 0 LVS_LK_U+ 0 LVS_LK_U- LVS_TX+ LVS_TX- LVS_TX+ LVS_TX- _L U_0 0.U_ U_ L ONNETOR LON L_VJ *0.u/0V_ 0.U_ *0U_0 LV LE SELET_, LVS_LK_L+ 0 LVS_LK_L- 0 LVS_TX0+ 0 LVS_TX0-0 LVS_TX+ 0 LVS_TX- 0 LVS_TX+ 0 LVS_TX- 0 LVS_TX+ 0 LVS_TX- 0 H:ENLE L:ISLE RWPROTETE PNEL LK PNEL T RWPROTETE *SHORT_P G VPU R 0K_ R0 P_ 0K_ R 0 R 0 P_ VPU R 0_ R N FH0MR0-00-P-L *0_ *0.u/0V_ PNEL LK PNEL T 0 *0.u/0V_ *0.u/0V_ *0.u/0V_ L_VJ *0U *0U PWM signal VPU VPU VPU Serial EEPROM 0 0 _LK _T P_ P_ R 0_ R 0_ RWPROTETE PNEL LK PNEL T 0.U U V N SL S 0 GN V V MER POWER V *0.u/V_ *0.u/V_ *0.u/V_ 0U/0V_ LV V LV 0.U_ 0U/0V_ 0.U_ 0 LVS IGON R 0K_ FOR EMI 0 PNEL V ONTROL LV Q U TEU F LV IN OUT LVS IGON R0 IN GN ON/OFF GN 0U/0V_ 0.U_ T0IGU--T V R 0K_ LV R _ N00E Q0 00pF_ R0 0_ R *0_ R Q O0 *0_ V 0 _PWR *0.u/V_ *0.u/V_ *0.u/V POWER + 0u/0V_ 000p/0V_ 0.u/0V POWER_ON# Quanta omputer Inc. PROJET : ENQ Size ocument Number Rev L PNEL/ ate: Tuesday, January 0, 00 Sheet of

20 N GN TXP TXN GN RXN RXP GN.V.V.V 0 GN GN GN V V V GN RSV GN V 0 XX V XX V ST H 0.0u/V_ ST_RXN0 0 ST_RXP0 0.0u/V_ 0.u/0V_ 0.u/0V_ 0 mils 0.u/0V_ 0.u/0V_ ST_TXP0 ST_TXN0 ST_RXN0 ST_RXP0 F +VST R0 0U_00 F +VST 0U_00 R0 V V FOR EMI u/v_ P +VST pad-rex P V ST--00-P-R sata-ck-0-l-p-r pad-rex P +VST pad-rex V_F PK# PIG# R R K_ *0K_ V_F IERST# R0 *.K_ V 0,,,, IERST# V_F IERST# P P P P P P P P0 PIOR# PIORY PK# P P0 PS# FLE# R *.K_ P P P P P P P P0 PIOR# PIORY PK# P P0 PS# FLE# N P P P0 P P P P P PREQ PIOW# IRQ PIG# P PS# F_SEL# P P P0 P P P P P PREQ PIOW# IRQ P PS# V_F F_SEL# V_F 0 0.u/0V_ 0.u/0V_ R K_ V V F NH0KF-T0 0 F *NH0KF-T U_ 0.u/0V_ L-0RL-TN-ZIF Quanta omputer Inc. PROJET : ENQ Size ocument Number Rev ST-H/F ate: Tuesday, January 0, 00 Sheet 0 of

21 ." MINI-ard I (WLN/ WiMX) V V V. V *0U/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0u/0V_ 0.00u/0V_ 0 0.u/0V_ 0u/0V_ *0U/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ V V. N Reserved Reserved ebug(pirst#) ebug(pilk) GN +.Vaux +.Vaux GN GN PETp0 PETn0 GN GN PERp0 PERn0 GN Reserved Reserved GN,, SERIRQ LP_RQ0# PETX+ PETX- PERX+ PERX-, PLK_ PIRST# LK_PIE_WLN LK_PIE_WLN# GN REFLK+ REFLK- GN LKREQ# Reserved Reserved WKE# +.V GN 0 +.V LE_WPN# LE_WLN# LE_WWN# GN 0 US_+ US_- GN SM_T SM_LK 0 +.V GN +.Vaux PERST# W_ISLE# 0 GN GN Reserved Reserved Reserved Reserved 0 Reserved +.V GN +.V V V V. WLN_LE# R *0_ US F US F# V. RF_EN_WLN V. V V R 0 *0K_ WLN_LE# WLN_LE# WL_SMT WL_SMLK *0U/0V_ SS L0,, *0K L,, R L,, L,, LFRME#,, ctive Low WLN_LE# USP+ USP- PIE_RST# 0,,0,, WLSW V ST SLK 0.u/0V_ 00 0u/0V_ 0.00u/0V_ V R 0_ V Q *N00E Q *N00E 0.u/0V_ RP 0.u/0V_ *.KX WL_SMT WL_SMLK R 0_ Quanta omputer Inc. PROJET : ENQ Size ocument Number Rev Mini-ard/WL ate: Tuesday, January 0, 00 Sheet of

22 emodulation Filter Place close to odec L HPOUT_R V *TI00U0/00 +V HPOUT_L MI-VREFO-R MI+ MI-VREFO-L IN GN SHN OUT SET R.K/F/ Vset =.V Vout =Vset[+R(,)/R(,GN)] + Place next to pin 0.U/V/XR/ U MXSEUK+T nd Source G R 0_ R 0K/F/ + 0U/0V_ 0.U/V/XR/ 0.U/V/XR/ 0.U/V/XR/ +V Place next to pin 0 0.U/V/XR/ V MP_GN Place next to pin P *0.U/V/XR/ 0U/.V/XR/00 V 0U/.V/XR/00 0U/.V/XR/00 Spilt by GN 0.U/V/XR/ MP_GN V T MP_GN V V L_SPK+ R_SPK+ EP#.U/.V/XR/00 0.U/V/XR/ 0.U/.V/XR/00 + VSS V PV SPK-L+ PVSS PVSS SPK-L- SPK-R- SPK-R+ PV P (Vista Premium Version) V N GPIO0/MI-T SPIFO/EP SPIFO PGN PVEE GPIO/MI-LK 0U/.V/XR/00 HP-OUT-R P# HP-OUT-L ST-OUT PVREF IT-LK MI-VREFO-R 0 VSS MI+_ MI-VREFO ST-IN R.K_ MI-VREFO-L V-IO VREF SYN 0 VSS RESET# 0U/.V/XR/00 V MONO-OUT PEEP LINE-R LINE-L MI-R MI-L JREF Sense- MI-R MI-L LINE-R LINE-L Sense L PEEP U 0 0 EEP_ u/0v_ 0 00P/0V_ SENSE# IGITL 0.U/V/XR/ R 0 u/0v_ R *0K_ R0 K_ 0 u/0v_ 0K/F/ MI_INTL NLOG MIIN-R MIIN-L MI+ HPSENSE# SPKR, MISENSE# +V Place next to pin ES-00- V. MI+ Placement near udio odec R R.K/F/ 0 0.U/V/XR/ R K_ 0K/F/ R *0_ 0U/.V/XR/00 lose to U lose to U L_SPK+ L_SPK- R_SPK- L_SPK- R_SPK- R_SPK+ L LM0SN MP_GN L LM0SN L LM0SN MP_GN L LM0SN MI-VREFO-R MI-VREFO-L ES P/0V/XR/00 000P/0V/XR/00 000P/0V/XR/00 000P/0V/XR/00 R.K/F_ R.K/F_ *U/V/XR/00 *U/V/XR/00 Internal Speaker N Internal SPK_L+ Internal SPK_L- Internal SPK_R- Internal SPK_R+ FH0MR0-00-P-L MI-IN Jack MP_GN Place next to pin Place next to pin MI_T MI_LK P# 0V : Power down lass SPK amplifer.v : Power up lass SPK amplifer Z_ITLK_UIO_R Z_ITLK_R 0p/0V_ Z_RESET#_UIO R _ +Z_V Z_RESET#_UIO Z_SYN_UIO Z_SIN0 0.U/V/XR/ R 0_ 0U/.V/XR/00 V MIIN-L MIIN-R MISENSE#.U/.V/XR/00 MIIN-L R MIIN-R R0.U/.V/XR/00 K/F_ K/F_ MIIN-L MIIN-R L L K0HM-T K0HM-T MIIN-L MIIN-R Normal Open Type N R 0_ R 0_ R 0_ R 0_ R 0_ R 0_ 0p/0V_ R _ Z_SOUT_UIO Z_ITLK_UIO Place next to pin Max. 00mVrms input for Mic-IN 0 0P/0V/XR/ 0P/0V/XR/ R 0_ R0 0_ R 0_ R *0_ R0 0_ R *0_ R 0_ MP_GN digital_ground MP_GN R *0_ MP_GN MP_GN Headphone-OUT Tied at one point only under the L or near the L nalog_ground For EMI HPOUT_L R HPOUT_L HPOUT_R R HPOUT_R HPSENSE# R/F/00 R/F/00 HPOUT_L HPOUT_R L L K0HM-T K0HM-T HPOUT_L HPOUT_R Normal Open Type N R 0R/J_ SM0K--F V R *0_ V 000P/0V/XR/ 000P/0V/XR/ U VOLMUTE# R M/J_ P# Z_RESET#_UIO P# EP# U WZ WZ U 0U/.V/XR/00 TSH0FU(F) TSH0FU(F) U R 0_ *000P/0V/XR/ Quanta omputer Inc. PROJET : JR Size ocument Number Rev Realtek L Tuesday, January 0, 00 ate: Sheet of

23 V V UZZER Z, SPKR R *0_ Q0 TEU R 0K_ Q MEN00E P_EEP R K/F_ UZZER_S Q MMT0 R 0.0U R *UZZER-KSSGJ0 UZZER-KSSGJ0-P ENEEP V V R *0_ R *.K_ TPM. U,, L0 L0 PP,, L L,, L 0 L TESTI/,, L L,, LFRME# LFRME# V 0 V, LP_RST# LRESET# V LPP# LPP# VS LKRUN# LKRUN#,, SERIRQ SERIRQ GN GN PLK_TPM LLK GN GPIO GN TPM_XOUT GPIO TESTI N R XTLO TPM_XIN N *_ XTLI/K IN N *SL TT. 0 Y *.K *P_ *P_ *P_ m m V +.VLW R *0_ R *.K_ +.VLW V 0.U_ 0.U_ 0.U_ U_ I/O ddress R Index 0 E * E ata F F Quanta omputer Inc. PROJET : ENQ Size ocument Number Rev HE PHONE MUTE/UZZER ate: Tuesday, January 0, 00 Sheet of

24 US on M/ P USP0- USP0+ USP- USP+ USP- USP+ RER US PORT X PLE NER ONN L WM0-0 L WM0-0 L0 WM0-0 0 *Z0-0H_ES *Z0-0H_ES *Z0-0H_ES *Z0-0H_ES *Z0-0H_ES *Z0-0H_ES US_0_F# US_0_F US F# US F US F# US F US F# US F 0 0 N0 X US N X US 0 0p/0V_NPO_ 0p/0V_NPO_ 0p/0V_NPO_ 0 0p/0V_NPO_ 0p/0V_NPO_ 0p/0V_NPO_ + 0 0U/.V + 0U/.V + 0U/.V USV VSUS USV VSUS R00 0_ R0 0_ USV VSUS R0 0_ R *0_ 0.U R0 *0_ 0.U R0 *0_ 0.U V V V 0mils 0mils 0mils U GN O IN OUT EN OUT EN O TPS0 U0 GN O IN OUT EN OUT EN O TPS0 U GN O IN OUT EN OUT EN O TPS0 USV : 0 mil USV : 0 mil USV : 0 mil USV : 0 mil USV : 0 mil USV : 0 mil US_OP0# US_OP# US_OP# US_OP# US_OP# US_OP# USV USV USV USV USV USV P pad-obs P pad-obs P pad-obs P pad-obs P pad-obs P pad-obs P US_0_F# US_0_F US F# US F US F# US F USP- USP+ USP- USP+ L WM0-0 WM0-0 L *Z0-0H_ES *Z0-0H_ES *Z0-0H_ES *Z0-0H_ES US F# US F R *K/F_ R *K/F_ N US 0 0p/0V_NPO_ 0p/0V_NPO_ 0p/0V_NPO_ 0p/0V_NPO_ + 0U/.V + 0U/.V USV USV USP- USP+ US_OP0# US_OP# US_OP# US_OP# US_OP# US_OP# VSUS R R R R R R L *WM0-0 0K 0K 0K 0K 0K 0K US F# US F V N *touch panel connector pad-obs P pad-obs P pad-obs P0 pad-obs P US F# US F US F# US F US F# USP- USP+ WM0-0 L *Z0-0H_ES *Z0-0H_ES US F# US F R *K/F_ R *K/F_ N US 0p/0V_NPO_ 0p/0V_NPO_ USV + 0U/.V pad-obs P US F pad-obs Quanta omputer Inc. PROJET : ENQ Size ocument Number Rev US on oard ate: Tuesday, January 0, 00 Sheet of

25 LN V X'tal MHz E V V 0 V/V PERST PIE_RST# 0,,0,, LN_WKE# R *0_ R EES GPP_TX0P_LN GPP_TX0N_LN LK_PIE_LN LK_PIE_LN# GPP_RX0P_LN GPP_RX0N_LN GPP_RXP_LN GPP_RXN_LN 0.u/0V_ u/0v_ RV MI0- MI0+ MI- MI+ 0.u/0V_ LFEE-R /F_ /F_ P MI0+ MI0- MI+ MI- 0/00 Transformer 0.0u/V_ 0.0u/V_ + u/.v_ U U V 0.u/0V_ 0.u/0V_ *0.u/0V_ *0.u/0V_ R0.K/F_ V MIP0 MIN0 N/F MIP MIN GN N/MIP N/MIN N/MIP N/MIN TRL 0.u/0V_ T- T+ T N N T R- R+ TX- TX+ 0 T N N T RX- RX+ RSET PERX+ PERX- P/N:0ILLN00 00% P/N:0PWLN0 0% X-TX0- X-TX0+ X-TX-G0 X-TX-G X-TX- X-TX+ MLKX MLKX RTL0EL EV + u/.v_ VTRL/SROUT GN RSET VTRVSR N/VSR N/ENSWREG KTL KTL N/V 0 N/LV_PLL LE0 V V GN HSIP HSIN REFLK_P REFLK_N EV HSOP HSON EGN N/SMLK N/SMT 0 R 0 0.u/0V_ LN_LE0# V V LE/EESK LE/EEI LE/EEO EES GN V 0 V ISOLTE LNWKE LKREQ R 000p/KV_ T LE/EESK LE/EEI LE/EEO EES ISOLTE LKREQ RJ P V V V R 0.u/0V_ *0K_ 0.u/0V_ P V pad-obs P pad-obs pad-obs RX+/+ X-TX+ X-TX0- X-TX0+ V R X-TX+ RX-/- X-TX- X-TX- X-TX0-0.u/0V_ R0 0_ R 0K_ Q N00E N *0_ 0 RJ-ONN 0.u/0V_ V 0.u/0V_ -LN_RST PI_PME# P0 pad-obs 0.u/0V_ X-TX0+ V V PIE_WKE# R0 K/F_ K_ MLKX MLKX EEPROM R0 LN Power LE/EESK LE/EEI LE/EEO R 0K_ P_.K_ U V S V SK I ORG O GN *TN Y MHZ 0 P_ GN V E V Quanta omputer Inc. PROJET : ENQ Size ocument Number Rev LN_RTL0EL/RJ ate: Tuesday, January 0, 00 Sheet of *0.u/0V_ R short

26 , LP_RST#,, T VPU VPU -LI GTE0 SERIRQ KSMI# SI# RIN# 0.U_ *0P_ R 00K_ PURST# U_,,,,,,,, 0.U_,, PLK_E R *_ L0 L L L PLK_E LFRME# PURST# 0.U_ Layout Note: Place all capacitors close to IT. 0.U_ Layout Note: net "VPU" and "RT_V" minimum trace width mils. PLK_E SS SS SS SS T 0.U_ 0 000P/V_ 0.U_ 0 0.U_ 0 V L0 L L L LPRST#/WUI/GP LPLK LFRME# LPP#/WUI/GPE G0/GP SERIRQ ESMI#/GP ESI#/GP WRST# KRST#/GP PWUREQ#/GP GP0/RX GP/TX 0.U_ VPU V VSTY 0 VSTY VSTY VSTY VSTY LP IR VRT VT V MY MY Note : Since all GPIO belong to VSTY power domain, and there are some special considerations below: () If it is output to external V derived power domain circuit, this signal should be isolated by a diode such as KRST# and G0. () If it is input from external V derived power domain circuit, this external circuit must consider not to float the GPIO input. L L 0.U_ Note : () Each input pin should be driven or pulled. () Each output-drain output pin should be pulled. VSTY GPE/ISLK GPE/ISS GPE/IS (For PLL Power) 0 KSO/GP KSO/GP GINT/GP L0HLT/GPE0 L0LLT/GPE T T T GPIO IT K0HS-T K0HS-T VPU VPU SUS# N_PWRG 0, RSMRST# VRON () SPWROK MINON,,, SUSON,, RV_ON ENEEP SMUS Pull Up for Low ctive Pin 0 GPG/I GPH/I GPH/I GPH/I GPH/I GPH/I/R GPH/I/R0 GPH0/I0/SHM SM US WKE UP PS/ PWM URT SMLK0/GP SMT0/GP SMLK/GP SMT/GP SMLK/GPF SMT/GPF PSLK0/GPF0 PST0/GPF PSLK/GPF PST/GPF PSLK/GPF PST/GPF PWM0/GP0 PWM/GP PWM/GP PWM/GP PWM/GP PWM/GP PWM/GP PWM/GP TH0/GP TH/GP TMR0/WUI/GP TMR/WUI/GP PWRSW/GPE RI#/WUI0/GP0 RI#/WUI/GP WUI/GPE RING#/PWRFIL#/LPRST#/GP TX/GP RX/GP0 HWPG MLK MT 0 URT_TX URT_RX MY MY MLK MT HWPG NSWON# WLSW -LI IN rightness UP# rightness W# LKRUN# VOLUME_UP# VOLUME_W# SS PWR_LE# PWR_LE0# SS NSWON# SUS# IN VPU R0 0K R 0K R 0K R 0K R *0K_ R 0K R *0K_ R 0K R 00K_ R0 0K V R 0K R *0K R 0K VOLUME V R 0K MLK MT NSWON# LKRUN# LE SELET_, LE SELET_, LE SELET_, VJ VOLMUTE# _POWER_ON# WLSW SWI# rightness UP# rightness W# FNSIG VOLUME_UPO# VOLUME_WO# NSWON# VLT_ON PIEPWR_ON VOLUME_UP# VOLUME_W# _SE# _SK _SI _SO R _ R _ VPU 0.U_ 0.U_ R 0K R 0K _SK_R _SI_R _SO_R VOLUME V VPU VOLUME V I socket P/N : G R _ R _ R _ U WZ U WZ R *0_ Mbit, SPI R 0K_ R0 U E# SK SI SO WX0 M SST P/N:KEFP0K0 M Winbond P/N:KEGFP0N0 Use Mbit in -test *0_ WP# R 0_ U V HOL# R U VSS WZ WZ R *0_ 0K_ V V VOLUME_UPO# 0.U_ VOLUME_WO# N 0 R 0K_ R *00K_ MY[..0] MX[..0] PWR_LE0# rightness UP# rightness W# NSWON# VOLUME_UP# VOLUME_W# VPU PWR_LE# 0 _SK 0 0 _SO 0 _SI 0 _SE# 0 00 MY0 MY MY MY MY 0 MY MY MY MY MY MY0 MY MY MY MY MY LER_MOS ST_LE# 0 FLE# FLRST#/WUI/GPG0/TM FLLK/SK FL/GPG FL/SO FLSH FL/SI FL0/SE# FLFRME#/GPG KSO0/P0 KSO/P KSO/P KSO/P KSO/P KMX KSO/P KSO/P KSO/P KSO/K# KSO/USY KSO0/PE KSO/ERR# KSO/SLT KSO KSO KSO KSI0/ST# KSI/F# KSI/INIT# KSI/SLIN# KSI KSI KSI KSI MX0 MX MX 0 MX MX MX MX MX H LE LUE F LE LUE VSS VSS VSS VSS VSS VSS VSS VSS 0.U_ R *0_ *LTST-0TKT/LUE LE R 0_ *LTST-0TKT/LUE LE R 0_ / / LOK IT V V 0/GPI0 /GPI /GPI /GPI /GPI /GPI /GPI /GPI 0/GPJ0 /GPJ /GPJ /GPJ /GPJ /GPJ U J00F0 0 0 KKE KK -PUHOL PMUX PMUX MI MI MI0 MI Y lose to IT Y.KHZ P_ P_ PMUX PMUX RT ETETION reserved VOLUME_UPO# VOLUME_WO# ST_ON VFN Layout Note:.kHz clock lines: a. If possible, please avoid using any through-hole. b. Please make the trace length short, and the trace width wide enough. c. The spacing to the closest neighbor should be wide enough. IN -LI NSWON# MT SUS# MLK NSWON# HWPG vloume up VPU SS_ MI0 MI MI MI -PUHOL GN short between GN of R and GN of IN. R0 short R0 short R0 short R0 short Q TEU R 00K_ R0 short R short R0 00K R short R 00K R short R 00K R 00K Model I N NSWON# HWPG SUS# *P_ ON *IPX SW-NHS-0-V-P-Og *P_ URT_TX URT_RX T T *P_ small board conn. WLN_LE# LUE *LTST-0TKT/LUE LE R0 0_ Wireless RF Power LE V 000P_ 0 0.U_ P_ P_ 000P_ Quanta omputer Inc. PROJET : ENQ Size ocument Number Rev E ITE Tuesday, January 0, 00 ate: Sheet of

27 V_R 0u/.V_ 0.u/0V_ V_R 0 0.u/0V_ 0.u/0V_ *0.u/0V_ +.V_V 0.u/0V_ 0.u/0V_ +.V_V L V. *K0HS0 0.u/0V_ Use 00 type and over 0 mils trace width on both side 0m S/MS_V 0mil S/MS_V Memory ard Power Supply reserved M_PWR_TRL# 0mil V_R 0.U U IN OUT N EN GN *G0TU L U S/MS_V 0U_00 V_R V_R R R R V_R 0K_ 00K_ 00K_ V_R MIO MIO MIO S_WP# MS LK MS_S/S_M MS_/S_ MS_/S_ MS_/S_ MS_0/S_0 +.V_V MIO 0,,0,, PIE_RST# PE0LK- PE0LK+ 0 V PIES_EN PIES MIO MIO MIO MIO V MIO MIO MIO MIO0 N N N GN GN GN TV 0 Three capacitor close the pin 0, and PREXT V_R JM MIO MIO MIO MIO0 MIO MIO XRSTN XTEST PLKN PLKP PV PGN PREXT PRXP PRXN PV PTXN PTXP 0 U GN MIO MIO R_LEN V 0 V V R_PTLN R_0N R_N N E_WKEN JMIRON PRXP_ PRXN_ S_# V_R +.V_V S/MS_V S_# MS_# R_PPE# +.V_V MIO MIO 0.u/0V_ 0.u/0V_ SS R_PPE# GPP_RXP_R GPP_RXN_R GPP_TXN_R GPP_TXP_R R_WKE# MS_/S_ MS_/S MIO00_INV V VSUS V_R OE GN MIO00_INV NW Q V OE V_R V_R MIO00_INV MS_/S MS_/S_ * To void SONY MS uo daptor Issue On S R R 0K *0_ R 0_ S/MS_V V_R MS/S_LK MS_S/S_M MS_0/S_0 MS_/S MS_/S MS_/S_ S_WP# R R *0K S_# reserved 0mil M_PWR_TRL# R0 S_T R S_T ON S_LK R S_V S_M *0K_ S_T0 S_T S_T S_T S_WP S_ 0mil S_GN S_GN GN 0 S_GN -IN- Memory onn. Q *O0 R *00K_ S/MS_V S/MS_V V_R V_R R R R0 MS LK R R 0K_ 0K_ 0K_.K_.K_ MS_# R S_# R _ S_WP# MS_S/S_M MIO.K_ mil MS/S_LK *p_ For PV(pin) 0u/.V_ 0.u/0V_ +.V_V 0 000p/0V_ PV(pin) must put 000pF close to PV(pin) (length must under 0mil) and trace width = 0mil, after 000pF, pls put 0.uF and then 0uF for it. S_# Q N00E-LF S/MS_V 0.U S/MS_V 0.U S/MS_V S/MS_V V_R 0.U MS/S_LK MS_S/S_M MS_0/S_0 MS_/S_ MS_/S_ MS_/S_ R *0K MS_# R R R R R ON MS_V MS_SLK MS_S MS/S_T0 MS_T MS_T0 MS_T MS_T 0 MS/S_T MS_T MS_T MS_INS 0 MS-VSS MS_GN MS_GN -IN- Memory onn. Quanta omputer Inc. PROJET : ENQ Size ocument Number Rev aughter oard : ard Reader ate: Tuesday, January 0, 00 Sheet of