ΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2017

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1 ΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2017 ΔΙΑΛΕΞΗ 2: ΑΞΙΟΛΟΓΗΣΗ ΨΗΦΙΑΚΩΝ ΚΥΚΛΩΜΑΤΩΝ ΣΤΟΧΟΙ ΣΧΕΔΙΑΣΗΣ ΧΑΡΗΣ ΘΕΟΧΑΡΙΔΗΣ [Προσαρμογή από Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al. ]

2 Overview of Last Lecture l Digital integrated circuits experience exponential growth in complexity (Moore s law) and performance l Design in the deep submicron (DSM) era creates new challenges Devices become somewhat different Global clocking becomes more challenging Interconnect effects play a more significant role Power dissipation may be the limiting factor l Our goal in this class will be to understand and design digital integrated circuits in the deep submicron era l Today we look at some basic design metrics ΗΜΥ307 Δ2 ΕΙΣΑΓΩΓΗ.2 Θεοχαρίδης, ΗΜΥ, 2017

3 Fundamental Design Metrics l Functionality l Cost NRE (fixed) costs - design effort RE (variable) costs - cost of parts, assembly, test l Reliability, robustness Noise margins Noise immunity l Performance Speed (delay) Power consumption; energy l Time-to-market ΗΜΥ307 Δ2 ΕΙΣΑΓΩΓΗ.3 Θεοχαρίδης, ΗΜΥ, 2017

4 Cost of Integrated Circuits l l NRE (non-recurring engineering) costs Fixed cost to produce the design design effort design verification effort mask generation Influenced by the design complexity and designer productivity More pronounced for small volume products Recurring costs proportional to product volume silicon processing also proportional to chip area assembly (packaging) test fixed cost cost per IC = variable cost per IC volume ΗΜΥ307 Δ2 ΕΙΣΑΓΩΓΗ.4 Θεοχαρίδης, ΗΜΥ, 2017

5 NRE Cost is Increasing ΗΜΥ307 Δ2 ΕΙΣΑΓΩΓΗ.5 Θεοχαρίδης, ΗΜΥ, 2017

6 Silicon Wafer Single die Wafer From ΗΜΥ307 Δ2 ΕΙΣΑΓΩΓΗ.6 Θεοχαρίδης, ΗΜΥ, 2017

7 Recurring Costs cost of die + cost of die test + cost of packaging variable cost = final test yield cost of wafer cost of die = dies per wafer die yield p (wafer diameter/2) 2 p wafer diameter dies per wafer = die area Ö 2 die area die yield = (1 + (defects per unit area die area)/a) -a ΗΜΥ307 Δ2 ΕΙΣΑΓΩΓΗ.7 Θεοχαρίδης, ΗΜΥ, 2017

8 Yield Example q Example wafer size of 12 inches, die size of 2.5 cm 2, 1 defects/cm 2, a = 3 (measure of manufacturing process complexity) 252 dies/wafer (remember, wafers round & dies square) die yield of 16% 252 x 16% = only 40 dies/wafer die yield! q Die cost is strong function of die area l proportional to the third or fourth power of the die area ΗΜΥ307 Δ2 ΕΙΣΑΓΩΓΗ.8 Θεοχαρίδης, ΗΜΥ, 2017

9 Reliability Noise in Digital Integrated Circuits l Noise unwanted variations of voltages and currents at the logic nodes q from two wires placed side by side capacitive coupling - voltage change on one wire can influence signal on the neighboring wire - cross talk inductive coupling - current change on one wire can influence signal on the neighboring wire v(t) i(t) q from noise on the power and ground supply rails can influence signal levels in the gate V DD ΗΜΥ307 Δ2 ΕΙΣΑΓΩΓΗ.9 Θεοχαρίδης, ΗΜΥ, 2017

10 Example of Capacitive Coupling l Signal wire glitches as large as 80% of the supply voltage will be common due to crosstalk between neighboring wires as feature sizes continue to scale Crosstalk vs. Technology Pulsed Signal 0.12m CMOS 0.16m CMOS Black line quiet Red lines pulsed Glitches strength vs technology 0.25m CMOS 0.35m CMOS From Dunlop, Lucent, 2000 ΗΜΥ307 Δ2 ΕΙΣΑΓΩΓΗ.10 Θεοχαρίδης, ΗΜΥ, 2017

11 Static Gate Behavior l Steady-state parameters of a gate static behavior tell how robust a circuit is with respect to both variations in the manufacturing process and to noise disturbances. l Digital circuits perform operations on Boolean variables x Î{0,1} l A logical variable is associated with a nominal voltage level for each logic state 1 Û V OH and 0 Û V OL V(x) V(y) V OH =! (V OL ) V OL =! (V OH ) q Difference between V OH and V OL is the logic or signal swing V sw ΗΜΥ307 Δ2 ΕΙΣΑΓΩΓΗ.11 Θεοχαρίδης, ΗΜΥ, 2017

12 DC Operation Voltage Transfer Characteristics (VTC) q Plot of output voltage as a function of the input voltage V(y) V(x) V(y) V OH = f (V IL ) f V(y)=V(x) V M Switching Threshold V OL = f (V IH ) V IL V IH V(x) ΗΜΥ307 Δ2 ΕΙΣΑΓΩΓΗ.12 Θεοχαρίδης, ΗΜΥ, 2017

13 Mapping Logic Levels to the Voltage Domain q The regions of acceptable high and low voltages are delimited by V IH and V IL that represent the points on the VTC curve where the gain = -1 "1" V OH V IH V(y) V OH Slope = -1 Undefined Region V IL Slope = -1 "0" V OL V OL V IL V IH V(x) ΗΜΥ307 Δ2 ΕΙΣΑΓΩΓΗ.13 Θεοχαρίδης, ΗΜΥ, 2017

14 Noise Margins q For robust circuits, want the 0 and 1 intervals to be as large as possible V DD V DD V OH Noise Margin High Noise Margin Low V OL NM H = V OH - V IH NM L = V IL - V OL "1" V IH Undefined Region V IL "0" Gnd Gate Output Gnd Gate Input q Large noise margins are desirable, but not sufficient ΗΜΥ307 Δ2 ΕΙΣΑΓΩΓΗ.14 Θεοχαρίδης, ΗΜΥ, 2017

15 The Regenerative Property q A gate with regenerative property ensures that a disturbed signal converges back to a nominal voltage level v 0 v 1 v 2 v 3 v 4 v 5 v 6 5 v 2 V (volts) 3 1 v 0 v t (nsec) ΗΜΥ307 Δ2 ΕΙΣΑΓΩΓΗ.15 Θεοχαρίδης, ΗΜΥ, 2017

16 Conditions for Regeneration v 0 v 1 v 2 v 3 v 4 v 5 v 6 v 1 = f(v 0 ) Þ v 1 = finv(v 2 ) v 3 f(v) finv(v) v 1 v 1 finv(v) v 3 f(v) v 2 v 0 v 0 v 2 Regenerative Gate Nonregenerative Gate q To be regenerative, the VTC must have a transient region with a gain greater than 1 (in absolute value) bordered by two valid zones where the gain is smaller than 1. Such a gate has two stable operating points. ΗΜΥ307 Δ2 ΕΙΣΑΓΩΓΗ.16 Θεοχαρίδης, ΗΜΥ, 2017

17 Noise Immunity q Noise margin expresses the ability of a circuit to overpower a noise source noise sources: supply noise, cross talk, interference, offset q Absolute noise margin values are deceptive a floating node is more easily disturbed than a node driven by a low impedance (in terms of voltage) l Noise immunity expresses the ability of the system to process and transmit information correctly in the presence of noise l For good noise immunity, the signal swing (i.e., the difference between V OH and V OL ) and the noise margin have to be large enough to overpower the impact of fixed sources of noise ΗΜΥ307 Δ2 ΕΙΣΑΓΩΓΗ.17 Θεοχαρίδης, ΗΜΥ, 2017

18 Directivity l A gate must be undirectional : changes in an output level should not appear at any unchanging input of the same circuit In real circuits full directivity is an illusion (e.g., due to capacitive coupling between inputs and outputs) l Key metrics: output impedance of the driver and input impedance of the receiver ideally, the output impedance of the driver should be zero input impedance of the receiver should be infinity ΗΜΥ307 Δ2 ΕΙΣΑΓΩΓΗ.18 Θεοχαρίδης, ΗΜΥ, 2017

19 Fan-In and Fan-Out q Fan-out number of load gates connected to the output of the driving gate gates with large fan-out are slower N q Fan-in the number of inputs to the gate gates with large fan-in are bigger and slower M ΗΜΥ307 Δ2 ΕΙΣΑΓΩΓΗ.19 Θεοχαρίδης, ΗΜΥ, 2017

20 The Ideal Inverter l The ideal gate should have infinite gain in the transition region a gate threshold located in the middle of the logic swing high and low noise margins equal to half the swing input and output impedances of infinity and zero, resp. V out R i = R o = 0 Fanout = NM H = NM L = VDD/2 ΗΜΥ307 Δ2 ΕΙΣΑΓΩΓΗ.20 Θεοχαρίδης, ΗΜΥ, 2017 V in

21 The Ideal Inverter l The ideal gate should have infinite gain in the transition region a gate threshold located in the middle of the logic swing high and low noise margins equal to half the swing input and output impedances of infinity and zero, resp. V out R i = R o = 0 g = - Fanout = NM H = NM L = VDD/2 ΗΜΥ307 Δ2 ΕΙΣΑΓΩΓΗ.21 Θεοχαρίδης, ΗΜΥ, 2017 V in

22 An Old-time Inverter NM L 3.0 (V) V out V M NM H V in (V) ΗΜΥ307 Δ2 ΕΙΣΑΓΩΓΗ.22 Θεοχαρίδης, ΗΜΥ, 2017

23 Delay Definitions V in V out V in input waveform Propagation delay? t V out output waveform signal slopes? t ΗΜΥ307 Δ2 ΕΙΣΑΓΩΓΗ.23 Θεοχαρίδης, ΗΜΥ, 2017

24 Delay Definitions V in V out input waveform V in 50% Propagation delay t p = (t phl + t plh )/2 t phl t plh t V out output waveform 50% 90% signal slopes t f 10% t r t ΗΜΥ307 Δ2 ΕΙΣΑΓΩΓΗ.24 Θεοχαρίδης, ΗΜΥ, 2017

25 Modeling Propagation Delay l Model circuit as first-order RC network v out (t) = (1 e t/t )V R v out where t = RC v in C Time to reach 50% point is t = ln(2) t = 0.69 t Time to reach 90% point is t = ln(9) t = 2.2 t q Matches the delay of an inverter gate ΗΜΥ307 Δ2 ΕΙΣΑΓΩΓΗ.25 Θεοχαρίδης, ΗΜΥ, 2017

26 A First-Order RC Network R v out v in C t p = ln (2) t = 0.69 RC Important model matches delay of inverter ΗΜΥ307 Δ2 ΕΙΣΑΓΩΓΗ.26 Θεοχαρίδης, ΗΜΥ, 2017

27 A First-Order RC Network (reference!) R v out v in C L E 0 1 T T Vdd = ò Pt ()dt = V i t dd ò supply ()dt = V C dv dd ò = C V 2 L out L dd E cap T T Vdd = ò P cap ()dt t = ò V out i cap ()dt t = ò C L V out dv = out C V 2 L dd ΗΜΥ307 Δ2 ΕΙΣΑΓΩΓΗ.27 Θεοχαρίδης, ΗΜΥ, 2017

28 Power and Energy Dissipation l Power consumption: how much energy is consumed per operation and how much heat the circuit dissipates supply line sizing (determined by peak power) P peak = V dd i peak battery lifetime (determined by average power dissipation) p(t) = v(t)i(t) = V dd i(t) P avg = 1/T ò p(t) dt = V dd /T ò i dd (t) dt packaging and cooling requirements l Two important components: static and dynamic E (joules) = C L V dd 2 P t sc V dd I peak P V dd I leakage f 0 1 = P 0 1 * f clock P (watts) = C L V dd2 f t sc V dd I peak f V dd I leakage ΗΜΥ307 Δ2 ΕΙΣΑΓΩΓΗ.28 Θεοχαρίδης, ΗΜΥ, 2017

29 Power and Energy Dissipation l Propagation delay and the power consumption of a gate are related l Propagation delay is (mostly) determined by the speed at which a given amount of energy can be stored on the gate capacitors the faster the energy transfer (higher power dissipation) the faster the gate q For a given technology and gate topology, the product of the power consumption and the propagation delay is a constant Power-delay product (PDP) energy consumed by the gate per switching event q An ideal gate is one that is fast and consumes little energy, so the ultimate quality metric is Energy-delay product (EDP) = power-delay 2 ΗΜΥ307 Δ2 ΕΙΣΑΓΩΓΗ.29 Θεοχαρίδης, ΗΜΥ, 2017

30 Summary Today s Lecture l Digital integrated circuits have come a long way and still have quite some potential left for the coming decades l Some interesting challenges ahead Getting a clear perspective on the challenges and potential solutions is the purpose of this course l Understanding the design metrics that govern digital design is crucial Cost, reliability, speed, power and energy dissipation ΗΜΥ307 Δ2 ΕΙΣΑΓΩΓΗ.30 Θεοχαρίδης, ΗΜΥ, 2017

31 Design Abstraction Levels SYSTEM + MODULE GATE CIRCUIT V in V out S n+ G DEVICE D n+ ΗΜΥ307 Δ2 ΕΙΣΑΓΩΓΗ.31 Θεοχαρίδης, ΗΜΥ, 2017

32 Device: The MOS Transistor Gate oxide Source n+ Polysilicon Gate Drain n+ Field-Oxide (SiO 2 ) p substrate p+ stopper Bulk contact CROSS-SECTION of NMOS Transistor ΗΜΥ307 Δ2 ΕΙΣΑΓΩΓΗ.32 Θεοχαρίδης, ΗΜΥ, 2017

33 Circuit: The CMOS Inverter V DD V in V out C L NEXT Lecture! ΗΜΥ307 Δ2 ΕΙΣΑΓΩΓΗ.33 Θεοχαρίδης, ΗΜΥ, 2017