ΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2017

Transcript

1 ΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2017 ΔΙΑΛΕΞΗ 16: Επικοινωνία Διασύνδεση Κωδικοποίηση ΧΑΡΗΣ ΘΕΟΧΑΡΙΔΗΣ (ack: Prof. Mary Jane Irwin and Vijay Narayanan) [Προσαρμογή από Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al. ]

2 Nature of Interconnect Local Interconnect Global Interconnect ΗΜΥ307 Δ16: Interconnect and Communication.2 Θεοχαρίδης, ΗΜΥ, 2017

3 Global Interconnect l System level signal interconnect - buses l Vdd and Gnd planes l System clock ΗΜΥ307 Δ16: Interconnect and Communication.3 Θεοχαρίδης, ΗΜΥ, 2017

4 Impact of Interconnect Parasitics l Reduced reliability l Reduced performance l Classes of parasitics capacitive resistive inductive ΗΜΥ307 Δ16: Interconnect and Communication.4 Θεοχαρίδης, ΗΜΥ, 2017

5 System Level Signal Interconnect W out X out Y out Z out Bus receivers Bus A in B in C in D in Tristate Bus drivers l Many drivers - only one active at a time l Many receivers - many may be active at a time ΗΜΥ307 Δ16: Interconnect and Communication.5 Θεοχαρίδης, ΗΜΥ, 2017

6 Tristate Buffers Three states - 0, 1, and z (high impedance) In Out En In 0!En 1 Out!In 1 0 En z (disconnected) ΗΜΥ307 Δ16: Interconnect and Communication.6 Θεοχαρίδης, ΗΜΥ, 2017

7 Reducing Effective Capacitance W out X out W out X out Y out Z out A in B in Y out Z out A in B in C in D in C in D in l Shared resources may also incur extra switching activity ΗΜΥ307 Δ16: Interconnect and Communication.7 Θεοχαρίδης, ΗΜΥ, 2017

8 Driving Large Capacitances In C L Out C L V swing/2 t phl = I av Increase with transistor sizing I D = k /2 W/L ( ) ΗΜΥ307 Δ16: Interconnect and Communication.8 Θεοχαρίδης, ΗΜΥ, 2017

9 Single Inverter as buffer Cin In A 1 u U*A CL = x. Cin Total propogation delay = tp(inv) + tp(buffer) tp0 - delay of minimum sized inverter with single minimum sized inverter for fanout tp = u. tp0 + x/u tp0 uopt = sqrt(x); tp,opt = 2 tp0. Sqrt(x) ΗΜΥ307 Δ16: Interconnect and Communication.9 Θεοχαρίδης, ΗΜΥ, 2017

10 Use Cascaded Buffers in 1 u u 2 u N-1 out C in C 1 C 2 C L C L = xc in = u N C in u opt = e ΗΜΥ307 Δ16: Interconnect and Communication.10 Θεοχαρίδης, ΗΜΥ, 2017

11 Use Cascaded Buffers in 1 u u 2 u N-1 out C in C 1 C 2 C L C L = xc in = u N C in u opt = e ΗΜΥ307 Δ16: Interconnect and Communication.11 Θεοχαρίδης, ΗΜΥ, 2017

12 t p as a Function of u and x 60.0 u/ln(u) 40.0 x=10,000 x= x=100 x= u ΗΜΥ307 Δ16: Interconnect and Communication.12 Θεοχαρίδης, ΗΜΥ, 2017

13 Impact of Cascading Buffers x Unbuffered Single Buffer Cascaded Buffers ,000 1, ,000 10, chip bus I/O pads t opt /t p0 versus x for various driver configurations C in = 10 ff in 1 micron CMOS ΗΜΥ307 Δ16: Interconnect and Communication.13 Θεοχαρίδης, ΗΜΥ, 2017

14 Designing Large Transistors D(rain) S D G D S(ource) S G(ate) Small transistors in parallel Circular transistors ΗΜΥ307 Δ16: Interconnect and Communication.14 Θεοχαρίδης, ΗΜΥ, 2017

15 Capacitive Coupling (Crosstalk) l Signal wire glitches as large as 80% of the supply voltage will be common due to crosstalk between neighboring wires as feature sizes continue to scale Crosstalk vs. Technology Pulsed Signal 0.12m CMOS 0.16m CMOS Black line quiet Red lines pulsed Glitches strength vs technology 0.25m CMOS 0.35m CMOS From Dunlop, Lucent, 2000 ΗΜΥ307 Δ16: Interconnect and Communication.15 Θεοχαρίδης, ΗΜΥ, 2017

16 Battling Capacitive Crosstalk l Avoid parallel lines l Use shielding GND shielding wire signal wire V dd shielding layer GND substrate (GND) ΗΜΥ307 Δ16: Interconnect and Communication.16 Θεοχαρίδης, ΗΜΥ, 2017

17 Inductive Effects l When wires are sufficiently long or circuits are sufficiently fast, inductance of the wire starts to dominate the delay behavior V in r l r l r l x r l V out g c g c g c g c l Must consider wire transmission line effects Wave mode instead of diffusion equations used so far Signal alternately transfers energy from capacitive to inductive modes ΗΜΥ307 Δ16: Interconnect and Communication.17 Θεοχαρίδης, ΗΜΥ, 2017

18 Transmission Line Considerations l Transmission line effects should be considered when the rise or fall time of the input signal is smaller than the time-of-flight of the transmission line Rule of Thumb t r (t f ) < 2.5 t flight = 2.5 L/v ΗΜΥ307 Δ16: Interconnect and Communication.18 Θεοχαρίδης, ΗΜΥ, 2017

19 Power and Ground Distribution V DD GND Logic Logic V DD V DD GND (a) Finger-shaped network GND (b) Network with multiple supply pins ΗΜΥ307 Δ16: Interconnect and Communication.19 Θεοχαρίδης, ΗΜΥ, 2017

20 Signaling Input and Output! Both data about the physical world and control signals sent to interact with the physical world are typically "analog" or continuously varying quantities. In order to use the power of digital circuits, one must convert from analog to digital form on the experimental measurement end and convert from digital to analog form on the control or output end of a laboratory system. V V t D/A Conversion Computer DAC t A/D Conversion DAC ΗΜΥ307 Δ16: Interconnect and Communication.20 Θεοχαρίδης, ΗΜΥ, 2017

21 Sampling l Sampling rate depends on clock frequency l Use Nyquist Criterion l Increasing sampling rate increases accuracy of conversion l Possibility of aliasing Sampling Signal: T w Sampling Period: T s = 1 f s Nyquist Criterion: fs > 2* f max ΗΜΥ307 Δ16: Interconnect and Communication.21 Θεοχαρίδης, ΗΜΥ, 2017

22 Aliasing High and low frequency samples are indistinguishable Results in improper conversion of the input signal Usually exists when Nyquist Criterion is violated Can exist even when: fs > * 2 f max Prevented through the use of Low-Pass (Anti-aliasing) Filters ΗΜΥ307 Δ16: Interconnect and Communication.22 Θεοχαρίδης, ΗΜΥ, 2017

23 Quantizing and Encoding l Approximates a continuous range of values and replaces it with a binary number l Error is introduced between input voltage and output binary representation l Error depends on the resolution of the ADC ΗΜΥ307 Δ16: Interconnect and Communication.23 Θεοχαρίδης, ΗΜΥ, 2017

24 Resolution resolution = Example: Vrange Maximum value of quantization error Error is reduced with more available memory V range =Input Voltage Range n= # bits of ADC = 7.0V n = 3 1V = 7V /(2 Vrange 3-1) n /( 2-1) Qerror = ±.5V = ± resolution / 2 Resolution ΗΜΥ307 Δ16: Interconnect and Communication.24 Θεοχαρίδης, ΗΜΥ, 2017

25 Resolution Increase in resolution improves the accuracy of the conversion Minimum voltage step recognized by ADC Analog Signal Digitized Signal- High Resolution Digitized Signal- Low Resolution ΗΜΥ307 Δ16: Interconnect and Communication.25 Θεοχαρίδης, ΗΜΥ, 2017

26 Digital to Analog to Digital Conversion DAC and ADC n bits Digital Circuit A/D ΗΜΥ307 Δ16: Interconnect and Communication.26 Θεοχαρίδης, ΗΜΥ, 2017

27 DAC the easy part! D/A conversion can be as simple as a weighted resistor network 4 - bit DAC Converter Resistor values correspond to binary weights of the number D 3 D 2 D 1 D 0, i.e. 1/8, 1/4, 1/2, and 1 ΗΜΥ307 Δ16: Interconnect and Communication.27 Θεοχαρίδης, ΗΜΥ, 2017

28 DAC v. 2 slightly modified A modification of the weighted resistor DAC is the so called R-2R LADDER DAC, that uses only 2 different resistances ΗΜΥ307 Δ16: Interconnect and Communication.28 Θεοχαρίδης, ΗΜΥ, 2017

29 ADC Harder and usually needs to be VERY fast! Types of A/D Converters Flash A/D Converter Successive Approximation A/D Converter Example of Successive Approximation Dual Slope A/D Converter Delta Sigma A/D Converter ΗΜΥ307 Δ16: Interconnect and Communication.29 Θεοχαρίδης, ΗΜΥ, 2017

30 Elements of a Flash A/D Converter Encoder Comparator ΗΜΥ307 Δ16: Interconnect and Communication.30 Θεοχαρίδης, ΗΜΥ, 2017

31 FLASH A/D CONVERTER Resolution = 7 Comparators 3 Bit Digital Output l l As the analog input voltage exceeds the reference voltage at each comparator, the comparator outputs will sequentially saturate to a high state. The priority encoder generates a binary number based on the highestorder active input, ignoring all other active inputs. ΗΜΥ307 Δ16: Interconnect and Communication.31 Θεοχαρίδης, ΗΜΥ, 2017

32 Flash A/D Converter Contd. Pros Fastest (in the order of nano seconds) Simple operational theory Speed is limited only by gate and comparator propagation delay Cons Each additional bit of resolution requires twice the number of comparators Expensive Prone to produce glitches in the output ΗΜΥ307 Δ16: Interconnect and Communication.32 Θεοχαρίδης, ΗΜΥ, 2017

33 Dual-Slope ADC * ΗΜΥ307 Δ16: Interconnect and Communication.33 Θεοχαρίδης, ΗΜΥ, 2017

34 SUCESSIVE APPROXIMATION A/D CONVERTER ΗΜΥ307 Δ16: Interconnect and Communication.34 Θεοχαρίδης, ΗΜΥ, 2017

35 Delta-Sigma ADC ΗΜΥ307 Δ16: Interconnect and Communication.35 Θεοχαρίδης, ΗΜΥ, 2017

36 Delta-Sigma ADC contd. #1 Delta-Sigma Modulator l l l l Over sampled input signal goes to the integrator Output of integration is compared to GND Iterates to produce a serial bit stream Output is serial bit stream with # of 1 s proportional to V in ΗΜΥ307 Δ16: Interconnect and Communication.36 Θεοχαρίδης, ΗΜΥ, 2017

37 #2 Digital Filter Delta-Sigma ADC contd. Decimator Pros High Resolution No need of precision components Cons Slow due to over sampling Good for low bandwidth ΗΜΥ307 Δ16: Interconnect and Communication.37 Θεοχαρίδης, ΗΜΥ, 2017

38 Sigma-Delta A/D Converter Contd. ΗΜΥ307 Δ16: Interconnect and Communication.38 Θεοχαρίδης, ΗΜΥ, 2017

39 ADC Comparison Type Speed(relative) Cost(Relative) Dual Slope Slow Med Flash Very fast High Successive approx Medium fast Low Sigma-Delta Slow Low ΗΜΥ307 Δ16: Interconnect and Communication.39 Θεοχαρίδης, ΗΜΥ, 2017

40 Priority Encoders - Example ΗΜΥ307 Δ16: Interconnect and Communication.40 Θεοχαρίδης, ΗΜΥ, 2017