Electronic Analysis of CMOS Logic Gates

Electronic Analysis of CMOS Logic Gates Dae Hyun Kim EECS Washington State University

References John P. Uyemura, Introduction to VLSI Circuits and Systems, 2002. Chapter 7

Goal Understand how to perform electronic analysis of CMOS logic gates. DC characteristics Noise margin Switching characteristics Power

Analysis DC Analysis Vin vs. Vout = Voltage Transfer Characteristic (VTC) Transient (switching) analysis Vin(t) vs. Vout(t) 0 0 tt

CMOS Inverter DC Characteristics Logic swing When = 0 = VV DDDD Output high voltage VV OOOO = VV DDDD When = VV DDDD = 0 Output low voltage VV OOLL = 0 Logic swing VV LL = VV OOOO VV OOOO = VV DDDD

CMOS Inverter DC Characteristics Region A (0 VV TTnn ) Mn Mp VV GGGGGG = 0 = VV GGGGGG < VV TTnn : Cut-off Mn Mp VV SSSSSS = VV DDDD C VV SSDDpp = VV DDDD VV SSSSSS VV TTTT VV SSSSSS = VV TTTT > 0 VV SSSSSS VV TTTT > VV SSSSSS : Linear A B D E VV DDDD

CMOS Inverter DC Characteristics Region B (VV TTTT < VV DDDD 2 ) Mn VV GGGGGG VV TTTT = VV TTTT > 0 VV DDDDDD = VV GGGGGG VV TTTT VV DDDDDD = VV TTTT < 0 Mp Mn VV GGGGGG VV TTTT < VV DDDDnn : Saturation C Mp VV SSSSSS = VV DDDD VV SSDDpp = VV DDDD A B D E VV SSSSSS VV TTTT VV SSSSSS = VV TTTT > 0 VV SSSSSS VV TTTT > VV SSSSSS : Linear = VV TTTT + ( VV TTTT ) 2 2 VV DDDD 2 VV TTTT VV DDDD ( VV TTTT ) 2

CMOS Inverter DC Characteristics Region C ( VV DDDD 2 ) Mn Mp VV GGGGGG VV TTTT VV DDDDDD = VV TTTT < 0 VV GGGGGG VV TTTT < VV DDDDnn : Saturation VV SSSSSS VV TTTT VV SSSSSS = VV TTTT < 0 C Mp Mn VV SSSSSS VV TTTT < VV SSSSSS : Saturation II DDDDDD = 2 (VV MM VV TTTT ) 2 II SSDDpp = 2 (VV DDDD VV MM VV TTpp ) 2 Solve II DDDDDD = II SSSSSS. VV MM A B D E VV MM = VV DDDD VV TTTT +VV TTTT 1+ ββpp ββnn ββpp VV MM

CMOS Inverter DC Characteristics Region D ( VV DDDD 2 < VV DDDD VV TTTT ) Mn VV GGGGGG VV TTTT = VV TTTT > 0 VV DDDDDD = VV GGGGGG VV TTTT VV DDDDDD = VV TTTT > 0 Mp Mn VV GGGGGG VV TTTT > VV DDDDnn : Linear C Mp VV SSSSSS = VV DDDD VV SSDDpp = VV DDDD A B D E VV SSSSSS VV TTTT VV SSSSSS = VV TTTT < 0 VV SSSSSS VV TTTT < VV SSSSSS : Saturation = VV TTTT ( VV TTTT ) 2 ( VV DDDD VV TTTT ) 2

CMOS Inverter DC Characteristics Region E (VV DDDD VV TTTT VV DDDD ) Mn Mp VV GGGGGG VV TTTT = VV TTTT > 0 Mp VV DDDDDD = VV GGGGGG VV TTTT VV DDDDDD = VV TTTT > 0 VV GGGGGG VV TTTT > VV DDDDDD : Linear C Mn VV SSSSSS = VV DDDD VV SSGGpp VV TTTT < 0: Cut-off 0 A B D E

CMOS Inverter DC Characteristics Voltage noise margin VVVVVV HH = VV OOOO VV IIII VVVVVV LL = VV IIII VV OOOO VV IIII : Min. high input voltage VV IILL : Max. low input voltage VV OOHH : Min. high output voltage VV OOLL : Max. low output voltage VV OOOO slope = -1 VV OOOO VV IIII VV IIII

CMOS Inverter Switching Characteristics tt rr : rise time tt ff : fall time CC oooooo : total output capacitance CC oooooo = CC FFFFFF + CC LL CC FFFFFF : FET capacitance CC FFFFFF = CC DDDD + CC DDpp VV DDDD CC LL» CC DDDD = CC GGGGnn + CC DDDDnn» CC DDpp = CC GGGGpp + CC DDDDpp CC LL : load capacitance 0 tt VV DDDD tt ff tt rr 0 tt

CMOS Inverter Switching Characteristics Fall time From = 0.9VV DDDD to = 0.1VV DDDD Fall time calculation Discharging (Natural response) ii ii = CC oooooo dd RR nn = dddd 1 = RR nn (VV DDDD VV TTnn ) tt = VV DDDD ee tt ττnn ττ nn = RR nn CC oooooo (time constant) RR nn CC oooooo tt = ττ nn ln VV DDDD tt ff = tt = 0.1VV DDDD tt = 0.9VV DDDD = ττ nn ln 10 ln 10 tt ff 2.2ττ nn 9 = ττ nn ln 9 tt HHHH = tt ff tt HHHH : high-to-low time

CMOS Inverter Switching Characteristics Rise time From = 0.1VV DDDD to = 0.9VV DDDD Rise time calculation Charging (Step response) RR pp ii ii = CC oooooo dd dddd = VV DDDD RR pp CC oooooo RR pp = 1 (VV DDDD VV TTpp ) tt = VV DDDD 1 ee tt ττpp ττ pp = RR pp CC oooooo (time constant) tt = ττ pp ln VV DDDD VV DDDD tt rr = tt = 0.9VV DDDD tt = 0.1VV DDDD = ττ pp ln 10 ln 10 tt rr 2.2ττ pp 9 = ττ pp ln 9 tt LLLL = tt rr tt LLHH : low-to-high time

CMOS Inverter Switching Characteristics Transient simulation of a CMOS inverter

CMOS Inverter Switching Characteristics Maximum signal frequency The largest frequency 1 ff mmmmmm = = 1 = tt HHHH +tt LLHH tt ff +tt rr Example RR nn = RR pp = 500Ω 1 2.2 (ττ nn +ττ pp ) CC oooooo = 10ffff VV DDDD ff mmmmmm = 1 2.2(5pppp+5pppp) 45GGGGGG Propagation delay Delay time from input to output 0 tt tt pp = tt pppp+tt pprr 2 tt pppp : output fall time (VV DDDD VV DDDD 2 ) tt pppp = ττ nn ln 2 tt pprr : output rise time (0 VV DDDD 2 ) tt pprr = ττ pp ln 2 VV DDDD VV DDDD 2 0 tt pppp tt pppp tt

CMOS Inverter General Analysis Output capacitance CC oooooo = CC FFFFFF + CC LL Rise time tt rr = ττ pp ln9 2.2RR pp CC FFFFFF + CC LL = tt rrr + 2.2RR pp CC LL RR pp = Fall time 1 (VV DDDD VV TTTT ) tt ff = ττ nn ln9 2.2RR nn (CC FFFFFF + CC LL ) = tt ff0 + 2.2RR nn CC LL RR nn = Speed vs. area 1 (VV DDDD VV TTTT ) ββ RR tt Area goes up, but the logic is faster.

CMOS Inverter Power Dissipation Power dissipation calculation PP = VV DDDD II DDDD PP = PP DDDD + PP dddddd PP DDDD : DC power Region A, E: II DDDD = 0 Actually, there is leakage current II DDDDDD.» II DDDDDD : quiescent leakage current II DDDD VV DDDD CMOS circuit PP DDDD = VV DDDD II DDDDDD PP dddddd : Dynamic power Charging/Discharging QQ ee = CC oooooo VV DDDD C PP = VV DDDD II DDDD = VV DDDD QQ ee TT = ffcc oooooo VV DDDD 2 A B D E PP = VV DDDD II DDDDDD + ffcc oooooo VV DDDD 2

NAND2 DC Characteristics VV TTTT,BB goes up. VV BB VV AA VV AA VV BB (i) 0 VV DDDD 0 VV DDDD (ii) VV DDDD 0 VV DDDD iii ii i (iii) 0 VV DDDD VV DDDD

NAND2 DC Characteristics VV MM ( = = VV MM ) nfet network: 2 pfet network: 2 Mn (VV AA ): VV GGGGGG VV TTTT VV DDDDDD = VV MM VV TTTT < VV MM < 0: Saturation Mn (VV BB ): VV GGGGGG VV TTTT VV DDDDDD = VV MM VV SS VV TTTT VV MM VV SS < 0: Saturation Mp: VV SSSSSS VV TTTT VV SSSSSS = VV DDDD VV MM VV TTTT VV DDDD VV MM < 0: Saturation II DDDDDD = ( 2 ) 2 (VV MM VV TTTT ) 2 II SSSSSS = (2) (VV 2 DDDD VV MM VV TTTT ) 2 Solve II DDDDDD = II SSSSSS. VV MM = VV DDDD VV TTTT + 1 2 VV TTTT For NANDk 1+ 1 2 ββnn ββpp ββnn ββpp VV BB VV MM = VV DDDD VV TTTT + 1 kk VV TTTT 1+ 1 kk ββpp VV AA

NOR2 DC Characteristics VV TTTT,BB goes up. VV AA VV BB VV AA VV BB (i) 0 VV DDDD 0 VV DDDD (ii) 0 0 VV DDDD (iii) 0 VV DDDD 0 i ii iii

NOR2 DC Characteristics VV MM ( = = VV MM ) nfet network: 2 pfet network: 2 Mn: VV GGGGGG VV TTTT VV DDDDDD = VV MM VV TTTT VV MM < 0: Saturation Mp (VV AA ): VV SSSSSS VV TTTT VV SSSSSS = VV DDDD VV MM VV TTTT VV DDDD VV MM < 0: Saturation Mp (VV BB ): VV SSSSSS VV TTTT VV SSSSSS = VV SS VV MM VV TTTT VV SS VV MM < 0: Saturation II DDDDDD = 2 2 (VV MM VV TTTT ) 2 II SSSSSS = (ββpp 2 ) (VV 2 DDDD VV MM VV TTTT ) 2 Solve II DDDDDD = II SSSSSS. VV MM = VV DDDD VV TTTT +2VV TTTT For NORk 1+2 ββpp ββnn ββpp VV AA VV MM = VV DDDD VV TTTT +kkvv TTTT 1+kk ββpp VV BB

Elmore Delay How to estimate delay in general RC networks. How to Start at the target sink node. Traverse the RC network toward the source. Whenever there is a resistor, multiply its resistance and its downstream capacitance and add it to the total delay. For two-pin nets RR oooooo ii RR 4 RR 1 RR 2 RR 3 RR... nn 2 RR nn 1 RR nn CC 1 CC 2 CC 3 CC nn 2 CC nn 1 CC nn CC LL ττ = RR nn CC nn + CC LL + RR nn 1 CC nn 1 + CC nn + CC LL + RR nn 2 CC nn 2 + CC nn 1 + CC nn + CC LL + + RR 3 CC 3 + + CC nn + CC LL + RR 2 CC 2 + + CC nn + CC LL + RR 1 CC 1 + + CC nn + CC LL + RR oooooo (CC 1 + + CC nn + CC LL )

Elmore Delay How to estimate delay in general RC networks. For multi-pin nets RR oooooo ii RR 4 RR 1 RR 2 RR 3 RR... nn 2 RR nn 1 RR nn o CC 1 CC 2 CC 3 CC nn 2 CC nn 1 CC nn CC LLL RR aa RR bb o CC aa CC bb CC LLL ττ o = RR nn CC nn + CC LLL + RR nn 1 CC nn 1 + CC nn + CC LL1 + RR nn 2 CC nn 2 + CC nn 1 + CC nn + CC LL1 + CC aa + CC bb + CC LLL + + RR 3 CC 3 + + CC nn + CC LLL + CC aa + CC bb + CC LLL + RR 2 CC 2 + + CC nn + CC LL1 + +CC aa + CC bb + CC LLL + RR 1 CC 1 + + CC nn + CC LL1 + CC aa + CC bb + CC LLL + RR oooooo (CC 1 + + CC nn + CC LL1 + +CC aa + CC bb + CC LLL )

NAND2 Switching Characteristics tt rr : rise time tt ff : fall time CC oooooo : total output capacitance CC oooooo = CC FFFFFF + CC LL CC FFFFFF : FET capacitance CC FFFFFF = CC DDDD + 2CC DDpp VV BB» CC DDDD = CC GGGGnn + CC DDDDnn» CC DDpp = CC GGGGpp + CC DDDDpp CC LL : load capacitance CC xx : parasitic capacitance VV AA CC xx

NAND2 Switching Characteristics Rise time If AAAA: 11 00 (best case) tt = VV DDDD 1 ee tt ττpp ττ pp = RR pp 2 CC oooooo VV BB tt rr 2.2ττ pp VV AA CC xx If AAAA: 11 10 or AAAA: 11 01 (worst case) tt = VV DDDD 1 ee tt ττpp ττ pp = RR pp CC oooooo tt rr 2.2ττ pp tt rr = 2.2RR pp CC FFFFFF + CC LL

NAND2 Switching Characteristics Fall time If AAAA: 00 11 or AAAA: 10 11 (best case) tt = VV DDDD ee tt ττnn ττ nn = 2RR nn CC oooooo tt ff 2.2ττ nn VV BB If AAAA: 01 11 (worst case) VV AA CC xx tt = VV DDDD ee tt ττnn ττ nn = 2RR nn CC oooooo + RR nn CC xx tt ff 2.2ττ nn tt ff = 2.2 2RR nn CC FFFFFF + CC LL + 2.2RR nn CC xx

NOR2 Switching Characteristics tt rr : rise time tt ff : fall time CC oooooo : total output capacitance CC oooooo = CC FFFFFF + CC LL CC FFFFFF : FET capacitance CC FFFFFF = 2CC DDDD + CC DDpp» CC DDDD = CC GGGGnn + CC DDDDnn» CC DDpp = CC GGGGpp + CC DDDDpp CC LL : load capacitance CC xx : parasitic capacitance VV AA VV BB CC yy

NOR2 Switching Characteristics Fall time If AAAA: 00 11 (best case) tt = VV DDDD ee tt ττnn ττ nn = RR nn 2 CC oooooo tt ff 2.2ττ nn VV AA CC yy If AAAA: 00 10 or AAAA: 00 01 (worst case) tt = VV DDDD ee tt ττnn VV BB ττ nn = RR nn CC oooooo tt ff 2.2ττ nn tt ff = 2.2RR nn CC oooooo

NOR2 Switching Characteristics Rise time If AAAA: 01 00 (best case) tt = VV DDDD 1 ee tt ττpp ττ pp = 2RR pp CC oooooo tt rr 2.2ττ pp VV AA CC yy If AAAA: 10 00 or AAAA: 11 00 (worst case) tt = VV DDDD 1 ee tt ττpp VV BB ττ pp = 2RR pp CC oooooo + RR pp CC yy tt rr 2.2ττ pp tt rr = 2.2[2RR pp CC FFFFFF + CC LL ] + 2.2RR pp CC yy

Power Dissipation Dynamic power PP dddddd = ααααααvv DDDD 2 αα: switching activity ff: clock frequency CC: capacitance More accurate formula PP dddddd = ffvv DDDD 2 αα ii CC ii nn ii=1

Transmission Gates and Pass Transistors Transmission gates Approximation ss RR TTTT = max (RR nn, RR pp ) CC iiii = CC nnnnnnnn,ssssssssssss + CC pppppppp,dddddddddd ss Pass transistors Rise time tt rr = 18RR nn CC oooooo Fall time tt ff = 2.94RR nn CC oooooo gg