SERVIE MANUAL DUAL AND FM TRANSEIVER i7e
INTRODUTION This service manual describes the latest service information for the I-7E DUAL AND FM TRANSEIVER at the time of publication MODEL I-7E VERSION Europe Italy SYMOL EUR ITR To upgrade quality, any electrical or mechanical parts and internal circuits are subject to change without notice or obligation. DANGER NEVER connect the transceiver to an A outlet or to a D power supply that uses more than V. This will ruin the transceiver. DO NOT expose the transceiver to rain, snow or any liquids. DO NOT reverse the polarities of the power supply when connecting the transceiver. DO NOT apply an RF signal of more than 0 dm (00 mw) to the antenna connector. This could damage the transceiver s front end. ING PARTS e sure to include the following four points when ordering replacement parts:. 0-digit order numbers. omponent part number and name. Equipment model name and unit name. Quantity required <SAMPLE > 0000 S.I MGP I-7E MAIN UNIT pieces 00090 Screw FH M. ZK I-7E bottom cover 0 pieces Addresses are provided on the inside back cover for your convenience. REPAIR NOTES. Make sure a problem is internal before disassembling the transceiver.. DO NOT open the transceiver until the transceiver is disconnected from its power source.. DO NOT force any of the variable components. Turn them slowly and smoothly.. DO NOT short any circuits or electronic parts. An insulated tuning tool MUST be used for all adjustments.. DO NOT keep power ON for a long time when the transceiver is defective.. DO NOT transmit power into a signal generator or a sweep generator. 7. ALWAYS connect a 0 d to 0 d attenuator between the transceiver and a deviation meter or spectrum analyzer when using such test equipment.. READ the instructions of test equipment thoroughly before connecting equipment to the transceiver.
TALE OF ONTENTS SETION SETION SETION SETION SPEIFIATIONS INSIDE VIEWS DISASSEMLY INSTRUTIONS IRUIT - REEIVER IRUITS............................................................ - - TRANSMITTER IRUITS......................................................... - - PLL IRUITS.................................................................. - - POWER SUPPLY IRUITS....................................................... - - PORT ALLOATIONS............................................................ - 0 SETION SETION SETION 7 SETION PARTS LIST MEHANIAL PARTS AND DISASSEMLY SEMI-ONDUTOR INFORMATION OARD LAYOUTS - ONTROL UNIT................................................................ - - MAIN UNIT..................................................................... - - VO UNIT..................................................................... - SETION 9 SETION 0 LOK DIAGRAM VOLTAGE DIAGRAMS 0 - ONTROL UNIT............................................................... 0-0 - MAIN AND VO UNITS..........................................................0 -
SETION SPEIFIATIONS M GENERAL Frequency range : VERSION [EUR] [ITR] RX (MHz).000.000, 0.000 0.000.000.000 0.000.000,.000.000 TX (MHz).000.000, 0.000 0.000.000.000 0.000.000,.000.000 Mode : FM, AM (AM range is.0.99 MHz and Rx only for [USA] and [EXP].) Nomber of memory channel : (including call channels and 0 scan edges) Usable temperature range : 0 to +0 ; + F to +0 F Frequency resolution :, 0,.,, 0,, 0 and 0 khz Frequency stability : ±0 ppm ( 0 to +0 ; + F to +0 F) Power supply requirement :. V D ± % (negative ground) urrent drain (at. V D) : Receive Standby (squelched). A Max. audio output. A Transmit at VHF 0 W/UHF W.0 A/.0 A Antenna connector : SO-9 (0 Ω) DATA connector : Mini DIN pin Dimensions : ontroller 0(W) 0(H) 7(D) mm; (W) (H) (D) inch (projections not included) Main unit 0(W) 0(H) 7(D) mm; (W) 9 (H) 7 (D) inch Weight : ontroller 0 g;.9 oz Main unit. kg;.0 lb M TRANSMITTER Output power : VHF 0 W/ W/ W (selectable) UHF W/ W/ W (selectable) Modulation system : Variable reactance frequency Maximum frequency deviation : ±.0 khz Spurious emissions : Less than 0 d Microphone connector : -pin modular jack (00 Ω) M REEIVER Receive system : Double-conversion superheterodyne Intermediate frequency : st IF. MHz/.0 MHz (Left/right side band) nd IF 0 khz/ khz Sensitivity : Less than 0. µv (at d SINAD) Squelch sensitivity : Less than 0. µv (at threshold) Selectivity (wide/narrow) : More than khz/ d Less than 0 khz/ 0 d Spurious and image rejection : More than 0 d Audio output power (at. V) : More than. W at 0% distortion with an Ω load External speaker connector : -conductor.(d) mm ( ")/ Ω All stated specifications are subject to change without notice or obligation. -
SETION INSIDE VIEWS ONTROL UNIT (TOP VIEW) Key back light (DS, DS: LN7G) LD back light DS-, DS7-9: SML-00MT DS-, DS0-: SML-00MLT Key back light (DS, DS7: LN7G) Key back light (DS, DS: LN7G) MAIN UNIT (TOP VIEW) VHF RX Pre amplifier (Q: SK7) UHF RX Pre amplifier (Q: SK7) VHF VHF low-pass low-pass filter filter AF amplifier (I0: LA) VO unit Power amplifier (Q7: RD70F) Drive amplifier (Q: SK07) Main PU (I0: HDFAFA0) Drive TX pre-amplifier (Q: (Q: SK07) SK) -
ONTROL UNIT (OTTOM VIEW) Dimmer circuit (Q-Q: S) ontrol Sub PUunit PU (I: HD77RH) +V regurator (I: TA7L0F) Mic amplifier I: TA7SF Q: S MAIN UNIT (OTTOM VIEW) Data comparator (I: TA7S0F) TA7S0F, D: MA07) + regurator (Q: S) Q: SA D: MA09 Reset I (I: S-09LM) D/A converter (I: MGP) UHF low-pass filter circuit Analog switch I007: U0FV I00: I00: U0FV I00: U0FV eramic bandpass filters FI000: FWM0E FI00: FWS0HT FI00: FWME FM IF I I00: TAFN I00: TAFN PLL circuit + regurator (I00: TA70F) Mic amplifier (I0: TA7SF) +V regurator (I00: TA70F) AP amplifier (I: TA7S0F) -
SETION DISASSEMLY INSTRUTIONS Removing the MAIN unit ➀ Unscrew screws A, and remove the cover. ➁ Disconnect two cables from J and J007. ➂ Remove the clip c. ➆ Unscrew screws I. ➇ Unscrew screws J, and remove MAIN unit. J A A I MAIN UNIT J J007 ➃ Unsolder points E. ➄ Unscrew screws F. ➅ Unsolder points G, and remove the cover H. E G F G H F -
Removing the ONTROL unit ➀ Remove knobs A. A A ➁ Unscrew screws, and remove the cover. ➂ Remove the plate, and remove ONTROL unit. ONTROL UNIT -
SETION IRUIT - REEIVER IRUITS -- TRIPLEXER AND RX AND ITHING IRUITS (MAIN UNIT) The transceiver has a triplexer (low-pass and high-pass filters) on the first stage from the antenna connector to separate the signals into VHF and UHF signals. The RF signals from the antenna connector are applied to the tripler or RX band swtich circuits. RF SIGNALS V-V ( MHz 0 MHz), U-V ( MHz 7 MHz) The V-V and U-V RF signals from the antenna connector pass through the low-pass filter (L7, L77, L0, 0, 09,,, ), and then applied to the TX/RX switching circuit (D, D, D, D7, D09). The filtered signals are amplified at the pre-amplifier (Q), and are applied to the left side or right side displayed RX circuits. RF SIGNALS U-U, V-U (7 MHz 0 MHz) The U-U and V-U RF signals from the antenna connector pass through the high-pass filter (L7, L, 0, 0,, ), and then applied to the TX/RX switching circuit (D, D, D, D00) via the R detector (D0, D). The filtered signals are amplified at the pre-amplifier (Q), and are applied to the left side or right side displayed RX circuits. RF SIGNALS U-U (0 MHz 000 MHz) The U-U RF signals from the antenna connector pass through the two low-pass filters (L7, L77, L0, 0, 09,,,, L7, L, ), and are then applied to the RX band swtiching circuit (D0). The filtered signals are amplified at the RF amplifier (Q), and are applied to the right side displayed RX circuits. RF SIGNALS V0 (7 MHz 0 MHz), V-U ( MHz 7 MHz) The V0 and V-U RF signals from the antenna connector are applied to the RX band swtiching circuit (Q, D, RL), and are applied to the left side displayed RX circuit. -- RF IRUIT FOR LEFT SIDE DISPLAY (MAIN UNIT) RF SIGNALS V-V ( MHz 0 MHz) The amplified signals are applied to the RF amplifier (Q9) after being passed through the attenuator (D9) and bandpass filter (D7, D). The signals are applied to the RX band switching circuit (D) via the another bandpass filter (D, D9) to supress the unwanted signals. RF SIGNALS V0 (7 MHz 0 MHz) The signals are applied to the RF amplifier (Q) after being passed through the RX band switching circuit (D) and bandpass filter (D). The amplified signals are applied to the RX band switching circuit (D) via the another bandpass filter (D) to supress the unwanted signals and attenuator (R9 R97). RF SIGNALS V-U ( MHz 7 MHz) The signals are applied to the RF amplifier (Q) after being passed through the RX band switching circuit (D) and bandpass filter (D9). The amplified signals are applied to the RX band switching circuit (D) via the attenuator (R9 R00) and another bandpass filter (D) to supress the unwanted signals. RF IRUIT FOR LEFT SIDE DISPLAY ANTENNA V-V ( MHz 7 MHz) RX PF RF PF D D, D9 Q9 D7, D ATT D9 PRE Q st mixer (I00) to nd mixer circuit st LO V0 (7 MHz 0 MHz) RX ATT PF RF PF RX D0 D Q D D V-U ( MHz 7 MHz) RX ATT PF RF PF RX D D Q D9 D RX Q, D, RL RX PF RF PF ATT V-U (7 MHz 0 MHz) PRE D9 D, D7 Q0 D, D7 D Q -
RF SIGNALS V-U (7 MHz 0 MHz) The amplified signals are applied to the RF amplifier (Q0) after being passed through the attenuator (D) and bandpass filter (D, D7). The signals are applied to the RX band switching circuit (D9) via the another bandpass filter (D, D7) to supress the unwanted signals. The signals from the RX band swtiching circuits are then applied to the left side displayed st mixer circuit (I00, pin ). -- ST MIXER AND ST IF IRUIT FOR LEFT SIDE DISPLAY (MAIN UNIT) The st mixer circuit converts the received RF signals to a fixed frequency of the st IF signal with a PLL output frequency. y changing the PLL frequency, only the desired frequency will pass through the bandpass filter at the next stage of st mixer circuit. The RF signals are mixed with st LO signals at the st mixer (I00) to produce a. MHz st IF signal. The st IF signal is output from pin, and passed through the crystal bandpass filter (FI00) to suppress unwanted harmonic components. The filtered signal is amplified at the IF amplifier (Q00) after being passed through the limiter circuit (D0). The amplified signal is applied to the nd mixer circuit (I00). -- ND IF AND DEMODULATOR IRUITS FOR LEFT SIDE DISPLAY (MAIN UNIT) The nd mixer circuit converts the st IF signal to a nd IF signal. A double conversion superheterodyne system (which converts receive signal twice) improves the image rejection ratio and obtains stable receiver gain. The FM I I (I00) contains the nd mixer, limiter and noise amplifiers, quadrature detector, S-meter detector, active filter circuits, etc. A nd LO signal (. MHz) is produced at the PLL circuit by dividing it s reference frequency. The. MHz st IF signal from the IF amplifier (Q00) is applied to the nd mixer section of the FM IF I (I00, pin ), and is mixed with the nd LO signal (. MHz) to be converted to a 0 khz nd IF signal. The nd IF signal is applied to the each demodulator circuits by AM or FM mode. FM MODE The nd IF signal is output from the FM IF I (I00, pin ) and passes through the ceramic bandpass filter (FI00). The filtered signal is fed back to the I, and amplified at the limiter amplifier section (pin ), then demodulated into AF signals at the quadrature detector section (pins 0, ). The detected AF signals are output from pin 9 and are applied to the AF circuit via the AM/FM selector circuit (I0, pins 7, ). AM MODE The nd IF signal is output from the FM IF I (I00, pin ) and passes through the ceramic bandpass filter (FI000). The filtered signal is applied to the AM detector circuit (Q07) to convert into AF signals, and then amplified at the Q0 (pins, ). The amplified AF signals are applied to the AF circuit via the AM/FM selector circuit (I0, pins, ). -- AF AMPLIFIER IRUIT FOR LEFT SIDE DISPLAY (MAIN UNIT) The AF amplifier circuit amplifies the demodulated AF signals to drive a speaker. The AF signals pass through the AF mute switch (Q00), and are then applied to the electric volume control circuit (I0, pin ) as VAFO signal after being passed through the low-pass filter (Q007). The level controlled AF signals are output from pin, and are then applied to the AF power amplifier (I0, pin ) via the VOUT signal. The power amplified AF signals are applied to the internal speaker (SP) via the [EXT SP] jack (J00). The electronic volume control circuit controls AF gain, therefore, the AF output level is according to the [VOL] setting and also the squelch conditions. ND IF AND DEMODULATOR IRUIT FOR LEFT SIDE DISPLAY AM AF signal to AM/FM selector R09 R09 09 FM or WFM AF signal to AM/FM selector nd IF filter AM IF 0 khz DET. amp. FI000 0 R 0. MHz 097 FI00 7 R0 07 Active filter FM detector 9 00 Noise detector Limiter amp. 0 0 R 7 R9 RSSI X00 L_R Noise comp. from Q0 Q09 nd Mixer I00 TAF VO UNIT PLL I I X. MHz st IF (. MHz) from Q00 "L_SQL" signal to the PU (I0, pin 0) "L_RSSI" signal to the PU (I0, pin ) -
-- NOISE SQUELH IRUIT FOR LEFT SIDE DISPLAY (MAIN UNIT) NOISE SQUELH A noise squelch circuit cuts out AF signals when no RF signal is received. y detecting noise components in the AF signal, the squelch circuit switches the AF mute switch. A portion of the AF signals from the FM IF I (I00, pin 9) are applied to the active filter section (I00, pin ). The active filter section amplifies and filters noise components. The filtered signals are applied to the noise detector section and output from the I00 (pin ) as the L_SQL signal. The L_SQL signal from I00 (pin ) is applied to the PU (I0, pin 0). The PU analyzes the noise condition and outputs the L_DET_MUTE signal to the AF mute switch (Q00). TONE SQUELH The tone squelch circuit detects AF signals and opens the squelch only when receiving a signal containing a matching subaudible tone (TSS). When tone squelch is in use, and a signal with a mismatched or no subaudible tone is received, the tone squelch circuit mutes the AF signals even when noise squelch is open. A portion of the AF signals from the FM IF I (I00, pin 9) passes through the low-pass filter (Q00) to remove AF (voice) signals. The filtered signal is applied to the TSS decoder which is inside the PU (I0, pin ) via the L_DTS_IN line to control the AF mute switch (Q00). --7 RF IRUIT FOR RIGHT SIDE DISPLAY (MAIN UNIT) RF SIGNALS U-V ( MHz 7 MHz) The amplified signals are applied to the RF amplifier (Q0) after being passed through the attenuator (D0) and bandpass filter (D, D). The signals are applied to the RX band switching circuit (D9) via the another bandpass filter (D, D0) to supress the unwanted signals. RF SIGNALS U-U (0 MHz 000 MHz) The signals are applied to the RF amplifier (Q) after being passed through the RX band switching circuit (D0). The amplified signals pass through the attenuator (L9, 0,,, R7 R0) and high-pass filter (L0, 7, 79), and are then applied to the another RF amplifier (Q) again. The signals pass through the attenuator (L0,, 0, R R) and RX bamd switching circuit (D). RF SIGNALS V-U (7 MHz 0 MHz) The amplified signals are applied to the RF amplifier (Q9) after being passed through the attenuator (D) and bandpass filter (D, D7). The signals are applied to the RX band switching circuit (D) via the another bandpass filter (D, D) to supress the unwanted signals. The signals from the RX band swtiching circuits are then applied to the right side displayed st mixer circuit (I00, pin ). -- ST MIXER AND ST IF IRUIT FOR RIGHT SIDE DISPLAY (MAIN UNIT) The st mixer circuit converts the received RF signals to a fixed frequency of the st IF signal with a PLL output frequency. y changing the PLL frequency, only the desired frequency will pass through the bandpass filter at the next stage of st mixer circuit. The RF signals are mixed with st LO signals at the st mixer (I00) to produce a.0 MHz st IF signal. The st IF signal is output from pin, and passed through the crystal bandpass filter (FI00) to suppress unwanted harmonic components. The filtered signal is amplified at the IF amplifier (Q0) after being passed through the limiter circuit (D0). The amplified signal is applied to the nd mixer circuit (I00). RF IRUIT FOR RIGHT SIDE DISPLAY ANTENNA U-V ( MHz 7 MHz) RX PF RF PF D9 D, D0 Q0 D, D ATT D0 PRE Q st mixer (I00) to nd mixer circuit st LO RX D ATT RF Q HPF U-U (0 MHz 000 MHz) ATT RF RX Q D0 V-U (7 MHz 0 MHz) RX PF RF PF ATT PRE D D, D Q9 D, D7 D Q -
--9 ND IF AND DEMODULATOR IRUITS FOR RIGHT SIDE DISPLAY (MAIN UNIT) The nd mixer circuit converts the st IF signal to a nd IF signal. A double conversion superheterodyne system (which converts receive signal twice) improves the image rejection ratio and obtains stable receiver gain. The FM I I (I00) contains the nd mixer, limiter and noise amplifiers, quadrature detector, S-meter detector, active filter circuits, etc. A nd LO signal (.9 MHz) is produced at the PLL circuit by dividing it s reference frequency. The.0 MHz st IF signal from the IF amplifier (Q0) is applied to the nd mixer section of the FM IF I (I00, pin ), and is mixed with the nd LO signal (.9 MHz) to be converted to a khz nd IF signal. The nd IF signal is applied to the each demodulator circuits by AM or FM mode. FM MODE The nd IF signal is output from the FM IF I (I00, pin ) and passes through the ceramic bandpass filter (FI00). The filtered signal is fed back to the I, and amplified at the limiter amplifier section (pin ), then demodulated into AF signals at the quadrature detector section (pins 0, ). The detected AF signals are output from pin 9 and are applied to the AF circuit via the AM/FM selector circuit (I0, pins 7, ). AM MODE The nd IF signal is output from the FM IF I (I00, pin ) and passes through the ceramic bandpass filter (FI00). The filtered signal is applied to the AM detector circuit (Q0) to convert into AF signals, and then amplified at the Q0 (pins, ). The amplified AF signals are applied to the AF circuit via the AM/FM selector circuit (I0, pins, ). --0 AF AMPLIFIER IRUIT FOR RIGHT SIDE DISPLAY (MAIN UNIT) The AF amplifier circuit amplifies the demodulated AF signals to drive a speaker. The AF signals pass through the AF mute switch (Q0), and are then applied to the electric volume control circuit (I0, pin ) as UAFO signal after being passed through the low-pass filter (Q00). The level controlled AF signals are output from pin 7, and are then applied to the AF power amplifier (I0, pin ) via the VOUT signal. The power amplified AF signals are applied to the internal speaker (SP) via the [EXT SP] jack (J00). When no plug is connected to the jack, the signals are fed back to the UHF audio input (I0, pin ) and combined with the UHF audio. The mixed audio is applied to the other external speaker jack (J00) and then to the internal speaker. The electronic volume control circuit controls AF gain, therefore, the AF output level is according to the [VOL] setting and also the squelch conditions. -- NOISE SQUELH IRUIT FOR RIGHT SIDE DISPLAY (MAIN UNIT) NOISE SQUELH A noise squelch circuit cuts out AF signals when no RF signal is received. y detecting noise components in the AF signal, the squelch circuit switches the AF mute switch. A portion of the AF signals from the FM IF I (I00, pin 9) are applied to the active filter section (I00, pin ). The active filter section amplifies and filters noise components. The filtered signals are applied to the noise detector section and output from the I00 (pin ) as the R_SQL signal. The R_SQL signal from I00 (pin ) is applied to the PU (I0, pin ). The PU analyzes the noise condition and outputs the R_DET_MUTE signal (pin ) to the AF mute switch (Q0). ND IF AND DEMODULATOR IRUIT FOR RIGHT SIDE DISPLAY AM AF signal to AM/FM selector R R7 R FM AF signal to AM/FM selector 0 R7 9 Limiter amp. 0 RSSI nd IF filter khz FI00 0 7 Active filter FM detector R79 AM DET. 0 Q0, Q0 Noise detector R7 X00 R_R Noise comp. nd Mixer X00.9 MHz I00 TAF st IF (.0 MHz) from Q0 "R_SQL" signal to the PU (I0, pin ) "R_RSSI" signal to the PU (I0, pin -
TONE SQUELH The tone squelch circuit detects AF signals and opens the squelch only when receiving a signal containing a matching subaudible tone (TSS). When tone squelch is in use, and a signal with a mismatched or no subaudible tone is received, the tone squelch circuit mutes the AF signals even when noise squelch is open. A portion of the AF signals from the FM IF I (I00, pin 9) passes through the low-pass filter (Q00) to remove AF (voice) signals. The filtered signal is applied to the TSS decoder which is inside the PU (I0, pin 9) via the R_DTS_IN line to control the AF mute switch (Q0). () 00 bps mode The data signals from the J00, pin are applied to the analog switch (I007, pin ) after being passed through the limiter circuit (D0). The signals pass through another analog swtich (I00, pins 0 and ), and are then applied to the ID limiter amplifier section (I000a, pin ). The signals pass through the de-emphasis circuit (0, R00) and splatter filter (I000d, pins, ). The signals are amplified at the buffer amplifier (I000c, pin 9), and are then applied to the D/A convertor I (I009, pin ) to control the modulation level. The AF or data signals are applied to the each VO circuit from the D/A convertor I (I009, pin ) as MOD signal. - TRANSMITTER IRUITS -- MIROPHONE AMPLIFIER IRUIT (MAIN AND ONTROL UNITS) The microphone amplifier circuit amplifies audio signals from the microphone to a level needed for the modulation circuit. The microphone amplifier circuit is commonly used for the both VHF and UHF bands. THE AF SIGNALS FROM THE MAIN UNIT The AF signals from the microphone (J00, pin ) pass through the high-pass filter (Q0), and are then applied to the microphone amplifier (I0, pin ). The amplified signals are applied to the analog switch (I00, pin ). The microphone sensitivity is controlled by the microphone sensitivity controller (Q0) via the MI_SENS line from the PU (I0). THE AF SIGNALS FROM THE ONTROL UNIT The AF signals from the microphone (ONTROL unit; J, pin ) are applied to the microphone amplifier (Q, I pin ). The amplified signals pass through the J, pin via the MI line, and are then applied to the analog switch (I00, pin ). The microphone sensitivity is controlled by the microphone sensitivity controller (Q0) via the MI_SENS line from the PU (I0). The each AF signals (from I00, pins, ) are applied to the ID limiter amplifier section (I000a, pin ), and then pass through the de-emphasis circuit (0, R00). The signals pass through the splatter filter (I000d, pins, ), and are then applied to the buffer amplifier (I000c, pin 9). The amplified signals are applied to the D/A convertor I (I009, pin ) to control the modulation level. THE DATA SIGNALS () 900 bps mode The data signals from the J00, pin are applied to the analog switch (I007, pin ) after being passed through the limiter circuit (D0). The signals pass through another analog swtich (I00, pins 9 and ), and are then applied to the buffer amplifier (I00c, pin 9) via the DATAMOD line. The amplified signals are applied to the D/A convertor I (I009, pin ) to control the modulation level. -- VHF MODULATION IRUIT (MAIN AND VO UNITS) The modulation circuit modulates the oscillating signal (RF signal) using the microphone audio signals. The MOD signal from the D/A convertor I (I009, pin ) changes the reactance of D (VO unit) to modulate the oscillated signal at the VHF-VO circuit (VO unit; Q). The modulated signal is amplified at the buffer amplifiers (VO unit; Q7, Q), and then passes through the VO swtich (VO unit; D, D). The TX LO signal passes through the low-pass filter (L90, L9, 7) and attenuator (, R ), and is then applied to the TX switch (D77) via the VHF_YGR line. The signal is applied to the drive/power amplifier circuits. -- UHF MODULATION IRUIT (MAIN UNIT) The MOD signal from the D/A convertor I (I009, pin ) changes the reactance of D0 to modulate the oscillated signal at the UHF-VO circuit (Q09). The modulated signal is amplified at the buffer amplifiers (Q0, Q07), and then passes through the VO swtich (D09, D00). The TX LO signal passes through the high-pass filter (L079,, ), and is then applied to the TX switch (D7) via the UHF_YGR line. The signal is applied to the drive/power amplifier circuits. -- DRIVE/POWER AMPLIFIER IRUITS (MAIN UNIT) The drive amplifier circuit amplifies the VO oscillated signal to the needed level at the power amplifier. Q7 is a power module which provides stable 0 W (UHF is W) output power with a. V D power source. The RF signal from the TX switch (D77; VHF, D7; UHF) is amplified at the buffer amplifier (Q), and is then applied to the pre-amplifier (Q). The amplified signal is amplified at the pre-drive (Q) and drive amplifier (Q), and then applied to the power amplifier (Q7) to obtain 0 W (UHF is W) of RF power. -
VHF RF SIGNAL The amplified signal passes throught the low-pass filter (D, D070), and is then applied to the R detector (D7, D). The signal is applied to the TX/RX switch (D), and passes through the low-pass filter (L7, L77, L0, 0, 09,,, ) to suppress high harmonics components. The signal is applied to the antenna connector after being passed through the reverse power detector circuit (D70, D7). UHF RF SIGNAL The amplified signal passes throught the TX/RX swtich (D7, D, D, D D, D), and is then applied to the R detector (D0, D). The signal passes through the high-pass filter (L7, L, 0, 0,, ) to suppress high harmonics components. The signal is applied to the antenna connector after being passed through the reverse power detector circuit (D70, D7). The detected voltage at the reverse detector ciruit is applied to the PU (I0, pin ) to switch from high power to middle power automatically when the R become worse. -- AP IRUIT (MAIN UNIT) The AP circuit protects the pre-drive (Q), drive amplifier (Q) and power amplifier (Q7) from a mismatched output load and stabilizes the output power. VHF AP IRUIT The R detector circuit (D7, D) detects forward signals and reflection signals at D7 and D respectively. The impedance is matched at 0 Ω and is increased when it is mismatched. UHF AP IRUIT The R detector circuit (D0, D) detects forward signals and reflection signals at D0 and D respectively. The impedance is matched at 0 Ω and is increased when it is mismatched. The detected voltage is applied to the diffrential amplifier (I, pin ) via the POWER_DET line, and the power setting voltage from the D/A convertor (I, pin ) is applied to another input (I, pin ) for the reference as PWRON line. When antenna impedance is mismatched, the detected voltage exceeds the power setting voltage. The output voltage of the differential amplifier (I, pin ) controls the input current of the pre-drive (Q), drive amplifier (Q) and power amplifier (Q7) to reduce the output power. - PLL IRUITS -- GENERAL A PLL circuit provides stable oscillation of the transmit frequency and the receive local frequency. The PLL circuit compares the phase of the divided VO frequency to the reference frequency. The PLL output frequency is controlled by a crystal oscillator and the divided ratio (N-data) of the programmable divider. -- PLL IRUIT FOR RIGHT SIDE DISPLAY (MAIN UNIT) The R-VO (for right side display) composes of VHF-VO and UHF-VO circuits. FROM THE VHF-VO IRUIT An oscillated signal from the VHF-VO circuit (Q0, D0, D0) passes through the buffer amplifiers (Q0, Q0) and VO switch (D0) is applied to the PLL I for right side display (I00, pin ) FROM THE UHF-VO IRUIT An oscillated signal from the UHF-VO circuit (Q0, D0 D0) passes through the buffer amplifiers (Q0,Q0) and VO switch (D0) is applied to the right side diplayed PLL I (I00, pin ) And is then prescaled in the PLL I based on the divided ratio (N-data). The reference signal is generated at the refenrece oscillator (VO unit; X,. MHz), and is then amplified at the buffer amplifier (Q0). The reference signal is also applied to the PLL I. The PLL I detects the outof-step phase using the reference frequency and outputs it from pin. The output signal is passed through the loop filter (Q00, Q0, D00) and is then applied to the right side display VO circuit as lock voltage. AP IRUIT Q uff. amp. RF signal from PLL circuit Q Pre drive Q7 Drive amp. TX PWRON VHF transmitter signal to antenna VHF R DETETOR (D7, D) I Q TX AP ONTROLLER UHF R DETETOR (D0, D) UHF transmitter signal to antenna -
-- R-VO IRUIT FOR RIGHT SIDE DISPLAY (MAIN UNIT) The VO circuit for right side display contains a separated the VHF-VO (Q0, D0, D0) and UHF-VO (Q09, D0 D0) circuits. VHF-VO (RX ONLY) The oscillated signal at the VHF-VO circuit is amplified at the buffer amplifier (Q0), and then passes through the attenuator (R09 R, ) and low-pass filter (L0, L0, 07, 9, 0, 9, 0). The signal is applied to the st mixer circuit for right side display (I00, pin ) via the VO switch (D0) as the st LO signal. A portion of the signal from the buffer amplifier (Q0) passes through the VO swtich (D0), and is then amplified at the buffer amplifier (Q0). The amplified signal is fed back to the PLL I (I00, pin ) as the comparison signal. UHF-VO The oscillated signal at the UHF-VO circuit is amplified at the buffer amplifiers (Q0, Q07), and is then applied to the VO switch (D09, D00) to divide UHF TX signal and RX signal. () UHF TX SIGNAL The TX UHF signal passes through the high-pass filter (L079,, ) to suppress harmonics components, and is then applied to the TX switch (D7). The signal is applied to the drive/power amplifier circuit. () RX SIGNAL The 00 MHz band RX signal is applied to the another VO switches (D0 and D09), and then passes through the attenuator (R0 R0, ) and low-pass fiilter (L0, L0, ). The filtered signal passes through the VO switch (Q0, D09), and is then applied to the st mixer circuit (I00, pin ) as the st LO signal. The 900 MHz band RX signal passes through the another VO switches (D07 and D0), and is then amplified at the buffer amplifier (Q0). The signal passes through the attenuator (L00, 0, 0) and low-pass fiilter (L0, L0,, 9, 0). The filtered signal passes through the VO switch (D0), and is then applied to the st mixer circuit (I00, pin ) as the st LO signal. A portion of the signal from the buffer amplifier (Q0) passes through the VO swtich (D0), and is then amplified at the buffer amplifier (Q0). The amplified signal is fed back to the PLL I (I00, pin ) as the comparison signal. -- PLL IRUIT FOR LEFT SIDE DISPLAY (VO UNIT) An oscillated signal from the L-VO circuit passes through the buffer amplifiers (Q7, Q) is applied to the PLL I for left side display (I, pin ). PLL IRUIT FOR RIGHT SIDE DISPLAY VHF VO for right side display Q0, D0, D0 Q0 uff. Q07 uff. D09, D00 VO LPF from the PLL circuit for left side display TX D77, D7 to TX amplifier circuit Q00, Q0, D00 Loop filter VHF VO for right side display Q0, D0, D0 Q0 uff. VO D0, D0 I00 (PLL I for right side display) ATT Q0 uff. LPF D0 VO st LO signal to the st mixer ciruict for right side display (I00, pin ) Phase Programmable Prescaler detector divider Programmable reference divider Shift register 9 0 PLLK PLLDATA Q0 uff. PLL I I VO UNIT X. MHz - 7
And is then prescaled in the PLL I based on the divided ratio (N-data). The reference signal is generated at the refenrece oscillator (X,. MHz). The reference signal is also applied to the PLL I. The PLL I detects the out-ofstep phase using the reference frequency and outputs it from pin. The output signal is passed through the loop filter (Q, Q, D) and is then applied to the left side display VO circuit as lock voltage. -- L-VO IRUIT FOR LEFT SIDE DISPLAY (VO AND MAIN UNITS) VHF TX SIGNAL The oscillated signal at the VO circuit is amplified at the buffer amplifiers (Q7 and Q), and then passes through the low-pass filter (MAIN unit; L90, L9, 7) and attenuator (R R, ) via the VO switch (D, D). The signal is applied to the drive/power amlifier circuit (MAIN unit) after being passed through the TX swtich (MAIN unit; D77). RX SIGNAL The oscillated signal at the VO circuit is amplified at the buffer amplifiers (Q7, Q), and is then applied to the VO switch (D7 D9, D). The signal is applied to the normal oscillating signal, twice oscillating signal or harf oscillating signal circuit. () NORMAL OSILLATING SIGNAL IRUIT The signal from the VO swtich (D7) passes through the attenuator (R, R7, R, ) and low-pass filter (L, L9,, 7,,, ), and then applied to the VO swtich (D0) which is controlled by the L_VR signal. () TWIE OSILLATING SIGNAL IRUIT The signal from the VO switch (D9) passes through the high-pass (L,,, 9), low-pass (L,,, 7) and high-pass (L,, ) filters to obtain twice oscillating signal. The signals is applied to the VO switch (D) which is controlled by the L_UR signal. () HARF OSILLATING SIGNAL IRUIT The signal from the VO switch (D) is applied to the prescaler circuit (I, pin ) to divide harf oscillating signal. The divided signal is applied to the VO switch (D). The reglator circuit provides the pre-scaler s power supply. The circuit is controlled by the L_LO_ signal. The signal from the each VO switch is applied to the st mixer circuit for right side display (MAIN unit; I00, pin ) as the st LO signal. A portion of the signal from the buffer amplifier (Q7) is amplified at the buffer amplifier (Q), and is then fed back to the PLL I (I, pin ) as the comparison signal. - POWER SUPPLY IRUITS -- ONTROL UNIT VOLTAGE LINE Line PU Description The. external D power from the power connector (MAIN unit; J000). The voltage is supplied to the LD back light circuit (DS DS), etc. ommon V converted from the line at the + regulator circuit (Q, Q, D). The output voltage is applied to the microphone amplifier regulator circuit (Q), key back light circuit (DS DS). ommon V converted from the line by the + regulator circuit (ONTROL unit; I). The output voltage is applied to the buffer amplifier (ONTROL unit; Q) and reset circuit (ON- TROL unit; I), control unit PU (I) and PTT detector (Q, D, D). PLL IRUIT FOR LEFT SIDE DISPLAY Q, Q, D Loop filter VO for left side display Q, D D VO UNIT Q7 uff. Q uff. Q uff. I (PLL I for left side display) D, D VO D, D VO LPF ATT D77, D7 TX from the PLL circuit for right side display to TX amplifier circuit st LO signal to the st mixer circuit for right side display Phase Programmable Prescaler detector divider Programmable reference divider Shift register 9 0 PLLK PLLDATA MAIN UNIT X. MHz Q009, Q0. MHz nd LO signal to the FM IF I for left side display (I00, pin ) -
-- MAIN UNIT VOLTAGE LINE MAIN UNIT VOLTAGE LINE ontinued Line V V VT UT VUT L_AM Description The. external D power from the power connector. The same voltage as the line which is controlled by the V regulator circuit (MAIN unit; Q00). When the [POWER] switch is pushed, the PU outputs control signal to the power switch controller (Q00) to turn the circuit ON. ommon V for the PU converted from the line by the V regulator circuit (I00). The voltage line is also applied to the PU when I- 70H is power OFF. ommon V converted from the V line at the + regulator circuit (I00). ommon V produced from the V line by the + regulator circuit (Q00, D0). The output signal is applied to the PTT detector (Q00), mic amplifier (I0, Q0), etc.vhf transmit. V produced from the line at the VT regulator circuit (Q9, Q). UHF transmit produced from the line at the UT regulator circuit (Q0, Q). VHF and UHF transmit V produced from the V line at the VUT regulator circuit (Q, D). The output voltage is applied to the buffer amplifier (Q), pre-amplifier (Q) and pre-driver (Q). Receive V produced from the line at the L_R regulator circuit (Q000). The output voltage is applied to the AM detector for left side display (Q0, Q07). Line L0_R L00_R R00_R L00_R R00_R L_VO PU Description Receive V produced from the line at the R_AM regulator circuit (Q). The output voltage is applied to the RF amplifier (Q) for left side display s 0 MHz bandpass filter. Receive V produced from the line at the L_AM regulator circuit (Q). The output voltage is applied to the RF amplifier (Q) for right side display s 00 MHz bandpass filter. Receive V produced from the line at the R_R regulator circuit (Q). The output voltage is applied to the RF amplifier (Q9) for right side display s 0 MHz bandpass filter. Receive V produced from the line at the R_AM regulator circuit (Q). The output voltage is applied to the RF amplifier (Q0) for left side display s 0 MHz bandpass filter. Receive V produced from the line at the L_AM regulator circuit (Q). The output voltage is applied to the RF amplifier (Q, Q) for right side display s 90 MHz bandpass filter. ommon V produced from the V line by the + regulator circuit (Q0). The output voltage is applied to the VO circuit (RF unit; Q, D D) and buffer amplifier (RF unit; Q). ommon V converted from the line by the + regulator circuit (ONTROL unit; I). The output voltage is applied to the buffer amplifier (ONTROL unit; Q) and reset circuit (ON- TROL unit; I). R_AM L_R R_R L0_R R0_R Receive V produced from the line at the R_R regulator circuit (Q00). The output voltage is applied to the AM detector for right side display (Q0, Q0). Receive V produced from the line at the L_AM regulator circuit (Q00). The output voltage is applied to the IF amplifier (Q00) and FM IF I (I00) for left side display. Receive V produced from the line at the R_AM regulator circuit (Q00). The output voltage is applied to the IF amplifier (Q0) and FM IF I (I00) for right side display. Receive V produced from the line at the L_R regulator circuit (Q). The output voltage is applied to the RF amplifier (Q9) for left side display s MHz bandpass filter. Receive V produced from the line at the R_R regulator circuit (Q). The output voltage is applied to the RF amplifier (Q0) for right side display s MHz bandpass filter. -- VO UNIT VOLTAGE LINE Line L_VO Description ommon V converted from the V line at the + regulator circuit (MAIN unit; I00). The output voltage is applied to the filter switch (I), loop filter (Q, Q, D) and buffer amplifier (Q). ommon V produced from the V line by the + regulator circuit (MAIN unit; Q00, D0). The output voltage is applied to the PTT I (I) and regulator circuit (Q9). ommon V produced from the V line by the + regulator circuit (Q0). The output voltage is applied to the VO circuit (RF unit; Q, D D) and buffer amplifier (RF unit; Q). - 9
- PORT ALLOATIONS -- PU (MAIN UNIT; I0) Pin number 0 7 0 7 9 0 9 0 7 Port name UMMUTE K_SHIFT TX_MUTE MI_PTT SU_SEL UTX_TRL VTX_TRL DTS_SEL ES_DATA ES_K P_PTT P_MOD_MUTE 9_DATA MI_U/D M_MUTE MI_SEL R_RSSI L_RSSI TEMP REV_DET R_SQL R_DTS_IN L_SQL L_DTS_IN DTMF DTS P_SQL Description Outputs microphone mute signal for right side display. Low: While microphone is muting. Output clock shift signal. Outputs transmit mute control signal. High:While transmit is muting. Input port for microphone s PTT detecting signal. Outputs sub band select signal. Outputs RF transmit power supply circuit control signal for left side display. High:While transmitting 00 79 MHz. Outputs RF transmit power supply circuit control signal for right side display. High:While transmitting 7 MHz. Outputs DTS filter select signal. I/O port the data signal from/to the EEPROM (I000, pin ). Outputs clock signal to the EEPROM (I000, pin ). Input port for PTT detect signal in packet mode. Outputs modulation mute signal on packet mode Low: While packet mod. is muting. Input port for data signal from HM-9. Input port for up/down signal from the microphone. Outputs the microphone mute signal to the ONTROL unit. Low: While the microphone is muting. Input port for the connecting microphone detect signal for HM-9. Low: While HM-9 is connecting. Input port for the RSSI signal from the FM IF I (I00, pin ) to detect receiving signal strength for right side display. Input port for the RSSI signal from the FM IF I (I00, pin )to detect receiving signal strength for left side display. Input port for chassis temperature detecting signal. Input port for the reverse power detecting signal. Input port for the squelch level for right side display. Input port for the DTS or TSS signal for right side display. Input port for the squelch level for the left side display. Input port for the DTS or TSS signal for left side display. Outputs DTMF, E-tone, beep signals. Outputs DTS and TSS signals Outputs the packet squelch signal. Pin number 9 0 7 0 7 9 7 7 7 Port name FAN_TRL LONE_OUT LONE_IN D/A_DATA D/A_K D/A_ST Description Outputs cooling fan control signal. Outputs the cloing data signal. Input port for the cloing data signal. Outputs serial data to the D/A converter I (I, pins 7). Outputs microphone mute control signal for MAIN unit. MM_MUTE Low: While the microphone is muting. Outputs AF mute control signal for left L_AF_MUTE side display. High:While AF audio is muting. Outputs AF mute control signal for right R_AF_MUTE side display. High:While AF audio is muting. Outputs detector mute signal for left L_DET_MUTE side display. Outputs detector mute signal for right R_DET_MUTE side display. AF_VOL_K Outputs the volume serial signal. AF_VOL_DATA Outputs the RX RF power supply control signal for left side display. L_RTRL Outputs the VO select signal for right side display. R_UVO_SEL High:While receiving 0 999.9 MHz on right side display. Input port for the PLL unlock signal for left side display (VO unit; I, pin 7). L_UNLOK Low: The PLL Lock voltage is unlock for left side display. Outputs 00or 900 bps packet baud 00/900SEL rate select signal. Low: 900 bps baud rate is selected. Outputs the 00 MHz receiver circuit select signal for left side display. L_RX00 High:While receiving 0 0 MHz on left side display. Outputs the 00 MHz receiver circuit select signal for left side display. L_RX00 High:While receiving 0 09.99 MHz on left side display. Outputs receive mode select signal for L_AM left side display. Low: AM mode is selected. Outputs receive mode select signal for R_AM right side display. Low: AM mode is selected. Outputs the 0 MHz receiver circuit select signal for left side display. R_RX0 Low: While receiving 7.99 MHz on left side display. Outputs the MHz receiver circuit select signal for left side display. L_RX0 Low: While receiving 7.99 MHz on left side display. Outputs the 00 MHz receiver circuit select signal for right side display. R_RX00 Low: While receiving 0 999.990 MHz on right side display. - 0
PU-ontinued Pin number 7 7 77 7 79 0 9 90 9 9 9 9 9 Port name L_00SHIFT R_RX00 R_RX0 LR_RTRL L_VO_SHIFT R00_SHIFT R_VVO_SEL L_PLL R_PLL R_UNLOK P_L/R_SEL MATRIX_IN MATRIX_IN PLLDATA PLLK MATRIX_OUT MATRIX_OUT MATRIX_OUT MATRIX_OUT Description Outputs shift signal to the 0 MHz bandpass filter for left side display. High:While receiving 0 0 MHz on left side display. Outputs the 0 MHz receiver circuit select signal for right side display. Low: While receiving 0 9.990 MHz on right side display. Outputs the MHz receiver circuit select signal for right side display. Low: While receiving 7 MHz on right side display. Outputs the RX RF power supply control signal for right side display. High:While receiving on left side display. Outputs the VO select signal for left side display. High:While transmitting 00 79 MHz on left side display. Outputs 0 MHz bandpass filter shift signal for right side display. High:While receiving 0 0 MHz on right side display. Output VO select signal for right side display. High:While receiving 7 MHz on right side display. Outputs PLL loop select signal for right side display. Outputs PLL loop select signal for left side display. Input port for the PLL unlock signal for right side display (I00, pin 7). Low: The PLL lock voltage is unlocked for right side display. Outputs packet band select signal. Input ports for Initial matrix. Outputs serial signal to the PLL I (I00, pins 9, 0 and VO unit; I, pins 9, 0). Outputs Initial matrix signal. -- D/A ONVERTER I (ONTROL UNIT; I) Pin number, 7 9, 9 Port name R_PF R_PF L_PF, L_PF, L_PF, L_PF L-ATT R-ATT PWRON R-PF, R-PF Description Output tracking signals to the bandpass filter for right side display. Output tracking signals to the bandpass filter for left side display. Outputs the attenuator circuit control signal for left side display. Outputs the attenuator circuit control signal for right side display. Outputs control signal for RF output power. Output tracking signals to the bandpass filter for right side display. -
SETION PARTS LIST [ONTROL UNIT] I 00070 S.I TA7S0F (TER) I 00070 S.I S-09LM-G7F-T I 00000 S.I TA7L0F (TER) I 0000 S.I HD77RH (FX-9D) I 000770 S.I TA7SF (TEL) Q Q Q Q Q Q7 Q Q9 Q0 Q Q Q Q Q 00090 S.TRANSISTOR S-GR (TER) 90000 S.TRANSISTOR XP0 (TX) 0000770 S.TRANSISTOR SA-GR (TER) 00090 S.TRANSISTOR S-GR (TER) 00090 S.TRANSISTOR S-GR (TER) 00090 S.TRANSISTOR S-GR (TER) 00090 S.TRANSISTOR S-GR (TER) 00090 S.TRANSISTOR S-GR (TER) 00090 S.TRANSISTOR S-GR (TER) 00090 S.TRANSISTOR S-GR (TER) 00090 S.TRANSISTOR S-GR (TER) 00090 S.TRANSISTOR S-GR (TER) 00090 S.TRANSISTOR S-GR (TER) 00090 S.TRANSISTOR S-GR (TER) D 70000 S.ZENER MA09-M (TX) D 70000 S.ZENER MA07-M (TX) D 700000 S.DIODE SS TE-7 D 79000000 S.ZENER MA0-L (TX) X 000000 S.ERAMI EFOS9E R 700090 VARIALE EVU-FAF0 (0K) R 700000 S.RESISTOR ERJGEYJ 0 V ( kω) R 700090 VARIALE EVU-FAF0 (0K) R 700000 S.RESISTOR ERJGEYJ 0 V ( kω) R 700090 VARIALE EVU-FAF0 (0K) R 700000 S.RESISTOR ERJGEYJ 0 V ( kω) R7 700090 VARIALE EVU-FAF0 (0K) R 700000 S.RESISTOR ERJGEYJ 0 V ( kω) R9 700000 S.RESISTOR ERJGEYJ 7 V (7 kω) R0 700000 S.RESISTOR ERJGEYJ 7 V (7 kω) R 700000 S.RESISTOR ERJGEYJ 7 V (7 kω) R 700000 S.RESISTOR ERJGEYJ 7 V (7 kω) R 700000 S.RESISTOR ERJGEYJ 7 V (.7 kω) R 700000 S.RESISTOR ERJGEYJ 7 V (7 kω) R 70000 S.RESISTOR ERAYKD V (0 kω) R 700000 S.RESISTOR ERAYKD V (0 kω) R7 700009 S.RESISTOR ERAYED V R 700000 S.RESISTOR ERJGEYJ 0 V (0 kω) R9 70000000 S.RESISTOR MR0EZHJ Ω (00) R0 700000 S.RESISTOR ERJGEYJ 7 V (.7 kω) R 700000 S.RESISTOR ERJGEYJ 7 V (.7 kω) R 7000070 S.RESISTOR ERJGEYJ 7 V (70 kω) R 700000 S.RESISTOR ERJGEYJ 0 V (0 kω) R 700000 S.RESISTOR ERJGEYJ 7 V (.7 kω) R 700000 S.RESISTOR ERJGEYJ 0 V (0 kω) R 700000 S.RESISTOR ERJGEYJ 7 V (.7 kω) R7 7000070 S.RESISTOR ERJGEYJ 7 V (70 kω) R 700000 S.RESISTOR ERJGEYJ 7 V (.7 kω) R9 700000 S.RESISTOR ERJGEYJ 0 V (0 kω) R0 700000 S.RESISTOR ERJGEYJ 0 V ( kω) R 700000 S.RESISTOR ERJGEYJ V (. kω) R 7000000 S.RESISTOR ERJGEYJ V ( kω) R 700000 S.RESISTOR ERJGEYJ 0 V (0 kω) R9 700000 S.RESISTOR ERJGEYJ 0 V (00 kω) R 7000000 S.RESISTOR ERJGEYJ 0 V ( MΩ) R 700000 S.RESISTOR ERJGEYJ 0 V ( kω) R 700000 S.RESISTOR ERJGEYJ 0 V ( kω) R 700000 S.RESISTOR ERJGEYJ 0 V ( kω) R 7000090 S.RESISTOR ERJGEYJ 9 V (90 Ω) R 700000 S.RESISTOR ERJGEYJ 0 V ( kω) R7 700000 S.RESISTOR ERJGEYJ 0 V ( kω) R 700000 S.RESISTOR ERJGEYJ 0 V ( kω) R9 7000090 S.RESISTOR ERJGEYJ 9 V (90 Ω) R0 700000 S.RESISTOR ERJGEYJ 0 V ( kω) [ONTROL UNIT] R 700000 S.RESISTOR ERJGEYJ 0 V ( kω) R 700000 S.RESISTOR ERJGEYJ 0 V ( kω) R 7000090 S.RESISTOR ERJGEYJ 9 V (90 Ω) R 700000 S.RESISTOR ERJGEYJ 0 V ( kω) R 700000 S.RESISTOR ERJGEYJ 0 V ( kω) R 700000 S.RESISTOR ERJGEYJ 0 V ( kω) R7 7000090 S.RESISTOR ERJGEYJ 9 V (90 Ω) R 700000 S.RESISTOR ERJGEYJ 0 V (00 kω) R9 700000 S.RESISTOR ERJGEYJ 0 V (00 kω) R0 700000 S.RESISTOR ERJGEYJ 0 V (00 kω) R 700000 S.RESISTOR ERJGEYJ V ( kω) R 700000 S.RESISTOR ERJGEYJ 0 V ( kω) R 700000 S.RESISTOR ERJGEYJ 7 V (.7 kω) R 700000 S.RESISTOR ERJGEYJ 7 V (.7 kω) R 7000090 S.RESISTOR ERJGEYJ 9 V (90 Ω) R 7000090 S.RESISTOR ERJGEYJ 9 V (90 Ω) R7 700000 S.RESISTOR ERJGEYJ V (0 Ω) R7 700000 S.RESISTOR ERJGEYJ 0 V ( kω) R7 700000 S.RESISTOR ERJGEYJ 0 V (0 kω) R7 700000 S.RESISTOR ERJGEYJ 0 V (0 kω) R7 700000 S.RESISTOR ERJGEYJ 0 V (0 kω) R7 700000 S.RESISTOR ERJGEYJ 0 V (0 kω) R7 700000 S.RESISTOR ERJGEYJ V ( kω) R77 700000 S.RESISTOR ERJGEYJ V ( kω) R7 700000 S.RESISTOR ERJGEYJ 7 V (.7 kω) R79 700000 S.RESISTOR ERJGEYJ 7 V (.7 kω) R0 700000 S.RESISTOR ERJGEYJ V (. kω) R 7000000 S.RESISTOR ERJGEYJ V ( kω) R 7000000 S.RESISTOR ERJGEYJ V ( kω) R 700000 S.RESISTOR ERJGEYJ V ( kω) R 7000070 S.RESISTOR ERJGEYJ 7 V (70 kω) R 7000000 S.RESISTOR ERJGEYJ V (. kω) 00000 S.ERAMI 0 J H 7K-T 00000 S.ERAMI 0 J H 7K-T 00000 S.ERAMI 0 J H 7K-T 00000 S.ERAMI 0 J H 7K-T 000070 S.ERAMI 0 H H 0J-T 00007090 S.ERAMI 0 H H 70J-T 7 000070 S.ERAMI 0 H H 0J-T 000070 S.ERAMI 0 H H 0J-T 0 000070 S.ERAMI 0 H H 0J-T 00000 S.ERAMI 0 J E 0K-T 00000 S.ERAMI 0 J H 0K-T 00000 S.ERAMI 0 J H 0K-T 00000 S.ERAMI 0 J H 0K-T 00000 S.ERAMI 0 J H 0K-T 00000 S.ERAMI 0 J H 0K-T 9 00000 S.ERAMI 0 J H 0K-T 0 0000 S.ELETROLYTI EEVA70SP 00000 S.ERAMI 0 J H 0K-T 00000 S.ERAMI 0 J A 0M-T 0000 S.ELETROLYTI EEVA00SR 00000 S.ERAMI 0 J H 0K-T 0000900 S.ERAMI 0 J H 0K-T 7 00000 S.ERAMI 0 J H 0K-T 0000 S.ELETROLYTI EEVA00SR 9 00000 S.ERAMI 0 J H 0K-T 0 00007090 S.ERAMI 0 H H 70J-T 00007090 S.ERAMI 0 H H 70J-T 00000 S.ERAMI 0 J H 0K-T 00000 S.ERAMI 0 J H 0K-T 0000900 S.ERAMI 0 J H 0K-T 00000 S.ERAMI 0 J E 0K-T 00000 S.ERAMI 0 J E 0K-T 7 00000 S.ERAMI 0 J E 0K-T 9 00000 S.ERAMI 0 J E 0K-T 0 00000 S.ERAMI 0 J E 0K-T 00000 S.ERAMI 0 J E 0K-T 00000 S.ERAMI 0 J H 0K-T 00000 S.ERAMI 0 J H 0K-T 00000 S.ERAMI 0 J H 0K-T 00000 S.ERAMI 0 J H 0K-T 000090 S.ERAMI 0 J H 9K-T 7 000090 S.ERAMI 0 J H 9K-T S.=Surface mount -
[ONTROL UNIT] 00000 S.TANTALUM TESVA V 0M-L 9 00090 S.TANTALUM TEMSVA A 7M-L 0 0000 S.TANTALUM TEMSVA E 0M-L 0000 S.TANTALUM TEMSVA A 0M-L J 000 ONNETOR 00L-P J 0070 ONNETOR 00L-P DS 000070 S.LED SML-00MT T DS 000070 S.LED SML-00MT T DS 000070 S.LED SML-00MT T DS 000000 S.LED SML-00MLT T DS 000000 S.LED SML-00MLT T DS 000000 S.LED SML-00MLT T DS7 000070 S.LED SML-00MT T DS 000070 S.LED SML-00MT T DS9 000070 S.LED SML-00MT T DS0 000000 S.LED SML-00MLT T DS 000000 S.LED SML-00MLT T DS 000000 S.LED SML-00MLT T DS 000000 S.LED LN7G-(TR) DS 000000 S.LED LN7G-(TR) DS 000000 S.LED LN7G-(TR) DS 000000 S.LED LN7G-(TR) DS7 000000 S.LED LN7G-(TR) DS 000000 S.LED LN7G-(TR) DS9 00000 LD L-000TAM S 00000 ENODER EVQ-VENF0 S 00000 ENODER EVQ-VENF0 EP 9000 S.EAD MMZ0Y 0T EP 9000 S.EAD MMZ0Y 0T EP 9000 S.EAD MMZ0Y 0T EP 9000 S.EAD MMZ0Y 0T EP 9000 S.EAD MMZ0Y 0T EP 9000 S.EAD MMZ0Y 0T EP7 9000 S.EAD MMZ0Y 0T EP 9000 S.EAD MMZ0Y 0T EP9 9000 S.EAD MMZ0Y 0T EP0 9000 S.EAD MMZ0Y 0T EP 9000 S.EAD MMZ0Y 0T EP 9000 S.EAD MMZ0Y 0T EP 9000 S.EAD MMZ0Y 0T EP 9000 S.EAD MMZ0Y 0T EP 90070 LD ONTAT SRN-9-SP-N-W EP 090097 P 7 EP7 9000 S.EAD MMZ0Y 0T [MAIN UNIT] I 0000 S.I MGP 7E I 00070 S.I TA7S0F (TER) I000 0000 S.I NJM90V-TE I00 00000 S.I TAFN (EL) I00 00000 S.I TSF (TER) I00 00000 S.I TAFN (EL) I00 0000 S.I GN009-0L I00 0000 S.I GN009-0L I00 000990 S.I MA0PFV-G-ND-ER I009 900000 S.I MFP-0 I000 0000 S.I HNXTI I00 000990 S.I S-09NM-G9F-T I00 000070 S.I TA70F (TEL) I00 0000 S.I TA70F (TEL) I00 00070 S.I TA7S0F (TER) I007 000090 S.I U0FV-E I00 000090 S.I U0FV-E I009 00070 S.I TSF (TER) I00 000090 S.I U0FV-E I0 00090 S.I M9FP 700 I0 0000 I LA I0 0000 S.I HDFAFA0 (FX-9 EXP) I0 000770 S.I TA7SF (TEL) I0 0000 S.I TWFU (TEL) I0 0000 S.I TWFU (TEL) Q 900000 S.TRANSISTOR DTAYUA T0 Q 900000 S.TRANSISTOR DTAYUA T0 Q 900000 S.TRANSISTOR DTAYUA T0 Q 900000 S.TRANSISTOR DTAYUA T0 Q 900000 S.TRANSISTOR DTAYUA T0 Q 900000 S.TRANSISTOR DTAYUA T0 Q 900000 S.TRANSISTOR DTAYUA T0 Q9 900000 S.TRANSISTOR DTEUA T0 Q0 900000 S.TRANSISTOR DTEUA T0 Q 000070 S.TRANSISTOR SA-GR (TER) Q 000070 S.TRANSISTOR SA-GR (TER) Q 00000 S.TRANSISTOR S T00 R Q 0000 S.TRANSISTOR S-L (TER) Q 0000 S.TRANSISTOR S-L (TER) Q 000090 S.FET SK Q 00070 S.TRANSISTOR SVH-TL Q9 000070 S.FET SK0 (TEL) Q0 000070 S.FET SK0 (TEL) Q 0000 S.FET SK7 (TEL) Q 9000070 S.TRANSISTOR DTAEUA T0 Q 0000 S.TRANSISTOR S-L (TER) Q 000070 S.FET SK7 (TEL) Q 00000 S.FET SK07 (TEL) Q 0000 S.TRANSISTOR S-L (TER) Q7 00090 FET RD70F Q 900000 S.TRANSISTOR DTEUA T0 Q9 00000 S.FET SK7-(TX) Q0 00000 S.FET SK7-(TX) Q 00070 S.TRANSISTOR SVH-TL Q 00070 S.TRANSISTOR SVH-TL Q 00000 S.FET SK7-(TX) Q 0000 S.TRANSISTOR S-L (TER) Q 0000 S.TRANSISTOR S00-T Q 00090 S.TRANSISTOR S-T R Q000 900000 S.TRANSISTOR DTAYUA T0 Q00 900000 S.TRANSISTOR DTEUA T0 Q00 900000 S.TRANSISTOR DTAYUA T0 Q00 90000 S.TRANSISTOR XP0 (TX) Q00 90000 S.TRANSISTOR XP0 (TX) Q00 900000 S.TRANSISTOR DTAZUA T0 Q00 900000 S.TRANSISTOR DTAZUA T0 Q007 900090 S.TRANSISTOR XP0-(TX).A Q00 900090 S.TRANSISTOR XP0-(TX).A Q009 0000 S.TRANSISTOR S-Y (TER) Q00 90000 S.FET SJ-GR (TER) Q0 90000 S.FET SJ-GR (TER) Q0 0000 S.TRANSISTOR S-L (TER) Q0 9000070 S.TRANSISTOR DTAEUA T0 Q0 900090 S.TRANSISTOR XP0-(TX).A Q0 0000 S.TRANSISTOR S0--TL Q07 900090 S.TRANSISTOR XP0-(TX).A Q00 0000770 S.TRANSISTOR SA-GR (TER) Q0 00090 S.TRANSISTOR S-GR (TER) Q0 900090 S.TRANSISTOR XP0-(TX).A Q0 0000 S.TRANSISTOR S-L (TER) S.=Surface mount -