SRVIC MANUAL MULTIBAND FM TRANSCIVR
INTRODUCTION This service manual describes the latest service information for the IC-TA/ at the time of publication. MODL IC-TA IC-T VRSION U.S.A. Australia S..Asia urope U.K. Italy SYMBOL USA- AUS SA UR UK ITA To upgrade quality, all electrical or mechanical parts and internal circuits are subject to change without notice or obligation. DANGR NVR connect the transceiver to an AC outlet or to a DC power supply that uses more than V. Such a connection could cause a fire hazard and/or electric. DO NOT expose the transceiver to rain, snow or any liquids. DO NOT reverse the polarities of the power supply when connecting the transceiver. DO NOT apply an RF signal of more than 0 dbm (00mW) to the antenna connector. This could damage the transceiver's front end. ORDRING PARTS Be sure to include the following four points when ordering replacement parts:. 0-digit order numbers. Component part number and name. quipment model name and unit name. Quantity required <SL ORDR> 0000 S.IC TBFN IC-TA/ RF UNIT pieces 0000 Screw PH BT Mx0 ZK IC-TA/ Chassis 0 pieces Addresses are provided on the inside back cover for your convenience. RPAIR NOTS. Make sure a problem is internal before disassembling the transceiver.. DO NOT open the transceiver until the transceiver is disconnected from its power source.. DO NOT force any of the variable components. Turn them slowly and smoothly.. DO NOT short any circuits or electronic parts. An insulated turning tool MUST be used for all adjustments.. DO NOT keep power ON for a long time when the transceiver is defective.. DO NOT transmit power into a signal generator or a sweep generator.. ALWAYS connect a 0 db to 0 db attenuator between the transceiver and a deviation meter or spectrum analyzer when using such test equipment.. RAD the instructions of test equipment thoroughly before connecting equipment to the transceiver.
TABL OF CONTNTS SCTION SPCIFICATIONS SCTION INSID VIWS SCTION DISASSMBLY INSTRUCTIONS SCTION CIRCUIT DSCRIPTION - RCIVR CIRCUITS.....................................................- - TRANSMITTR CIRCUITS.................................................- - PLL CIRCUITS...........................................................- - POWR SUPPLY CIRCUITS................................................- - PORT ALLOCATIONS.....................................................- SCTION ADJUSTMNT PROCDURS - PRPARATION..........................................................- - PLL ADJUSTMNT.......................................................- - RCIVR ADJUSTMNT..................................................- - TRANSMITTR ADJUSTMNT..............................................- SCTION PARTS LIST SCTION MCHANICAL PARTS AND DISASSMBLY SCTION SMI-CONDUCTOR INFORMATION SCTION BOARD LAYOUTS - LOGIC UNIT............................................................- - RF UNIT...............................................................- - VCO BOARD............................................................- SCTION 0 BLOCK DIAGRAM SCTION VOLTAG DIAGRAM - LOGIC UNIT............................................................- - RF UNIT...............................................................-
SCTION SPCIFICATIONS M GNRAL Frequency range : Version 0 MHz MHz 0 MHz 00 MHz. MHz (RX only) U.S.A. 0. TX: RX:.* TX: 0 0* 0 00 RX: 00.* 0.* Australia 0. 0 0 0 00 0.* S..Asia 0. TX:.* RX:.* 00.* 0 00 0.* urope, U.K. 0 0 0 0 00 0.* Italy 0 TX:.* RX:.* 00.* 0 00 0.* * Specifications guaranteed MHz, * Specifications guaranteed 0 0 MHz * Specifications guaranteed 0 0 MHz, * Not guaranteed Mode No. of memory channels Frequency stability Tuning steps Usable tempareture range Usable battery pack/case Power supply requirement Polarity Frequency resplution : FM and AM (RX only), WFM (Rx only) : (incl. 0 pairs of scan edges and call channels) : ± ppm max. ( 0 C to 0 C; F to 0 F) : *, 0,., *, 0,, 0, 0 and 00 khz *Not available for 00 MHz band : 0 C to 0 C; F to 0 F : BP-, BP-, BP-00 and BP- :. V DC or specified battery pack : Negative ground : khz and. khz (0 khz and. khz for 00 MHz band) Current drain (at. V DC) : (typical value) 0/ MHz 0 MHz 00 MHz TX High power Low power. A 0. A. A 0. A 0. A 0. A Rated output 0 ma RX Standby 0 ma (at. V) Power saved 0 ma (at. V) Anntena connector : SMA (0 Ω) Dimensions (projections not included) : (W) 0(H).(D) mm; (W) (H) (D) in Weight (with BP-/Ant.) : 0 g; 0. oz M TRANSMITTR Output power (at. V DC) : High.0 W typical (.0 W at 00 MHz band) Low.0 W typical (0. W at 00 MHz band) Modulation system Max. freq. deviation Spurious missions xternal MIC connector : Variable reactance modulation : ± khz : Less than 0 db (0 MHz, MHz and 0 MHz) Less than 0 db (other) Less than 0 db (urope version at 00 MHz) : -conductor.(d) mm ( ); kω -
M RCIVR Receiver system : Double-conversion superheterodyne Intermediate frequency : st. MHz (. MHz: WFM) nd 0 khz Sensitivity* : (except spurious points; typical values) Band FM AM WFM 0 MHz 0. µv 0. µv MHz 0. µv 0 MHz 0. µv 00 MHz 0. µv. MHz.0 µv * FM and WFM are measured at db SINAD, AM is measured at 0 db S/N. Squelch sensitivity : 0,, 0 MHz Less than 0. µv (Threshold) 00 MHz Less than 0. µv (Threshold) AM (0 MHz only) Less than 0. µv (Threshold) WFM Less than. µv (Threshold) Selectivity (except WFM) : More than khz/ db Less than 0 khz/ 0 db Spurious and image rejection ratio : 0, MHz More than 0 db 0 MHz More than 0 db 00 MHz More than db (except half IF, nd image, 0 MHz band IF and WFM) Audio output power : 0 mw typical at 0 % distortion with an Ω load All stated specifications are subject to change without notice or obligation. -
SCTION INSID VIWS LOGIC UNIT BOTTOM VIW Crystal filter (X: CR-.0MH) CPU (IC: MMLGP) AF volume (IC0: MFP) AF power amplifier (IC0: TAF) AF mute switch (Q: SJ) IF IC (IC0: TAFN) RF UNIT TOP VIW BOTTOM VIW Power amplifier (Q: SK0) Drive amplifier (Q: MRF) APC sensor drive amplifier Q: UN ( Q: XP0 ) WFM RF amplifier circuit APC control circuit st mixer (IC0: µpct) PLL IC (IC0: µpd0g) VCO circuit -
SCTION DISASSMBLY INSTRUCTIONS RMOVING TH CHASSIS PANL Remove knob A, and unscrew nut B. Unscrew screws C. Remove the chassis panel in the direction of the arrow. RMOVING TH SHILD PLAT Unsolder 0 points, F, to separate the shield plate and LOGIC unit. B Chassis panel C F Shield plate A F F LOGIC unit RMOVING TH LOGIC UNIT Remove the sealing rubber. Unsolder point, D, to separate a SNSOR control. Unscrew screws,. Unplug J to separate LOGIC unit and RF unit. Remove the LOGIC unit in the direction of the arrow. RMOVING TH RF UNIT Unsolder point, G, to separate [ANT] plug. Unscrew screws, H, to separate the RF unit. Remove the RF unit in the direction of the thick arrow. D D H Sealing rubber J G H [ANT] plug LOGIC unit RF unit Chassis panel -
SCTION CIRCUIT DSCRIPTION - RCIVR CIRCUITS -- DUPLXR CIRCUIT (RF UNIT) The transceiver has a duplexer (low-pass and high-pass filters) on the frist stage from the antenna connector to separate the signals into below UHF and SHF signals. The highpass filter (L L, C C and C C0) is for SHF (00 MHz) signal and the low-pass filter (C, C0, C C and L L) is for below UHF (0 MHz, MHz, 0 MHz and WFM) signals. The filtered SHF signal is applied to the low-pass fileter (C C, L and L). The RF signals below UHF pass through the duplexer circuit and are separated into VHF (0 MHz, MHz and WFM band) and UHF (0 MHz band) signals. The high-pass filter (C C, L, L) is for UHF (0 MHz band) signal and the low-pass filter (C C0, L0 L) is for VHF (0 MHz, MHz and WFM band) signals. The VHF signals are applied to the another duplexer circuit for separation into 0 MHz and above WFM band signals. The high-pass filter (C C, C and L L) is for MHz and WFM band signals and the low-pass filter (C C and L L) is for 0 MHz band signal. The separated signals are applied to each RF circuits. -- ANTNNA ITCHING CIRCUITS (RF UNIT) The antenna switching circuit functions as a low-pass filter while receiving. However, its impeadance becomes very high while transmitting by applying a current to D0 and D0 (0 MHz), D0 and D0 (MHz and WFM), D0 and D0 (0 MHz), D and D (00 MHz). Thus, transmit signals are blocked from entering the receiver circuits. The antenna switching circuit employs a /λ type diode switching system. The passed signals are then applied to each RF amplifier circuit. -- 0 MHz BAND RF CIRCUIT (RF UNIT) The RF circuit amplifies signals within the range of frequency coverage and filters out-of-band signals. The signals from the antenna switching circuit (D0 and D0) are amplified at the RF amplifier (Q0). The amplified signals pass through the tunable bandpass filter (L0 L0, C, C, C0, D0, D0) to suppress out-of-band signals, and are then applied to the st mixer circuit (IC0, pin ). -- MHz AND WFM BANDS RF CIRCUITS (RF UNIT) The signal from the antenna switching circuit (D0, D0) are applied to the each band-pass fileters and RF amplifier. RF signals MHz band The MHz band signals are applied to the RF amplifier (Q0) via the tunable bandpass filter (L0, L0, C0, D0). The amplified signals pass through the tunable bandpass filter (C C, D0, D0, L0, L0), and are then applied to the st mixer circuit (IC0, pin ). RF CIRCUIT SHF band (00 MHz) FI IC RF FI Q RF D, D ANT LPF HPF ANT to IF amp. (Q0) D0 Mode FM mode FI0. NHz XTAL CRAMIC FI0. NHz D0 Mode UHF band (0 MHz) VHF band ( MHz) IC0 st mixer st LO WFM band (RX only) IC0 RF D0, D0 D0 RF RF FI0 Q0 Q0 D0 D0 Q0 RF D0, D0 ANT D0, D0 ANT HPF HPF LPF LPF WFM mode VHF band (0 MHz) D0, D0 Q0 RF D0, D0 ANT LPF LVL CONV. Q "TUN" signal from IC, pin (LOGIC unit) -
RF signals WFM band The WFM band signals are applied to the RF amplifier (Q0) via the tunable band-pass filter (D0). The amplified signals pass through the tunable bandpass filter (D0), and are then applied to the st mixer circuit (IC0, pin ). Varactor diodes (D0, D0, D0, D0, D0, D0, D0) are employed by the tunable bandpass filter to tune the center frequency of the bandpass filter. These diodes are controlled by the PLL lock voltage and obtain good image response rejection. -- 0 MHz BAND RF CIRCUIT (RF UNIT) The signals from the antenna switching circuit (D0 and D0) are amplified at the RF amplifier (Q0). The amplified signals pass through the bandpass filter (FI0), and are then applied to the st mixer circuit (IC0, pin ) after being amplified at another RF amplifier (IC0). -- 00 MHz BAND RF CIRCUIT (RF UNIT) The signals from the antenna switching circuit (D and D) are amplified at the RF amplifier (Q). The amplified signals pass through the bandpass filter (FI), and are then applied to the RF amplifier (IC). The amplified signal is applied to the st mixer circuit (IC0, pin ) via the bandpass filter (FI). -- ST MIXR CIRCUIT (RF UNIT) The st mixer circuit converts the received RF signals into a fixed frequency of the st IF signal with a st LO output frequency. By changing the PLL frequency, only the desired frequency will pass through at the next stage of the st mixer. st mixer circuit produces the different st IF signal for WFM and other band signals. 0,, 0 and 00 MHz band The applied RF signals are mixed with st LO signals at the st mixer (IC0) to produce a. MHz st IF signal. The st IF signal is output from the st mixer (IC0, pin ), and then passed through the crystal bandpass filter (FI0) to suppress unwanted harmonic components. The filtered st IF signal is applied to the IF amplifier (IC0). The amplified signal is applied to the nd mixer circuit (LOGIC unit; IC0, pin ). WFM band The RF signals are mixed with st LO signals at the st mixer (IC0) to produce a. MHz st IF signal. The st IF signal is output from the st mixer (IC0, pin ), and then passed through the st IF filter (FI0) to suppress unwanted harmonic components. The filtered signal is applied to the nd mixer circuit (LOGIC unit; IC0, pin ). The st LO signals are gererated at the VCO circuit which consists of Q0, Q0, D0, Q, Q, D0, D for 0 MHz, MHz and WFM, Q, Q, D, D for 0 MHz, Q0, D, D for 00 MHz on the VCO unit. The st LO signal for 0,, 0, WFM band The st LO signals which are generated on the VCO unit are applied to the buffer-amplifier (Q and D for 0 MHz, MHz and WFM, Q for 0 MHz). The buffer-amplified signals are applied to the LO-amplifier (Q for 0 MHz, MHz and WFM, Q for 0 MHz), and are then applied to the st mixer circuit via the TX/RX switch (D0 and D0 for 0 MHz, MHz and WFM, D0 and D0 for 0 MHz) on the RF unit. The st LO signal for 00 MHz band The st LO signals which are generated on the VCO unit are applied to the buffer-amplifier (Q). The buffer-amplified signals are applied to the doubler circuit (Q), and passes through the high-pass and low-pass filter. The filtered signals are applied to the st mixer circuit (Q0) on the LOGIC unit after being amplified at the LO-amplifier (Q). nd IF AND DMODULATOR CIRCUITS (LOGIC unit) nd IF filter C C 0 khz FI0 R R0 R C R C AF signal to AF filter (LOGIC unit; IC) Active filter FM detector R0 C0 Noise detector Limiter amp. 0 C R C0 R RSSI Q0 Noise comp. nd Mixer WFM "nd LO" signal from IC0, pin (RF unit) IC0 TAFN nd IF (. MHz) from Q0 (RF unit) "NOIS" signal to the CPU pin "SD" signal to the CPU pin -
-- ND IF AND DMODULATOR CIRCUITS (RF AND LOGIC UNITS) The nd mixer circuit converts the st IF signal to the nd IF signal. A double conversion superheterodyne system (which converts receive signals twice) improves the image rejection ratio and obtain stable receiver gain. The FM IF IC (LOGIC unit; IC0) contains nd local oscillator, nd mixer, limiter amplifier, quadrature detector and S- meter detector circuits. The filtered st IF signal from the st IF filter (RF unit; FI0 or FI0) is mixed with the nd LO signal at the nd mixer (LOGIC unit; IC0) to produce the 0 khz nd IF signal. The nd IF signal passes through or bypasses (WFM mode signal) nd IF filter (FI0) where unwanted heterodyne signals are suppressed via the mode switch (LOGIC unit; D0, D0). The filtered signals are applied to the limiter amplifier section (LOGIC unit; IC0, pin ), and then applied to the quadrature detector section to demodulate the nd IF signal into AF signals. The demodulated AF signals are output from pin of the IF IC (LOGIC unit; IC0) and are applied to the AF circuit. -- AF LIFIR CIRCUIT (LOGIC UNIT) The AF amplifier circuit which is included a low-pass and high-pass filter, AF mute switch, AF volume controller and AF amplifier amplifies the demodulated AF signals to drive a speaker. The demodulated AF signals (DTO signal) from the FM IF IC (IC0) are passed through the AF filter (low-pass and high-pass filters). The filtered signals are applied to the AF mute switch (Q) which is controlled by RM/MM signals from the CPU (IC, pin ), and are then applied to the electric volume control circuit (IC0, IC0). The level controlled AF signals are output from volume IC (IC0, pin ) and are then applied to the AF amplifier (IC0, pin ). The AF signals are then applied to the internal speaker (SP) via the [XT SP] jack (LOGIC unit; J) when no plug is connected to the jack. The AF filter circuit (IC) removes AF signals below 00 Hz (CTCSS signals) for clear AF output and these are applied to the CPU (IC, pin) for CTCSS squelch detection via the CTCIN line. --0 SQULCH CIRCUIT (LOGIC UNIT) NOIS SQULCH The noise squelch circuit cuts out AF signals when no RF signals are received. By detecting noise components in the AF signals, the squelch circuit switches the AF mute switch. A portion of the AF signals from the FM IF IC (IC0, pin ) are applied to the active filter section (IC0, pin, ). The active filter section amplifies and filters noise components. The filtered signals are applied to the noise detector section and output from IC0 (pin ) as NOIS signal. ven when the squelch is closed, the AF mute switch (Q) opens at the moment of emitting beep tones. TON SQULCH The tone squelch circuit detects AF signals and opens the squelch only when receiving a signal containing a matching subaudible tone (CTCSS). When tone squelch is in use, and a signal with a mismatched or no subaudible tone is received, the tone squelch circuit mutes the AF signals even when noise squelch is open. A portion of the AF signals from the FM IF IC (IC0, pin) passes through the AF filter (IC) to remove AF (voice) signals and is applied to the CTCSS decoder inside the CPU (IC, pin ) via the CTCIN line to control the AF mute switch. - TRANSMITTR CIRCUITS -- MICROPHON LIFIR CIRCUIIT (LOGIC UNIT) The microphone amplifier circuit amplifies the audio signals from the microphone, within db/octave pre-emphasis characteristics (00 Hz khz), to a level needed for the modulation circuit. The AF signals from the internal microphone (MC) or external [MIC] jack (J) are applied to the microphone (limiter) amplifier (IC0, pin ) which has db/octave pre-emphasis characteristics, and are then passed through the lowpass filter (IC0, pin and ). The filetered signals are applied to the modulation circuit for each band in the RF unit via the band switch (Q0: for MHz band, Q0: for UHF band, Q0: for 0 MHz band, Q0: for 0MHz band) as the MOD signal. -- MODULATION CIRCUIT (VCO AND RF UNIT) The modulation circuit modulates the VCO oscillating signal (RF signal) using the microphone AF signals. () 0 MHz band The signals from the limiter amplifier (RF unit; IC0) changes the reactance of a diode (RF unit; D) to modulate the oscillated signal at the 0-VCO circuit (RF unit; Q, D, L ). The modulated signals are amplified at the buffer-amplifier (Q) and the LO amplifier (Q). The amplified signals are applied to the drive/power amplifier circuits for VHF band. () MHz band The signals from the limiter amplifier (RF unit; IC0) changes the reactance of a diode (VCO unit; D0) to modulate the oscillated signal at the -VCO circuit (VCO unit; Q, Q, D0, D D). The modulated signals are amplified at the buffer-amplifier (Q, Q) and the LO amplifier (Q). The amplified signals are applied to the drive/power amplifier circuits for VHF band. The NOIS signal from IC0 (pin ) is applied to the CPU (IC, pin ). The CPU analyzes the noise condition and outputs the RM/MM signal to AF mute switch (Q). -
() 0 MHz band The signals from the limiter amplifier (RF unit; IC0) changes the reactance of a diode (VCO unit; D) to modulate the oscillated signal at the 0-VCO circuit (VCO unit; Q, Q, D, D, L). The modulated signals are amplified at the buffer-amplifier (Q) and the LO amplifier (Q). The amplified signals are applied to the drive/power amplifier circuits for UHF band. () 00 MHz band The signals from the limiter amplifier (RF unit: IC0) changes the reactance of a diode (VCO unit; D) to modulate the oscillated signal at the 00-VCO circuit (VCO unit; Q0, D, D, L0). The modulated signals are amplified at the buffer-ampifier (Q). The amplified signals are applied to the doubler circuit (Q), and then passed through the high-pass (C C0, L, L) and the low-pass (C C, L, L) filters. The filtered signals are amplified at the buffer-amplifier (Q) and the LO amplifier (Q). The amplified signals are applied to the drive/power amplifier circuits for SHF band. -- DRIV/POWR LIFIR CIRCUITS (RF UNIT) The amplifier circuit amplifies the VCO oscillating signal to the output power level. () 0 MHz PA The signal from the LO amplifiers (Q) is amplified at the buffer-amplifier (Q) and the YGR amplifier (Q). The amplified signal is applied to the driver amplifiers (Q), and is then amplified at the power amplifier (Q) to obtain.0 W of RF power. The amplified signal is passed through the antenna switching circuit (D0 and D0) and low-pass filters, and is then applied to the antenna connector. () MHz PA The signal from the LO amplifiers (Q) is passed through the Tx/Rx switch (D0 and D0), and is amplified at the buffer-amplifier (Q) and the YGR amplifier (Q). The amplified signal is applied to the driver amplifiers (Q), and is then amplified at the power amplifier (Q) to obtain.0 W of RF power. The amplified signal is passed through the antenna switching circuit (D0 and D0), low-pass filters and high-pass filters. The signal is applied to the antenna connector. () 0 MHz PA The signal from the LO amplifiers (Q) is passed through the Tx/Rx switch (D0 and D0), and is amplified at the buffer amplifier (Q) and the YGR amplifier (Q). The amplified signal is applied to the driver amplifier (Q), and is then amplified at the power amplifier (Q) to obtain.0 W of RF power. The amplified signal is passed through the antenna switching circuit (D0 and D0), low-pass filters and high-pass filters. The low-pass filtered signal is applied to the antenna connector. () 00 MHz PA The signal from the LO amplifiers (Q) is passed through the Tx/Rx switch (D0 and D0), and is amplified at the buffer-amplifiers (Q and Q) and the YGR amplifier (Q). The amplified signal is applied to the driver amplifiers (Q) to obtain.0 W of RF power. The amplified signal is passed through the antenna switching circuit (D and D), low-pass filter and high-pass filters. The high-pass filtered signal is applied to the antenna connector. Collector voltages for the drive amplifier (Q) and control voltage for the power amplifier (Q) and YGR amplifier (Q) are controlled by the APC circuit to protect the power module from a mismatched condition as well as to stabilize the output power. -- APC CIRCUITS (RF UNIT) The APC circuit protects the power amplifier from a mismatched output load and stabilizes the output power. The APC circuit is designed to use VHF, UHF and SHF bands commonly. APC CONTROL CIRCUIT TXC Q APC SNSOR CIRCUIT Q R 00 MHz RF transmit signal YGR Drive to the antenna amp. Power amp. Q amp. Q Q C 0 MHz RF transmit signal 0, MHz RF transmit signal D/A CONVRTR PST IC0 IC (LOGIC unit) Differential amplifier YGR amp. Q YGR amp. Q VGGC -
The APC sensor (R) detects driving current from the drive voltage at the YGR (Q), drive (Q) and power (Q) amplifiers. The detected current is converted into DC voltage at Q, then applied to the APC control circuit (IC0, pin ). The applied voltage is compared with a PST voltage from the CPU via the D/A converter (LOGIC unit; IC), and the APC control circuit outputs VGGC voltage from pin to control the YGR, drive and power amplifiers. When the driving current is increased, input voltage of the differential amplifier (IC0, pin ) will be increased. In such cases, the differential amplifier output voltage (IC0, pin ) is decreased to reduce the driving current. - PLL CIRCUITS -- 0 MHz BAND PLL CIRCUIT (RF UNIT) The osillated signal at the MVCO (Q, D) is amplified at the buffer amplifiers (Q, Q). The amplified signal is applied to the PLL IC (IC0, pin ) via the buffer-amplifier (Q). The signal which is applied to the PLL IC (IC0) is divided by N-data from the CPU and phase-detected with the divided reference frequency ( khz) then output from pin. The output signal is converted into DC voltage at the active filter (Q0, Q0) and is fed back to the MVCO as the lock voltage. -- MHz BAND PLL CIRCUIT (VCO BOARD AND RF UNIT) The osillated signal at the -VCO circuit (VCO unit; Q, Q, D0 and D) is amplified at the buffer amplifiers (VCO unit; Q).The amplified signal is applied to the PLL IC (IC0, pin ) via a buffer-amplifier (Q0). The applied signal is divided by serial data from the CPU (Ndata) and phase-detected with the divided reference frequency ( khz) at the phase detector section in the PLL IC. The phase-detected signal is output from IC0 (pin ) and converted DC voltage at the active filter (Q, Q). The converted DC voltage is fed back to the VCO board as the VLV signal of the lock voltage. While operating in the MHz band, the lock voltage is applied to the CPU (LOGIC unit; IC) via the tune control circuit (Q0) to track the center frequency of the tunable bandpass filters (D0, D0, D0) as the TUN signal. -- 0 MHz BAND PLL CIRCUIT (VCO BOARD AND RF UNIT) The osillated signal at the 0-VCO circuit (VCO unit; Q, Q, D and Q) is amplified at the buffer-amplifiers (VCO unit; Q).The amplified signal is applied to the PLL IC (IC0, pin ) via a buffer-amplifier (Q0). The applied signal is divided by serial data from the CPU (Ndata) and phase-detected with the divided reference frequency ( khz) at the phase detector section in the PLL IC. The phase-detected signal is output from IC0 (pin ) and converted DC voltage at the active filter (Q, Q). The converted DC voltage is fed back to the VCO board as the VLV signal of the lock voltage. -- 00MHz BAND PLL CIRCUIT (VCO BOARD AND RF UNIT) The osillated signal at the 00-VCO circuit (VCO unit; Q0, D and D) is amplified at the buffer-amplifiers (VCO unit; Q and Q). The signal passes through the buffer amplifier (Q), the high-pass (C C0, L and L) and the low-pass filter (C C, L and L). The filtered signal is applied to the PLL IC (IC0, pin ) via the buffer amplifier (Q). The applied signal is divided by serial data from the CPU (Ndata) and phase-detected with the divided reference frequency ( khz) at the phase detector section in the PLL IC. The phase-detected signal is output from IC0 (pin ) and converted DC voltage at the active filter (Q, Q). The converted DC voltage is fed back to the VCO board as the VLV signal of the lock voltage. - POWR SUPPLY CIRCUITS VOLTAG LIN LIN HV CPU C R T DSCRIPTION The voltage from the external power supply or attached battery pack. The same voltage as the HV line (external power supply or battery pack) passed through a diode (RF unit; D). Common V converted from the line by C CPU regulator IC (LOGIC unit; IC). The output voltage is supplied to the C regulator circuits, etc. Common V converted from the line by the C regulator circuit (LOGIC unit; Q and Q) using the CPU regulator (LOGIC unit; IC.) Common V converted from the line by the regulator circuit (LOGIC unit; IC, Q, Q and Q) using the C regulator (LOGIC unit; Q and Q). V for receiver circuit converted from the line by the R regulator circuit (RF unit; Q and Q). V for transmitter circuit converted from the line by the T regulator circuit (RF unit; Q0 Q0 and D0). The T regulator circuit is controlled by the CPU (LOGIC unit; IC, pin ) via the TXC line. -
- PORT ALLOCATIONS -- I/O XPANDR IC (RF UNIT; IC) Pin number Port name Q Q Q Q Q Q Q Q Description Outputs VHVCO regulator control signal. Outputs VLVCO regulator control signal. Outputs MVCO regulator control signal. Outputs VCO shift signal for SHF, UHF, MHz and 0 MHz. Outputs VCO regulator control signal. Outputs UHVCO regulator control signal. Outputs UHF TX and RX regulator control signal. Outputs 00 MHz TX and RX regulator control signal. -- I/O XPANDR IC (RF UNIT; IC) Pin number Port name Q Q Q Q Q Q Description Outputs 00 MHz band RX regulator control signal. Outputs AM mode regulator control signal. Outputs WFM band RX switching control signal. Outputs WFM band RX regulator control signal. Outputs 0 MHz band TX and RX regulator control signal. Outputs VHF band TX and RX regulator control signal. PLL circuit Q0 TUN CTRL Loop filter "LOCKV" signal to the IC, pin X. MHz Q, Q VCO BOARD 00MHz VCO Q0, D, D 0 MHz VCO Q, Q, D, D MHz VCO Q, Q, D0, D 0MHz RX VCO Q0, Q0, D0 Q, D Loop Q0, filter Q0 Phase Programmable Prescaler detector counter 0 MHz TX VCO Programmable divider Q, Q Buff. Q Buff. Buff. Q, D Buff. Q IC0 (PLL IC) IC0 (PLL IC) Shift register Q Amp. Amp. Q Amp. Q Q0 Buff. Q Buff. CLK DATA STB D0, D0 TX/RX TX/RX D0, D0 TX/RX D0, D0 PSTB CLK DATA Buff. Q to transmitter circuit to transmitter circuit to transmitter circuit to st mixer circuit (IC0, pin ) to transmitter circuit -
-- CPU (LOGIC UNIT; IC) Pin number Port name VIN RMOT SD CTCIN LOCKV Description Input port for the over-voltage detection from connected battery pack or external power supply. Input port for remote control signals from an optional HM-A microphone via the [MIC] jack. Input port for the S-meter voltage. Input port for CTCSS decoded signals. Input port for the PLL lock voltage. Pin number 0 Port name CLONIN TXC RC CPUHV CHGC Description Input port for the cloning signal. Outputs T regulator control signal. High : While transmitting. Outputs R regulator control signal. High : While receiving. Input port for the reset signal from Q (LOGIC unit). Outputs control signal for charger circuit (RF unit; Q). High : While battery is charging. 0 THRMC SBATT CONT CTCOUT BP Input port for the tranceiver s internal temparature. Input port for the voltage (connected battery voltage). Outputs control signal for the LCD contrast. High : The LCD contrast is deep. Outputs CTCSS signals while transmitting. Output port for: Beep audio signals while receiving. DTMF signals or 0 Hz urope tone signal while transmitting. [UR], [ITA], [UK] AFON PCON TCON BLD LIGHT Outputs control signal for the AF amplifier requlator circuit. High : Activates the AF amplifier circuit. Outputs C regulator control signal (LOGIC unit; Q and Q). Outputs control signal for the urope tone and DTMF. Low : Activates the urope tone. High : Activates DTMF. Outputs BUSY LD control singal. Low : The BUSY LD is ON. Outputs LCD backlight control signal. High : Lights ON. BPCPI NOIS PDA/UL PDA/UL Input port for the bias control voltage to judge kinds of battery types. High : Supply the bias control voltage. Input port for the noise signal (pulsetype) from the IF IC (RF unit; IC 0, pin ). Outputs data signals to the PLL IC (RF unit; IC0, pin ). Input port for the PLL unlock signal from the PLL IC (RF unit; IC0, pin ). Outputs data signals to the PLL IC (RF unit; IC0, pin ). Input port for the PLL unlock signal from the PLL IC (RF unit; IC0, pin ). 0 MICC RM/MM POWR RST PTT CK Outputs control signal for the regulator secton of MIC amplifier (LOGIC unit; IC0). Low : Activates the MIC amplifier circuit. Outputs AF mute and MIC mute control signals. High : Mute is ON. Input port for the [POWR] switch. Input port for the RST signal from IC, pin (LOGIC unit). Input port for the [PTT] switch. Outputs clock signal to the PLL IC (IC0), PLL IC (IC0), D/A IC (IC), I/O IC (IC, IC) on the RF unit and PROM IC (LOGIC unit; IC). DAST Outputs strobe signals to the D/A IC (LOGIC unit; IC, pin). SIO Data bus line for the PROM (LOGIC unit; IC). IOST PLST PLST Outputs strobe signals to the I/O IC (RF unit; IC, pin and IC, pin ). Outputs strobe signals to the PLL IC (RF unit, IC0, pin). Outputs strobe signals to the PLL IC (RF unit, IC0, pin ).,, KR KR0 I, I KS KS0 DICK, DIUK Input ports for key matrix. Input ports for Initial matrix. Outputs port for key matrix. Input port for the up/down signal from the main dial (LOGIC unit; S). CLONOUT Output port for the cloning signal. -
SCTION ADJUSTMNT PROCDURS - PRPARATION RQUIRD TST QUIPMNT QUIPMNT GRAD AND RANG QUIPMNT GRAD AND RANG DC power supply RF power meter (terminated type) Frequency counter FM deviation meter Output voltage :. V DC Current capacity : A or more Measuring range : 0 W Frequency range : 00 MHz Impedance : 0 Ω R : Less than. : Frequency range : 0. 00 MHz Frequency accuracy : ± ppm or better Sensitivity : 00 mv or better Frequency range : 0 00 MHz Measuring range : 0 to ±0 khz DC voltmeter Audio generator Standard signal generator (SSG) Oscilloscope AC millivoltmeter Attenuator Input impedance Frequency range Measuring range Frequency range Output level Frequency range Measuring range Measuring range Power attenuation : 0 kω/v DC or better : 00 000 Hz : 00 mv : 00 MHz : 0. µv mv ( to dbm) : DC 0 MHz : 0.0 0 V : 0 mv 0 V : 0 or 0 db NTRING TH ADJUSTMNT MOD q Connect a kω terminator to the [SP] jack. w Push and hold the [SQL] key, and then turn power ON. Note: The frequency of wide range appears at the display using this operation. CONNCTION FM Deviation meter RF power meter 0 W/0 Ω Attenuator 0 db or 0 db to the antenna connector JIG Frequency counter kω Standard signal generator to [SP] jack - CAUTION: DO NOT transmit while an SSG is connected to the antenna connector. AD-SMA Optional SMA BNC adaptor to [MIC] jack /" (. mm) -conductor plug Audio generator AC millivoltmeter Power supply. V / A -
- PLL ADJUSTMNT The following adjustment must be performed at ADJUSTMNT MOD. ADJUSTMNT PLL LOCK VOLTAG RFRNC FRQUNCY ADJUSTMNT CONDITION.000 MHz Transmitting.000 MHz.000 MHz Transmitting 0.000 MHz Transmitting 0.000 MHz Transmitting 0.000 MHz Transmitting ADJUSTMNT MASURMNT VALU POINT UNIT LOCATION UNIT ADJUST RF Top Pannel Connect the DC voltmeter or an oscilloscope to VLV. Connect the DC voltmeter or an oscilloscope to MLV. Connect the DC voltmeter or an oscilloscope to VLV. Connect the DC voltmeter or an oscilloscope to ULV. Connect the DC voltmeter or an oscilloscope to LV. Loosely couple the frequency counter to the antenna connector. 0. V. V. V. V. V. V. V. V. V. V.0 V. V.0 V. V. V. V 0.0000 MHz Top panel Verify Push and hold the [SQL] key, then turn the [DIAL] DTCTR OUTPUT VOLTAG.000 MHz [USA-] only.000 MHz [ohter] Connect an SSG to the antenna connector and set as: Level : mv* ( dbm) Modulation : OFF LOGIC Connect a digitalvoltmeter to the check point Q..0 V LOGIC L0 *This output level of the standard signal generator (SSG) is indicated as SSG s open circuit. -
RF UNIT BOTTOM VIW LV PLL lock voltage check point (for 00 MHz) ULV PLL lock voltage check point (for 0 MHz) VLV PLL lock voltage check point (for 0 MHz RX, WFM and MHz) RF UNIT TOP VIW MLV PLL lock voltage check point (for 0 MHz TX) LOGIC UNIT TOP VIW L0 Detector Output voltage adjustment Q Detector Output voltage check point -
- RCIVR ADJUSTMNT The following adjustment must be performed at ADJUSTMNT MOD. ADJUSTMNT 0 MHz SNSITIVITY WFM SNSITIVITY AM SNSITIVITY VHF SNSITIVITY ADJUSTMNT CONDITION 0.000 MHz Connect an SSG to the antenna connector and a SINAD meter with an Ω load to the [SP] jack. Set an SSG as : Level : µv* ( 0 dbm) Deviation : ±. khz Modulation : khz.000 MHz [UR], [UK], [ITA].000 MHz [SA], [USA-].000 MHz [UR], [UK], [ITA], [AUS] Set an SSG as : Level :. µv* ( dbm) Deviation : ±. khz Modulation : khz 0.000 MHz 0.000 MHz Set an SSG as : Frequency : 0.000 MHz Level :.0 µv* (AM) ( 0 dbm) Modulation : khz Mod. depth : 0 %.0 MHz Set an SSG as : Frequency :.0 MHz.000 MHz Set an SSG as : Level :. µv* ( dbm) Deviation : ±. khz Modulation : khz 0.000 MHz MASURMNT ADJUSTMNT VALU POINT UNIT LOCATION UNIT ADJUST LOGIC Connect a multimeter Maximum voltage Top [DIAL] to check point panel SD. LOGIC LOGIC LOGIC Connect a multimeter to check point SD. Connect a multimeter to check point SD. Connect a multimeter to check point SD. Maximum voltage Maximum voltage Maximum voltage Top panel Top panel Top panel [DIAL] [DIAL] [DIAL] *This output level of the standard signal generator (SSG) is indicated as SSG s open circuit. -
LOGIC UNIT TOP VIW SD 0 MHz, WFM BAND, AIR BAND and MHz Sensitivity check point -
RCIVR ADJUSTMNT (Continued) The following adjustment must be performed on the normal mode after SNSITIVITY ADJUSTMNT in SCTION -. ADJUSTMNT ADJUSTMNT CONDITION UNIT MASURMNT LOCATION VALU ADJUSTMNT S-MTR (0 MHz band).000 MHz [UR], [UK], [ITA].000 MHz [AUS], [SA], [USA-] Connect the SSG to the antenna connector and set as: Level : µv* ( 0 dbm) Modulation : khz Deviation : ±. khz Connect a terminator to the [SP] jack. Top panel Push and hold the [SQL] key Set an SSG output level for the S-meter to S. 0. µv. µv (-dbm -0 dbm) Verify Increase an SSG output level. Front panel S-meter Full scale Verify (WFM band).000 MHz [SA], [USA-].000 MHz [UR], [UK],[ITA], [AUS] Connect the SSG to the antenna connector and set as: Level : µv* ( 0 dbm) Modulation : khz Deviation : ±. khz Connect a terminator to the [SP] jack. Top panel Push and hold the [SQL] key Increase an SSG output level. Front panel S-meter Full scale Verify ( MHz band).000 MHz [UR], [UK].000 MHz [ITA], [AUS], [SA], [USA-] Connect the SSG to the antenna connector and set as: Level : 0. µv* ( dbm) Modulation : khz Deviation : ±. khz Connect a terminator to the [SP] jack. Top panel Push and hold the [SQL] key Set an SSG output level for the S-meter to S. SSG Output level 0. µv 0. µv (-dbm -0 dbm) Verify Increase an SSG output level. Front panel S-meter Full scale Verify *This output level of the standard signal generator (SSG) is indicated as SSG s open circuit. -
RCIVR ADJUSTMNT (Continued) The SQULCH LVL adjustment must be performed on the normal mode after S-MTR ADJUSTMNT. ADJUSTMNT S-MTR (0 MHz band) (00 MHz band) SQULCH LVL 0 ADJUSTMNT CONDITION.000 MHz [USA-].000 MHz [other] Connect the SSG to the antenna connector and set as: Level : 0. µv* ( dbm) Modulation : khz Deviation : ±. khz Connect a terminator to the [SP] jack. Set an SSG output level for the S-meter to S. Increase an SSG output level. 0.000 MHz Connect the SSG to the antenna connector and set as: Level : µv* ( 0 dbm) Modulation : khz Deviation : ±. khz Connect a terminator to the [SP] jack. Set an SSG output level for the S-meter to S. Increase an SSG output level..000 MHz [USA-].000 MHz [other] Connect the SSG to the antenna connector and set as: Level : 0. µv* ( dbm) Modulation : khz Deviation : ±. khz Pre-set the R to maxmum clock-wise. ADJUSTMNT MASURMNT VALU POINT UNIT LOCATION UNIT ADJUST Top panel SSG Front panel Top panel SSG Front panel Speaker Output level S-meter Output level S-meter *This output level of the standard signal generator (SSG) is indicated as SSG s open circuit. LOGIC UNIT TOP VIW 0. µv. µv (-dbm -0 dbm) Full scale 0. µv. µv (-0dBm - dbm) Full scale At the point where the AF signal just disappears Push and hold the [SQL] key LOGIC Verify Verify Push and hold the [SQL] key Verify Verify R R Squelch level adjustment -
- TRANSMITTR ADJUSTMNT The following adjustment must be performed at ADJUSTMNT MOD. ADJUSTMNT ADJUSTMNT CONDITION UNIT MASURMNT LOCATION VALU ADJUSTMNT OUTPUT POWR (0 MHz).000 MHz [UR], [UK], [ITA].000 MHz [AUS], [SA], [USA-] Output power : High transmitting Top panel Connect an RF power meter to the antenna connector. more than W [DIAL] Output power Transmitting : Low 0. W ( MHz).000 MHz [UR], [UK].000 MHz [ITA], [AUS], [SA], [USA-] Output power : High Transmitting Top panel Connect an RF power meter to the antenna connector. more than W [DIAL] Output power Transmitting : Low 0. W (0 MHz).000 MHz [USA-].000 MHz [Other] Output power : High Transmitting Top panel Connect an RF power meter to the antenna connector. more than W [DIAL] Output power Transmitting : Low 0. W (00 MHz) 0.000 MHz Output power : High Transmitting Top panel Connect an RF power meter to the antenna connector. more than W [DIAL] Output power Transmitting : Low 0. W LOGIC UNIT TOP VIW R DTMF or TON CALL deviation adjustment R 0 MHz FM deviation adjustment R 0 MHz BAND FM deviation adjustment R 00 MHz FM deviation adjustment R MHz BAND FM deviation adjustment -
TRANSMITTR ADJUSTMNT (Continued) The following adjustment must be performed after RFRNC FRQUNCY ADJUSTMNT in SCTION -. ADJUSTMNT FM DVIATION (0 MHz) ( MHz) (0 MHz) (00 MHz) DTMF DVIATION (AUS, SA, USA- only) TON CALL DVIATION (UR, UK, ITA only) CTCSS DVIATION (0 MHz) ( MHz) (0 MHz) (00 MHz) ADJUSTMNT CONDITION.000 MHz [UR], [UK], [ITA].000 MHz [AUS], [SA], [USA-] Connect the audio generator to the [MIC] connector and set as: mv/.0 khz. Set the FM deviation meter as : HPF : OFF LPF : 0 khz De-emphasis : OFF Detector : (P P)/ Output power : High Transmitting.000 MHz [UR], [UK].000 MHz [ITA], [AUS], [SA], [USA-] Transmitting.000 MHz [USA-].000 MHz [Other] Transmitting 0.000 MHz Transmitting.000 MHz [USA-] only.000 MHz [AUS], [SA] only Push [D] key while transmitting. Transmitting.000 MHz Push [center of the multi-function] key while transmitting. Transmitting.000 MHz [UR], [UK], [ITA].000 MHz [AUS], [SA], [USA-] Tone frequency :. Hz Set an FM deviation meter as : LPF : khz Apply no audio signal to the [MIC] jack. Transmitting.000 MHz [UR], [UK].000 MHz [ITA], [AUS], [SA], [USA-] Transmitting.000 MHz [USA-].000 MHz [other] Transmitting 0.000 MHz Transmitting ADJUSTMNT MASURMNT VALU POINT UNIT LOCATION UNIT ADJUST Top panel Top panel Top panel Top panel Connect an FM deviation meter to the antenna connector through an attenuator. Connect an FM deviation meter to the antenna connector through an attenuator. Connect an FM deviation meter to the antenna connector through an attenuator. Connect an FM deviation meter to the antenna connector through an attenuator.. khz. khz. khz 0..0 khz LOGIC LOGIC LOGIC R R R R R R Verify -
SCTION PARTS LIST [LOGIC UNIT] RF ORDR NO. NO. DSCRIPTION IC 0000 S.IC MGP [USA-] only 00000 S.IC MML-0GP [other] IC 0000 S.IC X0SI-.T IC 0000 S.IC XCA00PR IC 0000 S.IC TCWFU (TL) IC 0000 S.IC MGP 0D IC 0000 S.IC S-HG-KC-T IC 0000 S.IC S-0ALMP-DAR-T IC0 0000 S.IC TAF (TP) IC0 0000 S.IC MFP 00C IC0 0000 S.IC TAS0F (TR) IC 0000 S.IC NJM0V-T IC0 0000 S.IC BA0F-T IC0 0000 S.IC TAFN (D,L) IC 00000 S.IC TCSF (TR) Q 0000 S.TRANSISTOR UN (TX) Q 0000 S.TRANSISTOR XP (TX) Q 0000 S.TRANSISTOR XP0-(TX) AB Q 00000 S.TRANSISTOR SB T00 R Q 0000 S.TRANSISTOR UN0 (TX) Q 0000 S.TRANSISTOR XP0-(TX) AB Q 00000 S.TRANSISTOR SB T00 R Q 00000 S.TRANSISTOR SD-S (TX) Q0 00000 S.TRANSISTOR SB0-S-TL Q0 0000 S.TRANSISTOR XP0-(TX) AB Q0 0000 S.TRANSISTOR UN (TX) Q0 00000 S.TRANSISTOR SB-R (TX) Q0 0000 S.TRANSISTOR UN (TX) Q0 000000 S.FT SJ-Q (TX) Q0 000000 S.FT SJ-Q (TX) Q0 000000 S.FT SJ-Q (TX) Q0 0000 S.TRANSISTOR UN (TX) Q0 0000 S.TRANSISTOR XP0-(TX) AB Q0 000000 S.FT SJ-Q (TX) Q 0000 S.TRANSISTOR UN (TX) Q 000000 S.FT SJ-Q (TX) Q0 0000 S.TRANSISTOR UN (TX) Q0 0000 S.TRANSISTOR XP (TX) Q0 0000 S.TRANSISTOR UN (TX) Q 0000 S.TRANSISTOR XP0-(TX) AB Q 00000 S.TRANSISTOR SD-S (TX) Q 0000 S.TRANSISTOR UN (TX) Q 00000 S.TRANSISTOR SD-S (TX) D 00000 S.DIOD MA (TX) D 0000 S.DIOD MAS-(TX) D 0000 S.DIOD MAS-(TX) D 00000 S.DIOD MAK (TX) [UK], [AUS] 00000 S.DIOD MAHK (TX) [UR], [USA-] 00000 S.DIOD MAWK (TX) [SA] D 00000 S.DIOD MAHK (TX) [ITA], [AUS], [SA], [USA-] D 00000 S.DIOD MAWK (TX) except [ITA] D 0000 S.DIOD MAS-(TX) except [ITA] D 00000 S.DIOD MAS (TX) D 00000 S.DIOD MAS (TX) D 0000 S.DIOD MAS-(TX) except [ITA] D 0000 S.DIOD MAS-(TX) D 0000 S.DIOD MAS-(TX) D 0000 S.DIOD MAS-(TX) D 0000 S.ZNR MA00-M (TX) D 0000 S.DIOD MAS-(TX) D0 000000 S.ZNR RD.M-TB D0 00000 S.DIOD SS (TL) D0 00000 S.DIOD SS (TL) FI0 00000 S.CRAMIC PBFC0RDR X 00000 S.XTAL CR- (.0 MHz) [LOGIC UNIT] RF ORDR NO. NO. DSCRIPTION L 00000 S.COIL CA-KN-0AQ=P L 00000 S.COIL MLF0A RK-T L 00000 S.COIL LQH N K 0 L0 00000 S.COIL LS- (AN-0GW=P) R 00000 S.THRMISTOR NTCCF0 AH KC-T R 000000 S.RSISTOR RJGJ 0 X (00 kω) R 00000 S.RSISTOR RJGJ X (0 Ω) R 00000 S.RSISTOR RJGJ X (0 Ω) R 000000 S.RSISTOR RJGJ 0 X (0 kω) R 00000 S.RSISTOR RJGJ X (0 kω) R0 00000 S.RSISTOR RJGJ X ( kω) R 00000 S.RSISTOR RR00R--D ( kω) R 00000 S.RSISTOR RR00R--D ( kω) R 00000 S.RSISTOR RR00R--D ( kω) R 000000 S.RSISTOR RJGJ 0 X (0 kω) R 000000 S.RSISTOR RJGJ 0 X (00 kω) R 000000 S.RSISTOR RJGJ X (. kω) R 000000 S.RSISTOR RJGJ X (. kω) R 00000 S.RSISTOR RJGJ 0 X ( kω) R 00000 S.RSISTOR RJGJ 0 X ( kω) R 00000 S.RSISTOR RJGJ 0 X ( kω) R 00000 S.RSISTOR RJGJ 0 X ( kω) R 00000 S.RSISTOR RJGJ 0 X ( kω) R 000000 S.RSISTOR RJGJ X (. kω) R 00000 S.RSISTOR RJGJ 0 X ( kω) R 00000 S.RSISTOR RJGJ 0 X ( kω) R 00000 S.RSISTOR RJGJ 0 X ( kω) R0 00000 S.RSISTOR RJGJ 0 X ( kω) R 00000 S.RSISTOR RJGJ 0 X ( kω) R 00000 S.RSISTOR RJGJ 0 X ( kω) R 00000 S.RSISTOR RJGJ 0 X ( kω) R 00000 S.RSISTOR RJGJ 0 X ( kω) R 00000 S.RSISTOR RJGJ 0 X ( kω) R 00000 S.RSISTOR RJGJ 0 X ( kω) R 00000 S.RSISTOR RJGJ 0 X ( kω) R 000000 S.RSISTOR RJGJ 0 X (00 kω) R 000000 S.RSISTOR RJGJ 0 X (00 kω) R 00000 S.RSISTOR RJGJ X (0 Ω) R 00000 S.RSISTOR RJGJ 0 X ( MΩ) R 00000 S.RSISTOR RJGJ X (0 kω) R 00000 S.RSISTOR RJGJ X (0 kω) R 00000 S.RSISTOR RJGJ X (0 kω) R 000000 S.RSISTOR RJGJ X (. kω) R 00000 S.RSISTOR RJGJ X ( kω) R 00000 S.RSISTOR RR00R--D ( kω) R 000000 S.RSISTOR RJGJ 0 X (0 kω) R 000000 S.RSISTOR RJGJ X (. kω) R 000000 S.RSISTOR RJGJ 0 X (0 kω) R 00000 S.RSISTOR RJGJ 0 X ( MΩ) R 00000 S.RSISTOR RR00R-0-D (00 kω) R 00000 S.RSISTOR RJGJ 0 X ( kω) R 00000 S.RSISTOR RJGJ X ( kω) R 000000 S.RSISTOR RJGJ 0 X (0 kω) R 00000 S.RSISTOR RJGJ X (0 kω) R 000000 S.RSISTOR RJGJ 0 X (0 kω) R0 00000 S.RSISTOR RJGJ 00 X (0 Ω) R0 00000 S.RSISTOR RJGJ X (0 Ω) R0 000000 S.RSISTOR MCR0ZHJ Ω (0) R0 000000 S.RSISTOR MCR0ZHJ Ω (0) R0 000000 S.RSISTOR MCR0ZHJ Ω (0) R0 000000 S.RSISTOR RJGJ X (. kω) R0 00000 S.RSISTOR RJGJ 0 X ( MΩ) R0 000000 S.RSISTOR RJGJ 0 X (0 kω) R0 00000 S.RSISTOR RJGJ 0 X ( kω) R0 00000 S.RSISTOR RR00R--D ( kω) R 00000 S.RSISTOR RR00P-0-D (0 kω) R 00000 S.RSISTOR RJGJ X ( kω) R 00000 S.RSISTOR RR00R--D ( kω) R 00000 S.RSISTOR RR00R-0-D (00 kω) R 000000 S.RSISTOR RJGJ X (. kω) R 00000 S.RSISTOR RJGJ 0 X ( MΩ) R 00000 S.RSISTOR RJGJ X (0 kω) R 000000 S.RSISTOR RJGJ X ( kω) R 000000 S.RSISTOR RJGJ X ( kω) S.=Surface mount -
[LOGIC UNIT] RF ORDR NO. NO. DSCRIPTION R 000000 S.RSISTOR RJGJ X ( kω) R 00000 S.RSISTOR RJGJ X (0 kω) R 000000 S.RSISTOR RJGJ 0 X (00 kω) R 00000 S.RSISTOR RJGJ X (0 kω) R 00000 S.RSISTOR RJGJ X (0 kω) R0 000000 S.RSISTOR RJGJ 0 X (00 kω) R 000000 S.RSISTOR RJGJ X ( kω) R 00000 S.RSISTOR RJGJ X (0 kω) R 00000 S.RSISTOR RJGJ X ( kω) R 00000 S.RSISTOR RJGJ X ( kω) R 00000 S.RSISTOR RJGJ 0 X (00 Ω) R0 00000 S.RSISTOR RJGJ X ( kω) R0 000000 S.RSISTOR RJGJ 0 X (0 kω) R0 000000 S.RSISTOR RJGJ X ( kω) R0 00000 S.RSISTOR RJGJ X ( kω) R0 00000 S.RSISTOR RJGJ 0 X (00 Ω) R0 000000 S.RSISTOR RJGJ 0 X (00 kω) R0 00000 S.RSISTOR RJGJ X (. MΩ) R0 00000 S.RSISTOR RJGJ X (0 kω) R0 000000 S.RSISTOR RJGJ X (. kω) R0 000000 S.RSISTOR RJGJ X (. kω) R 00000 S.RSISTOR RJGJ 00 X (0 Ω) R 00000 S.RSISTOR RJGJ X (0 kω) R 000000 S.RSISTOR RJGJ 0 X (00 kω) R 00000 S.RSISTOR RJGJ 0 X (00 Ω) R 00000 S.RSISTOR RJGJ X ( kω) R 0000000 S.RSISTOR RJGJ X (0 Ω) R 00000 S.RSISTOR RJGJ X (0 kω) R 00000 S.RSISTOR RJGJ 0 X ( kω) R 00000 S.RSISTOR RJGJ X (. kω) R0 000000 S.RSISTOR RJGJ X ( kω) R 000000 S.RSISTOR RJGJ X (. kω) R 00000 S.TRIMMR VM-XSX0 B (0) R 00000 S.RSISTOR RJGJ X ( kω) R 000000 S.RSISTOR RJGJ X ( kω) R 00000 S.TRIMMR VM-XSX0 B (0) R 00000 S.TRIMMR VM-XSX0 B (0) R 00000 S.TRIMMR VM-XSX0 B (0) R 00000 S.RSISTOR RJGJ X (0 kω) R 00000 S.RSISTOR RJGJ X (0 kω) R0 00000 S.RSISTOR RJGJ X (0 kω) R 00000 S.RSISTOR RJGJ X (0 kω) R 00000 S.RSISTOR RJGJ X ( kω) R 000000 S.RSISTOR RJGJ 0 X (0 kω) R 00000 S.RSISTOR RJGJ 0 X ( kω) R 00000 S.RSISTOR RJGJ 0 X ( kω) R 000000 S.RSISTOR RJGJ 0 X (0 kω) R 00000 S.RSISTOR RJGJ X (0 kω) R 00000 S.TRIMMR VM-XSX0 B (0) R 00000 S.RSISTOR RJGJ X (0 kω) R0 000000 S.RSISTOR RJGJ 0 X (0 kω) R 000000 S.RSISTOR RJGJ 0 X (0 kω) R 000000 S.RSISTOR RJGJ 0 X (0 kω) R 000000 S.RSISTOR RJGJ X ( kω) R 000000 S.RSISTOR RJGJ X (. kω) R 00000 S.RSISTOR RJGJ 0 X ( MΩ) R 00000 S.RSISTOR RJGJ X (0 kω) R0 000000 S.RSISTOR RJGJ 0 X (0 kω) R 000000 S.RSISTOR RJGJ ( kω) R 000000 S.RSISTOR RJGJ ( kω) R 000000 S.RSISTOR RJGJ X (. kω) R 000000 S.RSISTOR RJGJ ( kω) R 00000 S.RSISTOR RJGJ 0 X ( kω) R 000000 S.RSISTOR RJGJ ( kω) R 000000 S.RSISTOR RJGJ ( kω) R 00000 S.RSISTOR RJGJ X ( kω) R 00000 S.RSISTOR RJGJ X ( kω) R 000000 S.RSISTOR RJGJ X (. kω) R0 00000 S.RSISTOR RJGJ X (0 kω) R 000000 S.RSISTOR RJGJ X (0 kω) R 000000 S.RSISTOR RJGJ X (. kω) R 0000 S.TRIMMR VM-XSX0 B (0) R 00000 S.RSISTOR RJGJ X ( kω) R 00000 S.RSISTOR RJGJ X ( kω) R 00000 S.RSISTOR RJGJ X ( kω) R 00000 S.THRMISTOR TBPSRK0HQ R 000000 S.RSISTOR RJGJ 0 X (0 kω) R 00000 S.RSISTOR RJGJ X (0 kω) R 0000000 S.RSISTOR RJGJ X (0 Ω) R 00000 S.RSISTOR RJGJ X ( kω) R 00000 S.RSISTOR RJGJ 0 X ( kω) R 00000 S.RSISTOR RJGJ 0 X (00 Ω) [LOGIC UNIT] RF ORDR NO. NO. DSCRIPTION R 00000 S.RSISTOR RJGJ X ( kω) R 00000 S.RSISTOR RJGJ X ( kω) R 00000 S.RSISTOR RJGJ X (0 kω) R0 00000 S.RSISTOR RJGJ 0 X ( MΩ) R0 000000 S.RSISTOR MCR0ZHJ 0 Ω () C 0000 S.TANTALUM TMSVA A M-L C 0000 S.CRAMIC CU0KBQ C 0000 S.CRAMIC CUH0JCQ C 0000 S.CRAMIC CUH0JCQ C 0000 S.CRAMIC CU0KBQ C 0000 S.TANTALUM TMSVA A M-L C 0000 S.CRAMIC CU0KBQ C 00000 S.CRAMIC C0 JB C 0KT-N C 0000 S.CRAMIC CU0KBQ C0 00000 S.CRAMIC C00 JB C 0K-T-A C 00000 S.CRAMIC C0 JB C 0KT-N C 00000 S.CRAMIC C0 JB C 0KT-N C 0000 S.CRAMIC CU0KBQ C 0000 S.TANTALUM TMSVA V M-L C 0000 S.TANTALUM TMSVA C M-L C 0000 S.CRAMIC CU0KBQ C 0000 S.CRAMIC CU0KBQ C 0000 S.CRAMIC CU0KBQ C0 0000 S.CRAMIC CU0KBQ C 0000 S.CRAMIC CU0KBQ C 0000 S.CRAMIC CU0KBQ C 0000 S.CRAMIC CU0KBQ C0 0000 S.CRAMIC CU0KBQ C0 0000 S.CRAMIC CU0KBQ C0 0000 S.CRAMIC CU0KBQ C 0000 S.CRAMIC CU0KBQ C 0000 S.TANTALUM TMSVB 0J M-R C 0000 S.CRAMIC CU0KBQ C 0000 S.CRAMIC CU0KBQ C 00000 S.CRAMIC C0 JB C 0KT-N C 0000 S.TANTALUM TMSVB 0J M-L C 0000 S.CRAMIC CU0KBQ C 0000 S.TANTALUM TMSVB 0J M-R C0 00000 S.CRAMIC C00 JB C 0K-T-A C 0000 S.CRAMIC CU0KBQ C 00000 S.CRAMIC C0 JB C K-T-A C 0000 S.CRAMIC CU0KBQ C0 00000 S.CRAMIC C0 JB C K-T-A C0 00000 S.TANTALUM TMSVA A M-L C0 0000 S.CRAMIC CUH0JCQ C0 0000 S.CRAMIC CU0KBQ C0 0000 S.LCTROLYTIC CVCA0SP C0 0000 S.LCTROLYTIC CV0JA0SP C0 0000 S.TANTALUM TMSVA A M-L C0 0000 S.CRAMIC CU0KBQ C0 0000 S.CRAMIC CU0KBQ C0 0000 S.TANTALUM TMSVA A 0M-L C 0000 S.CRAMIC CU0KBQ C 0000 S.LCTROLYTIC CV0JAWP C 0000 S.TANTALUM CST0JYR C 0000 S.TANTALUM TMSVA C M-L C 00000 S.CRAMIC C0 JB C 0KT-N C 00000 S.CRAMIC C0 JB C 0KT-N C 00000 S.CRAMIC C0 JB C 0KT-N C0 00000 S.CRAMIC C0 JB C 0KT-N C0 00000 S.CRAMIC C0 JB H K-T-A C 00000 S.CRAMIC C0 JB C 0KT-N C 00000 S.CRAMIC C0 JB C K-T-A C 00000 S.CRAMIC C0 JB C 0KT-N C 00000 S.CRAMIC C0 JB C 0KT-N C 00000 S.CRAMIC C0 JB C 0KT-N C 00000 S.CRAMIC C0 JB C 0KT-N C 00000 S.CRAMIC CUH0JCQ C 00000 S.CRAMIC C0 JB C 0KT-N C 00000 S.CRAMIC C00 JB C 0K-T-A C0 00000 S.CRAMIC C00 JB C 0K-T-A C 0000 S.CRAMIC CU0KBQ C 00000 S.CRAMIC C0 JB H K-T-A C 00000 S.CRAMIC C0 JB H K-T-A C0 00000 S.CRAMIC C0 JB H K-T-A C0 00000 S.CRAMIC C0 JB H K-T-A C0 000000 S.CRAMIC C0 JB H K-T-A C0 0000 S.CRAMIC CU0KBQ C0 00000 S.CRAMIC C0 JB H K-T-A C0 0000 S.TANTALUM TMSVB 0J M-R S.=Surface mount -
[LOGIC UNIT] RF ORDR NO. NO. C0 0000 S.CRAMIC CU0KBQ C0 00000 S.CRAMIC CUHJCQ C0 0000000 S.CRAMIC C0 JB C K-T-A C0 0000 S.CRAMIC CUKBQ C 0000 S.TANTALUM TMSVA A M-L C 0000 S.CRAMIC CUKBQ C 00000 S.CRAMIC C0 JB H K-T-A C 0000 S.CRAMIC CU0KBQ C 0000 S.CRAMIC CU0KBQ C 0000 S.TANTALUM TMSVA A M-L C 00000 S.CRAMIC C0 JB C K-T-A C 00000 S.CRAMIC C00 JB C 0K-T-A C 0000 S.CRAMIC CU0KBQ C0 0000 S.CRAMIC CU0KBQ C 0000 S.CRAMIC CU0KBQ C 0000 S.CRAMIC CU0KBQ C 0000 S.CRAMIC CU0KBQ C 0000 S.CRAMIC CU0KBQ C 0000 S.CRAMIC CU0KBQ C 0000 S.CRAMIC CU0KBQ C 0000 S.CRAMIC CU0KBQ C 00000 S.CRAMIC C0 JB C K-T-A C 0000 S.CRAMIC CU0KBQ C00 00000 S.CRAMIC C0 JB C 0KT-N C0 0000 S.CRAMIC CUHJCQ C0 0000 S.CRAMIC CU0KBQ C0 00000 S.CRAMIC C00 JB C 0K-T-A C0 00000 S.CRAMIC C0 JB C 0KT-N C0 00000 S.CRAMIC C0 JB C 0KT-N C0 0000 S.TANTALUM CST0JYR C 0000 S.CRAMIC CUH0JCQ C 0000 S.CRAMIC CU0KBQ C 00000 S.CRAMIC C0 JB C 0KT-N C 00000 S.CRAMIC C0 JB C 0KT-N C 00000 S.CRAMIC C0 JB C 0KT-N C 00000 S.CRAMIC C0 JB C 0KT-N C 00000 S.CRAMIC C0 JB C 0KT-N C0 00000 S.CRAMIC C0 JB C K-T-A C 0000 S.CRAMIC CU0KBQ C 0000 S.CRAMIC CU0KBQ C 00000 S.CRAMIC C0 JB C 0KT-N C 0000 S.CRAMIC CU0KBQ C 00000 S.CRAMIC C00 JB C 0K-T-A C 00000 S.CRAMIC C0 JB C 0KT-N C 0000 S.CRAMIC CUH0JCQ C 00000 S.CRAMIC C00 JB C 0K-T-A C 00000 S.CRAMIC C0 JB C 0KT-N C 00000 S.CRAMIC C0 JB C K-T-A C 00000 S.CRAMIC C00 JB C 0K-T-A C 0000000 S.CRAMIC C0 JB C K-T-A C 0000 S.TANTALUM TMSVA A M-L C 0000 S.CRAMIC CU0KBQ C0 0000 S.CRAMIC CU0KBQ C0 0000 S.CRAMIC CU0KBQ C0 0000 S.CRAMIC CU0KBQ C0 0000 S.CRAMIC CU0KBQ C0 0000 S.CRAMIC CU0KBQ C0 0000 S.CRAMIC CU0KBQ C0 0000 S.CRAMIC CU0KBQ C 0000 S.CRAMIC CU0KBQ C 0000 S.CRAMIC CU0KBQ C 0000 S.CRAMIC CU0KBQ C 0000 S.CRAMIC CU0KBQ C 0000 S.CRAMIC CU0KBQ C 00000 S.CRAMIC C0 JB C 0KT-N C 0000 S.CRAMIC CUH0JCQ C 0000 S.CRAMIC CU0KBQ C 0000 S.CRAMIC CU0KBQ J 000 S.CONNCTOR AXKS0P J 00000 S.CONNCTOR HSJ0-000 J 0000 CONNCTOR HSJ-0000 DS 00000 S.LD CL-00YG-C-TS DS 000000 S.LD LTPA DS 000000 LCD LM-B MC 00000 MICROPHON M-0 DSCRIPTION [LOGIC UNIT] RF ORDR NO. NO. DSCRIPTION S 0000 S.ITCH VQ-WRR00 S0 000000 S.ITCH JPM0-0R S0 000000 S.ITCH JPM0-0R W 0000 WIR //00/X/X P 000 PCB B D P 000 LCD CONTACT SRCN--SP-N-W [RF UNIT] RF NO. ORDR NO. DSCRIPTION IC 0000 S.IC BU0BCFV- IC 0000 S.IC BU0BCFV- IC 0000 S.IC S-HG-KC-T IC 0000 S.IC µpct- IC0 0000 S.IC µpct- IC0 00000 S.IC µpct- IC0 0000 S.IC µpd0gs- (DS) IC0 0000 S.IC TBFN (L) IC0 00000 S.IC NJM0AV-T Q 00000 S.TRANSISTOR SD-S (TX) Q 0000 S.TRANSISTOR XP0-(TX) AB Q 00000 S.TRANSISTOR SB T00 R Q 00000 S.TRANSISTOR SB T00 R Q 0000 S.TRANSISTOR UN0 (TX) Q 0000 S.FT HAT0R-L Q 0000 S.TRANSISTOR XP0 (TX) Q 0000 S.TRANSISTOR SC (TL) Q 0000 S.TRANSISTOR UN (TX) Q0 0000 S.TRANSISTOR SC-T Q 0000 S.TRANSISTOR SC-T Q 0000 S.TRANSISTR SC-T R Q 0000 S.TRANSISTOR SC0--TL Q 0000 S.TRANSISTOR SC R-TB Q 0000 S.TRANSISTOR SC0-O (TR) Q 0000 S.TRANSISTOR SC R-TB Q 0000 S.FT MXRRT Q 0000 S.TRANSISTOR UN (TX) Q0 00000 S.TRANSISTOR SD-S (TX) Q0 000000 S.FT SK (TR) Q0 0000 S.TRANSISTOR UN (TX) Q0 00000 S.FT SK (TR) Q0 0000 S.TRANSISTOR XP (TX) Q 0000 S.TRANSISTOR SC-O (TRICOM) Q 00000 S.TRANSISTOR SC-O (TR) Q 0000 S.TRANSISTOR SC-T R Q0 0000 S.TRANSISTOR SC-T Q0 0000 S.TRANSISTOR UN (TX) Q0 0000 S.TRANSISTOR SC-T Q0 0000 S.TRANSISTOR XP (TX) Q0 0000 S.TRANSISTOR UN (TX) Q0 0000 S.TRANSISTOR XP (TX) Q0 00000 S.TRANSISTOR SC-O (TR) Q 00000 S.TRANSISTOR SC-O (TR) Q0 00000 S.FT SK0-Y (TR) Q0 00000 S.FT SK0-Y (TR) Q0 000000 S.TRANSISTOR SC-BL (TR) Q0 0000 S.TRANSISTOR SC0-O (TR) Q 00000 S.FT SK0-Y (TR) Q 000000 S.TRANSISTOR SC-BL (TR) Q 0000 S.TRANSISTOR SC0-O (TR) Q 0000 S.TRANSISTOR SC (M) -T R Q 0000 S.TRANSISTOR UN (TX) Q 0000 S.TRANSISTOR XP (TX) Q 0000 S.TRANSISTOR XP (TX) Q0 0000 S.TRANSISTOR UN (TX) Q 0000 S.TRANSISTOR SC0--TL Q 0000 S.TRANSISTOR SC0-O (TR) Q 0000 S.TRANSISTOR SC0-O (TR) Q 0000 S.TRANSISTOR SC-T Q 0000 S.TRANSISTOR UN (TX) S.=Surface mount -