EE434 ASIC & Digital Systems Arithmetic Circuits Spring 25 Dae Hyun Kim daehyun@eecs.wsu.edu
Arithmetic Circuits What we will learn Adders Basic High-speed 2
Adder -bit adder SSSSSS = AA BB CCCC CCCC = AA BB + BB CCCC + AA CCCC AA BB CCCC FA CCCC SS 3
Adder n-bit Adder BB nn BB nn 2 BB AA nn AA nn 2 AA CCCC CCCC SS nn SS nn 2 SS 4
Adder Two-operand adders Ripple carry adder Carry select adder Conditional sum adder Carry skip adder Prefix adders Carry lookahead adder Ling adder 5
Ripple Carry Adder BB nn AA nn BB nn 2 AA nn 2 BB 2 AA 2 BB AA BB AA CCCC nn CCCC nn CCCC nn 2 CCCC nn 2 CCCC 2 CCCC 2 CCCC CCCC CCCC CCCC FA FA FA FA FA CCCC SS nn SS nn 2 SS 2 SS SS 6
Ripple Carry Adder Delay computation FA delay: FFFF n-bit RCA delay: nn FFFF BB nn AA nn BB nn 2 AA nn 2 BB 2 AA 2 BB AA BB AA CCCC nn CCCC nn CCCC nn 2 CCCC nn 2 CCCC 2 CCCC 2 CCCC CCCC CCCC CCCC FA FA FA FA FA CCCC SS nn SS nn 2 SS 2 SS SS 7
Adder Bottleneck Carry propagation How to improve Parallelization 8
Carry Select Adder CCCC 2kk k-bit adder CCCC kk CCCC 2kk k-bit adder k-bit MUX CCCC kk k-bit adder CCCC CCCC 2kk SS 2kk SS kk SS kk SS 9
Carry Select Adder Example ii: 7 6 5 4 3 2 AA ii : BB ii : CCCC = 4-bit adder 4-bit adder 4-bit MUX 4-bit adder
Carry Select Adder Optimization example 64-bit carry select adder Assumptions The k-bit adder is a ripple-carry adder. Delay of a k-bit adder: kk FFFF Delay of a carry-out logic or a MUX: εε
Carry Select Adder Optimization k-bit adder k-bit adder k-bit adder k-bit adder k-bit adder k-bit adder CO logic CO logic CO logic k-bit MUX CCCC 3kk k-bit MUX CCCC 2kk k-bit MUX CCCC kk k-bit adder CCCC 4kk SS 4kk SS 3kk CCCC 3kk SS 3kk SS 2kk SS 2kk SS kk SS kk SS Delay: kk FFFF + 3 εε 2
Carry Select Adder Optimization (N-bit adder) k-bit adder # groups: N/k # Carry-out logic stages: N/k Delay: τ = kk FFFF + εε( NN kk ) ddττ = ddkk FFFF NN εε = kk 2 kk = NN εε FFFF 3
Carry Select Adder Delay: kk = NN εε FFFF Example 64-bit adder, FFFF = 2pppp, εε = 4pppp kk = 64 4 2 = 3.57 kk = 4. Delay: ττ = 4 2pppp + 4pppp 64 4 = 4pppp 4
Conditional Sum Adder Generate two sets of outputs for a given group of operand bits. Set : assumes the incoming carry is zero. Set 2: assumes the incoming carry is one. Once the incoming carry is known, select the correct set of outputs. 5
Conditional Sum Adder Generate two sets of outputs for a given group of operand bits. BB ii AA ii CCCC ii (= CCII ii+ ) FA CCCC ii SS ii Assuming incoming carry (CCCC ii ) = SS ii = SS ii = AA BB Delay = FFFF CCCC ii = CCCC ii = AA BB + (AA + BB) Delay = FFFF Assuming incoming carry (CCCC ii ) = SS ii = SS ii = AA BB Delay = FFFF CCCC ii = CCCC ii = AA BB + (AA + BB) Delay = FFFF 6
Conditional Sum Adder Generate two sets of outputs Step ii: 7 6 5 4 3 2 AA ii : BB ii : SS ii : CCCC ii : SS ii : CCCC ii : CCCC = 7
Conditional Sum Adder Merge two bits Step Step 2 ii: 7 6 5 4 3 2 AA ii : BB ii : SS ii : CCCC ii : SS ii : CCCC ii : SS ii : CCCC ii : SS ii : CCCC ii : CCCC = 8
Conditional Sum Adder Merge four bits Step Step 2 Step 3 ii: 7 6 5 4 3 2 AA ii : BB ii : SS ii : CCCC ii : SS ii : CCCC ii : SS ii : CCCC ii : SS ii : CCCC ii : SS ii : CCCC ii : SS ii : CCCC ii : CCCC = 9
Conditional Sum Adder Final Step Step 2 Step 3 ii: 7 6 5 4 3 2 AA ii : BB ii : SS ii : CCCC ii : SS ii : CCCC ii : SS ii : CCCC ii : SS ii : CCCC ii : SS ii : CCCC ii : SS ii : CCCC ii : Result CCCC = 2
Conditional Sum Adder Exercise Step Step 2 Step 3 Result ii: 7 6 5 4 3 2 AA ii : BB ii : SS ii : CCCC ii : SS ii : CCCC ii : SS ii : CCCC ii : SS ii : CCCC ii : SS ii : CCCC ii : SS ii : CCCC ii : CCCC = 2
Conditional Sum Adder Analysis Step Step 2 Step 3 ii: 7 6 5 4 3 2 AA ii : BB ii : SS ii : CCCC ii : SS ii : CCCC ii : SS ii : CCCC ii : SS ii : CCCC ii : SS ii : CCCC ii : SS ii : CCCC ii : ττ = FFFF ττ = FFFF + MMMMMM ττ = FFFF + 2 MMMMMM 22
Conditional Sum Adder Analysis N-bit conditional sum adder Delay of a -bit adder: FFFF Delay of a MUX: MMMMMM Delay: ττ = FFFF + (log 2 NN ) MMMMMM FFFF = 2pppp, NN = 64, MMMMMM = 8pppp ττ = 6pppp 23
Carry Skip Adder Split the input into a few groups. BB 5:2 AA 5:2 BB :8 AA :8 BB 7:4 AA 7:4 BB 3: AA 3: CC 6 4-bit block CC 2 4-bit block CC 8 4-bit block CC 4 4-bit block Carry generation (C 4, C 8, C 2, C 6, ) Generated internally Carry propagation Propagated only when p is. pp ii = AA ii BB ii pp ii+3:ii = pp ii+3 pp ii+2 pp ii+ pp ii 24
Carry Skip Adder Split the input into a few groups. Propagate carries. BB 5:2 AA 5:2 BB :8 AA :8 BB 7:4 AA 7:4 BB 3: AA 3: 4-bit block cc 2 4-bit block cc 8 4-bit block cc 4 cc 4-bit block cc 6 pp 5:2 pp :8 pp 7:4 pp 3: 25
Carry Skip Adder Exercise A = B = CI = BB 5:2 AA 5:2 BB :8 AA :8 BB 7:4 AA 7:4 BB 3: AA 3: 4-bit block cc 2 4-bit block cc 8 4-bit block cc 4 cc 4-bit block cc 6 pp 5:2 pp :8 pp 7:4 pp 3: 26
Carry Skip Adder Analysis N-bit carry skip adder Assumptions The k-bit adder is a ripple-carry adder. Delay of a k-bit adder: kk FFFF Delay of a MUX: εε Delay: ττ = kk FFFF + NN kk εε 27
Prefix Adder Carry generate GG ii = AA ii BB ii GG ii = only when AA ii, BB ii =, Carry propagate PP ii = AA ii BB ii (conceptually AA ii BB ii, practically AA ii + BB ii ) PP ii = only when AA ii, BB ii =, or, Carry out CC ii+ = AA ii BB ii + AA ii CC ii + BB ii CC ii = AA ii BB ii + CC ii AA ii + BB ii = AA ii BB ii + CC ii AA ii BB ii = GG ii + CC ii PP ii Sum SS ii = AA ii BB ii CC ii = PP ii CC ii 28
Prefix Adder Two blocks, B and B 2 overlap. (generate, propagate) of B : (g, p ) (generate, propagate) of B 2 : (g 2, p 2 ) B B 2 Merge B and B 2 into B (generate, propagate) of B: (g, p) B gg = gg + pp gg 2 pp = pp pp 2 29
Prefix Adder Example BB AA BB AA PP GG PP GG CC PP [:] = PP PP GG [:] = GG + PP GG PP ii and GG ii generation 3
Prefix Adder Basic principle Carry determination Given (gg, pp ) (gg, pp ) (gg ii 2, pp ii 2 ) (gg ii, pp ii ) Find (gg [:], pp [:] ) (gg [:], pp [:] ) (gg [ii 2:], pp [ii 2:] ) (gg [ii :], pp [ii :] ) Sum Given xx xx xx ii 2 xx ii Find xx xx + xx xx + xx + + xx ii 2 xx + xx + + xx ii 3
Prefix Adder Basic principle gg 3,pp 3 gg 2,pp 2 gg,pp gg,pp + + c c + + c c Sum network gg [2:],pp [2:] gg [:],pp [:] gg [3:],pp [3:] gg [:],pp [:] Carry network 32
Prefix Adder SS ii = AA ii BB ii CC ii Propagate carries gg ii,pp ii gg kk,pp kk GG ii = AA ii BB ii PP ii = AA ii BB ii SS ii = PP ii CC ii CC ii+ = GG ii + CC ii PP ii = gg, pp = (gg ii + pp ii gg kk, pp ii pp kk ) 33
Prefix Adder Example (ripple carry adder) xx 5 xx 4 xx 3 xx 2 xx xx xx 9 xx 8 xx 7 xx 6 xx 5 xx 4 xx 3 xx 2 xx xx ss 4 ss 3 ss 2 ss ss ss 9 ss 8 ss 7 ss 6 ss 5 ss 4 ss 3 ss 2 ss ss ss 5 34
Prefix Adder Kogge-Stone (min. logic depth, min. fanout, large area, routing) xx 5 xx 4 xx 3 xx 2 xx xx xx 9 xx 8 xx 7 xx 6 xx 5 xx 4 xx 3 xx 2 xx xx ss 5 ss 4 ss 3 ss 2 ss ss ss 9 ss 8 ss 7 ss 6 ss 5 ss 4 ss 3 ss 2 ss ss 35
Prefix Adder Brent-Kung (max. logic depth, min. area) xx 5 xx 4 xx 3 xx 2 xx xx xx 9 xx 8 xx 7 xx 6 xx 5 xx 4 xx 3 xx 2 xx xx ss 5 ss 4 ss 3 ss 2 ss ss ss 9 ss 8 ss 7 ss 6 ss 5 ss 4 ss 3 ss 2 ss ss 36
Prefix Adder Ladner-Fischer (min. logic depth, large fanout) xx 5 xx 4 xx 3 xx 2 xx xx xx 9 xx 8 xx 7 xx 6 xx 5 xx 4 xx 3 xx 2 xx xx ss 5 ss 4 ss 3 ss 2 ss ss ss 9 ss 8 ss 7 ss 6 ss 5 ss 4 ss 3 ss 2 ss ss 37
Prefix Adder Han-Carlson (Brent-Kung + Kogge-Stone) xx 5 xx 4 xx 3 xx 2 xx xx xx 9 xx 8 xx 7 xx 6 xx 5 xx 4 xx 3 xx 2 xx xx ss 5 ss 4 ss 3 ss 2 ss ss ss 9 ss 8 ss 7 ss 6 ss 5 ss 4 ss 3 ss 2 ss ss 38
Prefix Adder Analysis Generation of PP ii and GG ii : cc Merging: mm Sum: ss Delay: cc + kk mm + ss Example (6-bit adder) Ripple carry: cc + 5 mm + ss Kogge-Stone: cc + log 2 6 mm + ss = cc + 4 mm + ss Brent-Kung: cc + 6 mm + ss Ladner-Fischer: cc + log 2 6 mm + ss = cc + 4 mm + ss Han-Carlson: cc + 5 mm + ss 39
Carry Lookahead Adder Carry generate GG ii = AA ii BB ii GG ii = only when AA ii, BB ii =, Carry propagate PP ii = AA ii BB ii PP ii = only when AA ii, BB ii =, or, Sum SS ii = AA ii BB ii CC ii = PP ii CC ii Carry out CC ii+ = AA ii BB ii + AA ii CC ii + BB ii CC ii = AA ii BB ii + CC ii AA ii + BB ii = AA ii BB ii + CC ii AA ii BB ii = GG ii + CC ii PP ii 4
Carry Lookahead Adder Carry-out logic CC = GG + PP CC CC 2 = GG + PP CC = GG + PP GG + PP PP CC CC 3 = GG 2 + PP 2 CC 2 = GG 2 + PP 2 GG + PP 2 PP GG + PP 2 PP PP CC GG ii = AA ii BB ii PP ii = AA ii BB ii SS ii = PP ii CC ii CC ii+ = GG ii + CC ii PP ii CC 4 = GG 3 + PP 3 CC 3 = GG 3 + PP 3 GG 2 + PP 3 PP 2 GG + PP 3 PP 2 PP GG + PP 3 PP 2 PP PP CC Carry lookahead unit PP 3 GG 3 PP 2 GG 2 PP GG PP GG CC 4 Carry Lookahead Unit CC SS 3 4
Carry Lookahead Adder Delay computation GG ii, PP ii : gate delay SS : 2 gate delays CC = GG + PP CC : 3 gate delays CC 2 = GG + PP GG + PP PP CC : 3 gate delays CC 3 = GG 2 + PP 2 GG + PP 2 PP GG + PP 2 PP PP CC : 3 gate delays CC 4 = GG 3 + PP 3 GG 2 + PP 3 PP 2 GG + PP 3 PP 2 PP GG + PP 3 PP 2 PP PP CC : 3 gate delays SS, SS 2, SS 3 : 4 gate delays GG ii = AA ii BB ii PP ii = AA ii BB ii SS ii = PP ii CC ii CC ii+ = GG ii + CC ii PP ii 42
Carry Lookahead Adder A 4-bit carry lookahead adder BB 3 AA 3 BB 2 AA 2 BB AA BB AA Generate PP ii and GG ii. PP 3 GG 3 PP 2 GG 2 PP GG PP GG PP 3 GG 3 PP 2 GG 2 PP GG PP GG CC 4 Carry Lookahead Unit CC SS 3 43
Carry Lookahead Adder A 6-bit carry lookahead adder BB FF AA FF BB EE AA EE BB DD AA DD BB CC AA CC BB BB AA BB BB AA AA AA BB 9 AA 9 BB 8 AA 8 BB 7 AA 7 BB 6 AA 6 BB 5 AA 5 BB 4 AA 4 BB 3 AA 3 BB 2 AA 2 BB AA BB AA CC CC 6 SS 5 2 SS 8 SS 7 4 SS 3 PP ii and GG ii generation 4-bit carry lookahead unit 44
Carry Lookahead Adder Multi-level carry lookahead adder BB FF AA FF BB EE AA EE BB DD AA DD BB CC AA CC BB BB AA BB BB AA AA AA BB 9 AA 9 BB 8 AA 8 BB 7 AA 7 BB 6 AA 6 BB 5 AA 5 BB 4 AA 4 BB 3 AA 3 BB 2 AA 2 BB AA BB AA CC CC 6 SS 5 2 PP 5 2 GG 5 2 SS 8 PP 8 GG 8 SS 7 4 PP 7 4 GG 7 4 SS 3 PP 3 GG 3 PP ii and GG ii generation 4-bit carry lookahead unit with PP ii and GG ii. Multi-level carry lookahead unit 45
Carry Lookahead Adder Multi-level carry lookahead adder BB FF AA FF BB EE AA EE BB DD AA DD BB CC AA CC BB BB AA BB BB AA AA AA BB 9 AA 9 BB 8 AA 8 BB 7 AA 7 BB 6 AA 6 BB 5 AA 5 BB 4 AA 4 BB 3 AA 3 BB 2 AA 2 BB AA BB AA PP 5 2 GG 5 2 PP 8 GG 8 PP 7 4 GG 7 4 PP 3 GG 3 CC CC 6 SS 5 2 SS 8 SS 7 4 SS 3 PP 5 2 GG 5 2 CC 2 PP 8 GG 8 CC 8 PP 7 4 GG 7 4 CC 4 PP 3 GG 3 CC 6 CC 6 GG [ii+3,ii] : Block generate PP [ii+3,ii] : Block propagate PP ii and GG ii generation 4-bit carry lookahead unit with PP ii and GG ii. Multi-level carry lookahead unit 46
Carry Lookahead Adder Carry recurrence formula CC ii+ = GG ii + PP ii CC ii CC ii+4 = GG ii+3 + PP ii+3 CC ii+3 = GG ii+3 + PP ii+3 GG ii+2 + PP ii+2 CC ii+2 = GG ii+3 + PP ii+3 GG ii+2 + PP ii+3 PP ii+2 CC ii+2 = = GG ii+3 + PP ii+3 GG ii+2 + PP ii+3 PP ii+2 GG ii+ + PP ii+3 PP ii+2 PP ii+ GG ii + PP ii+3 PP ii+2 PP ii+ PP ii CC ii Block generate GG [ii+3,ii] = GG ii+3 + PP ii+3 GG ii+2 + PP ii+3 PP ii+2 GG ii+ + PP ii+3 PP ii+2 PP ii+ GG ii Block propagate PP [ii+3,ii] = PP ii+3 PP ii+2 PP ii+ PP ii Carry out CC ii+4 = GG [ii+3,ii] + CC ii PP [ii+3,ii] 47
Carry Lookahead Adder Delay computation GG ii, PP ii : gate delay Block propagate PP [ii+3,ii] = PP ii+3 PP ii+2 PP ii+ PP ii : 2 gate delays Block generate GG [ii+3,ii] = GG ii+3 + PP ii+3 GG ii+2 + PP ii+3 PP ii+2 GG ii+ + PP ii+3 PP ii+2 PP ii+ GG ii : 3 gate delays Carry out CC 4 = GG [3,] + CC PP [3,] : 4 gate delays CC 8 = GG [7,4] + CC 4 PP 7,4 = GG 7,4 + PP 7,4 GG 3, + PP 7,4 PP [3,] CC : 5 gate delays CC 2 : 5 gate delays CC 6 : 5 gate delays Sum SS [7,4] : 7 gate delays SS [,8] : 8 gate delays SS [5,2] : 8 gate delays 48
Carry Lookahead Adder BB 5:2 AA 5:2 BB :8 AA :8 BB 7:4 AA 7:4 BB 3: AA 3: 4-bit adder CC 2 4-bit adder CC 8 4-bit adder 4-bit adder P G P G P G P G CC 4 CC SS 5:2 SS :8 SS 7:4 SS 3: PP 3 GG 3 CC 3 PP 2 GG 2 PP GG CC CC 2 PP GG CC 6 CC 4 Lookahead Carry Unit CC CC PP 3 GG 3 49
Ling Adder A type of carry lookahead adder Achieves significant hardware savings. Modifications PP ii = AA ii BB ii tt ii = AA ii + BB ii h ii = CC ii + CC ii CC ii = GG ii + CC ii PP ii = repeated CC ii PP ii = CC ii PP ii + GG ii PP ii + PP ii CC ii PP ii = CC ii PP ii + (GG ii + PP ii CC ii ) PP ii = (CC ii + CC ii ) PP ii =CC ii = h ii PP ii 5
Ling Adder Modifications tt ii = AA ii + BB ii h ii = CC ii + CC ii GG ii h ii GG ii CC ii = GG ii + CC ii PP ii = GG ii + h ii PP ii = h ii GG ii + h ii PP ii = h ii GG ii + PP ii = h ii tt ii h ii = CC ii + CC ii = GG ii + CC ii PP ii + CC ii = GG ii + CC ii = GG ii + h ii tt ii 2 h ii = GG ii + h ii tt ii 2 = GG ii + tt ii 2 (GG ii 2 + h ii 2 tt ii 3 ) = GG ii + GG ii 2 + h ii 2 tt ii 2 tt ii 3 tt ii 2 GG ii 2 = GG ii 2 = GG ii + GG ii 2 + GG ii 3 tt ii 2 + GG ii 4 tt ii 2 tt ii 3 + h ii 4 tt ii 2 tt ii 3 tt ii 4 5
Ling Adder Modifications CC ii+4 = GG ii+3 + GG ii+2 tt ii+3 + GG ii+ tt ii+3 tt ii+2 + GG ii tt ii+3 tt ii+2 tt ii+ + CC ii tt ii+3 tt ii+2 tt ii+ tt ii SS ii = tt ii h ii+ + GG ii tt ii h ii Advantages Lower fan-in Suitable for some specific technologies. 52