Lecture Stage Frequency Response (1/10/02) Page 210-1

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1 Lecture Stage Frequency Response (1/10/02) Page 2101 LECTURE 210 DC ANALYSIS OF THE 741 OP AMP (READING: GHLM ) Objective The objective of this presentation is to: 1.) Identify the devices, circuits, and stages in the 741 operational amplifier 2.) Perform a dc bias analysis 3.) Compare hand calculations of dc analyses with PSpice simulations Outline 741 circuit topology and analysis PSpice analysis techniques and results Summary Lecture Stage Frequency Response (1/10/02) Page 2102 Circuit 741 OPERATIONAL AMPLIFIER Q12 Q9 Q8 Q19 Q15 R 5 Q11 39kΩ Q7 Q10 Q5 R 6 R 10 27Ω 40kΩ R 7 Q23B Q23A 27Ω Q21 v out Q22 Q24 R 4 R 1 R 3 R2 R 9 R 8 5kΩ 1kΩ 1kΩ 100Ω V EE Fig The 741 op amp is typical of a widely used standalone operational amplifiers.

2 Lecture Stage Frequency Response (1/10/02) Page 2103 Simplified, Conceptual Schematic Diagram of the 741 Op Amp V Bias Q19 v out Q23 Q5 V EE V EE Fig Lecture Stage Frequency Response (1/10/02) Page 2104 Multicollector Lateral PNP nepitaxial n (B) E E p (C 1 ) p (E) B 3 1 p (C 2 ) C 1 C 2 C 1 C 2 I s1 = 0.75Is I s2 = 0.25Is Is is the saturation current of the structure with both collectors connected together. B Fig

3 Lecture Stage Frequency Response (1/10/02) Page 2105 DC Analysis of the 741 Op Amp Bias circuitry: = 15V I ref Q12 R 5 39kΩ I 2 I 3 I1 I ref = V EE 2V BE R 5 = 733µA I 2 = I 13B = 0.75I ref = 550µA I 3 = I 13A = 0.25I ref = 180µA Q11 R 4 5kΩ Q10 I 1 = I 10 = V t R 4 [ln(i ref ) ln(i 1 )] = 19µA V EE = 15V Fig Lecture Stage Frequency Response (1/10/02) Page 2106 Simplified Schematic of the 741 Op Amp with Idealized Biasing = 15V Q9 Q8 550µA 180µA R 10 40kΩ Q19 R 6 27Ω R 7 27Ω v out 19µA Q5 Q7 Q23 R 1 R 3 R2 R9 R 8 1kΩ 1kΩ 100Ω V EE = 15V Fig

4 Lecture Stage Frequency Response (1/10/02) Page 2107 Input Stage Biasing of the 741 Op Amp = 15V I C9 Q9 Q8 I A I A2 I A2 19µA Q7 Q5 R 1 R 3 R2 1kΩ 1kΩ V EE = 15V Fig I A = I 8 = I 9 = 19µA I A2 = 9.5µA 9.5µA V BE5 = V t ln I SNPN = 0.553V I SNPN = 5fA V BE5 = 0.555V V B5 = V BE5 R 1 9.5µA = 0.565V I R3 = I 7 = V B5 R = 11.3µA 3 Lecture Stage Frequency Response (1/10/02) Page 2108 Darlington Gain Stage Biasing 550µA V BE17 = V t ln I SNPN V B17 = V BE17 R 8 550µA = 0.716V I R9 = V B17 R 9 = 14.3µA I B17 = 550µA β1 = 2.2µA R 9 R 8 100Ω I 16 = I B17 I R9 = 16.5µA V EE Fig

5 Lecture Stage Frequency Response (1/10/02) Page 2109 Output Stage Biasing of the 741 Op Amp = 15V I C 180µA R Q19 6 V 27Ω Bias I OUT R 10 R 7 40kΩ 27Ω V OUT Q23 V IN V EE = 15V Fig I 19 = V t I 18 R 10 ln I SNPN I 18 I 19 = 180µA I 18 = 164µA I 19 = 15.7µA V BE18 V BE19 V BE14 V BE20 I 18 I 19 I SNPN18 I SNPN19 = I SNPN14 = 4.5 I SNPN I S20 = 10fA I 14 = 150µA I 14 2 I SNPN14 I SNPN20 Lecture Stage Frequency Response (1/10/02) Page Circuit for SPICE Simulation 21 Q9 Q12 R 5 39kΩ Q11 Q10 Q Q Q Q22 Q19 Q15 R 4 R 1 R 3 R2 R R 9 8 5kΩ 1kΩ 1kΩ 100Ω R 16 6 R 10 27Ω 40kΩ 20 Q23B Q23A 27Ω Q21 Q24 18 v out V EE Fig R 7

6 Lecture Stage Frequency Response (1/10/02) Page Spice Simulations of the 741 Op Amp ua741 Operational Amp Spice File 741 OP AMP BIAS CIRCUIT Q PNP Q NPN Q NPN PNP PNP 3 Q NPN Q PNP Q NPN Q NPN Q23B PNP R K R K R K CC PF DIFF AMP Q NPN Q NPN PNP PNP Q NPN NPN Q NPN Q PNP Q PNP R K R K R K DARLINGTON NPN NPN R K R OUTPUT STAGE Q NPN NPN Q23A PNP NPN SPNP R K R R POWER SUPPLY VCC 21 0 DC=15 VEE 22 0 DC=15 ANALYSIS DC Sweep to find input offset voltage Connect output to inverting input for unity gain buffer Rshort VIN 1 0 DC 0 AC 0.DC VIN 15V 15V.1V Now provide input offset voltage VIN 2 0 DC= UV AC=0 Open Loop Gain Remove Rshort VIN 1 0 AC=1 VIN 2 0 DC= UV AC=0.AC DEC MEG Lecture Stage Frequency Response (1/10/02) Page SPICE File Continued.TF V(20) VIN Slew Rate Connect output (node 20 to node 2 with Rshort) VIN 1 0 PULSE (0 1 10us.001us.001us 10us 30us).TRAN.5us 30us.MODEL NPN NPN(IS=5E15 RB=200 RC=250 BF=250 BR=2 RE=2 VA=130 TF=.35NS CJE=1PF PE=.7V ME=.33 CJC=.3PF PC=.55V MC=.5 CCS=3PF PS=.52 MS=.5V).MODEL PNP PNP(IS=2E15 RB=300 RC=300 RE=10 BF=50 BR=4 VA=50 TF=30NS CJE=.3PF PE=.55V ME=.5 CJC=2PF PC=.55V MC=.5 CCS=3PF PS=.52V MS=.5V).MODEL SPNP PNP(IS=1E14 RB=150 RC=50 RE=2 BR=4 BF=50 VA=50 TF=20NS CJE=.5PF PE=.55V ME=.5 CJC=2PF PC=.52V MC=.5 CCS=3PF PS=.52V MS=.5V).OPTIONS LIMPTS=0.PROBE.END

7 Lecture Stage Frequency Response (1/10/02) Page Node Voltages SMALL SIGNAL BIAS SOLUTION TEMPERATURE = DEG C NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE ( 1) ( 2) 851.3E06 ( 3) (4) ( 5) ( 6) ( 7) ( 8) ( 9) ( 10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) 5.094E06 (21) (22) (23) (24) (25) (26) Lecture Stage Frequency Response (1/10/02) Page Bipolar Junction Transistors NAME Q5 MODEL NPN NPN PNP PNP NPN IB 3.44E E E E E08 IC 7.63E E E E E06 VBE 5.44E E E E E01 VBC 1.44E E E E E01 VCE 1.50E E E E E00 BETADC 2.22E E E E E02 GM 2.95E E E E E04 RPI 7.53E E E E E05 RX 2.00E E E E E02 RO 1.89E E E E E07 CBE 1.59E E E E E12 CBC 5.75E E E E E13 CJS 5.60E E E E E11 BETAAC 2.22E E E E FT/FT2 2.85E E E E e07 NAME Q7 Q8 Q9 MODEL NPN NPN PNP PNP NPN IC 7.52E E E E E05

8 Lecture Stage Frequency Response (1/10/02) Page Bipolar Junction Transistors Continued NAME Q12 Q11 Q10 MODEL PNP NPN NPN PNP PNP IB 1.34E E E E e05 IC 6.70E E E E E03 VBE 6.97E E E E VBC 0.00E E E E E01 VCE 6.97E E E E BETADC 4.98E E E E GM 2.59E E E E RPI 1.92E E E E RX 3.00E E E E NAME Q19 Q23A MODEL NPN NPN NPN PNP NPN SNPN IC 2.51E E E E E E04 VBE 7.02E E E E E E01 Comparison: Transistor Q5 Q7 Q8 Q9 Q10 Q11 Caculated 9.5µA 9.5µA 9.5µA 9.5µA 9.5µA 9.5µA 11.3µA 19µA 19µA 19µA 733µA SPICE 7.63µA 7.73µA 7.75µA 7.65µA 7.50µA 7.52µA 11.1µA 14.8µA 19.3µA 19.6µA 731µA Transistor Q11 Q12 Q12 Q19 Caculated 733µA 733µA 733µA 813µA 550µA 150µA 16.5µA 550µA 164µA 15.7µA 150µA SPICE 731µA 670µA 670µA 813µA 2500µA 290µA 30µA 2510µA 791µA 20.6µA 287µA Lecture Stage Frequency Response (1/10/02) Page PSpice Simulation Results Dynamic Range and Input Offset Voltage: 15V 10V 0V ( , u) 10V ( , ) 15V 15V 10V 5V 0V 5V 10V 15V V( 20) VI N

9 Lecture Stage Frequency Response (1/10/02) Page SUMMARY The 741 is a classic Op Amp that exemplifies many of our ECE 6412 circuit concepts DC bias in almost all transistors is set by R 5 Hand calculated and PSpice bias currents compare favorably (except for )