DIGITAL DESIGN WITH AN INTRODUCTION TO THE VERILOG HDL Fifth Edition

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1 SOLUTIONS MANUAL DIGITAL DESIGN WITH AN INTRODUCTION TO THE VERILOG HDL ifth Edition M. MORRIS MANO Professor Emeritus California State Universit, Los Angeles MICHAEL D. CILETTI Professor Emeritus Universit of Colorado, Colorado Springs rev 2/4/22 Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copright 22,

2 2 CHAPTER. Base-: Octal: He: A B C D E 2 Base A B (a) 32,768 (b) 67,8,864 (c) 6,87,947,674.3 (43) 5 = 4 * * * 5 = 58 (98) 2 = * * * 2 = 26 (435) 8 = 4 * * * 8 = 285 (345) 6 = 3 * * * 6 = bit binar: Decimal equivalent: = 65,535 Headecimal equivalent: 6.5 Let b = base (a) 4/2 = (b + 4)/2 = 5, so b = 6 (b) 54/4 = (5*b + 4)/4 = b + 3, so 5 * b = 52 4, and b = 8 (c) (2 *b + 4) + (b + 7) = 4b, so b =.6 ( 3)( 6) = 2 (6 + 3) + 6*3 = Therefore: = b + m, so b = 8 Also, 6*3 = (8) = (22) CD 6 = 2 = = (6235 ) 8.8 (a) Results of repeated division b 2 (quotients are followed b remainders): 43 = 25(); 7(); 53(); 26(); 3(); 6() 3() () Answer: _ 2 = A 6 (b) Results of repeated division b 6: 43 = 26(5); () (aster) Answer: A = _.9 (a). 2 = = (b) = *(.65) = (c) = 2 * /8 + 4/64 = (d) DADA.B 6 = 4*6 3 + * *6 + + /6 = 6, Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copright 22,

3 3 (e). 2 = =.825. (a). 2 =. 2 =.9 6 = + 9/6 =.563 (b). 2 =. 2 = = 6 + 4/6 = 6.25 Reason:. 2 is the same as. 2 shifted to the left b two places.... The quotient is carried to two decimal places, giving. Checking: 2 / 2 = 59 / 5. 2 = (a) and (b) 62 h and 958 h + = 6 = 55 2E h _ 2E h +34 h _ 34 h 62 h _ = 98 B A h = (a) Convert to binar: Integer Remainder Coefficient Quotient 27/2 = 3 + ½ a = 3/2 6 + ½ a = 6/2 3 + a 2 = 3/2 + ½ a 3 = ½ + ½ a 4 = Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copright 22,

4 4 27 = 2 Integer raction Coefficient.35 2 = +.63 a - =.63 2 = +.26 a -2 =.26 2 = +.52 a -3 =.52 2 = +.4 a -4 = = = (b) 2/ Integer raction Coefficient.6666_6666_67 2 = _3333_34 a - = = a -2 = = a -3 = = a -4 = = a -5 = = a -6 = = a -7 = = a -8 = = = =._ 2 =.AA 6 = /6 + /256 =.664 (Same as (b))..4 (a) _ (b) _ (c) _ s comp: _ s comp: _ s comp: _ 2s comp: _ 2s comp: _ 2s comp: _ (d) _ (e) _ (f) _ s comp: _ s comp: _ s comp: _ 2s comp: _ 2s comp: _ 2s comp: _ `.5 (a) 25,478,36 (b) 63,325,6 9s comp: 74,52,963 9s comp: 36,674,399 s comp: 74,52,964 s comp: 36,674,4 (c) 25,, (d) 9s comp: 74,999,999 9s comp: s comp: 75,, s comp:.6 C3D C3D: 5s comp: 3C2 s comp: 6s comp: 3C2 2s comp: = 3C2.7 (a) 2,579 2,579 97,42 (9s comp) 97,42 (s comp) ,579 = 2, ,42 = 258 (b) (9s comp) 982 ( comp) 25 8 = = (negative) Magnitude: 675 Result: 25 8 = 675 Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copright 22,

5 5 (c) 4, (9s comp) (s comp) = = (Negative) Magnitude: 238 Result: = -238 (d) (9s comp) (s comp) = = 886 (Positive) Result: = Note: Consider sign etension with 2s complement arithmetic. (a) _ (b) _ s comp: _ s comp: _ with sign etension 2s comp: _ 2s comp: _ Diff: _ (Positive) _ sign bit indicates that the result is negative Check:9-8 = + _ s complement _ 2s complement magnitude Result: -4 Check: = -4 (c) _ (d) _ s comp: _ s comp: _ with sign etension 2s comp: _ 2s comp: _ Diff: _ (negative) _ sign bit indicates that the result is positive _ (s comp) Result: 9 _ (2s complement) Check: 4 2 = 9 (magnitude) -44 (result) ; +8 8; ; (a) (+9286) + (_8) = = 87 (b) (+9286) + (-8) = = 8485 (c) (-9286) + (+8) = = 9955 (d) (-9286) + (-8) = = _ (Needs leading ero etension to indicate + value); +29 _ (Leading indicates + value) -49 _ + _ _ -29 _ (sign etension indicates negative value) (a) (+29) + (-49) = _ + _ = _ ( indicates negative value.) Magnitude = _ + _ = _ = 2; Result (+29) + (-49) = -2 (b) (-29) + (+49) = _ + _ = _ ( indicates positive value) (-29) + (+49) = +2 Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copright 22,

6 6 (c) Must increase word sie b (sign etension) to accomodate overflow of values: (-29) + (-49) = _ + _ = _ ( indicates negative result) Magnitude: _ = 78 Result: (-29) + (-49) = (9's comp) (s) comp (9's comp) (s) comp (a) (+9742) + (+64) 383 (b) (+9742) + (-64) = 92 Result: (+9742) + (-64) = 92 (c) -9742) + (+64) = = (negative) Magnitude: 9 Result: (-9742) + (64) = -9 (d) (-9742) + (-64) = = (Negative) Magnitude: 383 Result: (-9742) + (-64) = ,54 BCD: ASCII: ASCII:.23 ( 79) (+658) (,449).24 (a) (b) 6 3 Decimal (or ) (or ) Decimal (or ) (a) 6,248 BCD: (b) Ecess-3: (c) 242: (d) 63: Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copright 22,

7 7.26 6,248 9s Comp: 3, code: s comp c: (242 code alternative #) 6, (242 code alternative #2) s comp c Match Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copright 22,

8 8.27 or a deck with 52 cards, we need 6 bits (2 5 = 32 < 52 < 64 = 2 6 ). Let the msb's select the suit (e.g., diamonds, hearts, clubs, spades are encoded respectivel as,,, and. The remaining four bits select the "number" of the card. Eample: (ace) through (9), plus through (jack, queen, king). This a jack of spades might be coded as _. (Note: onl 52 out of 64 patterns are used.).28 G (dot) (space) B o o l e.29 Steve Jobs E5 76 E5 4A E : s 4: t E5: e 76: v E5: e 4A: j E: o 62: b 73: s = 94 printing characters.32 bit 6 from the right.33 (a) 897 (b) 564 (c) 87 (d) 2,99.34 ASCII for decimal digits with even parit: (): (): (2): (3): (4): (5): (6): (7): (8): (9):.35 (a) a b c a f b g c f g.36 a b a f b g f g Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copright 22,

9 9 CHAPTER 2 2. (a) + + ( + + )' ' ' ' ' ' ' () ()' ' ' ' ' + ' + ' (b) (c) + ( + ) ( + ) ( + )( + ) ( + ) + (c) (d) + + ( + ) ( + ) ( + ) + () () 2.2 (a) + ' = ( + ') = (b) ( + )( + ') = + ' = ( +') + ( + ') = + ' + + ' = (c) + ' + ' = ( + ') + ' = + ' = (d) (A + B)'(A' + B')' = (A'B')(A B) = (A'B')(BA) = A'(B'B)A = (e) (a + b + c')(a'b' + c) = aa'b' + ac + ba'b' + bc + c'a'b' + c'c = ac + bc +a'b'c' (f) a'bc + abc' + abc + a'bc' = a'b(c + c') + ab(c + c') = a'b + ab = (a' + a)b = b 2.3 (a) ABC + A'B + ABC' = AB + A'B = B Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copright 22,

10 (b) ' + = (' + ) = ( + ')( + ) = ( + ) (c) ( + )'(' + ') = ''(' + ') = '' (d) + (w + w') = ( +w + w') = (w + ) (e) (BC' + A'D)(AB' + CD') = BC'AB' + BC'CD' + A'DAB' + A'DCD' = (f) (a' + c')(a + b' + c') = a'a + a'b' + a'c' + c'a + c'b' + c'c' = a'b' + a'c' + ac' + b'c' = c' + b'(a' + c') = c' + b'c' + a'b' = c' + a'b' 2.4 (a) A'C' + ABC + AC' = C' + ABC = (C + C')(C' + AB) = AB + C' (b) ('' + )' w = ('')'' w =[ ( + )' + ] + + w = = ( + ')( + + ) + + w = + w = ( + w) + ( + ) + = + + (c) A'B(D' + C'D) + B(A + A'CD) = B(A'D' + A'C'D + A + A'CD) = B(A'D' + A + A'D(C + C') = B(A + A'(D' + D)) = B(A + A') = B (d) (A' + C)(A' + C')(A + B + C'D) = (A' + CC')(A + B + C'D) = A'(A + B + C'D) = AA' + A'B + A'C'D = A'(B + C'D) (e) ABC'D + A'BD + ABCD = AB(C + C')D + A'BD = ABD + A'BD = BD 2.5 (a) simplified (b) simplified (c) Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copright 22,

11 simplified (d) A B simplified (e) simplified (f) Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copright 22,

12 2 simplified 2.6 (a) A B C simplified (b) simplified (c) simplified Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copright 22,

13 3 (d) w simplified (e) A B C D simplified = (f) w simplified 2.7 (a) A B C D simplified Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copright 22,

14 4 (b) w simplified (c) A B C D (d) A B C D simplified simplified Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copright 22,

15 5 (e) A B C D simplified 2.8 ' = (w + )' = (w)'()' = (w' + ')(' + ') ' = w(w' + ')(' + ') + (w' + ')(' + ') = + ' = w + + (w + )' = A + A' = with A = w (a) ' = (' + ')' = (')'(')' = (' + )( + ') = + '' (b) ' = [(a + c) (a + b')(a' + b + c')]' = (a + c)' + (a + b')' + (a' + b + c')' =a'c' + a'b + ab'c (c) ' = [ + '(v'w + )]' = '['(v'w + )]' = '['v'w + ']' = '[('v'w)'(')'] = '[( + v + w') +( ' + ' + )] = ' + 'v + 'w' + '' + '' +' = '(v + w' + ' + ') 2. (a) + 2 = Σ m i + Σm 2i = Σ (m i + m 2i ) (b) 2 = Σ m i Σm j where m i m j = if i j and m i m j = if i = j 2. (a) (,, ) = Σ(, 4, 5, 6, 7) (b) (a, b, c) = Σ(, 2, 3, 7) = + ' + ' = bc + a'c' a b c 2.2 A = _ B = _ Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copright 22,

16 6 (a) A AND B = _ (b) A OR B = _ (c) A XOR B = _ (d) NOT A = _ (e) NOT B = _ 2.3 (a) u (u + ') Y = [(u + ')(' + )] (' + ) (b) u Y = (u or )' + (c) (u or )' u (u'+ ') Y = (u'+ ')( + ') (d) u ( + ') u( or ) Y = u( or ) + ' (e) u u ' Y = u + +u u (f) Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copright 22,

17 7 u Y = u + + '(u + ') (u + ') '(u + ') 2.4 (a) = + '' + ' (b) = + '' + ' = (' + ')' + ( + )' + ( + ')' (c) = + '' + ' (d) = [()' ('')' (')']' = + '' + ' = [()' ('')' (')']' Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copright 22,

18 8 (e) = + '' + ' = (' + ')' + ( + )' + ( + ')' 2.5 (a) T = A'B'C' + A'B'C + A'BC' = A'B'(C' + C) +A'C'(B' + B) = A'B' +A'C' = A'(B' + C') (b) T 2 =T ' = A'BC + AB'C' + AB'C + ABC' + ABC = BC(A' + A) + AB'(C' + C) + AB(C' + C) = BC + AB' + AB = BC + A(B' + B) = A + BC (3, 5, 6, 7) =Π (,, 2, 4) T = A'B'C' + A'B'C + A'BC' T 2 = A'BC + AB'C' + AB'C + ABC' + ABC A'B' A'C' T = A'B' A'C' = A'(B' + C') AC' T 2 =AC' + BC + AC = A+ BC AC BC 2.6 (a) (A, B, C) = A'B'C' + A'B'C + A'BC' + A'BC + AB'C' + AB'C + ABC' + ABC = A'(B'C' + B'C + BC' + BC) + A((B'C' + B'C + BC' + BC) = (A' + A)(B'C' + B'C + BC' + BC) = B'C' + B'C + BC' + BC = B'(C' + C) + B(C' + C) = B' + B = (b) (, 2, 3,..., n ) = Σm i has 2 n /2 minterms with and 2 n /2 minterms with ', which can be factored and removed as in (a). The remaining 2 n- product terms will have 2 n- /2 minterms with 2 and 2 n- /2 minterms with ' 2, which and be factored to remove 2 and ' 2. continue this process until the last term is left and n + ' n =. Alternativel, b induction, can be written as = n G + ' n G with G =. So = ( n + ' n )G =. Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copright 22,

19 9 2.7 (a) = (b + cd)(c + bd) bc + bd + cd + bcd = Σ(3, 5, 6, 7,, 4, 5) ' = Σ(,, 2, 4, 8, 9,, 2, 3) = Π(,, 2, 4, 8, 9,, 2, 3) a b c d (b) (cd + b'c + bd')(b + d) = bcd + bd' + cd + b'cd = cd + bd' = Σ (3, 4, 7,, 2,4, 5) = Π (,, 2, 5, 6, 8, 9,, 3) a b c d (c) (c' + d)(b + c') = bc' + c' + bd + c'd = (c' + bd) = Σ (,, 4, 5, 7, 8, 2, 3, 5) = Π (2, 3, 6, 9,,, 4) Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copright 22,

20 2 (d) bd' + acd' + ab'c + a'c' = Σ (,, 4, 5,,, 4) ' = Σ (2, 3, 6, 7, 8, 9, 2, 3, 5) = Π (2, 3, 6, 7, 8, 2, 3, 5) a b c d Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copright 22,

21 2 2.8 (a) w = ' + '' + w' + w' + w = Σ(, 5, 6, 7, 9,, 3, 4, 5 ) (b) ' ' ' w' w ' w 5 - Three-input AND gates 2 - Three-input OR gates Alternative: - ive-input OR gate 4 - Inverters (c) = ' + '' + w' + w' + w = ' + + w = ʹ + (w + ) (d) = ' + w + ) = Σ(, 5, 9, 3,,, 3, 5, 6, 7, 4, 5) = Σ(, 5, 6, 7, 9,,, 3, 4, 5) (e) ' w Inverter, 2 Two-input AND gates, 2 Two-input OR gates Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copright 22,

22 = B'D + A'D + BD ABCD -B'-D = = 3 = 9 = ABCD A'--D = = 3 = 5 = 7 ABCD -B-D = 5 = 7 = 3 = 5 = Σ(, 3, 5, 7, 9,,3, 5) = Π(, 2, 4, 6, 8,, 2, 4) 2.2 (a) (A, B, C, D) = Σ(2, 4, 7,, 2, 4) '(A, B, C, D) = Σ(,, 3, 5, 6, 8, 9,, 3, 5) (b) (,, ) = Π(3, 5, 7) ' = Σ(3, 5, 7) 2.2 (a) (,, ) = Σ(, 3, 5) = Π(, 2, 4, 6, 7) (b) (A, B, C, D) = Π(3, 5, 8, ) = Σ(,, 2, 4, 6, 7, 9,, 2, 3, 4, 5) 2.22 (a) (u + w)( + u'v) = u + uu'v + w + wu'v = u + w + wu'v = u + w = (u + w) = u + w (SOP form) = (u + w) (POS form) (b) ' + ( + ')( + ') = ' + ( + ' + ' + '') = ' + + ' + '' = ' + +' (SOP form) = (' + + ') (POS form) 2.23 (a) B'C +AB + ACD A B C D Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copright 22,

23 23 (b) (A + B)(C + D)(A' + B + D) A B C D (c) (AB + A'B')(CD' + C'D) A B C D (d) A + CD + (A + D')(C' + D) A B C D 2.24 = ' + ' and ( )' = ( + ')(' + ) Dual of ' + ' = (' + )( + ') = ( )' 2.25 (a) = ' = ' Not commutative ( ) = '' ( ) = (')' = ' + Not associative Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copright 22,

24 24 (b) ( ) = ' + ' = = ' + ' Commutative ( ) = (, 2, 4, 7) = ( ) Associative 2.26 Gate NAND (Positive logic) NOR (Negative logic) L L L H H L H H H H H L Gate NOR (Positive logic) NAND (Negative logic) L L L H H L H H H L L L 2.27 f = a'b'c' + a'bc' + a'bc + ab'c' + abc = a'c' + bc + a'bc' + ab'c' f 2 = a'b'c' + a'b'c + a'bc + ab'c' + abc = a'b' + bc + ab'c' a' b' a' a' b c' a' b c a' b c a b c f a' c' b c a' b c' a b' c' f a' b' c a' b c a b' c f 2 a' b' b c a b' c' f 2 Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copright 22,

25 (a) = a(bcd)'e = a(b' + c' + d')e = a(b' + c' + d')e = ab e + ac e + ad e = Σ( 7, 9, 2, 23, 25, 27, 29) a bcde a bcde (b) = a (c + d + e)= a'(c + d +e) + a(c'd'e') = a'c + a'd + a'e + ac'd'e' 2 = b'(c + d + e)f = b'cf + b'df + b'ef = a (c + d + e) = a'(c + d +e) + a(c'd'e') = a'c + a'd + a'e + ac'd'e' 2 = b'(c + d + e)f = b'cf + b'df + b'ef a'-c--- = 8 = 9 = = a'--d-- = 8 = 9 = = a'---e- = 2 = 3 = 6 = 7 a-c'd'e'- = 32 = 33 = 34 = 35 = 2 = 3 = 4 = 5 = 2 = 3 = 4 = 5 = = = 4 = 5 -b' c--f -b' -d-f -b' --ef = 24 = 25 = 26 = 27 = 28 = 29 = 3 = 3 = 2 = 2 = 22 = 23 = 28 = 29 = 3 = 3 = 8 = 9 = 22 = 23 = 26 = 27 = 3 = 3 = 9 = = 3 = 5 = 4 = 43 = 45 = 47 = 9 = = 3 = 5 = 4 = 43 = 45 = 47 = 3 = 7 = = 5 = 35 = 39 = 5 = 55 Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copright 22,

26 26 = Σ (2, 3, 6, 7, 8, 9,,, 2, 3, 4, 5, 8, 9, 22, 23, 24, 25, 26, 27, 28, 29, 3, 3, 32, 33, 34, 35 ) 2 = Σ (3, 7, 9, 3, 5, 35, 39, 4, 43, 45, 47, 5, 55) ab cdef 2 ab cdef 2 ab cdef 2 ab cdef 2 Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copright 22,