PD55003L-E. RF POWER TRANSISTOR The LdmoST Plastic FAMILY. General features. Description. PIN configuration. Order codes

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1 PD553L-E RF POWER TRANSISTOR The LdmoST Plastic FAMILY General features Excellent thermal stability Common source configuration P OUT =3W mith 17dB gain@5mhz/12.5v New leadless plastic package Esd protection Supplied in tape & reel of 3K units In compliance with 22/95/EC european directive PowerFLAT (5x5) Description The PD553L-E is a common source N- Channel, enhancement-mode lateral Field-Effect RF power transistor. It is designed for high gain, broadband commercial and industrial application. It operates at 12V in common source mode at frequencies of up to 1GHz. PD55L-E boasts the excellent gain, linearity and reliability of STH1LV latest LD-MOS technology mounted in the innovative leadless SMD plastic package, PowerFLAT. PD55L-E s superior linearity performances makes it an ideal solution for car mobile radio. PIN configuration TOP VIEW Order codes Sales Type Marking Package Packaging PD553L-E 553 PowerFLAT (5x5) TAPE & REEL February 26 Rev1 1/

2 Contents: PD553L-E Contents: 1 Electrical data Maximum Ratings Thermal data Electrical specification Typical performances Typical performance (broadband) Test circuit schematic Test Circuit Test circuit photomaster Package mechanical data Revision history /19 Rev1

3 PD553L-E Electrical data 1 Electrical data 1.1 Maximum Ratings Table 1. Absolute maximum ratings (T CASE =25 C) Symbol Parameter Value Unit V (BR)DSS Drain-Source Voltage 4 V V GS Gate-Source Volatge -.5 to+15 V I D Drain Current 2.5 A P DISS Power Dissipation (@T C = 7 C) 14 W T stg Storage Temperature 65 to +15 C T j Operating Junction Temperature 15 C 1.2 Thermal data Table 2. Thermal data Symbol Parameter Value Unit R th(j-c) Junction-Case Thermal Resistance 5.7 C/W Rev1 3/19

4 Electrical specification PD553L-E 2 Electrical specification (T CASE =25 C) Table 3. Static Symbol Test Condictions Min. Typ. Max. Unit I DSS V GS =V, V DS =28V 1 µa I GSS V GS =2V, V DS =V 1 µa V GS(Q) V DS =1V, I D =5mA V V DS(ON) V GS =1V, I D =.5A.36 V g fs V DS =1V, I D =1A 1. mho C iss 34 pf C oss V GS =V, V DS =12.5V, f=1mhz 23 pf C rss 1.8 pf Table 4. Dynamic Symbol Test Condictions Min. Typ. Max. Unit P 1dB V DD =12.5V, I DQ =5mA, f=5mhz 3 W G P V DD =12.5V, I DQ =5mA, P OUT =3W, f=5mhz db ηd V DD =12.5V, I DQ =5mA, P OUT =3W, f=5mhz 5 52 % Load mismatch Table 5. V DD =12.5V, I DQ =5mA, P OUT =3W, f=5mhz 2:1 VSWR Switching on/off (inductive load) Test Condictions Class Human Body Model 2 Machine Model M3 Table 6. Switching energy (inductive load) Test Methodology Rating J-STD-2B MSL 3 4/19 Rev1

5 PD553L-E Electrical specification Figure 1. Typical Input/Drain load Impedances D Z DL Typical Input Impedance Typical Drain Load Impedance G Zin S Table 7. Impedance Data FREQ. MHz Z IN (Ω) Z DL (Ω) j j j j j j 1.18 Rev1 5/19

6 Electrical specification PD553L-E 2.1 Typical performances Figure 2. Capacitance Vs supply Voltage Figure 3. Output Power Vs Input Power 1 f = 1 M Hz 6 5 Idq = 7 ma 1 4 Idq = 5 ma C (pf) Coss Ciss Pout (W) Crss Vds (V) 1 Vds = 12.5 V f = 5 MHz Pin (mw) Figure 4. Power Gain Vs Output Power Figure 5. Efficiency Vs Output Power Idq = 5 ma Idq = 7mA 6 5 Idq = 5 ma Gp (db) Idq = 3 ma Idq = 2 ma Nd (%) 4 3 Idq = 7 ma Vds = 12.5 V f = 5 MHz Pout (W) 1 Vds = 12.5 V f = 5 MHz Pout (W) Figure 6. Input Return Loss Vs Output Power Figure 7. Output Power Vs Bias Current 7 RL (db) Idq = 5 ma Pout (W) Idq = 7 ma Vds = 12.5 V f = 5 MHz Pout (W) 1 Pin = 2 dbm f = 5 MHz Vdd = 12.5 V Idq (ma) 6/19 Rev1

7 PD553L-E Electrical specification Figure 8. Efficiency Vs Bias Current Figure 9. Output Power Vs Supply Voltage Nd (%) Pin = 2 dbm f = 5 MHz Vdd = 12.5 V Idq (ma) Pout (W) Idq = 5 ma Pin = 2 dbm f = 5 MHz Vds (V) Figure 1. Output Power Vs Gate-Source Voltage Pout (W) Pin = 2 dbm Vdd = 12.5 V f = 5 MHz Vgs (V) Rev1 7/19

8 Electrical specification PD553L-E 2.2 Typical performance (broadband) Figure 11. Power Gain Vs Frequency Figure 12. Efficiency Vs Frequency Gp (db) Nd (%) Vds = 12.5 V Idq = 5 m A Pout = 3 W f (MHz) 1 Vds = 12.5 V Idq = 5 m A Pout = 3 W f (MHz ) Figure 13. Return Loss Vs Frequency -5-1 RL (db) Vds = 12.5 V Id q = 5 m A Pout = 3 W f (MHz) 8/19 Rev1

9 PD553L-E Test circuit schematic 3 Test circuit schematic VGG C8 C7 C6 R1 B1 R3 C13 B2 C14 C15 C16 VDD 1 2 L C5 R4 RF in N1 C1 Z1 Z2 C2 C3 Z3 Z7 Z8 Z9 Z1 Z4 Z6 Q Z5 C4 C9 C1 C11 C12 RF out N2 Z1 Z2.79 X X.8 Z3.217 X.8 Z4.59 X.8 Z5.452 X.223 Z6.26 X.223 Z7.118 X.8 Z8.315 X.8 Z9.866 X.8 Z1.512 X.8 Table 8. Test Circuit Component List Component Description B1, B2 FERRIDE BEAD C1, C12 3Pf, 1B ATC CHIP CAPACITOR C2, C3 15pF, 1B ATC CHIP CAPACITOR C4, C9 -:- 2 pf VARIABLE CAPACITOR JOHANSON C5, C13 12pF 1B ACT CHIP CAPACITOR C6, C14.1mF 1B ACT CAPACITOR C7, C15 12pF 1B ACT CAPACITOR C8, C16 1µF, 35V, SMD ELECTROLYTIC CAPACITOR C1 C11 R1.5 -:- 5pF VARIABLE CAPACITOR JOHANSON.8 -:- 1pF VARIABLE CAPACITOR JOHANSON 33KΩ CHIP RESISTOR 1W R2, R3 15Ω MELF RESISTOR 1W R4 1KΩ CHIP RESISTOR 1W N1, N2 TYPE N FLANGE MOUNT BOARD ROGER ULTRA LAM 2 THK.3 ε r = OZ ED Cu BOTH SIDES Rev1 9/19

10 Test circuit schematic PD553L-E 3.1 Test Circuit 3.2 Test circuit photomaster 4 inches 6.4 inches 1/19 Rev1

11 PD553L-E Test circuit schematic Table 9. (V DS =12.5V, I DS =.15A) S-Parameter (PD553L) FREQ IS 11 I S 11 Φ IS 21 I S 21 Φ IS 12 I S 12 Φ IS 22 I S 22 Φ (MHz) Rev1 11/19

12 Test circuit schematic PD553L-E Table 1. (V DS =12.5V, I DS =.8A) S-Parameter (PD553L) FREQ IS 11 I S 11 Φ IS 21 I S 21 Φ IS 12 I S 12 Φ IS 22 I S 22 Φ (MHz) /19 Rev1

13 PD553L-E Test circuit schematic Table 11. S-Parameter (PD553L) (V DS =12.5V, I DS =1.5A) FREQ IS 11 I S 11 Φ IS 21 I S 21 Φ IS 12 I S 12 Φ IS 22 I S 22 Φ (MHz) Rev1 13/19

14 Package mechanical data PD553L-E 4 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: 14/19 Rev1

15 PD553L-E Package mechanical data Table 12. PowerFLAT Mechanical Data Dim. mm inch MIN. TYP. MAX. MIN. TYP. MAX. A A A AA b c D d.3.11 E E e f g.74.3 h.21.8 Figure 14. PowerFLAT Package Dimensions Rev1 15/19

16 Package mechanical data PD553L-E Table 13. PowerFLAT Tape & Reel Dimensions DIM. mm. MIN. TYP MAX. Ao Bo Ko Figure 15. PowerFLAT Tape & Reel 16/19 Rev1

17 PD553L-E Package mechanical data Table 14. Recommended FOOTPRINT Rev1 17/19

18 Revision history PD553L-E 5 Revision history Table 15. Document revision history Date Revision Changes 14-Feb-26 1 First Issue 18/19 Rev1

19 PD553L-E Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners 26 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America Rev1 19/19